SUBJECT

DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

College of Technology
Bachelor of Technology
Semester-3rd

DIGITAL FUNDAMENTALS
Subject Code: 1010083212
IMPORTANT QUESTION BANK
TERM 2023-24

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 SUBJECT
DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

Sr.
No. Question Marks

Chapter 1 - Number System and logic gates

Do as directed:

1 1. (250.5)10 = ( )8 = ( )4 = ( )2 4
2. (2ED)16 =( )8 = ( )2 = ( )10
What is 1’s complement and 2’s complement? Where it is used? Give a specific example.
2 4
Given the two binary numbers X = 1010101 and Y = 1001011, perform the
3 subtraction X-Y using 1’s complements. 4

Given the Boolean function: F=xy+x’y’+y’z

4 1. Implement it with only NAND gates. 8

2. Implement it with only NOR gates.
Simplify the following Boolean expressions by manipulation of Boolean algebra.

5 1. F(x,y,z)= xy + xyz + xyz’+ x’yz 4

2. F(A,B,C,D)=A’C(A’BD)’+A’BC’D’+AB’C
Prove that:

6 1. wx+x’y+wy=wx+x’y 4
1. (AB+C+D)(C’+D)(C’+D+E)=ABC’+D
2. (A+B)’(A’+B’)’=0
State DE Morgan’s Theorem 4
7
Explain Error detecting and correcting codes. 4
8

Chapter 2: - Combinational digital circuits

Simplify the following Boolean functions using Karnaugh map:

1. F(A,B,C,D)=Π(0,1,2,3,4,10,11)
9 8
2. F(w,x,y,z)=Σm(0,1,2,4,5,12,13,14) + Σd(6,8,9).

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 SUBJECT
DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

Explain full adder/subtractor. Implement a full adder/subtractor with two half-

10 adder/subtractors and an OR gate 4

Simplify the function F(w,x,y,z)=Σ(0,1,2,8,10,11,14,15) using tabulation method. 8

11
Design a single bit magnitude comparator to compare two words A and B. 4
12
Draw the circuits diagram for 4-bit odd parity generator
13 4
1. What is an encoder? 2
14 2. List few applications of multiplexer.
3. Write down the difference between de-multiplexer and decoder.
Design 4-bit BCD adder. 4
15
Construct 4-bit binary parallel adder/subtractor using full adder and X-OR gate.
16 4
Design 8:1 multiplexer. 8
17
1. Obtain an 8:1 multiplexer using two 4:1 MUX.
2. Implement a 16:1 multiplexer using 4:1 Multiplexers.
18 8
3. Obtain a 16:1 multiplexer using 8:1 MUX.
4. Implement a full adder using 8:1 Multiplexer
Implement the following Boolean function using all 4:1 multiplexers.
19 8
f(A,B,C,D,E) = Ʃm(0,1,2,3,6,8,9,10,13,15,17,20,24)

20 Design 1:4 De-multiplxer.

4
1. Obtain a 1:4 de-multiplexer using 1:2 De-MUX.
21 2. Implement a 1:8 line De-multiplexer using 1:4De-Multiplexers. 4
3. Implement a full Subtracto using 1:8 De-Multiplexer.
Explain 3 to 8 line decoder. 4
22
1. Design priority encoder.
23 4
2. Design octal to binary encoder.

Chapter 3: - Sequential circuits & systems

1. Mention any two differences between the edge triggering and level triggering
2. What is a sequential circuit? Give an example.
24 3. Distinguish between latch and flip-flop 4
4. What is meant by the term “edge triggered”?
5. Define: Propagation Delay , Hold time, Rise time, Fall time

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 SUBJECT
DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

1. Explain gated S-R latch with waveforms.

25 8
2. Explain clocked S-R flip-flop.
1. Explain J-K flip-flop.
26 8
2. Explain Toggle (T) flip-flop.
Explain race-around condition in relation to the J-K flip-flops using timing relationships.
Draw the clocked Master-Slave J-K flip-flop configuration and explain how it removes 8
27
race-around condition in J-K flip-flops

What do you mean by PRESET and CLEAR inputs? 4

28
1. Conversion from S-R flip-flop to D flip-flop
2. Conversion from J-K flip-flop to T flip-flop
29 8
3. Conversion from S-R flip-flop to J-K flip-flop
4. Write the flip-flop excitation tables for JK and T FF.
Explain register classification in detail. 4
30
1. What is Buffer register?
31 2
2. Explain controlled buffer register.
Explain modes of operation in shift register. 4
32
1. Draw and explain 4-bit bidirectional serial shift register.
33 4
2. Draw and explain 4-bit bidirectional parallel shift register.
Draw and Explain Universal 4-bit shift register. 8
34
Design 4-bit 4 state ring counter. 8
35
Give difference between asynchronous and synchronous counters. 4
36
Design asynchronous up/down counter with waveforms. 8
37
Design 4-bit synchronous binary up/down counter 8
38
Design MOD-11 synchronous counter. 8
39
1. Design synchronous MOD-6 counter using clocked J-K flip-flops.
40 2. Design synchronous MOD-6 counter using clocked S-R flip-flops. 4
3. Design synchronous MOD-6 counter using clocked T flip-flops.
Briefly describe counter applications. 4
41
What is sequence generator?

Using J-K flip-flop design a synchronous counter that has the following sequence: 8
42
……..0-2-5-6-0-……

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 SUBJECT
DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

Undesired states 1,3,4,7 must always go 0 on next clock pulse.

Chapter 4- A/D and D/A convertors

Give detail advantages of digital system. 4

43
Explain DAC circuits:
44 8
1. Binary weighted registor DAC
2. R-2R Ladder DAC
Define the following in terms of DAC:

45 1. Linearity Error 2
2. Offset error
3. Gain error
Explain basic sample and hold circuit. 4
46
Describe the following ADCs:

1. The parallel comparator/Flash ADC

47 8
2. Counter type ADC
3. Successive approximation ADC
4. Dual slope type ADC
Chapter 5: - Memory Architecture
Explain memory organisation and operation. 3
48
Give detail classification of memory. 3
49
Write a note on “Types of ROMs”. 4
50
Compare:

1. EEPROM and EPROM

51 2. Volatile and Non-Volatile memories 4
3. SRAM and DRAM
4. RAM and ROM
5. EPROM and FLASH memory
Give detail classification of RAMs. 8
52
Write a short note on Flash memory.
53 8

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 SUBJECT
DIGITAL FUNDAMENTALS
Subject Code: (1010083212)
Question Bank SEMESTER:-3rd PREPARED BY:- Payal Roy

A16*4 size memory is available. Expand its word size so as to obtain a 16*8 memory.
54 8

Obtain a 32*4 memory using 16*4 memory chips. 8

55

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