VLSI Design

ECE314
Spring 2022
M4: Digital Building Blocks
Lecture 1
Adders
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE314 – M4 Lecture 1 1

 Outline

• Ripple Adder
• Full Adder Optimization
– Inversion Property Exploitation
– Setup Expressions & Manchester Carry
• Ripple Adder Improvement
– Carry-Bypass Adder
– Linear Carry-Select Adder
– Square-Root Carry-Select Adder
• Carry-Lookahead Adder

D. Khalil ECE314 – M4 Lecture 1 2

 Ripple Adder
A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA
(= Ci,1)
tcarry tcarry tcarry t sum
S0 S1 S2 S3

Simplest adder
In worst case, carry ripples from the least to most significant bits
tp = (N-1)tcarry + tsum
tcarry is critical and should be smaller than tsum
Worst case propagation delay is linear with the number of bits: tp = O(N)

D. Khalil ECE314 – M4 Lecture 1 3

 Full Adder
A B

Ci Co
FA

Co = AB  BCi  ACi
S = A BCi  ABCi  A BCi  ABCi
= ABCi  Co  A  B  Ci 
Other useful expressions
= A  B  Ci

D. Khalil ECE314 – M4 Lecture 1 4

 Static Full Adder Implementation
VDD
• Straight-forward VDD
Ci A B
implementation
A B
• Carry: 2 stages A
• Sum: 3 stages B
• Tall PMOS Ci B
VDD
stack A
Co
Carry: 3T Ci
Sum: 4T Ci A S
Ci
• Large size
28T A B B VDD
A B Ci A
• Carry load
6 gates + Co B
2 diffusions

Co = AB  BCi  ACi
• Better implementations exist
S = ABCi  Co  A  B  Ci 

D. Khalil ECE314 – M4 Lecture 1 5

 Mirror Full Adder Implementation
• A better implementation
VDD
of the pull-up network
VDD
• Carry: 2 stages B
• Sum: 3 stages A B B A B Ci VDD
A
• Better PMOS
stack A Co Ci
S
Ci S
Carry: 2T
A Ci
Sum: 3T
• Large size A
A B B A B Ci
28T VDD
B
• Carry load
6 gates +
Co
2 diffusions

Co = AB  BCi  ACi
• Better implementations exist
S = ABCi  Co  A  B  Ci 

D. Khalil ECE314 – M4 Lecture 1 6

 Outline

• Ripple Adder
• Full Adder Optimization
– Inversion Property Exploitation
– Setup Expressions & Manchester Carry
• Ripple Adder Improvement
– Carry-Bypass Adder
– Linear Carry-Select Adder
– Square-Root Carry-Select Adder
• Carry-Lookahead Adder

D. Khalil ECE314 – M4 Lecture 1 7

 Full Adder Inversion Property
Exploit inversion property for carry delay improvement
by removing the inverter for Co and using Co instead

D. Khalil ECE314 – M4 Lecture 1 8

 Full Adder Logic Setup
3 new variables:
Generate (G) = AB
Propagate (P) = A  B
Delete = A B
ONLY depend on A & B
No need to wait for Ci
New expressions for S & Co
based on G & P

Can derive expressions for S & Co based on D & P

Simple expressions  faster calculations

D. Khalil ECE314 – M4 Lecture 1 9

 Manchester Full Adder
Simplified one stage carry circuit by using G, D, and P
Dynamic implementation is even simpler
Transmission gate replaced by NMOS
No need of D

Static Manchester Carry Gate Dynamic Manchester Carry Gate

VDD VDD
Pi Pi

Gi
Co Ci Co
Ci
Gi
Di
Pi

D. Khalil ECE314 – M4 Lecture 1 10

 Outline

• Ripple Adder
• Full Adder Optimization
– Inversion Property Exploitation
– Setup Expressions & Manchester Carry
• Ripple Adder Improvement
– Carry-Bypass Adder
– Linear Carry-Select Adder
– Square-Root Carry-Select Adder
• Carry-Lookahead Adder

D. Khalil ECE314 – M4 Lecture 1 11

 Carry-Bypass (Skip) Adder
P0 G1 P1 G1 P2 G2 P3 G3

Ci,0 C o,0 C o,1 Co,2 Co,3

FA FA FA FA

Block Propagate
P0 G1 P1 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA
Co,3

MUX
Basic Idea:
• If (P0 & P1 & P2 & P3 = 1) then (Co,3 = Ci,0) else (“kill” or “generate”)
• Carry either propagates through bypass path or gets generated
somewhere inside the carry chain
• In either case, delay is smaller than normal ripple
• Small area overhead due to added MUX
D. Khalil ECE314 – M4 Lecture 1 12
 Carry-Bypass (Skip) Adder
EG: N=16
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
P0=0, P1=P2=P3=1 P4=P5=P6=P7=1 P8=P9=P10=P11=1 P12=P13=P14=P15=1
tsetup Setup Setup Setup Setup

3tcarry
C i,0 Carry Carry Carry Carry

4tcarry tbypass tbypass tbypass

Sum Sum Sum Sum

Ripple adder critical path: carry generate at bit 0 & propagate from bit 0tsum
to 15
Carry-bypass adder critical path: carry generate at bit 0, propagate from bit 0
to bit 3, bypass the middle 2 groups, & propagate from bit 12 to bit 15
longer path ?
Generally, for N = number of bits & M = group size in bits
N 
t p = tsetup  Mtcarry    1tbypass  M  1tcarry  tsum
M 
integer M optimal ?
D. Khalil ECE314 – M4 Lecture 1 13
 Linear Carry Select Adder
Setup
Basic Idea:
• Pre-compute carry chain P,G vectors
for both possible cases of
carry-in values (0 & 1) "0"
"0" Carry
• When carry-in arrives,
select the correct case
depending on the value "1"
• Only takes MUX delay for "1" Carry
selection Carry vectors
• In either case, delay is Ci Co
much smaller than ripple MUX
• Significant area overhead
due to added duplicate
carry chain and MUX
Sum

D. Khalil ECE314 – M4 Lecture 1 14

 Linear Carry Select Adder
EG: N=16
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
tsetup Setup Setup Setup Setup

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
4tcarry
"1" Carry "1" Carry "1" Carry "1" Carry
"1" "1" "1" "1"
t = 10 ns
t = 8ns
MUX MUX MUX MUX
Ci,0 Co,3 Co,7 Co,11 Co,15
tmux
tmux tmux tmux
Sum Sum Sum Sum

S0-3 S4-7 S8-11 tsum S12-15

Generally, for N = number of bits & M = group size in bits
longer path ?
t p = tsetup  Mt carry   N M tmux  t sum
M optimal ?
integer
D. Khalil ECE314 – M4 Lecture 1 15
 Linear Carry Select Adder
EG: N=16
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
tsetup Setup Setup Setup Setup

(1)
"0" Carry "0" Carry "0" Carry "0" Carry
"0" "0" "0" "0"
4tcarry
"1" Carry "1" Carry "1" Carry "1" Carry
"1" "1" "1" "1"
(5) (5) (5) (5)
(6) (7) (8)
MUX MUX MUX MUX
Ci,0 Co,3 Co,7 Co,11 Co,15
(9) tmux
tmux tmux tmux
Sum Sum Sum Sum

S0-3 S4-7 S8-11 tsum S12-15

Assume tsetup=tcarry=tmux=tsum=1 (10)
 Last MUX inputs are stable long time before MUX select arrives
Can we equalize such delays ?

D. Khalil ECE314 – M4 Lecture 1 16

 Square Root Carry Select Adder
EG: N=16
Bit 0-2 Bit 3-6 Bit 7-11 Bit 12-15
tsetup Setup Setup Setup Setup

(1)
"0" Carry "0" Carry "0" Carry "0" Carry
"0" "0" "0" "0"
3tcarry
"1" Carry "1" Carry "1" Carry "1" Carry
"1" "1" "1" "1"
(4) (5) (6) (5)
(5) (6) (7)
MUX MUX MUX MUX
Ci,0 Co,3 Co,7 Co,11 Co,15
(8) tmux
tmux tmux tmux
Sum Sum Sum Sum

S0-3 S4-7 tsum S12-15 (9)

S8-11
Generally, for M = first group size in bits & P = number of groups
t p = t setup  Mtcarry  Ptmux  t sum
P2  1  P2
For very large P, N = M  M  1  ...  M  P  1 =  P M     P  2 N
2  2  2 Square-root
D. Khalil ECE314 – M4 Lecture 1 17
 Outline

• Ripple Adder
• Full Adder Optimization
– Inversion Property Exploitation
– Setup Expressions & Manchester Carry
• Ripple Adder Improvement
– Carry-Bypass Adder
– Linear Carry-Select Adder
– Square-Root Carry-Select Adder
• Carry-Lookahead Adder

D. Khalil ECE314 – M4 Lecture 1 18

 Carry-LookAhead Adder (CLA)
• Better to eliminate carry ripple completely
Co,k = f Ak , Bk , Co,k 1  = Gk  Pk Co,k 1
• By expanding till Ci,0
Co,k = Gk  Pk Gk 1  Pk 1...  P1G0  P0Ci,0 
• Implement such logic for each bit
• Hence, carry & sum are independent of previous bits
• However, for N-bits, A0, B0 A1, B1 ••• AN-1, BN-1
the circuit will have N+1
branches with up to N+1
transistors in stack
• Hence, circuit becomes
very large and slow
• Must organize CLA Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1
adder in subgroups
to limit size of logic S S ••• SN-1
0 1

D. Khalil ECE314 – M4 Lecture 1 19

 References

• Rabaey, section 11.3

D. Khalil ECE314 – M4 Lecture 1 20