VLSI Design

ECE314
Spring 2022
M4: Digital Building Blocks
Lecture 2
Multipliers
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE314 – M4 Lecture 2 1

 Outline
• Multipliers
– Binary Multiplication Example
– Array Multiplier
– Carry-Save Multiplier
– Wallace Tree Multiplier

D. Khalil ECE314 – M4 Lecture 2 2

 Binary Multiplication Example

1 0 1 0 1 0 Multiplicand = M bits
x 1 0 1 1 Multiplier = N bits
1 0 1 0 1 0
1 0 1 0 1 0 Partial products
Operations: AND + Shift
0 0 0 0 0 0 Can be in parallel
+ 1 0 1 0 1 0
Result = M + N bits
1 1 1 0 0 1 1 1 0 Operation: Add
Wait for Carry

D. Khalil ECE314 – M4 Lecture 2 3

 Array Multiplier

• M=N=4 X3 X2 X1 X0 Y0
• Shift by routing
X3 X2 X1 X0 Y1 Z0

HA FA FA HA

X3 X2 X1 X0 Y2 Z1
X3 X2 X1 X0
x Y3 Y2 Y1 Y0
FA FA FA HA

Y3 Z2 Y0X3 Y0X2 Y0X1 Y0X0

X3 X2 X1 X0
Y1X3 Y1X2 Y1X1 Y1X0
FA FA FA HA + Y2X3 Y2X2 Y2X1 Y2X0

Z7 Z6 Z5 Z4 Z3 Y3X3 Y3X2 Y3X1 Y3X0

Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

D. Khalil ECE314 – M4 Lecture 2 4

 Array Multiplier
Critical Path M
•M=N=4 Critical Path 1
Critical Path 2
HA FA FA HA

• Multiple critical paths

N FA FA FA HA
• Difficult to optimize all
at the same time

FA FA FA HA

tmult  tand + M  1tcarry +  N  2 tcarry +  N  1t sum

D. Khalil ECE314 – M4 Lecture 2 5

 Carry-Save Multiplier

• M=N=4 • Carries are passed

diagonally downwards
(saved to next stage)
• Added vector-merging
adder VMA (fast)
• One critical path
(Optimized using VMA)
Assuming tcarry  t sum

t mult  t and +  N  1tcarry + M  1tcarry

Using an advanced vector merging adder

t mult  t and +  N  1tcarry + t merge

D. Khalil ECE314 – M4 Lecture 2 6

 Wallace Tree Multiplier
Adders as Data Compressors
Half Adder
• 2 inputs
• 2 ouputs
– 1 output in same column
– 2nd output in next column
Full Adder (3-2 compressor)
• 3 inputs
• 2 ouputs
– 1 output in same column
– 2nd output in next column

A B A B Ci

(2,2) (3,2)

Co S Co S

D. Khalil ECE314 – M4 Lecture 2 7

 Wallace Tree Multiplier
Transformation to Wallace Tree (M = N = 4)
Partial products First stage
6 5 4 3 2 1 0 6 5 4 3 2 1 0
Bit position

HA
(a) (b)

Second stage Final adder (vector merging)

6 5 4 3 2 1 0 6 5 4 3 2 1 0

VMA
FA HA
(c) (d)

D. Khalil ECE314 – M4 Lecture 2 8

 Wallace Tree Multiplier
Implementation of Wallace Tree (M = N = 4)

• Less components added to VMA (note the longer VMA)

• Less logic depth before VMA (can achieve less delay)

D. Khalil ECE314 – M4 Lecture 2 9

 References

• Rabaey, section 11.4

D. Khalil ECE314 – M4 Lecture 2 10