VLSI Design

ECE314
Spring 2022
M2: Interconnects
Lecture 2
Interconnect Delay & Power
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE314 – M2 Lecture 2 1

 Outline
• Wire Models
– Ideal
– Lumped C
– Lumped RC
– Lumped RLC
• Signal Propagation Definitions
• RC Delay
– RC Tree
– Elmore Delay
– Elmore Delay: Long Wire
– Elmore Delay: Gate + Long Wire
• Power Dissipation
– Dynamic Power Dissipation
– Static Power Dissipation
– Direct-Path (Short-Circuit) Power Dissipation

D. Khalil ECE314 – M2 Lecture 2 2

 Wire Models Introduction

• Integrated circuits wiring is very complicated,

contain many millions of tiny 3D structures

• Need to use simple models to simulate

• Models are approximation

– Must leave many details out
– Must retain important details
– Appropriate level of details depends on the desired questions
• Simulation do not tell what the circuit will really do
It tells what the MODEL of the circuit will do
• Simulations can answer the question you ask,
but does not tell you whether it is the right question

D. Khalil ECE314 – M2 Lecture 2 3

 Ideal Wire Model

• No parasitics

• Same voltage is present at every point of the wire at every point

in time – wire is equipotential
• Wire is a single electric node

• Only valid for extremely short wires, such as those between

nearest transistors

D. Khalil ECE314 – M2 Lecture 2 4

 Lumped C Wire Model

• Only consider parasitic capacitance

• Still the same voltage is present at every point of the wire at

every point in time – wire is equipotential
• Wire is a single electric node
• Does not introduce any wire delay
• Parasitic capacitance adds to the load capacitance at the output
connected to the wire, which impacts the gate performance

• Valid for short wires with negligible parasitic resistance when

switching frequency is not very high
• Inaccurate (pessimistic) for long wires
• Model of choice for most wires

D. Khalil ECE314 – M2 Lecture 2 5

 Lumped RC Wire Model

• Consider parasitic capacitance and resistance

• Wire is NOT a single electric node

• Wire is divided into n sections in series (sections  accuracy )
• 3 types of RC sections: L, T, and  (  is most accurate)

Error of 3 -sections < 3%

100 L-sections for similar
accuracy!

• Adds significant complexity

• Introduces wire delay

• Valid for long wires with significant parasitic resistance

• Model of choice for long wires
D. Khalil ECE314 – M2 Lecture 2 6
 Lumped RLC Wire Model

• Consider parasitic capacitance, inductance, and resistance

• Wire is NOT a single electric node

• Wire is divided into n sections in series (sections  accuracy )
• Similarly, 3 types of RLC sections: L, T, and  (  is most accurate)
• Adds significant complexity
• Introduces wire delay

• Valid for long wide wires with significant parasitic inductance

compared to resistance and very high switching frequency

D. Khalil ECE314 – M2 Lecture 2 7

 Outline
• Wire Models
– Ideal
– Lumped C
– Lumped RC
– Lumped RLC
• Signal Propagation Definitions
• RC Delay
– RC Tree
– Elmore Delay
– Elmore Delay: Long Wire
– Elmore Delay: Gate + Long Wire
• Power Dissipation
– Dynamic Power Dissipation
– Static Power Dissipation
– Direct-Path (Short-Circuit) Power Dissipation

D. Khalil ECE314 – M2 Lecture 2 8

 Signal Propagation Definitions

• Inverter Example Vin Vout

Vin
Propagation Delay
Input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
Output Signal
waveform 50% Transition
Times
10%
t
tf tr

D. Khalil ECE314 – M2 Lecture 2 9

 Outline
• Wire Models
– Ideal
– Lumped C
– Lumped RC
– Lumped RLC
• Signal Propagation Definitions
• RC Delay
– RC Tree
– Elmore Delay
– Elmore Delay: Long Wire
– Elmore Delay: Gate + Long Wire
• Power Dissipation
– Dynamic Power Dissipation
– Static Power Dissipation
– Direct-Path (Short-Circuit) Power Dissipation

D. Khalil ECE314 – M2 Lecture 2 10

 RC Delay

Delay and transition time for RC circuit

RDriver
Vout

Vout t   VDD 1  e t   V(0,VDD)
CLoad
  R Driver C Load

•  is called the RC time constant

• Time to reach 50% tp = ln(2) = 0.69

• Time from 10% to 90% tr = tf = ln(9) = 2.2

D. Khalil ECE314 – M2 Lecture 2 11

 RC Tree
RC Tree: 2
– A typical interconnect structure r2
r1 c2
– Single input (source) node, s s 1
4
r3 r4
– Unique resistive path exists between c4
source node and any other node c1
– All capacitors are between a node and ground 3
c3 ri
– No resistive loops
i
Path resistance ci
– sum of the resistances on path from input node to node i
i

rii   r j  r j  path s  i 
r44  r1  r3  r4
j 1
Shared path resistance
– resistance shared along paths from input node to nodes i and k
N
 
rik   r j  r j  paths  i   paths  k   ri 4  r1  r3
j 1
D. Khalil ECE314 – M2 Lecture 2 12
 Elmore Delay

Elmore delay for RC trees:

First-order time constant (Di ) between input node s
and node i in an RC tree is given by: 2
N r2
c2
 Di   rik Ck s
r1
1
k 1 r3 4
r4
c1 c4
t pi  0.69 Di
3
c3 ri
where
k is the network node i
N is the number of nodes in the network ci
Ck is the node capacitance
rik is the shared path resistance (resistance on the path from the
input s to node k that is on the path between the input and node i)

D. Khalil ECE314 – M2 Lecture 2 13

 Elmore Delay
Elmore delay limitation:
• Elmore delay determines the value of the dominant time constant
and thus is only good as a first-order approximation.
• It is sufficiently accurate for most applications.

Elmore is typically used for:

• Calculating delay of wire or tree
• Calculating delay of a series of pass transistors
• Calculating delay of pull-up and pull-down networks

D. Khalil ECE314 – M2 Lecture 2 14

 Elmore Delay
N
 Di   rik Ck
k 1
s x o
Example 1: 2 sections
 Do  RxC x  Rx  RL CL

2
r2
r1 c2
Example 2: Tree network s 1
4
r3 r4
c4
 Di  r1C1  r1C2  r1  r3 C3 c1
3
 r1  r3 C4  r1  r3  ri Ci c3 ri
i
ci
D. Khalil ECE314 – M2 Lecture 2 15
 Elmore Delay
Example 3: Chain network
D1=c1r1 D2=c1r1 + c2(r1+r2) Di=c1r1+ c2(r1+r2)+…+ci(r1+r2+…+ri)
r1 r2 ri-1 ri rN
1 2 i-1 i N
Vin VN
c1 c2 ci-1 ci cN

N N N i 
 DN   ci riN   ci rii   ci   r j 
i 1 i 1 i 1  j 1 
• For chain networks,
shared-path resistance is the same as path resistance
• For equal resistances and capacitances
r1  r2  ...  ri  r c1  c2  ...  ci  c
N ( N  1)
 DN  rc(1  2  ...  N )  rc
2
D. Khalil ECE314 – M2 Lecture 2 16
 Elmore Delay: Long Wire

(rw,cw,L) r1 r2 ri rN
1 2 i N
Vin VN Vin VN
c1 c2 ci cN

• Given a wire of length L, total resistance Rw and total capacitance Cw

• cw=Cw/ L and rw=Rw/L are capacitance and resistance per unit length
• Wire is modeled by N segments, each of length L/N
• For each segment i, ri = rw(L /N)= r and ci = cw(L /N)= c
N ( N  1)  L  L  N ( N  1)
 DN  rc   rw  cw 
2  N  N  2
N 1
 RwCw
2N
D. Khalil ECE314 – M2 Lecture 2 17
 Elmore Delay: Long Wire
N  1 RwCw rwcw L2
• For large N,  DN  RwCw  
2N 2 2
• Delay of a wire is a quadratic function of length L
• While equals RwCw for 1 L-section, approaches 0.5 RwCw as
number of sections increase. ( tp approaches 0.345 RwCw)
• Such relation is very close to the exact distributed model
 Can directly use  = 0.5 RwCw as approximation for long wire
rather than replacing wire with circuit models
Voltage Range 1 L-section ½ delay of 1 L-section Distributed RC
Lumped RC Lumped RC (exact)
0  63% () RC x2 0.5 RC 0.5 RC
0  50% (tp) 0.69 RC 0.345 RC 0.38 RC
10%  90% (tr) 2.2 RC 1.1 RC 0.9 RC
Note: Don’t get confused. For  & T sections, no need to multiply by ½.

D. Khalil ECE314 – M2 Lecture 2 18

 Elmore Delay: Gate + Long Wire
RDriver rw,cw, L
Vout

Vin CSelf Cin

RDriver Rw
Vout

Vin CSelf Cw/2 Cw/2 Cin

 1  1 
 D  RDriver  CSelf  Cw   RDriver  Rw  Cw  Cin 
 2  2 
1 
 RDriver CSelf  Cw  Cin   Rw  Cw  Cin 
2 
 Dgate  Dwire

D. Khalil ECE314 – M2 Lecture 2 19

 Elmore Delay: Gate + Long Wire
1 
 D  RDriver CSelf  Cw  Cin   Rw  Cw  Cin 
2 
1
 RDriver CSelf 
 Cw  Cin  rwcw L2  rw LCin
2
• Delay of a wire is a quadratic function of length L
• The propagation delay is given by:
t p  0.69 D  0.69 Dgate   Dwire   t pgate  t pwire
• Wire delay becomes more dominant when tpwire  tpgate

D. Khalil ECE314 – M2 Lecture 2 20

 Outline
• Wire Models
– Ideal
– Lumped C
– Lumped RC
– Lumped RLC
• Signal Propagation Definitions
• RC Delay
– RC Tree
– Elmore Delay
– Elmore Delay: Long Wire
– Elmore Delay: Gate + Long Wire
• Power Dissipation
– Dynamic Power Dissipation
– Static Power Dissipation
– Direct-Path (Short-Circuit) Power Dissipation

D. Khalil ECE314 – M2 Lecture 2 21

 Power Dissipation Components
Generally, 3 components of power dissipation in digital CMOS:
Dynamic Power
• Power drawn from supply associated with switching (voltage
transition) and charging/discharging of capacitances
• Dominant power component
Static (Steady-State) Power
• Power drawn from supply in absence of switching
(associated mainly with leakage)
• Ideally zero except for leakage
Direct-Path (Short-Circuit) Power
• Power drawn from supply associated with the current passing from
VDD to GND during switching when both NMOS & PMOS are ON
• Ideally zero except for non-zero rise/fall times

D. Khalil ECE314 – M2 Lecture 2 22

 Dynamic Power
Vdd
• Consider Vout transition from “0” to “1”
• Energy drawn from Vdd is CLVdd2
Vin Vout
• Half is dissipated in PMOS
& half is stored in CL
CL
• Now consider Vout transition from “1” to “0”
• The half stored in CL is dissipated in NMOS
2 2 2
• Hence, power is given by: P  C LVdd f 01  C LVdd f P01  C EFFVdd f
where f01 is the frequency of 01 transitions of output
f is the max rate (clock frequency)
P01 is the probability of 01 transitions in a clock period
CEFF is the average capacitance switched in a clock period
  dVout Vdd 2
E   iVdd t  Vdd dt  Vdd  C L dt  C LVdd  dVout  C LVdd
0 0 dt 0
  dVout Vdd 1 2
EC L   iVdd t  Vout dt   C L Vout dt  C L  Vout dVout  C LVdd
0 0 dt 0 2
D. Khalil ECE314 – M2 Lecture 2 23
 Static (Steady-State) Power
Vdd
• Consider Vout steady at “0”
M2
• There is a static current Istat from Vdd
due to subthreshold leakage, Vin Vout
junction leakage, and gate leakage
C
• Consider Vout steady at “1” M1 L
• There is a static current Istat into GND
due to subthreshold leakage,
junction leakage, and gate leakage
• Hence, power is given by: P  Vdd I stat
where Istat is the average static current

D. Khalil ECE314 – M2 Lecture 2 24

 Direct-Path (Short-Circuit) Power
Vdd
• Consider Vout transition
& non-zero rise/fall times
• There is direct path from Vin Vout
Vdd to GND for short period
when both PMOS & NMOS CL
are conducting simultaneously
• The resulting current ISC is approximated as
triangular spikes with height Ipeak and width tSC Ipeak
• Hence, energy in a transition is: E  I peak t SCVdd 2
• Assuming symmetrical rise/fall responses,
total energy in an output cycle of rise and fall is:
E  I peak t SCVdd tsc
• Hence, power is given by: P  I peak t SCVdd f 01
where f01 is the frequency of 01 transitions of output
• Note that larger CL causes less Ipeak. Why?

D. Khalil ECE314 – M2 Lecture 2 25

 References

• Rabaey, chapter 4, section 5.5

• T. Sakurai, Approximation of wiring delay in MOSFET LSI,
JSSC ,1983

D. Khalil ECE314 – M2 Lecture 2 26