PCS-9611S - X - Technical Manual - EN - Overseas General - X - R1.23

his
Copyright © 2021 NR. All rights reserved.
NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and
benefits afforded under P.R. China and international copyright and patent laws in its products,
including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is
licensed to use this document as well as all intellectual property rights owned or held by NR
Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how,
trade secrets, trademarks and trade names, service marks, design rights, database rights and
rights in data, utility models, domain names and all similar rights.
The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.
To the extent required the products described herein meet applicable IEC and IEEE standards,
but no such assurance is given with respect to local codes and ordinances because they vary
greatly.
Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered
sufficiently for your purposes, please do not hesitate to contact us.
Preface
Preface
About This Manual

The technical manual describes the protection, automation, control, and supervision functions of
PCS-9611S feeder relay, and contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per
function, as well as the hardware of the device. The manual can be used as a technical reference
during the engineering phase and during normal service. In addition, the manual also includes a
glossary that lists and defines technical terms used throughout the manual.
Product Documentation Set

The intended use of manuals throughout the product lifecycle is shown in the figure below.
DS SLG TM AM CPM OCM IMM CM STG
Planning
Ordering
Engineering
Installing
Commissioning
Operation
Maintenance
Disposal
The datasheet (DS) contains describes the control, protection, measurement and supervision
functions with the information of relevant hardware for the device.
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Preface
The selection guide (SLG) contains the explanation about the application option, the firmware
option, the software option, the hardware option and etc., and is instructive about how to order the
device based on expected configurations.
The technical manual (TM) contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per
function. The manual can be used as a technical reference during the engineering phase,
installation and commissioning phase, and during normal service.
The application manual (AM) contains application descriptions and instructions on how to
engineer the device using the configuration tool PCS-Studio. The manual can be used to find out
when and for what purpose a typical protection function can be used. The manual also
recommends a sequence for the engineering of protection, control, measurement and supervision
functions, HMI functions as well as communication engineering.
The communication protocol manual (CPM) describes the communication protocols supported
by the device. The manual concentrates on the vendor-specific implementations.
The operation and commissioning manual (OCM) contains instructions on how to operate and
commission the device. The manual describes how to identify disturbances and how to view
calculated and measured power grid data to determine the cause of a fault. The manual also
describes the process of testing the device in a substation which is not in service.
The installation and maintenance manual (IMM) contains instructions on how to install,
maintain and disposal the device. The manual provides procedures for mechanical and electrical
installation, lifecycle maintenance and repairing, and scrap disposal when decommissioning.
The cybersecurity manual (CM) describes the process for handling cyber security when
communicating with the device. Certification, Authorization with role-based access control, and
product engineering for cyber security related events are described and sorted by function. The
guideline can be used as a technical reference during the engineering phase, commissioning
phase, and during normal service.
The settings guide (STG) contains instructions on how to calculate the device's settings of
various functions (including the protection, automation, control, and supervision functions)
according to the different system parameters and fault conditions.
Safety Information
This manual is not a complete index of all safety measures required for operation of the
equipment (module or device). However, it comprises important information that must be followed
for personal safety, as well as to avoid material damage. Information is highlighted and illustrated
as follows according to the degree of danger:
Indicates an imminently hazardous situation that, if not avoided, will
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, could
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Preface
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, may result
in minor or moderate injury or equipment damage.
Indicates that property damage can result if the measures specified are
not taken.
Important information about the device, product handling or a certain

section of the documentation which must be given particular attention.
Instructions and Warnings

The following hazard statements apply to this device.
Disconnect or de-energize all external connections BEFORE opening this

device. Contact with hazardous voltages and currents inside this device
can cause electrical shock resulting in injury or death.
Contact with instrument terminals can cause electrical shock that can
result in injury or death.
Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.
Have only qualified personnel service this equipment. If you are not
qualified to service this equipment, you can injure yourself or others, or
cause equipment damage.
This device is shipped with default passwords. Default passwords should

be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access.
NR shall not be responsible for any damage resulting from unauthorized
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Preface
access.
DO NOT look into the fiber (laser) ports/connectors.
DO NOT look into the end of an optical cable connected to an optical

output.
DO NOT perform any procedures or adjustments that this instruction

manual does not describe.
During installation, maintenance, or testing of the optical ports, ONLY use

the test equipment qualified for Class 1 laser products!
Incorporated components, such as LEDs, transceivers, and laser emitters,

are NOT user serviceable. Return units to NR for repair or replacement.
Equipment components are SENSITIVE to electrostatic discharge (ESD).

Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.
Insufficiently rated insulation can deteriorate under abnormal operating

conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.
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SEVERE power and ground problems can occur on the communications

ports of this equipment as a result of using non-standard cables. Please
use the wiring method recommended in the manual for communication
terminals.
DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage
can result otherwise.
Use of controls or adjustments, or performance of procedures other than

those specified herein, may RESULT IN hazardous radiation exposure.
The firmware may be upgraded to add new features or enhance/modify

existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.
Document Conventions
⚫ The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.
⚫ Menu path is connected with the arrow "→" and bold.
For example: the access path of protection settings is: MainMenu→Settings→Protection

Settings
⚫ Settings not in the table should be placed in brackets.
For example: the system setting [Opt_SysFreq]
⚫ Cross-references are presented in italics.
For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1
⚫ Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.
For example: press the button "ENT".
Symbols
⚫ AND Gate
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& & &
⚫ OR Gate
>=1 >=1 >=1
⚫ Comparator
⚫ Binary signal Input
BI xxx
⚫ Signal input
SIG xxx
⚫ Setting input
SET xxx
⚫ Enable input
EN xxx
⚫ Timer
Optional definite-time or inverse-time characteristics
Timer
t
t
⚫ Timer
Fixed delay pickup (10ms), fixed delay drop-out (2ms)
10ms 2ms
⚫ Timer
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Settable delay pickup, fixed delay drop-out
[Tset1] 0ms
⚫ Timer
Fixed delay pickup, settable delay drop-out
0ms [Tset2]
⚫ Timer
Settable delay pickup, settable delay drop-out
[Tset1] [Tset2]
⚫ Generator
⚫ Transformer
⚫ Reactor
⚫ Motor
⚫ Capacitor
⚫ Busbar
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⚫ Circuit breaker
52
⚫ Current transformer
3CT
*
⚫ Voltage transformer
3VT
⚫ Disconnector
⚫ Earth
Three-phase Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN, YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
Warranty
This product is covered by the standard NR 10-year warranty. For warranty details, please consult
the manufacturer or agent for warranty information.
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Preface
Document Structure
This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using this device. To concentrate on
the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.
1 Introduction
Introduces the features of this device, summarizes functions and applications of the device.
2 Technical Data
Lists device specifications, type tests, and ratings.
3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, and provides the relevant logic diagrams.
4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.
5 Measurement
Provides information on viewing fundamental and metering quantities for voltages and currents,
as well as power and energy metering data.
6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.
7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.
8 Hardware
Describes the hardware of the PCS S series device family and provides general information on
the product structure and the modules’ information.
9 Settings
Provides a list of all PCS-9611S settings and their ranges, unit, steps, defaults. The organization
of the settings is similar to the settings organization in the device and in the PCS-Studio
configuration tool.
Appendix A Glossary
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Describes the abbreviations adopted in this manual.
Document Revision History

PN: ZL_PCS-9611S_X_Technical Manual_EN_Overseas General_X
Current version: R1.23
Corresponding Version
Date Description of change
Document Software
R1.00 R1.00 2019-01-31 ⚫ Form the original manual.
⚫ Positive-sequence overvoltage protection is added;

R1.01 R1.00 2019-04-24
⚫ Outmap settings are added.
⚫ Thermal overload protection and arc flash protection are
added;
⚫ Addition of GOOSE & SV communication information, such as
introduction, hardware specification, alarm signals and
R1.02 R1.11 2019-07-24 communication settings, for digital substation;
⚫ Update of description of double point status function;
⚫ Addition of position verification function for switchgear control;
⚫ Voltage selection function is modified;
⚫ Modification of I/O signals, logic diagrams and settings list of
manual synchronism check;
⚫ The NR6610B module is deleted;
⚫ Broken conductor protection is added;
R1.03 R1.12 2019-11-21 ⚫ The VT circuit supervision function is modified;
⚫ The control function is modified;
⚫ The NR6311A module is added.
⚫ The logic diagram of enabling/disabling phase overvoltage
protection, residual overvoltage protection, negative-sequence
overvoltage protection, positive-sequence overvoltage
protection and under voltage protection is modified;

R1.04 R1.14 2020-03-05
⚫ Switch-on-to-fault protection is modified;
⚫ Thermal overload protection is modified;
⚫ The NR6661A module is added.
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⚫ Measurement scope and accuracy are modified
⚫ The logic of the direction element of phase overcurrent
protection, earth fault overcurrent protection,
negative-sequence overcurrent protection and sensitive earth
fault protection are modified;
⚫ The operation characteristic and dropout characteristic of RMS
R1.10 R1.15 2020-07-07 overcurrent protection are modified;
⚫ Restricted earth-fault protection is added;
⚫ The single-end fault location function is added;
⚫ Two types of CPU modules are added;
⚫ The NR6663A module is added;
⚫ The device setting [En_PopupRecord_Blkd] is added.
⚫ PMU-related values and settings are added;
⚫ Three-phase current summation element is added;
⚫ Another group of phase overcurrent protection is added;
⚫ The “ALARM” LED indicator will not on when the device is
blocked;
⚫ Section 8.3 is modified;

R1.20 R1.17 2020-12-07
⚫ The NR6604A and NR6611A modules are added;
⚫ The DC analogue output module NR6632 is added;
⚫ The analog module NR6641-8I4U is added;
⚫ The voltage setting step of the system settings are modified.
⚫ Many global settings are added;
⚫ Modbus communication settings are added.
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⚫ The logic of SOTF protection is modified;
⚫ The arc flash protection is modified, some related technical
data are added;
⚫ Distance protection is added;
⚫ The supervision setting [64REF.En_AutoRecov_Alm_CTS] is
added;
⚫ The REF protection setting [64REF.I_NP_OnLoad] is added;

R1.21 R1.18 2021-02-07
⚫ The clock synchronization setting [En_ConvModeSNTP] is
added;
⚫ The setting range of the general communication setting
[B01.Opt_NetMode] is modified;
⚫ Frequency protection can operate to alarm, the corresponding
logic diagrams are modified, the corresponding output signals
and logic settings are added;
⚫ High impedance restricted earth fault protection application of
sensitive earth fault protection is added;

R1.22 R1.18 2021-04-01
⚫ The description of distance protection triggering fault location is
added.
⚫ The current/contact check logic for breaker failure protection is
added;
⚫ The two breaker failure protection settings [50BF.En_Curr] and
[50BF.En_CBPos] are added;
⚫ The distance SOTF protection is added;
⚫ Modify the setting range of the settings [50/51Px.C],
[50/51Gx.C], [A.50/51Gx.C], [50/51Qx.C], [50/51SEFx.C],

R1.23 R1.19 2021-08-01
[50/51Rx.C], [81Ox.t_Op], [81Ux.t_Op] and [S2.50/51Px.C];
⚫ Modify the default value of the general communication settings
[IP_LAN1], [IP_LAN2], [IP_LAN3] and [IP_LAN4];
⚫ The logic diagram of frequency rate-of-change protection is
modified;
⚫ The logic diagrams of arc sensor and arc flash protection are
modified.
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Introduction
1 Introduction
1
Table of Contents
1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-1
1.3 Features............................................................................................................ 1-8
List of Figures
Figure 1.1-1 Functional diagram of PCS-9611S ....................................................................... 1-1
PCS-9611S Feeder Relay 1-a

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1 Introduction
1-b PCS-9611S Feeder Relay

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Introduction
1.1 Application
The PCS-9611S relay is a protection, control and monitoring unit for various primary equipment
1
(such as overhead line, underground cable and transformer etc.) on solidly grounded, impedance
grounded, Peterson coil grounded and ungrounded system. This relay is suitable for wall surface
mounted indoors or outdoors or flush mounted into a control panel.
The function diagram of this relay is shown in Figure 1.1-1.
Busbar
3VTs
52
27P 59P 59Q VTS 59G 81U 81O 81R 25 79

1VT
67P 32R 21L
3CTs
*
50P 51P 49 CTS 50BF 51Q 46BC 50L/NL
1CT
*
50G SOTF 51G 67G 37 64REF
1CT
*
51SEF 60/59 60/50 67SEF FR

1VT
Load
Figure 1.1-1 Functional diagram of PCS-9611S
The PCS-9611S is widely adopted not only for conventional substations, but also for digital
substations. It supports IEC 61850 Editions 1 and 2 and provides GOOSE and SV network
interfaces with high real-time performance. The process level network supports peer-to-peer (P2P)
mode and networking mode, including single network mode and dual network mode. The station
level network can also receive and send MMS messages (such as interlocking signals) or process
level GOOSE messages (such as circuit breakers or disconnectors positions and trip signals).
1.2 Functions
1 Protection functions
PCS-9611S Feeder Relay 1-1

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1 Introduction
ANSI Protection Functions Remark

⚫ Up to 6 stages with independent logic
1 ⚫
⚫
Voltage control element for each stage
Optional direction element for each stage, including
forward direction, reverse direction and non-direction
67P
Phase overcurrent protection ⚫ Optional definite-time characteristic and inverse-time
50/51P
characteristic for each stage
⚫ Selectable trip purpose or alarm purpose for each
stage
⚫ Harmonic control element for each stage
⚫ Optional direction element for each stage, including
⚫ Optional measured zero-sequence current or
67G calculated zero-sequence current for each stage
Earth fault protection
50/51G ⚫ Optional definite-time characteristic and inverse-time
stage
⚫ Harmonic control element for each stage
⚫ Only measured zero-sequence current is supported
Another group of earth fault ⚫ Optional definite-time characteristic and inverse-time
A.50/51G
overcurrent protection characteristic for each stage
stage
⚫ Optional direction element for each stage, including
Negative-sequence
50/51Q ⚫ Optional definite-time characteristic and inverse-time
overcurrent protection
stage
⚫ Adopt the ratio of negative-sequence current to
46BC Broken conductor protection positive-sequence current (Ι2/Ι1) to detect the broken
conductor.
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Introduction
⚫ High impedance restricted earth fault protection

application
⚫ The measured zero-sequence current from the
high-precision CT is adopted
1
Sensitive earth fault
50/51SEF ⚫ Optional direction element for each stage, including
protection
⚫ Optional definite-time characteristic and inverse-time
stage
⚫ Full-current RMS value includes 2nd~11th harmonic
50/51R RMS overcurrent protection components
stage
⚫ Optional blocking condition, including circuit breaker
position and current criterion
37 Undercurrent protection
stage
⚫ Breaker failure protection and re-trip function
⚫ Optional current criterion (phase overcurrent element,
zero-sequence overcurrent element,
50BF Breaker failure protection negative-sequence overcurrent element)
⚫ It can be initiated by current, circuit breaker position or
external binary input
⚫ Two time delays
⚫ One stage of phase overcurrent SOTF protection
⚫ One stage of earth fault overcurrent SOTF protection
⚫ Harmonic control element for phase overcurrent SOTF
protection and earth fault overcurrent SOTF protection
⚫ Voltage control element for phase overcurrent SOTF
50PSOTF protection
50GSOTF Switch-on-to-fault protection ⚫ Distance SOTF protection shares pickup signal as
21SOTF initiation condition with distance protection
⚫ It is selectable among zone 2, 3 or 4 of distance
protection which is accelerated to trip by manual
closing or auto-reclosing
⚫ Distance SOTF protection can be controlled by power
swing blocking

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1 Introduction

1 59P Overvoltage protection ⚫

Optional phase voltage or phase-to-phase voltage
⚫ Optional “1-out-of-3” logic or “3-out-of-3” logic
stage
⚫ Optional phase voltage or phase-to-phase voltage
⚫ Optional “1-out-of-3” logic or “3-out-of-3” logic
27P Undervoltage protection
⚫ Check mode using circuit breaker position and current
criterion
⚫ Blocked by instantaneous VT circuit failure
stage
Negative-sequence
59Q ⚫ Selectable trip purpose or alarm purpose for each
overvoltage protection
stage
Positive-sequence ⚫ One stage of positive-sequence overvoltage protection
59Pos
overvoltage protection ⚫ Selectable trip purpose or alarm purpose
⚫ Optional measured zero-sequence voltage or
Residual overvoltage
59G calculated zero-sequence voltage
protection
stage
⚫ Voltage control element
81O Overfrequency protection
stage
⚫ Voltage control element
81U Underfrequency protection
stage
Frequency rate-of-change ⚫ Voltage control element
81R
protection ⚫ Selectable trip purpose or alarm purpose for each
stage
32R Reverse power protection ⚫ Selectable trip purpose or alarm purpose for each
stage

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Introduction

60/50 Current unbalance protection ⚫ Selectable trip purpose or alarm purpose for each
⚫
stage
Up to 2 stages with independent logic
1
60/59 Voltage unbalance protection ⚫ Selectable trip purpose or alarm purpose for each
stage
⚫ It can be triggered by on-load signal or circuit breaker
CLP Cold load pickup position
⚫ Short resetting is supported
⚫ Independent logic for auto-reclosing and manually
25 Synchro-check
closing
⚫ Two stages of thermal overload protection, one stage
49 Thermal overload protection
for alarm purpose and the other stage for trip purpose
⚫ Optional direction element
Restricted earth-fault ⚫ CT transient characteristic difference detection
64REF
protection ⚫ CT saturation detection based on 2nd and 3rd
harmonics
⚫ The arc flash signal is acquired by an arc sensor
50L/NL Arc flash protection
⚫ It is combined with the auxiliary fault current criterion
⚫ One shot or multi-shot
⚫ 3-pole AR
79 Auto-reclosing ⚫ It can be triggered by protection operation signal or
external binary input signal
⚫ Supports synchronism check or dead charge check
Another group of phase
S2.50/51P characteristic for each stage
stage
⚫ Up to 6 zones distance protection with settable
direction
⚫ Independent phase-to-phase measuring loops and
21L Distance protection three independent phase-to-ground measuring loops
⚫ Load encroachment
⚫ Power swing blocking and releasing
⚫ Faulty phase selection functions
FL Fault location function ⚫ Single-end fault location element
Current transformer
CTS
supervision
Voltage transformer
VTS
supervision
TCS Tripping circuit supervision
2 Control functions

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1 Introduction
⚫ Switchgear control
⚫ Double point status synthesis

1 ⚫ Remote/Local control mode switch
⚫ Interlocking logic for control
⚫ Direct control
⚫ Closing synchronism check with voltage selection
⚫ Switchgear trip counter
3 Measurement and metering
⚫ U, I, P, Q, Cos
⚫ Positive, negative and zero sequences
⚫ Max.15th harmonics
⚫ Energy metering (active and reactive energies for import and export)
⚫ Power Quality Supervision (PQS) with Total Harmonic Distortion (THD), deviation and
unbalance
⚫ DC analogue outputs (4~20mA, 0~10V, 0~5V or 0~20mA)
4 Synchrophasor measurement
⚫ The integrated Phasor Measurement Unit (PMU) function of synchrophasor

measurement is compatible with IEEE C37.118-2005, IEEE C37.118.1-2011, IEEE
C37.118.2-2011 and IEEE C37.118.1a-2014.
⚫ Supporting time synchronization by IRIG-B signal
⚫ Supporting P Class or M Class measurement (user selectable)
⚫ Measurement of three-phase and single-phase voltage and current
⚫ Measurement of positive/negative/zero-sequence voltage and current
⚫ Calculation of active power, reactive power, system frequency, and rate-of-change of

frequency (ROCOF)
⚫ Measurement of up to 32 binary status (user configurable)
⚫ Output of synchrophasor with timestamp, support of multiple protocols (TCP, TCP-UDP,

UDP) and multiple data rates for maximum 4 clients (PDC)
5 Supervision functions
⚫ VT circuit supervision
⚫ CT circuit supervision

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Introduction
⚫ Self-diagnostic
⚫ DC power supply supervision
⚫ System frequency supervision

1
⚫ Event recorder including 1024 disturbance items, 1024 change-of-state events, 1024
supervision events, 256 control logs and 1024 device logs.
⚫ Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file).
⚫ Single line diagram representation in display
6 Communication functions
⚫ Support of various protocols
➢ Modbus
➢ DNP3
➢ IEC 60870-5-103
➢ IEC 61850 Ed1 & Ed2
➢ IEC 62439 Parallel Redundancy Protocol (PRP)
➢ IEC 62439 High-availability Seamless Ring (HSR) Redundancy Protocol
➢ IEEE 802.1w Rapid Spanning Tree Protocol (RSTP)
⚫ Support for digital substation
➢ Extendable quantity of communication interfaces
➢ Support of IEC 61850 MMS Server
➢ Support of IEC 61850-8-1 GOOSE
➢ Support of IEC 61850-9-2LE SV
⚫ Up to four 10Base-T/100Base-TX copper Ethernet ports
⚫ Up to four 100Base-FX optical Ethernet ports
⚫ Two RS-485 serial ports for communication or printer
⚫ One RS-485/TTL serial port for clock synchronization
⚫ One BNC connector for clock synchronization
7 User Interfaces
⚫ Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and
set-point adjustment

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1 Introduction
⚫ Push buttons for open/close, switch for selection between local and remote control, and
user's login and logout authority management
1 ⚫ 4 Programmable operator pushbuttons with user-configurable labels
⚫ Up to 15/18 (6U, 1/3 × 19" or 6U, 1/2 × 19" chassis) programmable target LEDs with
user-configurable labels
⚫ 1 RS-232 rear port for printer (by jumper)
⚫ Language switchover—English+ selected language
⚫ Configuration tool—PCS-Studio
8 Additional functions
⚫ User programmable logic
⚫ Fault location
⚫ Fault phase selection
⚫ System phase sequences rotation function (ABC or ACB)
⚫ Clock synchronization
 IRIG-B: IRIG-B via RS-485 differential level, TTL level or BNC
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 IEEE1588: Clock message based on IEEE1588 via Ethernet network
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3): Clock messages through IEC103 protocol,

Modbus protocol and DNP3 protocol
⚫ Cyber security
 NERC CIP
 IEC 62351
 IEC 62443
 IEEE 1686
1.3 Features
⚫ Unified software and hardware platform, comprehensive power grid solutions of protection,
control, measurement and monitoring, easy to use and maintain.
⚫ High reliability and redundancy design for drive systems of the sampling circuit and the output

Date: 2021-08-01
Introduction
circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD
can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of
1
output relays.
⚫ Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analogue programming are supported.
⚫ Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be combined with different I/O modules, with online self-check and
monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.
⚫ Support memory check and error correction function, ensure high reliability and safety.
⚫ Support the internet communication protocol of native PRP/HSR and RSTP.
⚫ Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV
communication with multi-sampling rate.
⚫ Fully comply with cyber security standards, including IEC62443, IEC62351, IEEE1686,
NERC-CIP, support role based access control (RBAC), security audit, security encryption
communication and security tool, improve the cyber security capability of devices.
⚫ Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.
⚫ Settable secondary rated current (1A/5A) and settable voltage threshold of binary input
⚫ Support small size and large size LCD, control and multifunction button
⚫ Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.
⚫ Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm 2 lead
⚫ Multiple variants with case size 6U, 1/3 × 19" or 6U, 1/2 × 19"
⚫ Protection class of front side is up to IP54
⚫ PCS-Studio engineering tool is the application software on the user's PC for the interface with
PCS S series devices providing all the related functionality. It ranges from device configuration
to entire substation design of bay integration.
⚫ Support IEEE1588, IRIG-B clock synchronization
⚫ Support actual system phase sequence, either ABC or ACB, incorrect connection of actual
phase sequence can automatically be verified and relevant protection functions can be

Date: 2021-08-01
1 Introduction
blocked.
⚫ Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
1 its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
abnormality in advance.
⚫ Support setup up to 40 users and allow each user to own different password and access
authority.
⚫ Fully integrates multi functions into one device and can realize the protection and monitoring
function of feeder and capacitor etc.
⚫ Comprehensive functionality includes phase overcurrent protection, earth fault overcurrent

protection, negative-sequence overcurrent protection, sensitive earth fault protection,
overvoltage protection, undervoltage protection, frequency protection, reverse power
protection, breaker failure protection, undercurrent protection etc. The breaker failure,
reclosing, measuring, monitoring and control function are supported.
⚫ The overcurrent protection is combined with harmonic blocking and cold load pickup logic,
which can prevent mal-operation affected by inrush current while the transformer is no-load
energized.
⚫ Selectable IEC, ANSI inverse-time characteristic curves that can be defined by users, and the
inverse-time drop-out curve selection is supported.
⚫ Overvoltage and undervoltage protection support single phase and three phase operation
criteria setting, phase voltage and phase-to-phase voltage measurement mode are selectable,
which can be for various applications.
⚫ Complete event recording function is provided: 64 latest protection operation reports, 1024
latest supervision records, 1024 latest control operation records, 1024 latest user operation
records and 1024 latest records of time tagged sequence of event (SOE) can be recorded.

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2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1 2

2.1.1 AC Current Input ................................................................................................................... 2-1
2.1.2 AC Voltage Input................................................................................................................... 2-1
2.1.3 Power Supply ....................................................................................................................... 2-2
2.1.4 DC Analogue Output ............................................................................................................ 2-3
2.1.5 Binary Input .......................................................................................................................... 2-3
2.1.6 Binary Output........................................................................................................................ 2-5
2.2 Mechanical Specifications .............................................................................. 2-6

2.3 Ambient Temperature and Humidity Range .................................................. 2-7
2.4 Communication Port ....................................................................................... 2-7
2.4.1 EIA-485 Port ......................................................................................................................... 2-7
2.4.2 Ethernet Port ........................................................................................................................ 2-7
2.4.3 Optical Fiber Port ................................................................................................................. 2-8
2.4.4 Print Port............................................................................................................................... 2-9
2.4.5 Clock Synchronization Port .................................................................................................. 2-9
2.5 Type Tests ...................................................................................................... 2-10

2.5.1 Environmental Tests ........................................................................................................... 2-10
2.5.2 Mechanical Tests ................................................................................................................ 2-10
2.5.3 Electrical Tests.................................................................................................................... 2-10
2.5.4 Electromagnetic Compatibility ............................................................................................ 2-10
2.6 Certifications .................................................................................................. 2-12

2.7 Liquid Crystal Display (LCD) ........................................................................ 2-12
2.8 Terminals ........................................................................................................ 2-12
2.8.1 Ring Ferrule ........................................................................................................................ 2-12
2.8.2 Pin Ferrule .......................................................................................................................... 2-13
2.9 Measurement Scope and Accuracy ............................................................. 2-13

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2.10 Synchrophasor Measurement .................................................................... 2-13

2.10.1 Synchrophasor Measurement under Steady-state .......................................................... 2-13
2.10.2 Frequency and ROCOF Measurement under Steady-state ............................................ 2-14
2.10.3 Active and Reactive Power Measurement under Steady-state ....................................... 2-14
2 2.10.4 Synchrophasor Measurement under Modulation ............................................................. 2-15
2.10.5 Frequency and ROCOF Measurement under Modulation ............................................... 2-15
2.10.6 Synchrophasor Measurement under Frequency Ramp ................................................... 2-15
2.10.7 Frequency and ROCOF Measurement under Frequency Ramp ..................................... 2-15
2.10.8 Synchrophasor Measurement under Step Change ......................................................... 2-16
2.10.9 Frequency and ROCOF Measurement under Step Change ........................................... 2-16
2.10.10 Measurement Reporting Latency ................................................................................... 2-16
2.10.11 Synchrophasor Communication ..................................................................................... 2-17
2.11 Management Function ................................................................................. 2-17

2.11.1 Control Performance ........................................................................................................ 2-17
2.11.2 Clock Performance ........................................................................................................... 2-17
2.11.3 Fault and Disturbance Recording ..................................................................................... 2-17
2.11.4 Binary Input Signal ........................................................................................................... 2-17
2.12 Protective Functions ................................................................................... 2-17

2.12.1 Phase Overcurrent Protection (50/51P) ........................................................................... 2-17
2.12.2 Earth Fault Protection (50/51G) ....................................................................................... 2-18
2.12.3 Another Group of Earth Fault Overcurrent Protection...................................................... 2-19
2.12.4 Negative-sequence Overcurrent Protection (50/51Q) ..................................................... 2-20
2.12.5 Broken Conductor Protection (46BC) .............................................................................. 2-21
2.12.6 Sensitive Earth Fault Protection (50/51SEF) ................................................................... 2-21
2.12.7 RMS Overcurrent Protection (50/51R) ............................................................................. 2-22
2.12.8 Phase Overvoltage Protection (59P) ............................................................................... 2-22
2.12.9 Residual Overvoltage Protection (59G) ........................................................................... 2-22
2.12.10 Negative-sequence Overvoltage Protection (59Q) ........................................................ 2-22
2.12.11 Positive-sequence Overvoltage Protection (59Pos) ...................................................... 2-23
2.12.12 Phase Undervoltage Protection (27P) ........................................................................... 2-23

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2 Technical Data
2.12.13 Overfrequency Protection (81O) .................................................................................... 2-23
2.12.14 Underfrequency Protection (81U) .................................................................................. 2-24
2.12.15 Frequency Rate-of-change Protection (81R) ................................................................. 2-24
2.12.16 Reverse Power Protection (32R) ................................................................................... 2-24
2.12.17 Undercurrent Protection (37) .......................................................................................... 2-24

2
2.12.18 Breaker Failure Protection (50BF) ................................................................................. 2-25
2.12.19 Switch-on-to-Fault Protection (SOTF)............................................................................ 2-25
2.12.20 Thermal Overload Protection (49) .................................................................................. 2-25
2.12.21 Restricted Earth Fault Protection (64REF) .................................................................... 2-25
2.12.22 Arc Flash Protection ....................................................................................................... 2-26
2.12.23 Current Unbalance Protection (60/50) ........................................................................... 2-26
2.12.24 Voltage Unbalance Protection (60/59) ........................................................................... 2-26
2.12.25 Auto-reclosing (79) ......................................................................................................... 2-26
2.12.26 Another Group of Phase Overcurrent Protection (S2.50/51P)....................................... 2-27
2.12.27 Distance Protection (21L)............................................................................................... 2-27
2.12.28 Transient Overreach ....................................................................................................... 2-27
2.12.29 Fault Locator................................................................................................................... 2-27
2.13 Communication Functions ......................................................................... 2-27

2.13.1 GOOSE ............................................................................................................................ 2-27
2.13.2 SV ..................................................................................................................................... 2-28
PCS-9611S Feeder Relay 2-c

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2-d PCS-9611S Feeder Relay

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2 Technical Data
2.1 Electrical Specifications
“System phase sequence”, which can be set by PCS-Studio, this setting

informs the device of the actual system phase sequence, either ABC or 2
ACB. CT and VT inputs on the device, labelled as A, B and C, must be
connected to system phase A, B and C for correct operation.
2.1.1 AC Current Input
⚫ Conventional AC current input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated current (In) 1A/5A (Settable)
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.05VA/phase @1A, <0.25VA/phase @5A
Number Up to 7 current inputs according to various applications
⚫ AC current input for sensitive earth fault protection or high impedance REF protection
Rated current (In) 1A
Linear to 0.01A~5A
Thermal withstand
-continuously 20A
-for 10s 100A
-for 1s 300A
-for half a cycle 750A
Burden <0.15VA/phase @1A
2.1.2 AC Voltage Input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz

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2 Technical Data
Rated voltage (Un) 100V~130V
Linear to 1V~300V
Thermal withstand Phase-to-ground Phase-to-phase
-continuously 300V 519V
-10s 600V 1038V
2 -1s 660V 1141V
Burden at rated <0.10VA/phase @100V
Number Up to 7 voltage inputs according to various applications
2.1.3 Power Supply
100Vac/110Vac/115Vac
110Vdc/125Vdc 24Vdc/30Vdc
Rated voltage 120Vac/127Vac/220Vac
220Vdc/250Vdc 48Vdc/60Vdc
230Vac/240Vac/250Vac
IEC 61000-4-11:2017
Permissible voltage range IEC 61000-4-29:2000
88~300Vdc 80~275Vac 18~72Vdc
IEC 60255-26:2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage
Quiescent condition <15W (Default hardware configuration)
Additional for each

0.25W ~ 0.35W
energized SFP
Quiescent condition: <1W
For BI modules with high power

binary inputs (Binary inputs which
provide settable conducting mode
by high power with constant
current drain):
Burden
0.014W @24Vdc
Additional for each BI
0.031W @48Vdc
Additional for each energized
module
0.096W @110Vdc
binary input
0.115W @125Vdc
0.27W @220Vdc
0.33W @250Vdc
For BI modules without high

power binary inputs:
0.004W @24Vdc

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2 Technical Data
0.015W @48Vdc
0.08W @110Vdc
0.106W @125Vdc
0.32W @220Vdc
0.41W @250Vdc
Additional for each BO Quiescent condition: <0.1W 2

module Additional for each energized relay: <0.44W
Additional module for SV

<7W
sampling
2.1.4 DC Analogue Output
Standard IEC 60255-1:2009
Input range 0~10V or 0~20mA
Accuracy 0.1%
2.1.5 Binary Input
Settable pickup voltage and dropout voltage
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA
On value (Default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc
Off value (Default set) <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (1 min)
Up to 34 (6U, 1/3 × 19", ring ferrule), 41 (6U, 1/3 × 19", pin ferrule), 84
Number (6U, 1/2 × 19", ring ferrule) or 105 (6U, 1/2 × 19", pin ferrule) binary
inputs according to various hardware configurations
Settable pickup voltage and dropout voltage which supports high-power binary input
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.86mA 0.92mA 1.23mA 1.33mA
On value (Default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc
Off value (Default set) <55Vdc <62.5Vdc <110Vdc <125Vdc

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2
Rated voltage 110Vac 220Vac
Rated current drain 0.73mA 1.47mA
On value (Default set) 69.3~132Vac 138.6~264Vac
Off value (Default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 110Vac 220Vac
On value (Default set) 69.3~132Vac 138.6~264Vac
Off value (Default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 24Vdc 48Vdc
On value (Default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (Default set) <12Vdc <24Vdc

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2
Rated voltage 24Vdc 48Vdc
On value (Default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (Default set) <12Vdc <24Vdc
2.1.6 Binary Output
Tripping/signalling contact
Output mode Potential free contact
Maximum system voltage 250Vac, 300Vdc
Continuous carry 10A
Pickup time (Typical value) <5ms
Drop-off time (Resistive load) <6ms
0.5A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
0.5A@48Vdc
0.35A@110Vdc
Cyclic capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc
0.15A@250Vdc

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2 Technical Data
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
2 outputs according to various hardware configurations
Heavy-capacity tripping contact
Output mode Potential free contact
MOV Protection (Maximum voltage) 350Vdc, 275Vac
Continuous carry 10A
Pickup time (Typical value) <1ms
Drop-out time (Resistive load) <10ms
10A@48V L/R=40ms
10A@110V L/R=40ms
Breaking capacity 10A@125V L/R=40ms
10A@220V L/R=20ms
10A@250V L/R=20ms
10A@48V L/R=40ms
Cyclic Capacity (4cycles in 1 second, 10A@110V L/R=40ms
followed by 2 minutes idle for thermal 10A@125V L/R=40ms
dissipation) 10A@220V L/R=20ms
10A@250V L/R=20ms
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Up to 4 (6U, 1/3 × 19", ring ferrule) or 12 (6U, 1/2 × 19", ring ferrule)
Number heavy-capacity binary outputs according to various hardware
configurations
2.2 Mechanical Specifications
Chassis color Silver grey
Approx. 8.66kg (6U, 1/2 × 19")

Weight per device
Approx. 6.93kg (6U, 1/3 × 19")

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2 Technical Data
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection Class
Standard IEC 60529-2013
IP52 2
Front side IP54 (valid for surface mounting mode of 6U, 1/3 × 19" or 6U, 1/2 × 19"
case with sealing strip)
Other sides IP50
Rear side, connection terminals IP20
2.3 Ambient Temperature and Humidity Range
-40°C to +80°C (Readability of display may be impaired below -20°C

Operating temperature
and above 70°C)
Transport and storage temperature

-40°C to +80°C
range
Permissible humidity 5%~95%, without condensation
Pollution degree Ⅱ
Altitude <3000m
2.4 Communication Port
2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997 or Modbus
Maximum capacity 32
Maximum transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port
Connector type RJ-45
Transmission standard 100Base-TX

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2 Technical Data
Max. transmission distance 100m
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
Connector type LC
2 Fiber type Multi mode
Wave length 1310nm
Transmission standard 100Base-FX
Max. transmission distance 2km
Min. transmission power 50μm: -24dBm 62.5μm: -20dBm
Min. receiving power -31dBm
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
2.4.3 Optical Fiber Port
For Process Level
Characteristics Glass optical fiber
Connector type LC
Fiber type Multi mode
Transmission standard 100Base-FX
Max. transmission distance 2km
Wave length 1310nm/850nm
Min. transmission power -20dBm
Min. receiving power -31dBm
For Arc-Flash Sensor
Characteristics Glass optical fiber
Connector type ST
Sensor type Point sensor
Operating temperature -40°C ~ +70°C
Optical fiber length Optional: 10m, 20m or 30m (Default: 10m)
Minimum permissible bend radius 15mm
Wave length 350nm~1100nm
Sensor spectral response 300~400nm
Sensor optical viewing angle 0°~180°

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2 Technical Data
Sensor effective optical diameter 8mm
Sensor base material Stainless steel or zinc alloy
Sensor window material UV glass
Sensor size φ10*30mm
Fiber material PMMA
Fiber diameter 1.0mm (Core diameter) 2

Cable diameter 2.2mm
Fiber loss ≤0.2dB/m
Tensile strength 70N
Bending radius ≥30mm
2.4.4 Print Port
Type RS-232
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
2.4.5 Clock Synchronization Port
Type RS-485 serial port
Input Demodulated IRIG-B or PPS
Nominal voltage 5Vdc±10%
Maximum voltage 5.5Vdc
Input impedance 2.5kΩ
Isolation 500Vdc
Type BNC port (Female connector)
Input Demodulated IRIG-B or PPS
Nominal voltage 5Vdc±10%
Maximum voltage 5.5Vdc
Characteristic impedance 50Ω
Isolation 500Vdc

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2 Technical Data
2.5 Type Tests
2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007

2 Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration IEC 60255-21-1:1988 Class Ⅱ
Shock IEC 60255-21-2:1988 Class Ⅱ
Bump IEC 60255-21-2:1988 Class Ⅰ
Seismic IEC 60255-21-3:1988 Class Ⅱ
2.5.3 Electrical Tests
Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 61000-4-2:2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radiated amplitude-modulated
Radio frequency interference tests 10V/m (rms), f=80~1000MHz, 1400~2700MHz
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Fast transient disturbance tests IEC 60255-26:2013

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2 Technical Data
Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-26:2013
Power supply, AC input, I/O port: class Ⅳ, 1.2/50μs

Surge immunity test
Common mode: 4kV
Differential mode: 2kV 2

IEC 60255-26:2013
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ, 10V (rms), 150
Conducted RF electromagnetic
kHz~80MHz
disturbance
Spot frequency
10V (rms), f=27MHz/68MHz
Power frequency magnetic field IEC 61000-4-8: 2009
immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2016
Pulse magnetic field immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2016
immunity class Ⅴ, 100kHz & 1MHz–100A/m
IEC 60255-26:2013
Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average
0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average
IEC 60255-26:2013
30MHz~230MHz: 40dB (μV/m) quasi peak @10m,
50dB (μV/m) quasi peak @3m

Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,
Radiated emission 57dB (μV/m) quasi peak @3m
1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)
peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)
peak @3m
Auxiliary power supply performance IEC 60255-26:2013
- Voltage dips Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions 50ms for interruption without rebooting (typical configuration)

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2 Technical Data
2.6 Certifications
⚫ ISO9001:2015
⚫ ISO14001:2015
⚫ ISO45001:2018
2
⚫ ISO/IEC27001:2013
⚫ CMMI L5
⚫ EMC: 2014/30/EU, EN60255-26:2013
⚫ Products safety (LVD): 2014/35/EU, EN60255-27:2014
⚫ BS EN 50419:2006 (Directive 2012/19/EU (WEEE));
⚫ RoHS directive 2011/65/EU;
⚫ RoHS directive (EU) 2015/863;
⚫ IEC 61850: Edition 2, Parts 6, 7-1, 7-2, 7-3,7-4 and 8-1
⚫ IEC 61850: Edition 2, GOOSE Performance Class P1 (3ms)
⚫ IEEE 1588: IEEE Std C37.238TM-2017
⚫ DNP: DNP 3.0
⚫ PRP: IEC 62439-3 Ed.3 (IS 2016)
⚫ HSR: IEC 62439-3 Ed.3 (IS 2016)
2.7 Liquid Crystal Display (LCD)
Type Resolution
Large size (6U 1/2 × 19" case) 320x240 pixels
Small size (6U 1/3 × 19" case) 240x160 pixels
2.8 Terminals
2.8.1 Ring Ferrule
Connection Type Wire Size Screw Type Torque
AC current Screw terminals, 1.5~4mm2 lead M4 1.6~1.8 N⋅m
AC voltage Screw terminals, 0.8~4mm2 lead M4 1.6~1.8 N⋅m
Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N⋅m

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Contact I/O Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N⋅m
Grounding (Earthing) connection BVR type, 0.8~4mm2 lead M3 0.6~0.8 N⋅m
2.8.2 Pin Ferrule
Connection Type Wire Size Screw Type Torque
Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N⋅m

2
Contact I/O Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N⋅m
2.9 Measurement Scope and Accuracy
Item Range Accuracy
±0.2°at 0.2×In＜I＜4.0×In
Phase range 0°~360°
±0.5°at 0.1×In＜I＜0.2×In
Frequency fn±5Hz Max. 0.002Hz
±0.2% of I at 0.2×In＜I＜4.0×In
Current 0.06~4.00In
±0.6% of I at 0.06×In＜I＜0.2×In
Voltage 5~300V 0.2% of U at 5V<U<300V
±0.5% of P, @Un, at 0.1×In＜I＜4.0×In

Active power (W) 0.06~4.00In
±1% of P, @Un, at 0.06×In＜I＜0.1×In
±0.5% of Q, @Un, at 0.1×In＜I＜4.0×In

Reactive power (VAr) 0.06~4.00In
±1% of Q, @Un, at 0.06×In＜I＜0.1×In
±0.5% of S, @Un, at 0.1×In＜I＜4.0×In

Apparent power (VA) 0.06~4.00In
±1% of S, @Un, at 0.06×In＜I＜0.1×In
±0.5% of Wh, @Un, at 0.1×In＜I＜4.0×In

Energy (Wh) 0.06~4.00In
±1% of Wh, @Un, at 0.06×In＜I＜0.1×In
±0.5% of VArh, @Un, at 0.1×In＜I＜4.0×In

Energy (VAh) 0.06~4.00In
±1% of VArh, @Un, at 0.06×In＜I＜0.1×In
2.10 Synchrophasor Measurement
2.10.1 Synchrophasor Measurement under Steady-state
P Class TVE Limit M Class TVE Limit

Influence Reference
Max Max
Quantity Condition Range Range
TVE (%) TVE (%)
Frequency range fn (50Hz, 60Hz) ± 2.0Hz 0.5 ± 5.0Hz for Fs ≥ 25 0.5

Date: 2021-08-01
2 Technical Data
Voltage 80% to 120%

100% rated 0.5 10% to 120% rated 0.5
magnitude rated
Current 10% to 200%

100% rated 0.5 10% to 200% rated 0.5
magnitude rated
Phase angle | fin – f0 | < 0.25Hz ±π radians 0.5 ±π radians 0.5
2 Harmonic 1%, each

10%, each harmonic up
distortion < 0.2% (THD) harmonic up to 1 1
to 50th
(single harmonic) 50th
Out-of-band < 0.2% of input 10% of input signal

None None 1.3
interference signal magnitude magnitude for Fs ≥ 10.
2.10.2 Frequency and ROCOF Measurement under Steady-state
P Class Error Limit M Class Error Limit

Influence Quantity Reference Condition
Max FE Max RFE Max FE Max RFE
Range: f0 ± 2.0 Range: ± 5.0 Hz for Fs ≥ 25

Signal frequency Frequency = fn
0.005Hz 0.4Hz/s 0.005Hz 0.1Hz/s
1% each harmonic up to
Harmonic distortion < 0.2% (THD) 10% each harmonic up to 50th
50th
(single harmonic) Fs > 20
0.005Hz 0.4Hz/s 0.025Hz 6Hz/s
Interfering signal 10% of signal

Out-of-band <0.2% of input signal No requirements
magnitude
interference magnitude
None None 0.01Hz 0.1Hz/s
2.10.3 Active and Reactive Power Measurement under Steady-state

Influence Reference
Max Err Max
(%) Err (%)
Frequency range fn (50Hz, 60Hz) ± 2.0Hz 1 ± 5.0Hz for Fs ≥ 25 1
Voltage 80% to 120%

100% rated 1 10% to 120% rated 1
magnitude rated
Current 10% to 200%

100% rated 1 10% to 200% rated 1
magnitude rated
Phase angle | fin – f0 | < 0.25Hz ±π radians 1 ±π radians 1
Harmonic 1%, each 10%, each harmonic up

< 0.2% (THD) 1 1
distortion harmonic up to to 50th

Date: 2021-08-01
2 Technical Data

Influence Reference
Max Err Max
(%) Err (%)
(single harmonic) 50th
Out-of-band < 0.2% of input 10% of input signal

None None 1.5
interference signal magnitude magnitude for Fs ≥ 10. 2
2.10.4 Synchrophasor Measurement under Modulation
P Class TVE Limit M Class TVE Limit

Modulation
Reference Condition Max Max
Level Range Range
TVE TVE
kx = 0.1, 100% rated signal

3% 3%
ka = 0 radian magnitude, f nominal
Modulation frequency 0.1 Modulation frequency
kx = 0,
100% rated signal to less of Fs/10 or 2Hz 0.1 to less of Fs/5 or 5Hz
ka = 0.1 3% 3%
magnitude, f nominal
radian
2.10.5 Frequency and ROCOF Measurement under Modulation
P Class M Class
Modulation Level Reference Condition
Max FE Max RFE Max FE Max RFE
kx = 0.1, ka = 0 radian 100% rated signal magnitude, f nominal 0.06Hz 3Hz/s 0.3Hz 30Hz/s
kx = 0, ka = 0.1 radian 100% rated signal magnitude, f nominal 0.06Hz 3Hz/s 0.3Hz 30Hz/s
2.10.6 Synchrophasor Measurement under Frequency Ramp
TVE Limit
Test Signal Reference Condition
Ramp Rate PMU Class Ramp Range Max TVE
P class ± 2Hz 1%
Linear frequency 100% rated signal
± 1.0Hz/s Less of ± (Fs/5) or ±
ramp magnitude, f nominal M class 1%
5Hz
2.10.7 Frequency and ROCOF Measurement under Frequency Ramp
Reference
Test Signal Transition Time Error Requirements for Compliance
Condition
100% rated signal ± 2/Fs for the P class M class
Ramp tests magnitude and 0 start and end of Max FE Max RFE Max FE Max RFE
radian base angle ramp 0.01Hz 0.4Hz/s 0.01Hz 0.2Hz/s

Date: 2021-08-01
2 Technical Data
2.10.8 Synchrophasor Measurement under Step Change
P class M class
Step Change Reference |Delay Max |Delay Max

Response Response
Specification Condition time| Overshoot / time| Overshoot /
Time (s) Time (s)
(s) Undershoot (s) Undershoot
2 All test
Magnitude ±
conditions
10% 1/(4 5% of step 1/(4 10% of step
nominal at 2/f0 7/Fs
kx = ± 0.1 ×Fs) magnitude ×Fs) magnitude
start or end of
ka = 0
step
All test
Angle ± 10° conditions

1/(4 5% of step 1/(4 10% of step
kx = 0 nominal at 2/f0 7/Fs
×Fs) magnitude ×Fs) magnitude
ka = ± π/18 start or end of
step
2.10.9 Frequency and ROCOF Measurement under Step Change
P Class M Class
Step Change Reference Frequency ROCOF Frequency ROCOF
Specification Condition Response Response Response Response
Time Time Time Time
All test conditions

Greater of
Magnitude step nominal at start or 5/f0 6/f0 14/f0
14/f0 or 14/Fs
end of step
All test conditions

Greater of
Phase step nominal at start or 5/f0 6/f0 14/f0
14/f0 or 14/Fs
end of step
2.10.10 Measurement Reporting Latency
Performance class Maximum Measurement Reporting Latency (s)
P class 2/Fs
M class 7/Fs

Date: 2021-08-01
2 Technical Data
2.10.11 Synchrophasor Communication
Item Data
100/50/25fps @ 50Hz
Output rate
120/60/30/20/15/12/10fps @ 60Hz
Supported protocol TCP, TCP-UDP, UDP(Unicast/Broadcast/Multicast)

2
Supported client number Max. 4 PDCs
2.11 Management Function
2.11.1 Control Performance
Control mode Local or remote
Response time of local control ≤1s
Response time of remote control ≤3s
2.11.2 Clock Performance
Real time clock accuracy ≤1s/day
Accuracy of GPS synchronization ≤1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.11.3 Fault and Disturbance Recording
Settable pre-disturbance, post-disturbance and maximum recorded

Duration & Recording position
duration
Sampling rate Up to 9.6kHz
2.11.4 Binary Input Signal
Resolution of binary input signal ≤1ms
Binary input mode Potential-free contact
2.12 Protective Functions
2.12.1 Phase Overcurrent Protection (50/51P)
Without direction controlled element
Pickup current 1.0×Setting
Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater

Date: 2021-08-01
2 Technical Data
Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater
Pickup time ≤25ms (at 2 times current setting)
Operating time delay accuracy

≤1%×Setting or 25ms (at 2 times current setting)
(Definite-time characteristics)
2 Operating time delay accuracy

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
(Inverse-time characteristics)
Drop-out time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics)
Drop-out time accuracy (Inverse-time

≤5% of calculated value or 30ms
characteristics)
Drop-out ratio 0.95
With direction controlled element

characteristics)
characteristics)
Drop-out ratio 0.95
Phase angel accuracy ≤3°
2.12.2 Earth Fault Protection (50/51G)

Date: 2021-08-01
2 Technical Data

characteristics)
2
characteristics)
Drop-out ratio 0.95

characteristics)
characteristics)
Drop-out ratio 0.95
2.12.3 Another Group of Earth Fault Overcurrent Protection

characteristics)

Date: 2021-08-01
2 Technical Data

characteristics)
Drop-out ratio 0.95
2.12.4 Negative-sequence Overcurrent Protection (50/51Q)
2 Without direction controlled element

characteristics)
characteristics)
Drop-out ratio 0.95

characteristics)
characteristics)
Drop-out ratio 0.95

Date: 2021-08-01
2 Technical Data
2.12.5 Broken Conductor Protection (46BC)
Current setting Accuracy ≤1%×Setting or 0.01In, whichever is greater
Operating time delay accuracy ≤1%×Setting or 30ms (at 2 times current setting)
Dropout ratio 0.97 2

2.12.6 Sensitive Earth Fault Protection (50/51SEF)
Current setting accuracy ≤0.5%×Setting or 1mA, whichever is greater

Operating time delay accuracy ≤5% of calculated value + 0.5% current tolerance or 35ms
(Inverse-time characteristics) (1.2≤I/Ip≤30)

characteristics)
characteristics)
Drop-out ratio 0.95
Current setting accuracy ≤0.5%×Setting or 1mA, whichever is greater

Operating time delay accuracy ≤5% of calculated value + 0.5% current tolerance or 35ms
(Inverse-time characteristics) (1.2≤I/Ip≤30)

characteristics)
characteristics)

Date: 2021-08-01
2 Technical Data
Drop-out ratio 0.95
2.12.7 RMS Overcurrent Protection (50/51R)

2 Current setting accuracy ≤2.5%×Setting or 0.01In, whichever is greater
Drop-out time accuracy ≤1%×Setting or 30ms
Drop-out ratio 0.95
2.12.8 Phase Overvoltage Protection (59P)
Pickup voltage 1.0×Setting
Pickup time ≤35ms (at 1.1 times voltage setting)

≤1%×Setting or 35ms (at 1.1 times voltage setting)
Operating time accuracy
≤5% of calculated value + 1% voltage tolerance or 40ms (1.1≤U/Up≤2)
Drop-out ratio Settable 0.93~1.00, default value: 0.98
2.12.9 Residual Overvoltage Protection (59G)
Operating time delay accuracy ≤1%×Setting or 35ms (at 1.1 times voltage setting)
2.12.10 Negative-sequence Overvoltage Protection (59Q)

Date: 2021-08-01
2 Technical Data
2.12.11 Positive-sequence Overvoltage Protection (59Pos) 2

2.12.12 Phase Undervoltage Protection (27P)

≤1%×Setting or 35ms (at 0.9 times voltage setting)
Operating time accuracy
≤5% of calculated value + 1% voltage tolerance or 50ms (U/Up≤0.9)
2.12.13 Overfrequency Protection (81O)
Pickup frequency 1.0×Setting
Frequency setting accuracy ≤ 0.01Hz
Pickup time ≤70ms
Time delay accuracy ≤1%×Setting+70ms
Drop-out time accuracy ≤40ms
Drop-out frequency 1.0×Setting

Date: 2021-08-01
2 Technical Data
2.12.14 Underfrequency Protection (81U)
Frequency setting accuracy ≤ 0.01Hz
Pickup time ≤70ms
2 Time delay accuracy ≤1%×Setting+70ms
2.12.15 Frequency Rate-of-change Protection (81R)
Frequency rate-of-change setting

≤ 0.02Hz
accuracy
Data window 4 cycles
Pickup time ≤70ms
Time delay accuracy ≤1%×Setting+70ms
2.12.16 Reverse Power Protection (32R)
Pickup power 1.0×Setting
Power setting accuracy ≤2%×Setting or 0.01pu, whichever is greater
Current setting accuracy ≤1%×Setting or 0.01pu, whichever is greater
Pickup time ≤30ms (at 2 times power setting)
Operating time delay accuracy ≤1%×Setting or 30ms (at 2 times power setting)
Drop-out ratio 0.95
2.12.17 Undercurrent Protection (37)

Date: 2021-08-01
2 Technical Data
Pickup time ≤30ms (at 0.5 times current setting)
Operating time delay accuracy ≤1%×Setting or 30ms (at 0.5 times current setting)
Drop-out ratio 1.1
2.12.18 Breaker Failure Protection (50BF) 2

Drop-out time <20ms (at 2 times current setting)
Drop-out ratio 0.95
2.12.19 Switch-on-to-Fault Protection (SOTF)
Pickup time accuracy ≤30ms (at 2 times current setting)
Drop-out time ≤30ms
0.98 (phase overcurrent SOTF protection)

Drop-out ratio
0.97 (earth fault overcurrent SOTF)
2.12.20 Thermal Overload Protection (49)
≤2.5% of operating time or 30ms, whichever is greater (for current

Operating time
between 1.2 and 20 multiples of pickup)
Reset time ≤30ms
2.12.21 Restricted Earth Fault Protection (64REF)
Tolerance of operating current ≤5% of operating current or 0.02×In, whichever is greater
Dropout ratio ≥95%

Date: 2021-08-01
2 Technical Data
Operating time (without time delay, 50Hz: ≤30ms (3I0d>2 times current setting, internal fault)
without blocking criterion) 60Hz: ≤25ms (3I0d>2 times current setting, internal fault)
Tolerance of time setting ≤1% of setting +30ms (3I0d>2 times current setting)
Dropout time ≤30ms

2
2.12.22 Arc Flash Protection
Tolerance of current setting ≤1%×Setting or 0.01In, whichever is greater

Tolerance of time setting ≤ 1%×Setting + 10ms (at 1.5 times current setting)
2.12.23 Current Unbalance Protection (60/50)
Drop-out ratio 0.95
2.12.24 Voltage Unbalance Protection (60/59)
Drop-out ratio 0.95
2.12.25 Auto-reclosing (79)
Phase angel accuracy (synchronism

≤2°
check)
Voltage setting accuracy
≤1%×Setting or 0.1V, whichever is greater
(synchronism check)
Frequency setting accuracy
0.01Hz
(synchronism check)
Time delay accuracy (synchronism
≤1%×Setting+20ms
check)

Date: 2021-08-01
2 Technical Data
Time delay accuracy (Reclaim) ≤1%×Setting+20ms
Time delay accuracy (Reclosing) ≤1%×Setting+20ms
2.12.26 Another Group of Phase Overcurrent Protection (S2.50/51P)

2

characteristics)
characteristics)
Drop-out ratio 0.95
2.12.27 Distance Protection (21L)
Impedance setting accuracy ≤2.5%×Setting or 0.1Ω, whichever is greater
Resetting ratio 1.05
Operating time accuracy ≤1%×Setting+30ms
≤5% (SIR≤30)
Transient overreaching
≤10% (SIR≥30)
2.12.28 Transient Overreach
Accuracy for all high-speed protection ≤2%
2.12.29 Fault Locator
Accuracy for multi-phase faults with < ±2.5%

single end feed
Tolerance will be higher in case of single-phase fault with high ground resistance.
2.13 Communication Functions

2.13.1 GOOSE
Receiving Control Block (RCB) Max. 64 (Typical configuration: 50×FCD+200×BOOL+16×FLOAT)

Date: 2021-08-01
2 Technical Data
Sending Control Block (SCB) Max. 16 (Typical configuration: 100×BOOL)
Receiving route delay Max. 2ms
Sending route delay Max. 3ms
2 The capacity of GOOSE receiving and sending is determined by the

number of configured boards and control & protection functions.
2.13.2 SV
Receiving Control Block (RCB) Max. 12
Receiving route delay Max. 2ms
The capacity of SV receiving is determined by the number of configured

boards and control & protection functions.

Date: 2021-08-01
Table of Contents
3.1 Three-phase Current Element (TCUR3P) ....................................................... 3-1

3.1.1 Function Description............................................................................................................. 3-1
3.1.2 Function Block Diagram ....................................................................................................... 3-2
3.1.3 I/O Signals ............................................................................................................................ 3-2 3

3.1.4 Settings ................................................................................................................................. 3-3
3.2 Three-phase Voltage Element (TVOL3P)........................................................ 3-3

3.2.3 I/O Signals ............................................................................................................................ 3-4
3.2.4 Settings ................................................................................................................................. 3-5
3.3 One-phase Current Element (TCUR1P).......................................................... 3-5

3.3.3 I/O Signals ............................................................................................................................ 3-5
3.3.4 Settings ................................................................................................................................. 3-6
3.4 One-phase Voltage Element (TVOL1P) .......................................................... 3-6

3.4.3 I/O Signals ............................................................................................................................ 3-6
3.4.4 Settings ................................................................................................................................. 3-7
3.5 Three-phase Current Summation Element (TCUR3P_3SD).......................... 3-7

3.5.3 I/O Signals ............................................................................................................................ 3-8
3.6 Phase Overcurrent Protection (50/51P) ......................................................... 3-9


Date: 2021-08-01
3.6.2 Function Block Diagram ..................................................................................................... 3-21
3.6.3 I/O Signal ............................................................................................................................ 3-22
3.6.4 Logic ................................................................................................................................... 3-23
3.6.5 Settings ............................................................................................................................... 3-23
3.7 Earth Fault Overcurrent Protection (50/51G) ............................................... 3-39

3.7.1 Function Description........................................................................................................... 3-39
3 3.7.3 I/O Signal ............................................................................................................................ 3-48
3.7.4 Logic ................................................................................................................................... 3-49
3.7.5 Settings ............................................................................................................................... 3-49
3.8 Another Group of Earth Fault Overcurrent Protection ............................... 3-64

3.8.3 I/O Signal ............................................................................................................................ 3-71
3.8.4 Logic ................................................................................................................................... 3-72
3.8.5 Settings ............................................................................................................................... 3-72
3.9 Negative-sequence Overcurrent Protection (50/51Q) ................................. 3-84

3.9.3 I/O Signal ............................................................................................................................ 3-93
3.9.4 Logic ................................................................................................................................... 3-94
3.9.5 Settings ............................................................................................................................... 3-94
3.10 Broken Conductor Protection (46BC) ........................................................ 3-99

3.10.1 Function Description......................................................................................................... 3-99
3.10.2 Function Block Diagram ................................................................................................. 3-100
3.10.3 I/O Signals ...................................................................................................................... 3-100
3.10.4 Logic ............................................................................................................................... 3-101
3.10.5 Settings........................................................................................................................... 3-101
3.11 Sensitive Earth Fault Protection (50/51SEF) ........................................... 3-101

3.11.1 Function Description ....................................................................................................... 3-102

Date: 2021-08-01
3.11.3 I/O Signal ........................................................................................................................ 3-110
3.11.4 Logic ................................................................................................................................ 3-111
3.11.5 Settings ............................................................................................................................ 3-111
3.11.6 High Impedance Restricted Earth Fault Protection Application ..................................... 3-122
3.12 RMS Overcurrent Protection (50/51R) ...................................................... 3-126

3.12.1 Function Description....................................................................................................... 3-126
3.12.2 Function Block Diagram ................................................................................................. 3-132 3

3.12.3 I/O Signal ........................................................................................................................ 3-132
3.12.4 Logic ............................................................................................................................... 3-133
3.12.5 Settings........................................................................................................................... 3-133
3.13 Phase Overvoltage Protection (59P) ........................................................ 3-137

3.13.3 I/O Signal ........................................................................................................................ 3-142
3.13.4 Logic ............................................................................................................................... 3-143
3.13.5 Settings........................................................................................................................... 3-143
3.14 Residual Overvoltage Protection (59G) ................................................... 3-146

3.14.3 I/O Signal ........................................................................................................................ 3-150
3.14.4 Logic ............................................................................................................................... 3-150
3.14.5 Settings........................................................................................................................... 3-150
3.15 Negative-sequence Overvoltage Protection (59Q) .................................. 3-151

3.15.3 I/O Signals ...................................................................................................................... 3-154
3.15.4 Logic ............................................................................................................................... 3-155
3.15.5 Settings........................................................................................................................... 3-155
3.16 Positive-sequence Overvoltage Protection (59Pos) ............................... 3-156
PCS-9611S Feeder Relay 3-c

Date: 2021-08-01
3.16.3 I/O Signals ...................................................................................................................... 3-159
3.16.4 Logic ............................................................................................................................... 3-159
3.16.5 Settings........................................................................................................................... 3-159
3.17 Phase Undervoltage Protection (27P) ...................................................... 3-160

3 3.17.2 Function Block Diagram ................................................................................................. 3-166
3.17.3 I/O Signal ........................................................................................................................ 3-167
3.17.4 Logic ............................................................................................................................... 3-168
3.17.5 Settings........................................................................................................................... 3-169
3.18 Overfrequency Protection (81O)............................................................... 3-173

3.18.3 I/O Signals ...................................................................................................................... 3-175
3.18.4 Logic ............................................................................................................................... 3-175
3.18.5 Settings........................................................................................................................... 3-175
3.19 Underfrequency Protection (81U)............................................................. 3-177

3.19.3 I/O Signals ...................................................................................................................... 3-179
3.19.4 Logic ............................................................................................................................... 3-180
3.19.5 Settings........................................................................................................................... 3-180
3.20 Frequency Rate-of-change Protection (81R) ........................................... 3-182

3.20.3 I/O Signals ...................................................................................................................... 3-184
3.20.4 Logic ............................................................................................................................... 3-184
3.20.5 Settings........................................................................................................................... 3-185
3.21 Reverse Power Protection (32R) .............................................................. 3-187
3-d PCS-9611S Feeder Relay

Date: 2021-08-01
3.21.3 I/O Signals ...................................................................................................................... 3-189
3.21.4 Logic ............................................................................................................................... 3-190
3.21.5 Settings........................................................................................................................... 3-190
3.22 Cold Load Pickup Logic (CLP) ................................................................. 3-191

3.22.2 Function Block Diagram ................................................................................................. 3-191 3

3.22.3 I/O Signals ...................................................................................................................... 3-191
3.22.4 Logic ............................................................................................................................... 3-192
3.22.5 Settings........................................................................................................................... 3-192
3.23 Undercurrent Protection (37) .................................................................... 3-195

3.23.3 I/O Signals ...................................................................................................................... 3-199
3.23.4 Logic ............................................................................................................................... 3-200
3.23.5 Settings........................................................................................................................... 3-200
3.24 Breaker Failure Protection (50BF) ............................................................ 3-201

3.24.3 I/O Signals ...................................................................................................................... 3-203
3.24.4 Logic ............................................................................................................................... 3-204
3.24.5 Settings........................................................................................................................... 3-205
3.25 Switch-on-to-Fault Protection (SOTF) ...................................................... 3-206

3.25.3 I/O Signals ...................................................................................................................... 3-208
3.25.4 Logic ............................................................................................................................... 3-209
3.25.5 Settings........................................................................................................................... 3-211
3.26 Thermal Overload Protection (49) ............................................................ 3-212
PCS-9611S Feeder Relay 3-e

Date: 2021-08-01
3.26.3 I/O Signals ...................................................................................................................... 3-216
3.26.4 Logic ............................................................................................................................... 3-217
3.26.5 Settings........................................................................................................................... 3-217
3.27 Restricted Earth Fault Protection (64REF) .............................................. 3-218

3 3.27.2 Function Block Diagram ................................................................................................. 3-225
3.27.3 I/O Signals ...................................................................................................................... 3-225
3.27.4 Logic ............................................................................................................................... 3-226
3.27.5 Settings........................................................................................................................... 3-227
3.28 Arc Flash Protection (50L/NL) .................................................................. 3-227

3.28.3 I/O Signals ...................................................................................................................... 3-231
3.28.4 Logic ............................................................................................................................... 3-232
3.28.5 Settings........................................................................................................................... 3-232
3.29 Current Unbalance Protection (60/50) ...................................................... 3-233

3.29.3 I/O Signals ...................................................................................................................... 3-235
3.29.4 Logic ............................................................................................................................... 3-236
3.29.5 Settings........................................................................................................................... 3-236
3.30 Voltage Unbalance Protection (60/59) ...................................................... 3-236

3.30.3 I/O Signals ...................................................................................................................... 3-239
3.30.4 Logic ............................................................................................................................... 3-240
3.30.5 Settings........................................................................................................................... 3-240
3.31 Automatic Reclosure (79).......................................................................... 3-240
3-f PCS-9611S Feeder Relay

Date: 2021-08-01
3.31.3 I/O Signals ...................................................................................................................... 3-250
3.31.4 Settings........................................................................................................................... 3-251
3.32 Another Group of Phase Overcurrent Protection (S2.50/51P) ............... 3-253

3.32.3 I/O Signal ........................................................................................................................ 3-261 3

3.32.4 Logic ............................................................................................................................... 3-262
3.32.5 Settings........................................................................................................................... 3-262
3.33 Distance Protection (21L) ......................................................................... 3-272

3.33.1 Functions Description ..................................................................................................... 3-273
3.33.3 I/O Signals ...................................................................................................................... 3-290
3.33.4 Logic ............................................................................................................................... 3-292
3.33.5 Settings........................................................................................................................... 3-295
3.34 Distance SOTF Protection (21SOTF)........................................................ 3-298

3.34.3 I/O Signals ...................................................................................................................... 3-299
3.34.4 Logic ............................................................................................................................... 3-299
3.34.5 Settings........................................................................................................................... 3-301
3.35 VT Circuit Supervision (VTS) .................................................................... 3-303

3.35.1 General Application ........................................................................................................ 3-303
3.35.3 Function Block ................................................................................................................ 3-304
3.35.4 I/O Signals ...................................................................................................................... 3-304
3.35.5 Logic ............................................................................................................................... 3-304
3.35.6 Settings........................................................................................................................... 3-305
3.36 CT Circuit Supervision (CTS).................................................................... 3-306
PCS-9611S Feeder Relay 3-g

Date: 2021-08-01
3.36.3 I/O Signals ...................................................................................................................... 3-307
3.36.4 Logics ............................................................................................................................. 3-307
3.36.5 Settings........................................................................................................................... 3-307
List of Figures
3 Figure 3.6-1 The enabling and blocking logic of phase overcurrent protection .................. 3-9
Figure 3.6-2 Logic diagram of the fault detector element of phase overcurrent protection3-10
Figure 3.6-3 Logic diagram of the voltage control element of phase overcurrent protection3-11
Figure 3.6-4 The direction element operation characteristics when phase A voltage is
polarized ..................................................................................................................................... 3-12
Figure 3.6-5 Logic diagram of forward and reverse direction element of phase overcurrent
protection ................................................................................................................................... 3-15
Figure 3.6-6 Logic diagram of harmonic control element of phase overcurrent protection3-16
Figure 3.6-7 Definite-time operation characteristic curve of phase overcurrent protection3-17
Figure 3.6-8 Inverse-time operation characteristic curve of phase overcurrent protection3-18
Figure 3.6-9 Definite-time drop-out characteristic of phase overcurrent protection ......... 3-19
Figure 3.6-10 Inverse-time drop-out characteristic curve of phase overcurrent protection3-20
Figure 3.6-11 Inverse-time drop-out characteristic of phase overcurrent protection ....... 3-21
Figure 3.6-12 Logic diagram of phase overcurrent protection ............................................ 3-23
Figure 3.7-1 The enabling and blocking logic of earth fault overcurrent protection ......... 3-40
Figure 3.7-2 Logic diagram of the fault detector element of earth fault overcurrent
protection ................................................................................................................................... 3-40
Figure 3.7-3 The direction element operation characteristics when zero-sequence voltage
is polarized ................................................................................................................................. 3-41
Figure 3.7-4 Logic diagram of forward and reverse direction element of earth fault
overcurrent protection .............................................................................................................. 3-42
Figure 3.7-5 Logic diagram of harmonic control element of earth fault overcurrent
protection ................................................................................................................................... 3-43
Figure 3.7-6 Definite-time operation characteristic curve of earth fault overcurrent

protection ................................................................................................................................... 3-44
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Date: 2021-08-01
Figure 3.7-7 Inverse-time operation characteristic curve of earth fault overcurrent

protection ................................................................................................................................... 3-45
Figure 3.7-8 Definite-time drop-out characteristic of earth fault overcurrent protection.. 3-46
Figure 3.7-9 Inverse-time drop-out characteristic curve of earth fault overcurrent protection
..................................................................................................................................................... 3-47
Figure 3.7-10 Inverse-time drop-out characteristic of earth fault overcurrent protection 3-48
Figure 3.7-11 Logic diagram of earth fault overcurrent protection...................................... 3-49
Figure 3.8-1 The enabling and blocking logic of another group of earth fault overcurrent
protection ................................................................................................................................... 3-65 3
Figure 3.8-2 Logic diagram of the fault detector element of another group of earth fault
Figure 3.8-3 Definite-time operation characteristic curve of another group of earth fault
Figure 3.8-4 Inverse-time operation characteristic curve of another group of earth fault
Figure 3.8-5 Definite-time drop-out characteristic of another group of earth fault

Figure 3.8-6 Inverse-time drop-out characteristic curve of another group of earth fault
Figure 3.8-7 Inverse-time drop-out characteristic of another group of earth fault

Figure 3.8-8 Logic diagram of another group of earth fault overcurrent protection ......... 3-72
Figure 3.9-1 The enabling and blocking logic of negative-sequence overcurrent protection3-85
Figure 3.9-2 Logic diagram of the fault detector element of negative-sequence overcurrent
protection ................................................................................................................................... 3-85
Figure 3.9-3 The direction element operation characteristics of negative-sequence

Figure 3.9-4 Logic diagram of forward and reverse direction element of negative-sequence
Figure 3.9-5 Definite-time operation characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-89
Figure 3.9-6 Inverse-time operation characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-90
Figure 3.9-7 Definite-time drop-out characteristic of negative-sequence overcurrent

protection ................................................................................................................................... 3-91
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Date: 2021-08-01
Figure 3.9-8 Inverse-time drop-out characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-92
Figure 3.9-9 Inverse-time drop-out characteristic of negative-sequence overcurrent

protection ................................................................................................................................... 3-93
Figure 3.9-10 Logic diagram of negative-sequence overcurrent protection ...................... 3-94
Figure 3.10-1 Logic of broken conductor protection .......................................................... 3-101
Figure 3.11-1 The enabling and blocking logic of sensitive earth fault protection.......... 3-102
Figure 3.11-2 Logic diagram of the fault detector element of sensitive earth fault protection3-102
3 Figure 3.11-3 The direction element operation characteristics of sensitive earth fault
protection ................................................................................................................................. 3-103
Figure 3.11-4 Logic diagram of forward and reverse direction element of sensitive earth
fault protection ........................................................................................................................ 3-104
Figure 3.11-5 Definite-time operation characteristic curve of sensitive earth fault protection
................................................................................................................................................... 3-106
Figure 3.11-6 Inverse-time operation characteristic curve of sensitive earth fault protection3-107
Figure 3.11-7 Definite-time drop-out characteristic of sensitive earth fault protection .. 3-108
Figure 3.11-8 Inverse-time drop-out characteristic curve of sensitive earth fault protection3-109
Figure 3.11-9 Inverse-time drop-out characteristic of sensitive earth fault protection ... 3-110
Figure 3.11-10 Logic diagram of sensitive earth fault protection .......................................3-111
Figure 3.12-1 The enabling and blocking logic of RMS overcurrent protection .............. 3-126
Figure 3.12-2 Logic diagram of the fault detector element of RMS overcurrent protection3-127
Figure 3.12-3 Definite-time operation characteristic curve of RMS overcurrent protection3-128
Figure 3.12-4 Inverse-time operation characteristic curve of RMS overcurrent protection3-129
Figure 3.12-5 Definite-time dropout characteristic of RMS overcurrent protection ........ 3-130
Figure 3.12-6 Inverse-time dropout characteristic curve of RMS overcurrent protection3-131
Figure 3.12-7 Inverse-time dropout characteristic of RMS overcurrent protection ......... 3-132
Figure 3.12-8 Logic diagram of RMS overcurrent protection ............................................. 3-133
Figure 3.13-1 The enabling and blocking logic of phase overvoltage protection ............ 3-138
Figure 3.13-2 Logic diagram of the fault detector element of phase overvoltage protection3-138
Figure 3.13-3 Definite-time operation characteristic curve of phase overvoltage protection3-139
Figure 3.13-4 Inverse-time operation characteristic curve of phase overvoltage protection3-140
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Date: 2021-08-01
Figure 3.13-5 Definite-time drop-out characteristic of phase overvoltage protection .... 3-141
Figure 3.13-6 Logic diagram of phase overvoltage protection .......................................... 3-143
Figure 3.14-1 The enabling and blocking logic of residual overvoltage protection ........ 3-147
Figure 3.14-2 Logic diagram of the fault detector element of residual overvoltage
protection ................................................................................................................................. 3-148
Figure 3.14-3 Definite-time operation characteristic curve of residual overvoltage

protection ................................................................................................................................. 3-148
Figure 3.14-4 Definite-time drop-out characteristic of residual overvoltage protection . 3-149
Figure 3.14-5 Logic diagram of residual overvoltage protection ....................................... 3-150

3
Figure 3.15-1 Logic diagram of enabling/disabling negative-sequence overvoltage
protection ................................................................................................................................. 3-152
Figure 3.15-2 Logic diagram of the fault detector of negative-sequence overvoltage

protection ................................................................................................................................. 3-152
Figure 3.15-3 Operation characteristic curve of negative-sequence overvoltage protection3-153
Figure 3.15-4 Definite-time drop-out characteristic of negative-sequence overvoltage

protection ................................................................................................................................. 3-154
Figure 3.15-5 Logic diagram of negative-sequence overvoltage protection .................... 3-155
Figure 3.16-1 Logic diagram of enabling/disabling positive-sequence overvoltage

protection ................................................................................................................................. 3-156
Figure 3.16-2 Logic diagram of the fault detector of positive-sequence overvoltage

protection ................................................................................................................................. 3-157
Figure 3.16-3 Operation characteristic curve of positive-sequence overvoltage protection3-157
Figure 3.16-4 Definite-time drop-out characteristic of positive-sequence overvoltage

protection ................................................................................................................................. 3-158
Figure 3.16-5 Logic diagram of positive-sequence overvoltage protection ..................... 3-159
Figure 3.17-1 The enabling and blocking logic of phase undervoltage protection ......... 3-161
Figure 3.17-2 Logic diagram of the fault detector element of phase undervoltage protection
................................................................................................................................................... 3-163
Figure 3.17-3 Definite-time operation characteristic curve of phase undervoltage protection

................................................................................................................................................... 3-164
Figure 3.17-4 Inverse-time operation characteristic curve of phase undervoltage protection

................................................................................................................................................... 3-165
Figure 3.17-5 Definite-time drop-out characteristic of undervoltage protection ............. 3-166
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Date: 2021-08-01
Figure 3.17-6 Logic diagram of phase undervoltage protection ........................................ 3-168
Figure 3.18-1 Logic diagram of enabling/disabling overfrequency protection ................ 3-173
Figure 3.18-2 Logic diagram of the fault detector of overfrequency protection .............. 3-174
Figure 3.18-3 Operation characteristic curve of overfrequency protection ..................... 3-174
Figure 3.18-4 Logic diagram of overfrequency protection ................................................. 3-175
Figure 3.19-1 Logic diagram of enabling/disabling underfrequency protection .............. 3-178
Figure 3.19-2 Logic diagram of the fault detector of underfrequency protection ............ 3-178
3 Figure 3.19-3 Operation characteristic curve of underfrequency protection ................... 3-179
Figure 3.19-4 Logic diagram of underfrequency protection ............................................... 3-180
Figure 3.20-1 Logic diagram of enabling/disabling frequency rate-of-change protection3-182
Figure 3.20-2 Logic diagram of the fault detector of frequency rate-of-change protection3-183
Figure 3.20-3 Operation characteristic curve of frequency rate-of-change protection ... 3-183
Figure 3.20-4 Logic diagram of frequency rate-of-change protection............................... 3-184
Figure 3.21-1 Logic diagram of enabling/disabling reverse power protection ................ 3-187
Figure 3.21-2 Logic diagram of the fault detector of reverse power protection .............. 3-188
Figure 3.21-3 Operation characteristic curve of reverse power protection ...................... 3-189
Figure 3.21-4 Logic diagram of reverse power protection.................................................. 3-190
Figure 3.22-1 Logic diagram of cold load pickup logic ....................................................... 3-192
Figure 3.23-1 Logic diagram of enabling/disabling undercurrent protection................... 3-196
Figure 3.23-2 Logic diagram of the fault detector of undercurrent protection ................ 3-197
Figure 3.23-3 Operation characteristic curve of undercurrent protection ........................ 3-198
Figure 3.23-4 Logic diagram of undercurrent protection.................................................... 3-200
Figure 3.24-1 Logic of enabling breaker failure protection ................................................ 3-204
Figure 3.24-2 Logic of breaker failure initiating signal abnormality .................................. 3-204
Figure 3.24-3 Logic of current/contact check ...................................................................... 3-204
Figure 3.24-4 Logic of breaker failure protection ................................................................ 3-205
Figure 3.25-1 The enabling and blocking logic of SOTF protection .................................. 3-207
Figure 3.25-2 Logic of auto-reclosing signal........................................................................ 3-209
Figure 3.25-3 Logic of manual closing signal ...................................................................... 3-209
Figure 3.25-4 Logic of phase overcurrent SOTF protection ............................................... 3-210
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Date: 2021-08-01
Figure 3.25-5 Logic of earth fault overcurrent SOTF protection ........................................ 3-210
Figure 3.26-1 The operation characteristic curve of thermal overload protection .......... 3-213
Figure 3.26-2 Logic diagram of enabling/disabling thermal overload protection ............ 3-215
Figure 3.26-3 Logic diagram of the fault detector of thermal overload protection (method 1)
................................................................................................................................................... 3-215
Figure 3.26-4 Logic diagram of thermal overload protection (method 1) ......................... 3-217
Figure 3.27-1 Application for one side of a transformer ..................................................... 3-218
Figure 3.27-2 REF protection principle ................................................................................. 3-220

3
Figure 3.27-3 Operation characteristic of REF protection .................................................. 3-222
Figure 3.27-4 Currents at an external earth fault ................................................................. 3-222
Figure 3.27-5 Currents at an internal earth fault .................................................................. 3-223
Figure 3.27-6 Logic of enabling restricted earth fault protection ...................................... 3-226
Figure 3.27-7 Pickup logic of restricted earth fault protection .......................................... 3-226
Figure 3.27-8 Logic diagram of restricted earth fault protection ....................................... 3-226
Figure 3.28-1 Arc flash sensor diagram ................................................................................ 3-228
Figure 3.28-2 Logic diagram of enabling/disabling arc flash protection .......................... 3-229
Figure 3.28-3 Logic diagram of the arc sensor .................................................................... 3-229
Figure 3.28-4 Logic diagram of the fault detector of arc flash protection ........................ 3-230
Figure 3.28-5 Logic diagram of arc flash protection ........................................................... 3-232
Figure 3.29-1 Application of the current unbalance protection ......................................... 3-233
Figure 3.29-2 Logic diagram of enabling/disabling current unbalance protection .......... 3-234
Figure 3.29-3 Logic diagram of the fault detector of current unbalance protection........ 3-234
Figure 3.29-4 Operation characteristic curve of current unbalance protection ............... 3-235
Figure 3.29-5 Logic diagram of current unbalance protection........................................... 3-236
Figure 3.30-1 Application of the voltage unbalance protection ......................................... 3-237
Figure 3.30-2 Logic diagram of enabling/disabling voltage unbalance protection ......... 3-238
Figure 3.30-3 Logic diagram of the fault detector of voltage unbalance protection ....... 3-238
Figure 3.30-4 Operation characteristic curve of voltage unbalance protection ............... 3-239
Figure 3.30-5 Logic diagram of voltage unbalance protection .......................................... 3-240
Figure 3.31-1 Logic of enabling AR ....................................................................................... 3-241
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Date: 2021-08-01
Figure 3.31-2 Logic of synchronism check mode selection for AR ................................... 3-242
Figure 3.31-3 Logic of AR block............................................................................................. 3-243
Figure 3.31-4 Logic of AR ready ............................................................................................ 3-244
Figure 3.31-5 Tripping initiating AR ....................................................................................... 3-244
Figure 3.31-6 CB state initiating AR ...................................................................................... 3-245
Figure 3.31-7 One-shot AR ..................................................................................................... 3-245
Figure 3.31-8 Reclosing output logic .................................................................................... 3-246
3 Figure 3.31-9 Reclosing failure and success ....................................................................... 3-247
Figure 3.31-10 Transient fault................................................................................................. 3-248
Figure 3.31-11 Permanent fault ([79.Num]=2) ....................................................................... 3-249
Figure 3.32-1 The enabling and blocking logic of another group of phase overcurrent
protection ................................................................................................................................. 3-254
Figure 3.32-2 Logic diagram of the fault detector element of another group of phase
overcurrent protection ............................................................................................................ 3-254
Figure 3.32-3 Definite-time operation characteristic curve of another group of phase

Figure 3.32-4 Inverse-time operation characteristic curve of another group of phase

Figure 3.32-5 Definite-time drop-out characteristic of another group of phase overcurrent

protection ................................................................................................................................. 3-258
Figure 3.32-6 Inverse-time drop-out characteristic curve of another group of phase

Figure 3.32-7 Inverse-time drop-out characteristic of another group of phase overcurrent

protection ................................................................................................................................. 3-260
Figure 3.32-8 Logic diagram of another group of phase overcurrent protection ............ 3-262
Figure 3.33-1 Quadrilateral forward direction distance element ........................................ 3-276
Figure 3.33-2 Quadrilateral reverse direction distance element ........................................ 3-276
Figure 3.33-3 Quadrilateral non direction distance element .............................................. 3-276
Figure 3.33-4 Shift impedance characteristics of forward direction ................................. 3-277
Figure 3.33-5 Shift impedance characteristics of reverse direction .................................. 3-278
Figure 3.33-6 Mho forward direction distance element....................................................... 3-279
Figure 3.33-7 Mho reverse direction distance element ....................................................... 3-280
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Date: 2021-08-01
Figure 3.33-8 Mho non direction distance element ............................................................. 3-280
Figure 3.33-9 Phase-to-ground operating characteristics for forward fault ..................... 3-281
Figure 3.33-10 Phase-to-phase operating characteristics for forward fault ..................... 3-281
Figure 3.33-11 Operating characteristics for reverse fault ................................................. 3-282
Figure 3.33-12 Operating characteristics of three-phase close-in fault ............................ 3-282
Figure 3.33-13 Operating characteristics of three-phase close-in fault ............................ 3-283
Figure 3.33-14 Phase-to-phase mutual inductance ............................................................. 3-283
Figure 3.33-15 Zero-sequence mutual inductance for double-circuit lines ...................... 3-284 3
Figure 3.33-16 Distance element with load encroachment ................................................. 3-285
Figure 3.33-17 Faulty phase selection based on I0 and I2A ................................................. 3-289
Figure 3.33-18 Logic of fault detector ................................................................................... 3-292
Figure 3.33-19 Logic of enabling distance protection (x=1~4) ........................................... 3-292
Figure 3.33-20 Logic of distance protection (phase-to-ground, x=1~4) ............................ 3-293
Figure 3.33-21 Logic of distance protection (phase-to-phase, x=1~4) .............................. 3-294
Figure 3.33-22 Logic of distance protection operating (zone x, x=1~4) ............................ 3-294
Figure 3.33-23 Logic of PSBR (x=1~4) .................................................................................. 3-295
Figure 3.34-1 Logic of enabling distance SOTF protection ................................................ 3-299
Figure 3.34-2 Logic of manual closing signal ...................................................................... 3-300
Figure 3.34-3 Logic of auto-reclosing signal........................................................................ 3-300
Figure 3.34-4 Logic of distance SOTF protection by manual closing signal.................... 3-301
Figure 3.34-5 Logic of distance SOTF protection by 3-pole AR ......................................... 3-301
Figure 3.34-6 Logic of distance SOTF protection ................................................................ 3-301
Figure 3.35-1 VT circuit supervision logic diagram............................................................. 3-304
Figure 3.36-1 Logic of CT circuit failure................................................................................ 3-307
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Date: 2021-08-01
3-p PCS-9611S Feeder Relay

Date: 2021-08-01
3.1 Three-phase Current Element (TCUR3P)
Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phase angles of three phase currents, etc. All
calculated information of three-phase current element is used for protection logic calculation.
Three-phase current element is a basic element, for a specific application,

the displayed signals and settings may have different prefixes in front of
them.
3
3.1.1 Function Description
Three-phase current element has following functions:
1. Pre-process three phase currents
2. Calculate information related to three-phase current
When any phase current is greater than 0.04In, the input current signals are valid and the valid
signal will be outputted for programmable logic application.
CT circuit supervision of three-phase current is carried out by the CTS element, which can refer to
Section 3.36 for details.

Date: 2021-08-01
3.1.2 Function Block Diagram
TCUR3P
in_ia I3P
in_ib Ia_Sec
in_ic Ib_Sec
Ic_Sec
I1_Sec
3 I2_Sec
3I0_Cal_Sec
Ang(Ia-Ib)
Ang(Ib-Ic)
Ang(Ic-Ia)
Ang(Ia)
Ang(Ib)
Ang(Ic)
Ang(3I0_Cal)
Alm_CTS
Flg_OnLoad
3.1.3 I/O Signals
No. Input Signal Description

1 in_ia Sampled value of phase-A current
2 in_ib Sampled value of phase-B current
3 in_ic Sampled value of phase-C current
No. Output Signal Description
1 I3P A current data set
2 Ia_Sec Amplitude of secondary phase-A current
3 Ib_Sec Amplitude of secondary phase-B current
4 Ic_Sec Amplitude of secondary phase-C current
5 I1_Sec Amplitude of secondary positive-sequence current
6 I2_Sec Amplitude of secondary negative-sequence current
7 3I0_Cal_Sec Amplitude of calculated secondary residual current
8 Ang(Ia-Ib) Phase angle between phase A and phase B currents
9 Ang(Ib-Ic) Phase angle between phase B and phase C currents
10 Ang(Ic-Ia) Phase angle between phase C and phase A currents
11 Ang(Ia) Phase angle of phase-A current

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12 Ang(Ib) Phase angle of phase-B current

13 Ang(Ic) Phase angle of phase-C current
14 Ang(3I0_Cal) Phase angle of calculated residual current
15 Alm_CTS CT secondary circuit failure
16 Flg_OnLoad A flag indicating that the load current is detected
3.1.4 Settings
Access path: MainMenu  Settings  Global Settings  System Settings
No. Item Range Step Unit Default Description

1
2
Prot.I1n
Prot.I2n
0~9999
1 or 5
1
-
A
A
1000
1
Primary current value of the three-phase CT
Secondary current value of the three-phase CT
3
Enabled, Logic setting of enabling/disabling the current
3 Prot.En_RevCT - - Disabled
Disabled polarity of the three-phase CT reversed
3.2 Three-phase Voltage Element (TVOL3P)
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.
Three-phase voltage element has following functions:
1. Pre-process three phase voltages
2. Calculate information related to three phase voltages
VT circuit failure supervision of three-phase voltage is carried out by the VTS element, which can
refer to Section 3.32 for details.

Date: 2021-08-01
TVOL3P
in_ua U3P
in_ub Ua_Sec
in_uc Ub_Sec
BI_En_VT Uc_Sec
U1_Sec
3 U2_Sec
3U0_Cal_Sec
Ang(Ua-Ub)
Ang(Ub-Uc)
Ang(Uc-Ua)
Ang(Ua)
Ang(Ub)
Ang(Uc)
Ang(3U0_Cal)
Alm_VTS
3.2.3 I/O Signals
No. Input signal Description

1 in_ua Sampled value of phase-A voltage
2 in_ub Sampled value of phase-B voltage
3 in_uc Sampled value of phase-C voltage
4 BI_En_VT Input signal of indicating VT in service
No. Output signal Description
1 U3P A voltage data set
2 Ua_Sec Amplitude of phase-A secondary voltage
3 Ub_Sec Amplitude of phase-B secondary voltage
4 Uc_Sec Amplitude of phase-C secondary voltage
5 U1_Sec Amplitude of positive-sequence secondary voltage
6 U2_Sec Amplitude of negative-sequence secondary voltage
7 3U0_Cal_Sec Amplitude of calculated residual secondary voltage
8 Ang(Ua-Ub) Phase angle between phase A and phase B voltages
9 Ang(Ub-Uc) Phase angle between phase B and phase C voltages
10 Ang(Uc-Ua) Phase angle between phase C and phase A voltages
11 Ang(Ua) Phase angle of phase-A voltage

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12 Ang(Ub) Phase angle of phase-B voltage

13 Ang(Uc) Phase angle of phase-C voltage
14 Ang(3U0_Cal) Phase angle of calculated residual voltage
15 Alm_VTS VT secondary circuit abnormality
3.2.4 Settings

1 Prot.U1n 1~1100 0.001 kV Rated value of primary voltage of the three-phase VT
2 Prot.U2n 1~120
Enabled,
0.001 V Rated value of secondary voltage of the three-phase VT
3
3 En_VT Enabled Logic setting to put the three-phase VT into service
Disabled
3.3 One-phase Current Element (TCUR1P)
One-phase current element is responsible for pre-processing measured one-phase current and
calculating the magnitude and the phase angle of the one-phase current, etc. All calculated
information of one-phase current element is used for the protection logic calculation.
One-phase current element has following functions:
1. Pre-process measured one-phase current
2. Calculate information related to the one-phase current
TCUR1P
x.in_ip x.I1P
x.3I0_Ext_Sec
x.Ang(3I0_Ext)
x.Flg_OnLoad
3.3.3 I/O Signals

1 x.in_ip Measured one-phase current
1 x.I1P A current data set
2 x.3I0_Ext_Sec Amplitude of external residual secondary current
3 x.Ang(3I0_Ext) Phase angle of external residual current

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4 x.Flg_OnLoad A flag indicating there is load current
3.3.4 Settings
One-phase current element is a basic element, for a specific application,

the displayed settings may have different prefixes in front of them.

3 1 x.I1n 0~9999 1 A 1000 Primary rated current of the one-phase CT
2 x.I2n 1 or 5 - A 1 Secondary rated current of the one-phase CT
Enabled, Logic setting of enabling/disabling the current
3 x.En_RevCT - - Disabled
Disabled polarity of the one-phase CT
3.4 One-phase Voltage Element (TVOL1P)
One-phase voltage element is responsible for pre-processing one-phase voltage and calculating
the magnitude and the phase angle of the one-phase voltage, etc. All calculated information of
one-phase voltage element is used for the protection logic calculation.
One-phase voltage element has following functions:
1. Pre-process measured one-phase voltage
2. Calculate information related to one-phase voltage
TVOL1P
in_up U1P
BI_En_VT U_Sec
Ang(U)
3.4.3 I/O Signals

1 x.iIn_up Measured one-phase voltage
2 BI_En_VT Input signal of indicating VT in service
1 U1P A voltage data set

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2 U_Sec Amplitude of the one-phase voltage (secondary value)

3 Ang(U) Phase angle of the one-phase voltage
3.4.4 Settings
One-phase voltage element is a basic element, for a specific application,

the displayed settings may have different prefixes in front of them.

3
1 x.U1n 0~1100 0.001 kV - Primary rated voltage of the one-phase VT
2 x.U2n 1~200 0.001 V - Secondary rated voltage of the one-phase VT
3.5 Three-phase Current Summation Element (TCUR3P_3SD)
Three-phase current summation element is responsible for calculating the sum of multiple current
inputs in one side of transformer. All calculated information of three-phase current summation
element is used for the protection logic calculation.
Three-phase current summation element is used to calculate the sum of several groups of
currents
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.

Date: 2021-08-01
TCUR3P_3SD
in_i3p1 I3P
in_i3p2 Ia_Sec
Ib_Sec
Ic_Sec
I1_Sec
3 I2_Sec
3I0_Cal_Sec
Ang(Ia-Ib)
Ang(Ib-Ic)
Ang(Ic-Ia)
Ang(Ia)
Ang(Ib)
Ang(Ic)
Ang(3I0_Cal)
Flg_OnLoad
3.5.3 I/O Signals

1 in_i3p1 Sampled value of the 1st group of three-phase current
2 in_i3p2 Sampled value of the 2nd group of three-phase current
1 I3P A current data set
2 Ia_Sec Amplitude of phase-A secondary current
3 Ib_Sec Amplitude of phase-B secondary current
4 Ic_Sec Amplitude of phase-C secondary current
5 I1_Sec Amplitude of positive sequence secondary current
6 I2_Sec Amplitude of negative sequence secondary current
7 3I0_Cal_Sec Amplitude of calculated residual secondary current
8 Ang(Ia-Ib) Phase angle between phase A and phase B currents
9 Ang(Ib-Ic) Phase angle between phase B and phase C currents
10 Ang(Ic-Ia) Phase angle between phase C and phase A currents
11 Ang(Ia) Phase angle of phase-A current
12 Ang(Ib) Phase angle of phase-B current
13 Ang(Ic) Phase angle of phase-C current

Date: 2021-08-01

14 Ang(3I0_Cal) Phase angle of calculated residual current
15 Flg_OnLoad A flag indicating there is load current detected
3.6 Phase Overcurrent Protection (50/51P)

Phase overcurrent protection is the most widely used type of protection element in power systems.
It can be used as the main protection of the feeder, and can also be used as the backup protection
for power equipment such as transformers, reactors, and motors. When a fault occurs in the
system, a fault current will be generated and the phase overcurrent protection can reflect the
increase of the fault current.
3
The device can provide six stages of phase overcurrent protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics.
The drop-out characteristics can be set as instantaneous drop-out, definite-time drop-out or
inverse-time drop-out. Users can choose whether it is blocked by the voltage control element,
direction control element, or harmonic control element, users can also choose whether it is
controlled by cold load pickup. The direction control element can be set as no direction, forward
direction and reverse direction. The phase overcurrent protection picks up when the current
exceeds the current threshold value, and operates after a certain time delay, once the fault
disappears, the phase overcurrent protection will drop-out.
Phase overcurrent protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, overcurrent protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overcurrent protection.
The enabling and blocking logic of phase overcurrent protection is shown in the figure below:
EN 50/51Px.En &
50/51Px.On
SIG 50/51Px.Enable
&
SIG 50/51Px.Block ≥1 50/51Px.Blocked
SIG Fail_Device
&
50/51Px.Valid
Figure 3.6-1 The enabling and blocking logic of phase overcurrent protection
The logic diagram of the fault detector element of phase overcurrent protection is as follows:

Date: 2021-08-01
SET Ia>0.95×[50/51Px.I_Set]
>=1
SET Ib>0.95×[50/51Px.I_Set] &
0 500ms &
SET Ic>0.95×[50/51Px.I_Set]
50/51Px.Pkp
SIG 50/51Px.On
SIG 50/51Px.Valid
&
FD.Pkp
SET [50/51Px.Opt_Trp/Alm]=Alm
3 Figure 3.6-2 Logic diagram of the fault detector element of phase overcurrent protection
3.6.1.1 Voltage Control Element
When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the
voltage control element can be adopted to increase the sensitivity for this kind of fault. Users can
enable or disable the voltage control element via the setting [50/51Px.En_Volt_Blk] (x=1~6). If the
VT circuit supervision function is enabled for the device, and the setting [50/51P.En_VTS_Blk] is
set as “Enabled”, when VT circuit failure happens, the device will issue a VT circuit failure alarm
signal [VTS.Alm], and the voltage controlled phase overcurrent protection will be blocked. If the
voltage control element of phase overcurrent protection is not enabled, phase overcurrent
protection will not affected by VT circuit failure. The corresponding relationship between the
phase-segregated overcurrent element and the voltage control element is as follows.
Voltage control
Phase A Phase B Phase C
criterion
Phase-to-phase Uab<[50/51P.VCE.Upp] Uab<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp]
criterion Uca<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp] Uca<[50/51P.VCE.Upp]
Negative-sequence
U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2]
criterion
Zero-sequence
U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0]
criterion
The relationship between the phase-to-phase criterion, the negative-sequence criterion and the
zero-sequence criterion is "or". The logic diagram of the voltage control element action is shown
below:

Date: 2021-08-01
EN [50/51P.En_VTS_Blk] &
>=1
SIG VTS.Alm &
SIG Uab, Ubc, Uca
criterion
Voltage
&
50/51P.VCE.Op
SIG U2, U0_Cal
SIG Prot.BI_En_VT &
EN [En_VT]
3
Figure 3.6-3 Logic diagram of the voltage control element of phase overcurrent protection
3.6.1.2 Direction Control Element
In order to ensure the selectivity of phase overcurrent protection, direction control element is
introduced. The setting [50/51Px.Opt_Dir] (x=1~6) is used for users to select the directional mode
of each stage of phase overcurrent protection: no direction, forward direction and reverse
direction are selectable.
Takes the phase A fault as an example, the polarization mode is set as “Up”, its operation
characteristics are shown in the figure below. The principle of phase B and phase C is the same. If
the positive-sequence voltage or the phase-to-phase voltage is polarized, the operation
characteristics are the same.
The operation boundary of the forward direction element can be set by [50/51P.DIR.phi_Min_Fwd]
and [50/51P.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51P.DIR.phi_Min_Rev] and [50/51P.DIR.phi_Max_Rev].

Date: 2021-08-01
Ua
[50/51P.DIR.phi_Min_Fwd]
Non-operating Ia
area
[50/51P.DIR.phi_Max_Rev] Operating area in

forward direction
[50/51P.DIR.RCA]
3 Operating area in
reverse direction
[50/51P.DIR.phi_Max_Fwd]
[50/51P.DIR.phi_Min_Rev] Non-operating
area
Figure 3.6-4 The direction element operation characteristics when phase A voltage is polarized
Where:
The sensitivity angle of the direction control element (RCA) can be set by the setting
[50/51P.DIR.RCA].
The selection of the polarization voltage can be set by the setting [50/51P.DIR.Opt_PolarizedVolt].
The following table shows the relationship between the operating current, the polarized voltage
and the polarization mode.
Direction criterion (for “ABC” system phase sequence)

Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Phase-A Positive-sequence
Phase A Angle_A=Angle(U1)-Angle(Ia)-RCA
current Ia voltage
Positive-sequence Phase-B Positive-sequence
Phase B Angle_B=Angle(U1)-Angle(Ib)-RCA-120º
voltage polarized current Ib voltage
Phase-C Positive-sequence
Phase C Angle_C=Angle(U1)-Angle(Ic)-RCA+120º
current Ic voltage
Phase-A Phase-to-phase
Phase A Angle_A=Angle(Ubc)-Angle(Ia)-RCA+90º
current Ia voltage Ubc
Phase-to-phase Phase-B Phase-to-phase
Phase B Angle_B=Angle(Uca)-Angle(Ib)-RCA+90º
voltage polarized current Ib voltage Uca
Phase-C Phase-to-phase
Phase C Angle_C=Angle(Uab)-Angle(Ic)-RCA+90º
current Ic voltage Uab
Phase-to-ground Phase A Phase-A Phase-to-ground Angle_A=Angle(Ua)-Angle(Ia)-RCA

Date: 2021-08-01
voltage polarized current Ia voltage Ua

Phase-B Phase-to-ground
Phase B Angle_B=Angle(Ub)-Angle(Ib)-RCA
current Ib voltage Ub
Phase-C Phase-to-ground
Phase C Angle_C=Angle(Uc)-Angle(Ic)-RCA
current Ic voltage Uc
In order to improve the reliability of the direction control element, the direction control element with
the above three polarization modes must be used in conjunction with the negative-sequence
direction criterion. The negative-sequence direction criterion is shown in the table below.
Negative-sequence direction criterion

Operating current Polarized voltage Angle difference 3
Negative-sequence current Negative-sequence voltage Angle_I2=Angle(U2)-Angle(I2)-RCA+180º
For the “ACB” system phase sequence, the angle difference under
positive-sequence voltage polarization mode and phase-to-phase voltage
polarization mode is different from that of the “ABC” system phase
sequence, as shown in the following table:
Direction criterion (for “ACB” system phase sequence)

Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Phase-A Positive-sequence
Phase A Angle_A=Angle(U1)-Angle(Ia)-RCA
current Ia voltage
Positive-sequence Phase-B Positive-sequence
Phase B Angle_B=Angle(U1)-Angle(Ib)-RCA+120º
voltage polarized current Ib voltage
Phase-C Positive-sequence
Phase C Angle_C=Angle(U1)-Angle(Ic)-RCA-120º
current Ic voltage
Phase-A Phase-to-phase
Phase A Angle_A=Angle(Ubc)-Angle(Ia)-RCA+270º
current Ia voltage Ubc
Phase-to-phase Phase-B Phase-to-phase
Phase B Angle_B=Angle(Uca)-Angle(Ib)-RCA+270º
voltage polarized current Ib voltage Uca
Phase-C Phase-to-phase
Phase C Angle_C=Angle(Uab)-Angle(Ic)-RCA+270º
current Ic voltage Uab
Therefore, the criterion for the three-phase direction control element is as follows:
Three-phase direction control element

Direction element Operating condition
Angle_A forward direction operates and Angle_I2 reverse direction does not
Phase A forward direction
operate.
Angle_A reverse direction operates and Angle_I2 forward direction does not
Phase A reverse direction
operate.
Phase B forward direction Angle_B forward direction operates and Angle_I2 reverse direction does not

Date: 2021-08-01
operate.
Angle_B reverse direction operates and Angle_I2 forward direction does not
Phase B reverse direction
operate.
Angle_C forward direction operates and Angle_I2 reverse direction does not
Phase C forward direction
operate.
Angle_C reverse direction operates and Angle_I2 forward direction does not
Phase C reverse direction
operate.
The direction element calculation needs to judge the current threshold and voltage threshold. The
corresponding phase operating current must be greater than the minimum operating current
setting [50/51P.DIR.I_Min], otherwise the direction element can not operate. For the voltage, it has
3 memory function that can eliminate the dead zone of the direction element when the close up
three-phase short circuit fault occurs. When the polarized voltage is less than the minimum
operating voltage setting [50/51P.DIR.U_Min], the polarized voltage will not be used to judge the
direction, the positive-sequence voltage before two cycles is used to judge the direction.
Polarized voltage Operating current

Phase-to-phase voltage Phase current
Phase-to-ground voltage Phase current
Positive-sequence voltage Phase current
Negative-sequence voltage Negative-sequence current
The logic diagram of the forward direction element and reverse direction element is shown as
below.
SIG VTS.Alm & >=1

&
SIG Three-phase currents 50/51P.FwdDir.Op
Forward direction
SIG Three-phase voltages

criterion
SIG Memorized U1
SET [50/51P.DIR.Opt_PolarizedVolt]
SIG Prot.BI_En_VT &
EN [En_VT]
SET Iop>[50/51P.DIR.I_Min]

Date: 2021-08-01
SIG VTS.Alm & >=1

&
SIG Three-phase currents 50/51P.RevDir.Op
Reverse direction
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [50/51P.DIR.Opt_PolarizedVolt]
SIG Prot.BI_En_VT &

3
EN [En_VT]
SET Iop>[50/51P.DIR.I_Min]
Figure 3.6-5 Logic diagram of forward and reverse direction element of phase overcurrent protection
Where:
Memorized U1: the positive-sequence memory voltage, it refers to the positive-sequence voltage
of two cycles before the polarized voltage is less than the minimum operating voltage setting
[50/51P.DIR.U_Min], and it is calculated from the three-phase voltage.
Iop: the operating current.
3.6.1.3 Harmonic Control Element
When transformer and other equipment are energized without any load, the inrush current may be
generated, which may cause the mal-operation of the phase overcurrent protection. According to
the characteristics of high secondary harmonic component in the inrush current and low
secondary harmonic component in common fault current, the secondary harmonic control element
is added to prevent the phase overcurrent protection from mal-operation due to inrush current. For
the harmonic control element, the harmonic blocking mode can be selected through the setting
[50/51P.HMB.Opt_Blk], it can support phase locking, cross locking, and maximum phase locking.
The correspondences are shown in the following table:
Harmonic blocking criterion

Setting Value
Phase A Phase B Phase C
1 PhaseBlk Ia2/Ia1>[50/51P.HMB.K_Hm2] Ib2/Ib1>[50/51P.HMB.K_Hm2] Ic2/Ic1>[50/51P.HMB.K_Hm2]
2 CrossBlk (Ia2/Ia1) or (Ib2/Ib1) or (Ic2/Ic1)> [50/51P.HMB.K_Hm2]
Max(Ia2, Ib2, Ic2)/Ia1> Max(Ia2, Ib2, Ic2)/Ib1> Max(Ia2, Ib2, Ic2)/Ic1>
3 MaxPhaseBlk
[50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2]
Where:
Ia1, Ib1, Ic1: the fundamental current;
Ia2, Ib2, Ic2: the secondary harmonic component of the current.

Date: 2021-08-01
When the fundamental current is greater than the setting [50/51P.HMB.I_Rls], the harmonic
blocking element of the corresponding phase is released.
The following figure shows the logic diagram of the harmonic control element of phase
overcurrent protection.
SET Imax>[50/51P.HMB.I_Rls]
SIG Ia1, Ib1, Ic1

&
50/51P.HMB.Op
Harmonic
criterion
SIG Ia2, Ib2, Ic2
3 SET [50/51P.HMB.Opt_Blk]
Figure 3.6-6 Logic diagram of harmonic control element of phase overcurrent protection
Where:
Ia1, Ib1, Ic1: the fundamental current
Ia2, Ib2, Ic2: the 2nd harmonic current
Imax: the maximum phase current
3.6.1.4 Operation Characteristic
Phase overcurrent protection can operate without time delay or operate with a definite-time limit, it
can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and
ANSI C37.112 standards. Phase overcurrent protection can support definite-time limit, IEC &
ANSI standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51Px.Opt_Curve] (x=1~6), the relationship between the value of
the setting and the curve is shown in the table below.
50/51Px.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely Inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal Inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately Inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite Time - - - -
ANSILTE ANSI Long Time Extremely Inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long Time Very Inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long Time Inverse 0.086 0.02 0.185 4.6
IECN IEC Normal Inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IEC IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short-time inverse 0.05 0.04 0 -
IECLT IEC Long-time inverse 120.0 1.0 0 -
IECDefTime IEC Definite Time - - - -

Date: 2021-08-01
50/51Px.Opt_Curve Time Characteristic k α c tr

UserDefine Programmable
Only when the setting [50/51Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Px.K], [50/51Px.C] and [50/51Px.Alpha]
are useful, the inverse-time operating curve is determined by the three settings.
⚫ Without time delay
When I > Ip , phase overcurrent protection operates immediately.
⚫ Definite-time characteristic
When I > Ip , the protection operates with a time delay of top (i.e. the value of the setting 3
[50/51Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
IP I
Figure 3.6-7 Definite-time operation characteristic curve of phase overcurrent protection
⚫ Inverse-time characteristic
When I > Ip , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Px.tmin] (x=1~6). The
inverse-time operation characteristic equation is:
 k 
t= 
+ c   TMS
(I / I P ) −1 
Where:
Ip is the current setting [50/51Px.I_Set];

TMS is the inverse-time time multiplier, i.e. the setting [50/51Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Px.K];

Date: 2021-08-01
c is the inverse-time coefficient C, i.e. the setting [50/51Px.C];

 is the inverse-time coefficient Alpha, i.e. the setting [50/51Px.Alpha];
I is the measured current.
The inverse-time operation characteristic curve is shown as below:
t min
IP ID I
Figure 3.6-8 Inverse-time operation characteristic curve of phase overcurrent protection
When the applied current is not a fixed value, but changes with time, the operating behaviour of
the protection is shown in the following equation:
T0
1
 t ( I )dt
0
=1
Where:
T0 is the operating time of the protection element;
t(I) is the theoretical operating time when the current is I.
3.6.1.5 Drop-out Characteristic
The supported drop-out characteristics of the phase overcurrent protection include instantaneous
drop-out, definite-time drop-out and ANSI inverse-time drop-out.
When the operating curve is selected as definite-time, IEC inverse-time or user-defined

inverse-time characteristic, the drop-out characteristic can only be selected as instantaneous
drop-out or definite-time drop-out, if inverse-time drop-out is selected, the alarm signal
"Fail_Settings" will be issued and the device will be blocked.
When the operating curve is selected as ANSI inverse-time characteristic, the drop-out
characteristic can be selected as instantaneous drop-out, definite-time drop-out and ANSI

Date: 2021-08-01
inverse-time drop-out.
⚫ Instantaneous drop-out
When I <0.95* Ip , the protection drops out immediately.
⚫ Definite-time drop-out
When I <0.95* Ip , the protection drops out with a time delay of tdr (i.e. the value of the setting
[50/51Px.t_DropOut]), and the drop-out characteristic curve is shown in the following figure:
Start time
I>Ip 3
Start
signal
Operating
signal
Protection
Operating threshold operate
Operating
counter
t dr t dr t dr
Dropout time setting
Dropout time
Dropout time
Figure 3.6-9 Definite-time drop-out characteristic of phase overcurrent protection
⚫ Inverse-time drop-out
When I > Ip , the inverse-time operating accumulator begins to accumulate, the accumulated
value after t p (Assuming t p is less than the theoretical operating time) is calculated according
to the following equation:
tp
1
I tp =  dt
0
t(I )
At this time, if I <0.95* Ip , the protection element starts drop-out, and the drop-out characteristic
meets the following equation:

Date: 2021-08-01
TR
1
I tp −  dt = 0
t (I )
0 R
Where:
T R is the drop-out time;
tR( I ) is the drop-out characteristic equation
When I <0.95* Ip , the inverse-time drop-out characteristic equation is as follows:
 
3 tR = 
tr
2
 TMS
1 − ( I / I P ) 
Where:
Ip is the current setting [50/51Px.I_Set];

TMS is the inverse-time factor, i.e. the setting [50/51Px.TMS];
tr is the drop-out time coefficient, it is the drop-out time required for the current to drop to 0 after
the protection operates.
When 0.95* Ip < I < Ip , the accumulator will neither accumulate nor drop out
The inverse time drop-out characteristic curve is shown in the figure below.
tr
IP I
Figure 3.6-10 Inverse-time drop-out characteristic curve of phase overcurrent protection
The correspondence between the start signal, operating signal, and operating accumulator in the
inverse-time drop-out characteristic is shown in the figure below:

Date: 2021-08-01
Start time
I>Ip
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter
tr Dropout time coefficient

Dropout time
Dropout time
Figure 3.6-11 Inverse-time drop-out characteristic of phase overcurrent protection
50/51P
50/51Px.Enable 50/51Px.On
50/51Px.Block 50/51Px.Blocked
50/51Px.Valid
50/51Px.St
50/51Px.StA
50/51Px.StB
50/51Px.StC
50/51Px.Op
50/51Px.Op.PhA
50/51Px.Op.PhB
50/51Px.Op.PhC
50/51P.FwdDir.Op
50/51P.RevDir.Op
50/51Px.Alm

Date: 2021-08-01
3.6.3 I/O Signal

Stage x of phase overcurrent protection enabling input, it is triggered from
1 50/51Px.Enable
binary input or programmable logic etc. (x=1~6)
Stage x of phase overcurrent protection blocking input, it is triggered from
2 50/51Px.Block
1 50/51Px.On Stage x of phase overcurrent protection is enabled
2 50/51Px.Blocked Stage x of phase overcurrent protection is blocked
3 3
4
50/51Px.Valid
50/51Px.St
Stage x of phase overcurrent protection is valid
Stage x of phase overcurrent protection starts
5 50/51Px.StA Stage x of phase overcurrent protection starts (Phase A)
6 50/51Px.StB Stage x of phase overcurrent protection starts (Phase B)
7 50/51Px.StC Stage x of phase overcurrent protection starts (Phase C)
8 50/51Px.Op Stage x of phase overcurrent protection operates
9 50/51Px.Op.PhA Stage x of phase overcurrent protection operates (Phase A)
10 50/51Px.Op.PhB Stage x of phase overcurrent protection operates (Phase B)
11 50/51Px.Op.PhC Stage x of phase overcurrent protection operates (Phase C)
12 50/51Px.Alm Stage x of phase overcurrent protection alarms
13 50/51P.FwdDir.Op The forward direction element of phase overcurrent protection operates
14 50/51P.RevDir.Op The reverse direction element of phase overcurrent protection operates

Date: 2021-08-01
3.6.4 Logic
SET Ia>[50/51Px.I_Set]
SIG 50/51P.VCE.Op_A >=1 &
EN [50/51Px.En_Volt_Blk]
SIG 50/51P.FwdDir.Op_A
selection
Direction
SIG 50/51P.RevDir.Op_A
SIG [50/51Px.Opt_Dir] 50/51Px.StA

&
SIG 50/51P.HMB.Op_A & & Timer
EN [50/51Px.En_Hm_Blk]
t
t
&
50/51Px.Op.PhA
3
SIG 50/51Px.Pkp
SET [50/51Px.Opt_Trp/Alm]=Trp
&
50/51Px.Alm.PhA
SET [50/51Px.Opt_Trp/Alm]=Alm
SIG 50/51Px.StA
>=1
SIG 50/51Px.StB 50/51Px.St
SIG 50/51Px.StC
SIG 50/51Px.Op.PhA
>=1
SIG 50/51Px.Op.PhB 50/51Px.Op
SIG 50/51Px.Op.PhC
SIG 50/51Px.Alm.PhA
>=1
SIG 50/51Px.Alm.PhB 50/51Px.Alm
SIG 50/51Px.Alm.PhC
Figure 3.6-12 Logic diagram of phase overcurrent protection
3.6.5 Settings
Access path: MainMenu  Settings  Protection Settings  OC Settings
No. Settings Range Default Unit Step Description

The low voltage blocking setting
1 50/51P.VCE.Upp 10~100 70 V 0.001 of the voltage control element of
phase overcurrent protection
The negative-sequence voltage
blocking setting of the voltage
2 50/51P.VCE.U2 2~57 8 V 0.001
control element of phase
The residual voltage setting (set
according to 3U0) of voltage
3 50/51P.VCE.3U0 2~57 8 V 0.001

Date: 2021-08-01

The relay characteristic angle of
4 50/51P.DIR.RCA -180~179 45 deg 1 the direction control element of
The relay negative-sequence
50/51P.DIR.RCA_N characteristic angle of the
5 -180~179 45 deg 1
egOC direction control element of
The minimum boundary of the
50/51P.DIR.phi_Min
6 10~90 90 deg 1 forward direction element of
_Fwd
3 phase overcurrent protection
The maximum boundary of the
50/51P.DIR.phi_Ma
x_Fwd
50/51P.DIR.phi_Min
8 10~90 90 deg 1 reverse direction element of
_Rev
50/51P.DIR.phi_Ma
x_Rev
The voltage polarization mode
for direction control element of
Upp; Upp: phase-to-phase voltage
50/51P.DIR.Opt_Pol
10 Up; Upp - - polarized
arizedVolt
U1 Up: phase-to-ground voltage
polarized
U1: positive-sequence voltage
polarized
The minimum operating current
setting for the direction control
11 50/51P.DIR.I_Min (0.05~1)In 0.05 - 0.001
element of phase overcurrent
protection
The minimum operating voltage
12 50/51P.DIR.U_Min 1~10 4 V 0.001
protection

Date: 2021-08-01

Logic setting to determine the
behaviour of phase overcurrent
protection when VT circuit
supervision function is enabled
and VT circuit failure happens.
Disabled; Disabled: phase overcurrent
13 50/51P.En_VTS_Blk Disabled - -
Enabled protection will not affected by VT
circuit failure
Enabled: voltage controlled
phase overcurrent protection will
be blocked by VT circuit failure
3
signal
The percent setting of the
50/51P.HMB.K_Hm
14 0.1~1 0.2 - 0.001 harmonic control element of
2
The current setting for releasing
15 50/51P.HMB.I_Rls 2~150 20 A 0.001 the harmonic control element of
The setting used to select the
harmonic blocking mode of
PhaseBlk phase overcurrent protection
50/51P.HMB.Opt_Bl
16 CrossBlk PhaseBlk - - PhaseBlk: phase blocking
k
MaxPhaseBlk CrossBlk: cross blocking
MaxPhaseBlk: maximum phase
blocking
The current setting of stage 1 of
17 50/51P1.I_Set 0.05~200 15 A 0.001
The operating time setting of
18 50/51P1.t_Op 0 ~100 0.1 s 0.001 stage 1 of phase overcurrent
protection
The drop-out time setting of
19 50/51P1.t_DropOut 0 ~100 0 s 0.001 stage 1 of phase overcurrent
protection

Date: 2021-08-01

The logic setting for
enabling/disabling the voltage
control element of stage 1 of
Disabled: stage 1 of phase
50/51P1.En_Volt_Bl Disabled; overcurrent protection is not
20 Disabled - -
k Enabled controlled by the voltage control
element
Enabled: stage 1 of phase
3 overcurrent protection
controlled by the voltage control
is
element
Non_Directional The setting used to select the
Non_Directio
21 50/51P1.Opt_Dir Forward - - directional mode of stage 1 of
nal
Reverse phase overcurrent protection.
enabling/disabling the harmonic
50/51P1.En_Hm_Bl Disabled; overcurrent protection is not
22 Disabled - -
k Enabled controlled by the harmonic
control element
overcurrent protection is
controlled by the harmonic
control element
Disabled;
23 50/51P1.En Enabled - - enabling/disabling the stage 1 of
Enabled
Enabling stage 1 of phase
overcurrent protection operate
50/51P1.Opt_Trp/Al Trp;
24 Trp - - to trip or alarm.
m Alm
Trp: for tripping purpose
Alm: for alarm purpose

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV; The setting for selecting the
ANSILT; inverse-time operation
25 50/51P1.Opt_Curve IECDefTime - -
IECN; characteristic curve of stage 1 of
IECV;
IEC;
phase overcurrent protection.
3
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
The setting for selecting the
inverse-time drop-out
Inst; characteristic curve of stage 1 of
50/51P1.Opt_Curve
26 DefTime; Inst - - phase overcurrent protection
_DropOut
IDMT Inst: instantaneous drop-out
DefTime: definite-time drop-out
IDMT: inverse-time drop-out
The time multiplier setting of
27 50/51P1.TMS 0.04~ 20 1 - 0.001 stage 1 of phase overcurrent
protection
The minimum operating time
28 50/51P1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of phase
The constant “k” of the
customized inverse-time
0.000
29 50/51P1.K 0.001~120 0.14 - operation characteristic of stage
1
1 of phase overcurrent
protection
The constant “α” of the
0.000
30 50/51P1.Alpha 0.01 ~3 0.02 - operation characteristic of stage
1
protection

Date: 2021-08-01

The constant “C” of the
0.000
31 50/51P1.C 0 ~1.2 0 - operation characteristic of stage
1
protection
32 50/51P2.I_Set 0.05~200 15 A 0.001
3 protection
protection
35 Disabled - -
element
element
Non_Directio
nal
37 Disabled - -
control element
control element
Disabled;
Enabled

Date: 2021-08-01

m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
3
IECV; phase overcurrent protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P2.Opt_Curve
_DropOut
protection
0.000
1
protection

Date: 2021-08-01

0.000
1
protection
0.000
1
3 protection
47 50/51P3.I_Set 0.05~200 15 A 0.001
protection
protection
50 Disabled - -
element
element
Non_Directio
nal

Date: 2021-08-01

52 Disabled - -
control element
overcurrent
controlled by
protection
the harmonic
is
3
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P3.Opt_Curve
_DropOut

Date: 2021-08-01

protection
0.000
1
3 3 of phase overcurrent
protection
0.000
1
protection
0.000
1
protection
62 50/51P4.I_Set 0.05~200 15 A 0.001
protection
protection
65 Disabled - -
element
element

Date: 2021-08-01

Non_Directio
nal
67 Disabled - -
k Enabled controlled
control element
by the harmonic
3
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

50/51P4.Opt_Curve
_DropOut
3 protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
77 50/51P5.I_Set 0.05~200 15 A 0.001
protection
protection

Date: 2021-08-01

80 Disabled - -
element
is
3
element
Non_Directio
nal
82 Disabled - -
control element
control element
Disabled;
Enabled
m Alm

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
3 IECV;
IEC;
phase overcurrent protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P5.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection

Date: 2021-08-01

0.000
1
protection
92 50/51P6.I_Set 0.05~200 15 A 0.001
protection 3
protection
95 Disabled - -
element
element
Non_Directio
nal
97 Disabled - -
control element
control element
Disabled;
Enabled

Date: 2021-08-01

m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
3 ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P6.Opt_Curve
_DropOut
protection
0.000
1
protection

Date: 2021-08-01

0.000
1
protection
0.000
1
protection
3
3.7 Earth Fault Overcurrent Protection (50/51G)
The normal operating power system is three-phase symmetrical, its zero-sequence current and
voltage are theoretically zero. Most of the faults are three-phase asymmetrical, according to the
asymmetry of the fault, various protections reflect sequence component principle can be
constituted. Earth fault overcurrent protection has been widely used in power systems, it can be
used for the fault conditions that zero-sequence fault current flows into the earth, including
single-phase earth fault and phase-to-phase short-circuit earth fault etc..
The device can provide six stages of earth fault overcurrent protection with independent logic.
Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The drop-out characteristics can be set as instantaneous drop-out, definite-time
drop-out or inverse-time drop-out. Users can choose whether it is blocked by the direction control
element or the harmonic control element, users can also choose whether it is controlled by cold
load pickup. The direction control element can be set as no direction, forward direction and
reverse direction. The zero-sequence current used by earth fault overcurrent protection can be
calculated zero-sequence current or the measured zero-sequence current, it can operate to trip or
alarm, it can be enabled or blocked by the external binary input.
Earth fault overcurrent protection can be enabled or disabled via the settings or binary input
signals, for some specific applications, the protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block earth fault overcurrent
protection. The enabling and blocking logic of earth fault overcurrent protection is shown in the
figure below:

Date: 2021-08-01
EN 50/51Gx.En &
50/51Gx.On
SIG 50/51Gx.Enable
&
SIG 50/51Gx.Block ≥1 50/51Gx.Blocked
SIG Fail_Device
&
50/51Gx.Valid
3 Figure 3.7-1 The enabling and blocking logic of earth fault overcurrent protection
The logic diagram of the fault detector element of earth fault overcurrent protection is as follows:
SET 3I0>0.95*[50/51Gx.3I0_Set] & 50/51Gx.Pkp

0 500ms
&
SIG 50/51Gx.On &
FD.Pkp
SIG 50/51Gx.Valid
EN [50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.7-2 Logic diagram of the fault detector element of earth fault overcurrent protection
In order to ensure the selectivity of earth fault overcurrent protection, direction control element is
introduced. The setting [50/51Gx.Opt_Dir] (x=1~6) is used for users to select the directional mode
of each stage of earth fault overcurrent protection: no direction, forward direction and reverse
The operation boundary of the forward direction element can be set by [50/51G.DIR.phi_Min_Fwd]
and [50/51G.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51G.DIR.phi_Min_Rev] and [50/51G.DIR.phi_Max_Rev].

Date: 2021-08-01
-U0
[50/51G.DIR.phi_Min_Fwd]
Non-operating I0
area
Operating area in
[50/51G.DIR.phi_Max_Rev] forward direction
[50/51G.DIR.RCA]
Operating area in
reverse direction
3
[50/51G.DIR.phi_Max_Fwd]
Non-operating
area
[50/51G.DIR.phi_Min_Rev]
Figure 3.7-3 The direction element operation characteristics when zero-sequence voltage is polarized
Where:
[50/51G.DIR.RCA].
The forward direction characteristic is:
-[50/51G.DIR.phi_Min_Fwd]<angle<[50/51G.DIR.phi_Max_Fwd]
The reverse direction characteristic is:
180-[50/51G.DIR.phi_Min_Rev]<angle<180+[50/51G.DIR.phi_Max_Rev]
Polarized
Polarization mode Operating current Angle difference
voltage
Zero-sequence Calculated residual current 3I0_Cal -3U0 angle=angle(-3U0)-angle(3I0_Cal)-RCA
voltage polarized Measured residual current 3I0_Ext -3U0 angle=angle(-3U0)-angle(3I0_Ext)-RCA
corresponding operating current must be greater than the minimum operating current setting
[50/51G.DIR.3I0_Min], otherwise the direction element can not operate. The polarized voltage
must be greater than the minimum operating voltage setting [50/51G.DIR.3U0_Min], otherwise the
direction element can not operate.
The logic diagram of the forward direction element and reverse direction element is as follows.

Date: 2021-08-01
EN [50/51G.En_VTS_Blk] &
SIG VTS.Alm & >=1

&
SIG 3I0_Ext, 3I0_Cal
direction
Forward
criterion
50/51G.FwdDir.Op
SIG 3U0_Cal
EN [En_VT] &
3 SIG Prot.BI_En_VT
SET Iop>[50/51G.DIR.3I0_Min]
SET Upo>[50/51G.DIR.3U0_Min]
EN [50/51G.En_VTS_Blk] &
SIG VTS.Alm & >=1

SIG 3I0_Ext, 3I0_Cal &
direction
Reverse
criterion
50/51G.RevDir.Op
SIG 3U0_Cal
EN [En_VT] &
SIG Prot.BI_En_VT
SET Iop>[50/51G.DIR.3I0_Min]
SET Upo>[50/51G.DIR.3U0_Min]
Figure 3.7-4 Logic diagram of forward and reverse direction element of earth fault overcurrent protection
Where:
3I0_Ext is the measured residual current.
3I0_Cal is the calculated residual current.
3U0_Cal: the calculated residual voltage
Upo: the polarized voltage.
3.7.1.2 Harmonic Control Element
Zero-sequence harmonic control element can be used together with earth fault overcurrent
protection when harmonic blocking is required, the zero-sequence current can be the calculated
zero-sequence current or the measured zero-sequence current.

Date: 2021-08-01
When the percentage of the second harmonic component to fundamental component of residual
current is greater than the setting [50/51G.HMB.K_Hm2], harmonic blocking element operates to
block stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm_Blk] is
enabled.
When the fundamental zero-sequence current is greater than the setting [50/51G.HMB.I_Rls], the
harmonic blocking element is released.
The following figure shows the logic diagram of the harmonic control element of earth fault
SET 3I0>[50/51G.HMB.I_Rls] 3
&
SIG 3I0_Ext or 3I0_Cal
50/51G.Hm_Op
Harmonic
blocking
logi c
SET 3I02/3I0>[50/51G.HMB.K_Hm2]
Figure 3.7-5 Logic diagram of harmonic control element of earth fault overcurrent protection
Where:
3I0_Ext, 3I0_Cal: the measured residual current and the calculated residual current
3I02: the 2nd harmonic residual current
Earth fault overcurrent protection can operate without time delay or operate with a definite-time
limit, it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3
and ANSI C37.112 standards. Earth fault overcurrent protection can support definite-time limit,
IEC & ANSI standard inverse time limit and user-defined inverse-time limit, users can select the
wanted operating curve by the setting [50/51Gx.Opt_Curve], the relationship between the value of
50/51Gx.Opt_Curve Time Characteristic k α c tr


Date: 2021-08-01
50/51Gx.Opt_Curve Time Characteristic k α c tr

Only when the setting [50/51Gx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Gx.K], [50/51Gx.C] and [50/51Gx.Alpha]

3 When I 0 > I 0 p , the protection operates immediately.
When I 0 > I 0 p , the protection operates with a time delay of top (i.e. the value of the setting
[50/51Gx.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
I0p I0
Figure 3.7-6 Definite-time operation characteristic curve of earth fault overcurrent protection
When I 0 > I 0 p , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I 0 . The larger current is, the smaller the operating time is, but not
unlimited. When the current is large enough to a certain threshold ( I 0 p ), the inverse-time
operating time will not continue to decrease, then the operation characteristic becomes the
definite-time characteristic, and the operating time is tmin , i.e. the setting [50/51Gx.tmin]. The
 k 
t =  
+ c   TMS
(I 0 / I 0P ) − 1 
Where:

Date: 2021-08-01
I 0 p is the current setting [50/51Gx.3I0_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51Gx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Gx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Gx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Gx.Alpha];
I 0 is the measured zero-sequence current.

3
t
t min
I0P ID I0
Figure 3.7-7 Inverse-time operation characteristic curve of earth fault overcurrent protection
When the applied zero-sequence current I 0 is not a fixed value, but changes with time, the
operating behaviour of the protection is shown in the following equation:
T0
1
 t ( I )dt
0 0
=1
Where:
t(I0) is the theoretical operating time when the current is I 0 .
The supported drop-out characteristics of the earth fault overcurrent protection include
instantaneous drop-out, definite-time drop-out and ANSI inverse-time drop-out.


Date: 2021-08-01

When I 0 <0.95* I 0 p , the protection drops out immediately.
3 When I 0 <0.95* I 0 p , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51Gx.t_DropOut]), the drop-out characteristic curve is shown in the following figure:
Start time
I0>I0p
Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.7-8 Definite-time drop-out characteristic of earth fault overcurrent protection
When I 0 > I 0 p , the inverse-time operating accumulator begins to accumulate, the accumulated
tp
1
Itp =  t(I
0
0
dt
)

Date: 2021-08-01
At this time, if I 0 <0.95* I 0 p , the protection element starts drop-out, and the drop-out
characteristic meets the following equation:
TR
1
I tp − t
0 R (I )
dt = 0
Where:

When I 0 <0.95* I 0 p , the inverse-time drop-out characteristic equation is as follows: 3

 tr 
tR =  2
 TMS
1 − ( I 0 / I 0 P ) 
Where:
I0P is the current setting [50/51Gx.3I0_Set];
TMS is the inverse-time factor, i.e. the setting [50/51Gx.TMS];
I 0 is the measured current.

When 0.95* I 0 p < I 0 < I 0 p , the accumulator will neither accumulate nor drop out
tr
I0 P I0
Figure 3.7-9 Inverse-time drop-out characteristic curve of earth fault overcurrent protection

Date: 2021-08-01
Start time
I0>I0p
Start
signal
3 Operating
signal
Protection
Operating
counter

Dropout time
Dropout time
Figure 3.7-10 Inverse-time drop-out characteristic of earth fault overcurrent protection
50/51G
50/51Gx.Enable 50/51Gx.On
50/51Gx.Block 50/51Gx.Blocked
50/51Gx.Valid
50/51Gx.St
50/51Gx.Op
50/51Gx.Alm
50/51Gx.FwdDir.Op
50/51Gx.RevDir.Op
3.7.3 I/O Signal

Stage x of earth fault overcurrent protection enabling input, it is triggered from
1 50/51Gx.Enable
2 50/51Gx.Block Stage x of earth fault overcurrent protection blocking input, it is triggered from

Date: 2021-08-01

1 50/51Gx.On Stage x of earth fault overcurrent protection is enabled
2 50/51Gx.Blocked Stage x of earth fault overcurrent protection is blocked
3 50/51Gx.Valid Stage x of earth fault overcurrent protection is valid
4 50/51Gx.St Stage x of earth fault overcurrent protection starts
5 50/51Gx.Op Stage x of earth fault overcurrent protection operates
6 50/51Gx.Alm Stage x of earth fault overcurrent protection alarms
7 50/51G.FwdDir.Op The forward direction element of earth fault overcurrent protection operates
8 50/51G.RevDir.Op The reverse direction element of earth fault overcurrent protection operates
3.7.4 Logic
3
SET 3I0>[50/51Gx.3I0_Set]
SIG 50/51G.FwdDir.Op 50/51Gx.St

&
selection
Direction
SIG 50/51G.RevDir.Op & Timer

t
SET [50/51Gx.Opt_Dir] t
SIG 50/51G.HMB.Op &
EN [50/51Gx.En_Hm_Blk]
SIG 50/51Gx.Pkp
&
50/51Gx.Op
SET [50/51Gx.Opt_Trp/Alm]=Trp
&
50/51Gx.Alm
SET [50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.7-11 Logic diagram of earth fault overcurrent protection
3.7.5 Settings
Access path: MainMenu  Settings  Protection Settings  ROC Settings

The relay characteristic angle
of the direction control
1 50/51G.DIR.RCA -180~179 45 deg 1
element of earth fault
50/51G.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd earth fault overcurrent
protection

Date: 2021-08-01

50/51G.DIR.phi_Max_ forward direction element of
3 10~90 90 deg 1
protection
50/51G.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
Rev earth fault overcurrent
protection
3 5
50/51G.DIR.phi_Max_
10~90 90 deg 1
reverse direction element of
protection
The minimum operating
current setting for the direction
6 50/51G.DIR.3I0_Min (0.05~1)In 0.05 - 0.001
control element of earth fault
voltage setting for the direction
7 50/51G.DIR.3U0_Min 1~10 4 V 0.001
behaviour of earth fault
overcurrent protection when
VT circuit supervision function
is enabled and VT circuit
failure happens.
Disabled;
8 50/51G.En_VTS_Blk Disabled - - Disabled: earth fault
Enabled
overcurrent protection will not
affected by VT circuit failure
earth fault overcurrent
protection will be blocked by
VT circuit failure signal
harmonic control element of
9 50/51G.HMB.K_Hm2 0.1~1 0.2 - 0.001
protection
The current setting for
releasing the harmonic control
10 50/51G.HMB.I_Rls 2~150 20 A 0.001

Date: 2021-08-01

residual current that used for
stage 1 of earth fault
Ext; overcurrent protection
11 50/51G1.Opt_3I0 Ext - -
Cal Ext: the measured residual
current
Cal: the calculated residual
current
The current setting of stage 1
12 50/51G1.3I0_Set 0.05~200 15 A 0.001 of earth
protection
fault overcurrent
3
13 50/51G1.t_Op 0 ~100 0.1 s 0.001 stage 1 of earth fault
14 50/51G1.t_DropOut 0 ~100 0 s 0.001 stage 1 of earth fault
Non_Direction The setting used to select the
al; Non_Directio directional mode of stage 1 of
15 50/51G1.Opt_Dir - -
Forward; nal earth fault overcurrent
Reverse protection.
enabling/disabling the
the stage 1 of earth fault
Disabled: stage 1 of earth fault
Disabled;
16 50/51G1.En_Hm_Blk Disabled - - overcurrent protection is not
Enabled
control element
Enabled: stage 1 of earth fault
control element
Disabled; enabling/disabling the stage 1
17 50/51G1.En Enabled - -
Enabled of earth fault overcurrent
protection
Enabling stage 1 earth fault
Trp;
18 50/51G1.Opt_Trp/Alm Trp - - to trip or alarm.
Alm

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
inverse-time operation
ANSILT;
19 50/51G1.Opt_Curve IECDefTime - - characteristic curve of stage 1
IECN;
of earth fault overcurrent
3 IECV;
IEC;
protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
characteristic curve of stage 1
Inst; of earth fault overcurrent
50/51G1.Opt_Curve_
20 DefTime; Inst - - protection
DropOut
DefTime: definite-time
drop-out
21 50/51G1.TMS 0.04~ 20 1 - 0.001 stage 1 of earth fault
22 50/51G1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of earth fault
0.000
23 50/51G1.K 0.001~120 0.14 - operation characteristic of
1
0.000
24 50/51G1.Alpha 0.01 ~3 0.02 - operation characteristic of
1

Date: 2021-08-01

0.000
25 50/51G1.C 0 ~1.2 0 - operation characteristic of
1
26 50/51G2.Opt_3I0 Ext - -
current
3
current
27 50/51G2.3I0_Set 0.05~200 15 A 0.001 of earth fault overcurrent
protection
30 50/51G2.Opt_Dir - -
Reverse protection.
Disabled;
Enabled
control element
control element
protection

Date: 2021-08-01

Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
3 ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G2.Opt_Curve_
DropOut
drop-out
0.000
1

Date: 2021-08-01

0.000
1
0.000
1
3
41 50/51G3.Opt_3I0 Ext - -
current
current
protection
45 50/51G3.Opt_Dir - -
Reverse protection.

Date: 2021-08-01

Disabled;
Enabled
control element
3 Enabled: stage 3 of earth fault

control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

50/51G3.Opt_Curve_
DropOut
drop-out
51 50/51G3.TMS 0.04~ 20 1 - 0.001

3
0.000
1
0.000
1
0.000
1
56 50/51G4.Opt_3I0 Ext - -
current
current
protection

Date: 2021-08-01

60 50/51G4.Opt_Dir - -
3 Reverse protection.
Disabled;
Enabled
control element
control element
protection
Trp;
Alm

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
protection. 3
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G4.Opt_Curve_
DropOut
drop-out
0.000
1
0.000
1

Date: 2021-08-01

0.000
1
71 50/51G5.Opt_3I0 Ext - -
3 Cal Ext: the measured residual
current
current
protection
75 50/51G5.Opt_Dir - -
Reverse protection.
Disabled;
Enabled
control element
control element
protection

Date: 2021-08-01

Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
3
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G5.Opt_Curve_
DropOut
drop-out
0.000
1

Date: 2021-08-01

0.000
1
0.000
1
86 50/51G6.Opt_3I0 Ext - -
current
current
protection
90 50/51G6.Opt_Dir - -
Reverse protection.

Date: 2021-08-01

Disabled;
Enabled
control element
3
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

50/51G6.Opt_Curve_
DropOut
drop-out
3 96 50/51G6.TMS 0.04~ 20 1 - 0.001

0.000
1
0.000
1
0.000
1
3.8 Another Group of Earth Fault Overcurrent Protection

For the applications of some grounding transformers and station transformers that two sets of
residual currents are required, the device provides another group of earth fault overcurrent
protection.
The device can provide six stages of another group of earth fault overcurrent protection with
independent logic. Each stage can be independently set as definite-time characteristics or
inverse-time characteristics. The drop-out characteristics can be set as instantaneous drop-out,
definite-time drop-out or inverse-time drop-out. The protection fixedly adopts the measured
residual current, the calculated residual current is not supported. It can operate to trip or alarm, it

Date: 2021-08-01
can be enabled or blocked by the external binary input.
Another group of earth fault overcurrent protection can be enabled or disabled via the settings or
binary input signals, for some specific applications, the protection needs to be blocked by the
external signal, so the device provides a function block input signal to be used to block another
group of earth fault overcurrent protection. The enabling and blocking logic of another group of
earth fault overcurrent protection is shown in the figure below:
EN A.50/51Gx.En &
A.50/51Gx.On
SIG A.50/51Gx.Enable
&
3
SIG A.50/51Gx.Block ≥1 A.50/51Gx.Blocked
SIG Fail_Device
&
A.50/51Gx.Valid
Figure 3.8-1 The enabling and blocking logic of another group of earth fault overcurrent protection
The logic diagram of the fault detector element of another group of earth fault overcurrent
protection is as follows:
SET 3I0>0.95*[A.50/51Gx.3I0_Set] & A.50/51Gx.Pkp

0 500ms
&
SIG A.50/51Gx.On &
FD.Pkp
SIG A.50/51Gx.Valid
EN [A.50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.8-2 Logic diagram of the fault detector element of another group of earth fault overcurrent
protection
Another group of earth fault overcurrent protection can operate without time delay or operate with
a definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets
the IEC60255-3 and ANSI C37.112 standards. Another group of earth fault overcurrent protection
can support definite-time limit, IEC & ANSI standard inverse time limit and user-defined
inverse-time limit, users can select the wanted operating curve by the setting
[A.50/51Gx.Opt_Curve], the relationship between the value of the setting and the curve is shown
in the table below.
A.50/51Gx.Opt_Curve Time Characteristic k α c tr


Date: 2021-08-01
A.50/51Gx.Opt_Curve Time Characteristic k α c tr

3 IECST IEC Short-time inverse 0.05 0.04 0 -
Only when the setting [A.50/51Gx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [A.50/51Gx.K], [A.50/51Gx.C] and
[A.50/51Gx.Alpha] are useful, the inverse-time operating curve is determined by the three
settings.
When I 0 > I 0 p , the protection operates immediately.
[A.50/51Gx.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
I0p I0
Figure 3.8-3 Definite-time operation characteristic curve of another group of earth fault overcurrent
protection

Date: 2021-08-01
affected by the applied current I 0 . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [A.50/51Gx.tmin]. The inverse-time
operation characteristic equation is:
 k 
t =  
+ c   TMS
(I 0 / I 0P ) − 1 
Where:
I 0 p is the current setting [A.50/51Gx.3I0_Set];

3
TMS is the inverse-time time multiplier, i.e. the setting [A.50/51Gx.TMS];
k is the inverse-time coefficient K, i.e. the setting [A.50/51Gx.K];

c is the inverse-time coefficient C, i.e. the setting [A.50/51Gx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [A.50/51Gx.Alpha];
I 0 is the measured zero-sequence current.

t min
I0P ID I0
Figure 3.8-4 Inverse-time operation characteristic curve of another group of earth fault overcurrent
protection
When the applied zero-sequence current I 0 is not a fixed value, but changes with time, the

Date: 2021-08-01
T0
1
 t ( I )dt
0 0
=1
Where:
t(I0) is the theoretical operating time when the current is I 0 .
The supported drop-out characteristics of another group of earth fault overcurrent protection
3 include instantaneous drop-out, definite-time drop-out and ANSI inverse-time drop-out.

When I 0 <0.95* I 0 p , the protection drops out with a time delay of tdr (i.e. the value of the
setting [A.50/51Gx.t_DropOut]), and the drop-out characteristic curve is shown in the following
figure:

Date: 2021-08-01
Start time
I0>I0p
Start
signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.8-5 Definite-time drop-out characteristic of another group of earth fault overcurrent protection
tp
1
Itp =  t(I
0
0
dt
)
TR
1
I tp − t
0 R (I )
dt = 0
Where:

When I 0 <0.95* I 0 p , the inverse-time drop-out characteristic equation is as follows:

Date: 2021-08-01
 tr 
tR =  2
 TMS
1 − ( I / I P ) 
Where:
IP is the current setting [A.50/51Gx.3I0_Set];
TMS is the inverse-time factor, i.e. the setting [A.50/51Gx.TMS];
3 I 0 is the measured current.

tr
I0 P I0
Figure 3.8-6 Inverse-time drop-out characteristic curve of another group of earth fault overcurrent
protection

Date: 2021-08-01
Start time
I0>I0p
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter

Dropout time
Dropout time
Figure 3.8-7 Inverse-time drop-out characteristic of another group of earth fault overcurrent protection
A.50/51G
A.50/51Gx.On
A.50/51Gx.Enable A.50/51Gx.Blocked
A.50/51Gx.Block A.50/51Gx.Valid
A.50/51Gx.St
A.50/51Gx.Op
A.50/51Gx.Alm
3.8.3 I/O Signal

Stage x of another group of earth fault overcurrent protection enabling input, it
1 A.50/51Gx.Enable
is triggered from binary input or programmable logic etc. (x=1~6)
Stage x of another group of earth fault overcurrent protection blocking input, it
2 A.50/51Gx.Block
1 A.50/51Gx.On Stage x of another group of earth fault overcurrent protection is enabled
2 A.50/51Gx.Blocked Stage x of another group of earth fault overcurrent protection is blocked
3 A.50/51Gx.Valid Stage x of another group of earth fault overcurrent protection is valid
4 A.50/51Gx.St Stage x of another group of earth fault overcurrent protection starts

Date: 2021-08-01
5 A.50/51Gx.Op Stage x of another group of earth fault overcurrent protection operates

6 A.50/51Gx.Alm Stage x of another group of earth fault overcurrent protection alarms
3.8.4 Logic
A.50/51Gx.St
Timer &
SET 3I0>[A.50/51Gx.3I0_Set] & A.50/51Gx.Op
t
t
SIG A.50/51Gx.Pkp
SET [A.50/51Gx.Opt_Trp/Alm] = Trp &

3 A.50/51Gx.Alm
SET [A.50/51Gx.Opt_Trp/Alm] = Alm
Figure 3.8-8 Logic diagram of another group of earth fault overcurrent protection
3.8.5 Settings
Access path: MainMenu  Settings  Protection Settings  ROC2 Settings

The current setting of stage
1 A.50/51G1.3I0_Set 0.05~200 15 A 0.001 1 of another group of earth
fault overcurrent protection
stage 1 of another group of
2 A.50/51G1.t_Op 0 ~100 0.1 s 0.001
protection
3 A.50/51G1.t_DropOut 0 ~100 0 s 0.001
protection
Disabled; enabling/disabling the stage
4 A.50/51G1.En Enabled - -
Enabled 1 of another group of earth
Enabling stage 1 of another
group of earth fault
Trp; overcurrent protection
5 A.50/51G1.Opt_Trp/Alm Trp - -
Alm operate to trip or alarm.

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
6 A.50/51G1.Opt_Curve IECDefTime - - characteristic curve of stage
IECN;
1 of another group of earth
IECV;
IEC;
fault overcurrent protection. 3
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
characteristic curve of stage
Inst; 1 of another group of earth
A.50/51G1.Opt_Curve
7 DefTime; Inst - - fault overcurrent protection
_DropOut
drop-out
8 A.50/51G1.TMS 0.04~ 20 1 - 0.001
protection
setting of stage 1 of another
9 A.50/51G1.tmin 0 ~10 0.02 s 0.001
0.000 operation characteristic of
10 A.50/51G1.K 0.001~120 0.14 -
1 stage 1 of another group of
protection

Date: 2021-08-01

11 A.50/51G1.Alpha 0.01 ~3 0.02 -
protection
12 A.50/51G1.C 0 ~1.2 0 -
3 1 stage 1 of another group of
protection
14 A.50/51G2.t_Op 0 ~100 0.1 s 0.001
protection
15 A.50/51G2.t_DropOut 0 ~100 0 s 0.001
protection

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
A.50/51G2.Opt_Curve
_DropOut
drop-out
20 A.50/51G2.TMS 0.04~ 20 1 - 0.001
protection
21 A.50/51G2.tmin 0 ~10 0.02 s 0.001
22 A.50/51G2.K 0.001~120 0.14 -
protection

Date: 2021-08-01

23 A.50/51G2.Alpha 0.01 ~3 0.02 -
protection
24 A.50/51G2.C 0 ~1.2 0 -
protection
26 A.50/51G3.t_Op 0 ~100 0.1 s 0.001
protection
27 A.50/51G3.t_DropOut 0 ~100 0 s 0.001
protection

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
A.50/51G3.Opt_Curve_D
ropOut
drop-out
32 A.50/51G3.TMS 0.04~ 20 1 - 0.001
protection
33 A.50/51G3.tmin 0 ~10 0.02 s 0.001
34 A.50/51G3.K 0.001~120 0.14 -
protection

Date: 2021-08-01

35 A.50/51G3.Alpha 0.01 ~3 0.02 -
protection
36 A.50/51G3.C 0 ~1.2 0 -
protection
38 A.50/51G4.t_Op 0 ~100 0.1 s 0.001
protection
39 A.50/51G4.t_DropOut 0 ~100 0 s 0.001
protection

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
drop-out
44 A.50/51G4.TMS 0.04~ 20 1 - 0.001
protection
45 A.50/51G4.tmin 0 ~10 0.02 s 0.001
46 A.50/51G4.K 0.001~120 0.14 -
protection

Date: 2021-08-01

47 A.50/51G4.Alpha 0.01 ~3 0.02 -
protection
48 A.50/51G4.C 0 ~1.2 0 -
protection
50 A.50/51G5.t_Op 0 ~100 0.1 s 0.001
protection
51 A.50/51G5.t_DropOut 0 ~100 0 s 0.001
protection

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
drop-out
56 A.50/51G5.TMS 0.04~ 20 1 - 0.001
protection
57 A.50/51G5.tmin 0 ~10 0.02 s 0.001
58 A.50/51G5.K 0.001~120 0.14 -
protection

Date: 2021-08-01

59 A.50/51G5.Alpha 0.01 ~3 0.02 -
protection
60 A.50/51G5.C 0 ~1.2 0 -
protection
62 A.50/51G6.t_Op 0 ~100 0.1 s 0.001
protection
63 A.50/51G6.t_DropOut 0 ~100 0 s 0.001
protection

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
drop-out
68 A.50/51G6.TMS 0.04~ 20 1 - 0.001
protection
69 A.50/51G6.tmin 0 ~10 0.02 s 0.001
70 A.50/51G6.K 0.001~120 0.14 -
protection

Date: 2021-08-01

71 A.50/51G6.Alpha 0.01 ~3 0.02 -
protection
72 A.50/51G6.C 0 ~1.2 0 -
protection
3.9 Negative-sequence Overcurrent Protection (50/51Q)

When a phase-to-phase fault occurs in the system, the fault current is small, and the phase
current criterion may not be able to detect the fault. At this time, the negative-sequence
overcurrent protection with higher sensitivity can be used. Negative-sequence overcurrent
protection can also be used to detect the broken phase operation or load unbalance.
The device can provide two stages of negative-sequence overcurrent protection with independent
logic. Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The drop-out characteristics can be set as instantaneous drop-out, definite-time
drop-out or inverse-time drop-out. For a double-circuit or a ring network line, the
negative-sequence fault current may have different flow direction. Considering the protection
selectivity, the negative-sequence overcurrent protection can be blocked by the direction control
element. Negative-sequence overcurrent protection can operate to trip or alarm, it can be enabled
or blocked by the external binary input.
Negative-sequence overcurrent protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, the protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block negative-sequence
overcurrent protection. The enabling and blocking logic of negative-sequence overcurrent
protection is shown in the figure below:

Date: 2021-08-01
EN [50/51Qx.En] &
50/51Qx.On
SIG 50/51Qx.Enable
&
SIG 50/51Qx.Block ≥1 50/51Qx.Blocked
SIG Fail_Device
&
50/51Qx.Valid
Figure 3.9-1 The enabling and blocking logic of negative-sequence overcurrent protection
3
The logic diagram of the fault detector element of negative-sequence overcurrent protection is as
follows:
SET I2>0.95×[50/51Qx.I2_Set] & 50/51Qx.Pkp

0 500ms &
SIG 50/51Qx.On &
FD.Pkp
SIG 50/51Qx.Valid
SET [50/51Qx.Opt_Trp/Alm]=Alm
Figure 3.9-2 Logic diagram of the fault detector element of negative-sequence overcurrent protection
In order to ensure the selectivity of negative-sequence overcurrent protection, direction control

element is introduced. The setting [50/51Qx.Opt_Dir] (x=1 and 2) is used for users to select the
directional mode of each stage of negative-sequence overcurrent protection: no direction, forward
direction and reverse direction are selectable.
The operation boundary of the forward direction element can be set by [50/51Q.DIR.phi_Min_Fwd]
and [50/51Q.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51Q.DIR.phi_Min_Rev] and [50/51Q.DIR.phi_Max_Rev].
For the direction control element of negative-sequence overcurrent protection, the

negative-sequence voltage is polarized, the operation characteristic is shown as below.

Date: 2021-08-01
-U2
[50/51Q.DIR.phi_Min_Fwd]
Non-operating I2
area
[50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction
[50/51Q.DIR.RCA]
3 Operating area in
reverse direction
[50/51Q.DIR.phi_Max_Fwd]
Non-operating
area
[50/51Q.DIR.phi_Min_Rev]
Figure 3.9-3 The direction element operation characteristics of negative-sequence overcurrent protection
Where:
[50/51Q.DIR.RCA].

-[50/51Q.DIR.phi_Min_Fwd]<angle<[50/51Q.DIR.phi_Max_Fwd]

180-[50/51Q.DIR.phi_Min_Rev]<angle<180+[50/51Q.DIR.phi_Max_Rev]
Polarized
voltage
Negative-sequence
Negative-sequence current I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA
voltage polarized
operating current must be greater than the minimum operating current setting
[50/51Q.DIR.I2_Min], otherwise the direction element can not operate. The polarized voltage must
be greater than the minimum operating voltage setting [50/51Q.DIR.U2_Min], otherwise the
direction element can not operate.

Date: 2021-08-01
EN [50/51Q.En_VTS_Blk] &
SIG VTS.Alm & >=1

&
SIG I2
direction
Forward
criterion
50/51Q.FwdDir.Op
SIG U2
EN [En_VT] &
SIG Prot.BI_En_VT 3
SET Iop>[50/51Q.DIR.I_Min]
SET Upo>[50/51Q.DIR.U_Min]
EN [50/51Q.En_VTS_Blk] &
SIG VTS.Alm & >=1

SIG I2 &
direction
Reverse
criterion
50/51Q.RevDir.Op
SIG U2
EN [En_VT] &
SIG Prot.BI_En_VT
SET Iop>[50/51Q.DIR.I2_Min]
SET Upo>[50/51Q.DIR.U2_Min]
Figure 3.9-4 Logic diagram of forward and reverse direction element of negative-sequence overcurrent
protection
Where:
I2: the negative-sequence current.
U2: the negative-sequence voltage.
Negative-sequence overcurrent protection can operate instantaneously or operate with a

definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets the
IEC60255-3 and ANSI C37.112 standards. Negative-sequence overcurrent protection can support
definite-time limit, IEC & ANSI standard inverse time limit and user-defined inverse-time limit,

Date: 2021-08-01
users can select the wanted operating curve by the setting [50/51Qx.Opt_Curve] (x=1 or 2), the
relationship between the value of the setting and the curve is shown in the table below.
50/51Qx.Opt_Curve Time Characteristic k α c tr

3 ANSILT ANSI Long Time Inverse 0.086 0.02 0.185 4.6
Only when the setting [50/51Qx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Qx.K], [50/51Qx.C] and [50/51Qx.Alpha]
⚫ Without time delay (Instantaneously)
When I 2 > I 2 p , the protection operates immediately.
[50/51Qx.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2021-08-01
t op
I2p I2
Figure 3.9-5 Definite-time operation characteristic curve of negative-sequence overcurrent protection
affected by the applied current I 2 . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Qx.tmin]. The inverse-time
k
t={ α + c} × TMS
(I2 ⁄I2p ) − 1
Where:
I 2 p is the current setting [50/51Qx.I2_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51Qx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Qx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Qx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Qx.Alpha];
I 2 is the measured negative-sequence current.


Date: 2021-08-01
3 t min
I2P ID I2
Figure 3.9-6 Inverse-time operation characteristic curve of negative-sequence overcurrent protection
When the applied negative-sequence overcurrent current I 2 is not a fixed value, but changes
with time, the operating behaviour of the protection is shown in the following equation:
T0
1
∫ dt = 1
t(I2 )
0
Where:
t(I2) is the theoretical operating time when the current is I2 .

The supported drop-out characteristics of the negative-sequence overcurrent protection include



Date: 2021-08-01
When I 2 <0.95* I 2 p , the protection drops out with a time delay of tdr (i.e. the value of the setting
[50/51Qx.t_DropOut]), and the drop-out characteristic curve is shown in the following figure:
Start time
I2>I2p
Start
3
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.9-7 Definite-time drop-out characteristic of negative-sequence overcurrent protection
tp
1
I tp =  dt
0
t(I2 )
TR
1
I tp −  dt = 0
0
tR ( I 2 )

Date: 2021-08-01
Where:
tR( I 2 ) is the drop-out characteristic equation
When I 2 <0.95* I 2 p , the inverse-time drop-out characteristic equation is as follows:
tr
t R (I2 ) = { 2} × TMS
1 − (I2 /I2p )
3
Where:
I 2 p is the current setting [50/51Qx.I2_Set];
TMS is the inverse-time factor, i.e. the setting [50/51Qx.TMS];
I 2 is the measured negative-sequence current.
tr
Figure 3.9-8 Inverse-time drop-out characteristic curve of negative-sequence overcurrent protection

Date: 2021-08-01
Start time
I2>I2p
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter

Dropout time
Dropout time
Figure 3.9-9 Inverse-time drop-out characteristic of negative-sequence overcurrent protection
50/51Q
50/51Qx.On
50/51Qx.Enable
50/51Qx.Blocked
50/51Qx.Block
50/51Qx.Valid
50/51Qx.St
50/51Qx.Op
50/51Qx.Alm
50/51Q.FwdDir.Op
50/51Q.RevDir.Op
3.9.3 I/O Signal

Stage x of negative-sequence overcurrent protection enabling input, it is
1 50/51Qx.Enable
triggered from binary input or programmable logic etc. (x=1~2)
Stage x of negative-sequence overcurrent protection blocking input, it is
2 50/51Qx.Block
1 50/51Qx.On Stage x of negative-sequence overcurrent protection is enabled
2 50/51Qx.Blocked Stage x of negative-sequence overcurrent protection is blocked

Date: 2021-08-01
3 50/51Qx.Valid Stage x of negative-sequence overcurrent protection is valid

4 50/51Qx.St Stage x of negative-sequence overcurrent protection starts
5 50/51Qx.Op Stage x of negative-sequence overcurrent protection operates
6 50/51Qx.Alm Stage x of negative-sequence overcurrent protection alarms
The forward direction element of negative-sequence overcurrent protection
7 50/51Q.FwdDir.Op
operates
The reverse direction element of negative-sequence overcurrent protection
8 50/51Q.RevDir.Op
operates
3.9.4 Logic
3 SET I2>[50/51Qx.I2_Set]
50/51Qx.St
SIG 50/51Q.FwdDir.Op
&
& Timer
selection
Direction
t
SIG 50/51Q.RevDir.Op
t
SET [50/51Qx.Opt_Dir]
SIG 50/51Qx.Pkp
&
50/51Qx.Op
SET [50/51Qx.Opt_Trp/Alm]=Trp
&
50/51Qx.Alm
SET [50/51Qx.Opt_Trp/Alm]=Alm
Figure 3.9-10 Logic diagram of negative-sequence overcurrent protection
3.9.5 Settings
Access path: MainMenu  Settings  Protection Settings  NegOC Settings

1 50/51Q.DIR.RCA -180~179 45 deg 1
element of negative-sequence
50/51Q.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd negative-sequence
50/51Q.DIR.phi_Max forward direction element of
3 10~90 90 deg 1
_Fwd negative-sequence
50/51Q.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
Rev negative-sequence

Date: 2021-08-01

50/51Q.DIR.phi_Max reverse direction element of
5 10~90 90 deg 1
_Rev negative-sequence
6 50/51Q.DIR.I2_Min (0.05~1)In 0.05 - 0.001 control element of
negative-sequence
The minimum operating 3
7 50/51Q.DIR.U2_Min 1.0~10.0 4 V 0.001 control element of
negative-sequence
behaviour of
negative-sequence
failure happens.
Disabled;
8 50/51Q.En_VTS_Blk Disabled - - Disabled: negative-sequence
Enabled
negative-sequence
overcurrent protection will be
blocked by VT circuit failure
signal
9 50/51Q1.I2_Set 0.05~200 15 A 0.001 of negative-sequence
10 50/51Q1.t_Op 0.03 ~100 0.1 s 0.001 stage 1 of negative-sequence
11 50/51Q1.t_DropOut 0 ~100 0 s 0.001 stage 1 of negative-sequence
al Non_Directio directional mode of stage 1 of
12 50/51Q1.Opt_Dir - -
Forward nal negative-sequence
Reverse overcurrent protection.

Date: 2021-08-01

13 50/51Q1.En Enabled - -
Enabled of negative-sequence
Enabling stage 1 of
negative-sequence
Trp; overcurrent protection operate
14 50/51Q1.Opt_Trp/Alm Trp - -
Alm to trip or alarm.
3 Alm: for alarm purpose

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
15 50/51Q1.Opt_Curve IECDefTime - - characteristic curve of stage 1
IECN;
of negative-sequence
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst; of negative-sequence
50/51Q1.Opt_Curve_
16 DefTime; Inst - - overcurrent protection
DropOut
drop-out
17 50/51Q1.TMS 0.04~ 20 1 - 0.001 stage 1 of negative-sequence
setting of stage 1 of
18 50/51Q1.tmin 0 ~10 0.02 s 0.001
negative-sequence

Date: 2021-08-01

19 50/51Q1.K 0.001~120 0.14 - 0.0001 operation characteristic of
stage 1 of negative-sequence
20 50/51Q1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
3
21 50/51Q1.C 0 ~1.2 0 - 0.0001 operation characteristic of
25 50/51Q2.Opt_Dir - -
Enabling stage 2 of
negative-sequence

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
3 IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51Q2.Opt_Curve_
DropOut
drop-out
31 50/51Q2.tmin 0 ~10 0.02 s 0.001
negative-sequence

Date: 2021-08-01

3.10 Broken Conductor Protection (46BC)

Single-phase earthing fault and two-phases earthing fault are the most common fault on circuits,
the fault is easy to detect because the fault current will increase obviously.
3
Broken-conductor fault is difficult to detect since there is no increase of current but
negative-sequence current, so negative-sequence overcurrent protection can be considered to
detect broken-conductor fault. However, under heavy load condition, negative-sequence current is
relative large due to unbalance loading, but negative-sequence current because of
broken-conductor fault under light load condition is relative small. If negative-sequence current
protection is set larger than maximum negative-sequence current under loading,
negative-sequence overcurrent protection may be failure to operate if broken-conductor fault
happens under light load condition, negative-sequence overcurrent protection is therefore not
suitable to apply for broken-conductor fault.
The network of single-phase broken condition is similar to that of two-phases earthing fault,
positive-sequence, negative-sequence and zero-sequence network is connected in parallel, I2/I1=
Z0/(Z0+Z2), generally, zero-sequence impedance is larger than positive-sequence impedance, i.e.
I2/I1>0.5. The network of two-phases broken condition is similar to that of single-phase earthing
fault, positive-sequence, negative-sequence and zero-sequence network is connected in series,
so I2/I1=1. Hence, broken conductor protection based on the ratio of negative-sequence current to
positive sequence current can detect the broken-conductor fault.
Broken-conductor fault mainly is single-phase broken or two-phases broken. According to the ratio
of negative-sequence current to positive-sequence current (I2/I1), it is used to judge whether there
is a broken-conductor fault. Negative-sequence current under normal operating condition (i.e.
unbalance current) is due to CT error and unbalance load, so the ratio of negative-sequence
current to positive-sequence current (amplitude) is relative steady. The value with margin can then
be used as the setting of broken conductor protection. It is mainly used to detect broken-conductor
fault and CT circuit failure as well.

Date: 2021-08-01
46BC
46BC.Enable 46BC.On
46BC.Block 46BC.Blocked
46BC.Valid
46BC.St
46BC.Op
3 46BC.Alm
3.10.3 I/O Signals

1 46BC.Enable Input signal of enabling broken conductor protection
2 46BC.Block Input signal of blocking broken conductor protection
1 46BC.On Broken conductor protection is enabled.
2 46BC.Blocked Broken conductor protection is blocked.
3 46BC.Valid Broken conductor protection is valid.
4 46BC.St Broken conductor protection starts.
5 46BC.Op Broken conductor protection operates.
6 46BC.Alm Broken conductor protection alarms.

Date: 2021-08-01
3.10.4 Logic
EN [46BC.En] &
46BC.On
SIG 46BC.Enable
&
SIG 46BC.Block >=1 46BC.Blocked
SIG Fail_Device
&
46BC.Valid
SIG 46BC.Valid
3
SET Ia>[46BC.I_Min]
>=1 &
SET Ib>[46BC.I_Min] 46BC.St
SET Ic>[46BC.I_Min]
[46BC.t_Op] 0ms &
SET I2/I1>[46BC.I2/I1_Set]
46BC.Op
SET [46BC.Opt_Trp/Alm]=Trp
&
46BC.Alm
SET [46BC.Opt_Trp/Alm]=Alm
Figure 3.10-1 Logic of broken conductor protection
3.10.5 Settings
Access path: MainMenu  Settings  Protection Settings  BCP Settings
No. Setting Range Default Unit Step Description

Minimum operating current setting of
1 46BC.I_Min (0.05~40) In 1.000 A 0.001
broken conductor protection
Ratio setting (negative-sequence
2 46BC.I2/I1_Set 0~5 0.500 - 0.001 current to positive-sequence current) of
Time delay of broken conductor
3 46BC.t_Op 0~10 1.000 s 0.001
protection
Disabled Enabling/disabling broken conductor
4 46BC.En Enabled - -
Enabled protection
Enabling/disabling broken conductor
Trp protection operate to trip or alarm
5 46BC.Opt_Trp/Alm Trp - -
Alm Trp: for tripping purpose
3.11 Sensitive Earth Fault Protection (50/51SEF)

If a single-phase earth fault occurs in some non-effectively grounded systems, the amplitude of

Date: 2021-08-01
the earth current is small due to the large ground resistance, so it is difficult to detect by the
ordinary CTs. Sensitive earth fault protection using high-precision CT can effectively detect the
earth current.
The device can provide six stages of sensitive earth fault protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics.
The drop-out characteristics can be set as instantaneous drop-out, definite-time drop-out or
inverse-time drop-out. Users can choose whether it is blocked by the direction control element.
The direction control element can be set as no direction, forward direction and reverse direction.
3 The zero-sequence current used by sensitive earth fault protection is the measured
zero-sequence current from the high-precision CT. Sensitive earth fault protection can operate to
trip or alarm, it can be enabled or blocked by the external binary input.
Sensitive earth fault protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, the protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block sensitive earth fault protection.
The enabling and blocking logic of sensitive earth fault protection is shown in the figure below:
EN 50/51SEFx.En &
50/51SEFx.On
SIG 50/51SEFx.Enable
&
SIG 50/51SEFx.Block ≥1 50/51SEFx.Blocked
SIG Fail_Device
&
50/51SEFx.Valid
Figure 3.11-1 The enabling and blocking logic of sensitive earth fault protection
The logic diagram of the fault detector element of sensitive earth fault protection is as follows:
SET Isef>0.95*[50/51SEFx.3I0_Set] & 50/51SEFx.Pkp

0 500ms
&
SIG 50/51SEFx.On &
FD.Pkp
SIG 50/51SEFx.Valid
EN [50/51SEFx.Opt_Trp/Alm]=Alm
Figure 3.11-2 Logic diagram of the fault detector element of sensitive earth fault protection
In order to ensure the selectivity of sensitive earth fault protection, direction control element is
introduced. The setting [50/51SEFx.Opt_Dir] (x: 1~6) is used for users to select the directional

Date: 2021-08-01
mode of each stage of sensitive earth fault protection: no direction, forward direction and reverse
-U0
[50/51SEF.DIR.phi_Min_Fwd]
Non-operating Isef
area
Operating area in
[50/51SEF.DIR.phi_Max_Rev] forward direction
3
[50/51SEF.DIR.RCA]
Operating area in
reverse direction
[50/51SEF.DIR.phi_Max_Fwd]
Non-operating
area
[50/51SEF.DIR.phi_Min_Rev]
Figure 3.11-3 The direction element operation characteristics of sensitive earth fault protection
Where:
[50/51SEF.DIR.RCA].
The operation boundary of the forward direction element can be set by

[50/51SEF.DIR.phi_Min_Fwd] and [50/51SEF.DIR.phi_Max_Fwd].
The operation boundary of the reverse direction element can be set as

[50/51SEF.DIR.phi_Min_Rev] and [50/51SEF.DIR.phi_Max_Rev].
-[50/51SEF.DIR.phi_Min_Fwd]<angle<[50/51SEF.DIR.phi_Max_Fwd]
180-[50/51SEF.DIR.phi_Min_Rev]<angle<180+[50/51SEF.DIR.phi_Max_Rev]
Polarized
voltage
Zero-sequence The sensitive earth fault current -3U0 Angle=Angle(-3U0)-Angle(Isef)-RCA

Date: 2021-08-01
voltage polarized Isef
operating current must be greater than the minimum operating current setting
[50/51SEF.DIR.3I0_Min], otherwise the direction element can not operate. The polarized voltage
must be greater than the minimum operating voltage setting [50/51SEF.DIR.3U0_Min], otherwise
the direction element can not operate.
3 EN [50/51SEF.En_VTS_Blk] &
SIG VTS.Alm & >=1

&
SIG Isef
direction
Forward
criterion
50/51SEF.FwdDir.Op
SIG 3U0_Cal
EN [En_VT] &
SIG Prot.BI_En_VT
SET Iop>[50/51SEF.DIR.I_Min]
SET Upo>[50/51SEF.DIR.U_Min]
EN [50/51SEF.En_VTS_Blk] &
SIG VTS.Alm & >=1

SIG Isef &
direction
Reverse
criterion
50/51SEF.RevDir.Op
SIG 3U0_Cal
EN [En_VT] &
SIG Prot.BI_En_VT
SET Iop>[50/51SEF.DIR.3I0_Min]
SET Upo>[50/51SEF.DIR.3U0_Min]
Figure 3.11-4 Logic diagram of forward and reverse direction element of sensitive earth fault protection
Where:
Isef: the sensitive earth fault current.
3U0_Cal: the calculated residual voltage.

Date: 2021-08-01
Sensitive earth fault protection can operate without time delay or operate with a definite-time limit,
it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and
ANSI C37.112 standards. Sensitive earth fault protection can support definite-time limit, IEC &
ANSI standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51SEFx.Opt_Curve] (x=1~6), the relationship between the
value of the setting and the curve is shown in the table below.
50/51SEFx.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely Inverse 28.2 2.0 0.1217 29.1 3
Only when the setting [50/51SEFx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51SEFx.K], [50/51SEFx.C] and
[50/51SEFx.Alpha] are useful, the inverse-time operating curve is determined by the three
settings.
When Isef > Isef _ set , the protection operates immediately.
When Isef > Isef _ set , the protection operates with a time delay of top (i.e. the value of the setting
[50/51SEFx.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2021-08-01
t op
I sef_set Isef
Figure 3.11-5 Definite-time operation characteristic curve of sensitive earth fault protection
When Isef > Isef _ set , the inverse-time accumulator begins to accumulate, and the operating time
is affected by the applied current Isef . The operating time will decrease with the current
increasing, but the operating time shall not less than tmin , i.e. the setting [50/51SEFx.tmin]. The
k
t={ + c} × TMS
(Isef ⁄Isef−set )α − 1
Where:
Isef _ set is the current setting [50/51SEFx.3I0_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51SEFx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51SEFx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51SEFx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51SEFx.Alpha];
Isef is the measured zero-sequence current.

Date: 2021-08-01
t min
3
I Sef_set ID Isef
Figure 3.11-6 Inverse-time operation characteristic curve of sensitive earth fault protection
When the applied zero-sequence current Isef is not a fixed value, but changes with time, the
T0
1
 t(I
0 sef )
dt = 1
Where:
t ( I sef ) is the theoretical operating time when the current is Isef .
The supported drop-out characteristics of the sensitive earth fault protection include

When Isef <0.95* Isef _ set , the protection drops out immediately.

Date: 2021-08-01
When Isef <0.95* Isef _ set , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51SEFx.t_DropOut]), and the drop-out characteristic curve is shown in the following
figure:
Start time
Isef>Isef_set
Start
signal
3
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.11-7 Definite-time drop-out characteristic of sensitive earth fault protection
When Isef > Isef _ set , the inverse-time operating accumulator begins to accumulate, the
accumulated value after t p (Assuming t p is less than the theoretical operating time) is
calculated according to the following equation:
tp
1
I tp =  t(I
0 sef )
dt
At this time, if Isef <0.95* Isef _ set , the protection element starts drop-out, and the drop-out
TR
1
I tp −  dt = 0
0
t R ( I sef )
Where:

Date: 2021-08-01
tR ( I sef ) is the drop-out characteristic equation
When Isef <0.95* Isef _ set , the inverse-time drop-out characteristic equation is as follows:
tr
t R (I) = 2 × TMS
I
1 − (I sef )
{ sef_set }
Where:
Isef _ set is the current setting [50/51SEFx.3I0_Set];

3
TMS is the inverse-time factor, i.e. the setting [50/51SEFx.TMS];
Isef is the measured current.
When 0.95* Isef _ set < Isef < Isef _ set , the accumulator will neither accumulate nor drop out
tr
Isef_set Isef
Figure 3.11-8 Inverse-time drop-out characteristic curve of sensitive earth fault protection

Date: 2021-08-01
Start time
Isef>Isef_set
Start
signal
Operating
signal
3 Operating threshold
Protection
operate
Operating
counter

Dropout time
Dropout time
Figure 3.11-9 Inverse-time drop-out characteristic of sensitive earth fault protection
50/51SEF
50/51SEFx.Enable 50/51SEFx.On
50/51SEFx.Block 50/51SEFx.Blocked
50/51SEFx.Valid
50/51SEFx.St
50/51SEFx.Op
50/51SEFx.Alm
50/51SEF.FwdDir.Op
50/51SEF.RevDir.Op
3.11.3 I/O Signal

Stage x of sensitive earth fault protection enabling input, it is triggered from
1 50/51SEFx.Enable
Stage x of sensitive earth fault protection blocking input, it is triggered from
2 50/51SEFx.Block
1 50/51SEFx.On Stage x of sensitive earth fault protection is enabled

Date: 2021-08-01
2 50/51SEFx.Blocked Stage x of sensitive earth fault protection is blocked

3 50/51SEFx.Valid Stage x of sensitive earth fault protection is valid
4 50/51SEFx.St Stage x of sensitive earth fault protection starts
5 50/51SEFx.Op Stage x of sensitive earth fault protection operates
6 50/51SEFx.Alm Stage x of sensitive earth fault protection alarms
7 50/51SEF.FwdDir.Op The forward direction element of sensitive earth fault protection operates
8 50/51SEF.RevDir.Op The reverse direction element of sensitive earth fault protection operates
3.11.4 Logic
SET Isef>[50/51SEFX.3I0_Set]
50/51SEFx.St
3
SIG 50/51SEF.FwdDir.Op
&
& Timer
selection
Direction
t
SIG 50/51SEF.RevDir.Op
t
SET [50/51SEFx.Opt_Dir]
SIG 50/51SEFx.Pkp
&
50/51SEFx.Op
SET [50/51SEFx.Opt_Trp/Alm]=Trp
&
50/51SEFx.Alm
SET [50/51SEFx.Opt_Trp/Alm]=Alm
Figure 3.11-10 Logic diagram of sensitive earth fault protection
3.11.5 Settings
Access path: MainMenu  Settings  Protection Settings  SEF Settings

1 50/51SEF.DIR.RCA -180~179 45 deg 1 the direction control element of
sensitive earth fault protection
50/51SEF.DIR.phi_Mi
n_Fwd
50/51SEF.DIR.phi_M
ax_Fwd
50/51SEF.DIR.phi_Mi
n_Rev
50/51SEF.DIR.phi_M
ax_Rev

Date: 2021-08-01

50/51SEF.DIR.3I0_Mi setting for the direction control
6 (0.005~1)In 0.05 - 0.001
n element of sensitive earth fault
protection
50/51SEF.DIR.3U0_ setting for the direction control
7 1.0~10.0 4 V 0.001
Min element of sensitive earth fault
protection
3 behaviour of sensitive earth fault

50/51SEF.En_VTS_Bl Disabled; Disabled: sensitive earth fault
8 Disabled - -
k Enabled protection will not affected by VT
circuit failure
will be blocked by VT circuit
failure signal
9 50/51SEF1.3I0_Set 0.005~2 1 A 0.001
10 50/51SEF1.t_Op 0 ~100 0.1 s 0.001 stage 1 of sensitive earth fault
protection
50/51SEF1.t_DropOu
11 0 ~100 0 s 0.001 stage 1 of sensitive earth fault
t
protection
Non_Dire
12 50/51SEF1.Opt_Dir Forward - - directional mode of stage 1 of
ctional
Reverse sensitive earth fault protection.
Disabled;
13 50/51SEF1.En Enabled - - enabling/disabling the stage 1 of
Enabled
Enabling stage 1 of sensitive
earth fault protection operate to
50/51SEF1.Opt_Trp/ Trp;
14 Trp - - trip or alarm.
Alm Alm

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
50/51SEF1.Opt_Curv ANSILT; IECDefTi inverse-time operation
15 - -
e IECN; me characteristic curve of stage 1 of
IECV;
IEC;
sensitive earth fault protection.
3
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF1.Opt_Curv
16 DefTime; Inst - - sensitive earth fault protection
e_DropOut
17 50/51SEF1.TMS 0.04~ 20 1 - 0.001 stage 1 of sensitive earth fault
protection
18 50/51SEF1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of sensitive
earth fault protection
19 50/51SEF1.K 0.001~120 0.14 - 0.0001 operation characteristic of stage
1 of sensitive earth fault
protection
20 50/51SEF1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of stage
protection

Date: 2021-08-01

21 50/51SEF1.C 0 ~1.2 0 - 0.0001 operation characteristic of stage
protection
22 50/51SEF2.3I0_Set 0.005~2 1 A 0.001
3 protection
50/51SEF2.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
28 - -
IECV; sensitive earth fault protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

50/51SEF2.Opt_Curv
e_DropOut
protection
3
protection
protection
protection
35 50/51SEF3.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF3.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2021-08-01

Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
3 ANSIDefTime;
ANSILTE;
41 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF3.Opt_Curv
e_DropOut
protection
protection

Date: 2021-08-01

protection
protection
3
48 50/51SEF4.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF4.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
54 - -
3 IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF4.Opt_Curv
e_DropOut
protection
protection
protection

Date: 2021-08-01

protection
61 50/51SEF5.3I0_Set 0.005~2 1 A 0.001
protection 3
50/51SEF5.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
67 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

50/51SEF5.Opt_Curv
e_DropOut
3 protection
protection
protection
protection
74 50/51SEF6.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF6.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2021-08-01

Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
3
80 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF6.Opt_Curv
e_DropOut
protection
protection

Date: 2021-08-01

protection
3 protection
3.11.6 High Impedance Restricted Earth Fault Protection Application
The sensitive earth fault protection can be used as high impedance restricted earth fault
protection.
Restricted earth fault (REF) protection is used for the transformer single-phase winding earth fault,
and the protected winding must be earthed. In the case of delta windings, the winding must be
earthed via an earthing transformer, the earthing transformer is connected between the winding
and the CT. REF protection can be applied to protect two-winding transformer, three-winding
transformer or auto-transformer.
REF protection is a kind of differential protection, the differential current is the vector difference of
the neutral current (i.e. the current flowing in the neutral line) and the residual current of the
transformer incoming line. For an internal fault, the differential current is equal to the earth fault
current. REF protection operates on the fault current only, and is not dependent on load current,
this makes REF protection a very sensitive protection.
The sensitive earth fault protection can be used to accomplish the function of high impedance
restricted earth fault protection. Once it is used as high impedance restricted earth fault protection,
the direction control element should be disabled, and it will not be controlled by voltage element.
3.11.6.1 Function Description
The connected analog quantity of high impedance REF protection is the sum current of the
transformer incoming line three-phase current and the neutral point current. The device provides a
highly sensitive current input channel, and a large resistance is connected to the circuit. In order
to prevent the device from overvoltage, a varistor is generally connected in parallel. The details
are shown in the figure below:

Date: 2021-08-01
IH
*
HV side LV side
*
*
IH_NP
V *
Rstab
IREF
High impedance REF 3
High impedance REF protection has no restraint characteristics and it will trip when the input
current IREF is greater than the current threshold. The high impedance differential technology is
realized by connecting a sufficiently high impedance in the input circuit of the protection device,
which makes the differential voltage under external fault conditions lower than the voltage
corresponding to the operating current of the drive device. This ensures the stability against an
external fault, so high impedance REF protection only reflects the internal fault.
Normal CT1 Saturated CT2
Zm1 RW1 RL1 RL2 RW2 Zm2
Rstab If
Udiff_ext
High impedance REF
The above figure shows the high impedance REF protection schematic diagram, CT1 and CT2
are located at both ends of the protected equipment.
When an external fault occurs, assuming that CT1 transfers normally and CT2 is fully saturated in
the most severe case, the excitation impedance of CT2 (Zm2) is 0, then the maximum unbalance
voltage of the measurement circuit is:
Udiff_ext = If ∗ (R W2 + R L2 )
In where:
Udiff_ext is the maximum voltage that may be felt at both ends of the measurement circuit when an
external fault occurs.
If is the secondary current under the maximum external fault.

Date: 2021-08-01
R W2 is the secondary impedance of CT2
R L2 is the circuit resistance of CT2
By reasonably selecting the stable resistance R stab and setting the current setting value ISet to
make the product larger than Udiff_ext , the protection will be reliable and it will not mal-operate.
When an internal fault occurs, it is equivalent to injecting current into the parallel CT excitation
impedance and protection measurement circuit. The shunt ratio of the two determines the fault
current magnitude felt by the device. Because the excitation impedance of the CT is usually very
large, the fault current is also very large, and the operating current setting is small, so the device
can feel a large operating current for internal fault and operate reliably.
3 3.11.6.2 Setting Principle
High impedance REF usually requires higher sensitivity for an internal fault, so its current setting
is relatively low, and user can refer to the following setting principles.
Step 1: According to the short-circuit current and circuit impedance, the voltage value
corresponds to the most severe external fault can be calculated:
Uset = K rel ∗ If ∗ (R W + R L )
In where:
If is the maximum secondary current for an external fault.
R W is the secondary impedance of CT.
R L is the resistance value of the entire CT measurement circuit, the resistance of the two cables
back and forth needs to be summed.
When multiple sets of CT parameters are inconsistent, R W and R L take the maximum value of
each CT circuit. The typical value of R L is about 1Ω.
K rel is the reliability coefficient, usually it takes 1.25.
Step 2: For an internal fault, the fault current will be shunted on the excitation circuit of each CT
and the parallel non-linear resistance. The current setting can be estimated by this way.
Imin⁡ _int Uset

Iset = -N* *Iex -Ivar (Uset )
kr Uknee
point
In where:
𝐼min⁡ _𝑖𝑛𝑡 is the minimum fault current for internal fault (current from fault point to ground).
𝐼𝑣𝑎𝑟 (𝑈𝑠𝑒𝑡 ) is the non-linear resistance shunted current when the measurement circuit voltage is
𝑈𝑠𝑒𝑡 .
𝑈𝑘 is the knee voltage of CT.
𝐼𝑚 is the excitation current corresponds to the knee voltage of CT (𝑈𝑘 ), and the maximum value is
taken when the CT characteristics of each side are different.

Date: 2021-08-01
N is the number of CTs involved in the high impedance REF protection calculation, and N is 4 for a
three-phase CT on one side and a residual CT on the other side.
K rel is the reliability coefficient, usually it takes 0.2~0.5.
The current is relatively large when the metal earth fault occurs, if the calculation result is large, in
order to ensure the accuracy and sensitivity, it can be adjusted according to the rated current of
the transformer local winding. The recommended setting range is 0.1~0.8 of the winding rated
current.
The final setting range is recommended to be 0.1~0.5In. The typical setting value is 0.1~0.2In.
3.11.6.3 Stable Resistance Selection

3
Stable resistance selection method:
First calculate the voltage Uset through the external fault, and then calculate the current setting
𝐼𝑠𝑒𝑡 according to the internal fault, and divide the two to obtain the selectable impedance.
𝑅𝑠𝑡𝑎𝑏 = Uset /𝐼𝑠𝑒𝑡 − 𝑅𝑟𝑒𝑙𝑎𝑦 = K rel ∗ If ∗ (R W + R L )/𝐼𝑠𝑒𝑡 − 𝑅𝑟𝑒𝑙𝑎𝑦
In where:
𝑅𝑟𝑒𝑙𝑎𝑦 is the circuit impedance of the high impedance REF device, it is usually small and can be
ignored in the calculation process.
The more common selection range of the stable resistance is about 200~2000Ω.
Non-linear resistance selection method:
During actual application, in order to ensure the safety of the secondary circuit, when the
calculated RMS value of the secondary circuit voltage exceeds 1500V (i.e. the peak value
exceeds 2100V), it is necessary to connect a non-linear resistor in parallel to the secondary circuit
to avoid the overvoltage.
3.11.6.4 CT Requirement
The high impedance REF protection usually has higher requirements for CT. The specific
requirements and suggestions are as follows:
1) The CT characteristics and CT ratio of all sides are the same, and the error of the CT turns
ratio is required to be as small as possible. It is recommended to use PX type CT. This type of
CT is a low-magnetic-leakage CT, and the CT ratio error is limited, usually not more than
±0.25%. In addition, 5P type CT can also be used.
2) CT has a higher knee voltage. The recommended knee voltage Uk is (2~8) ∗ Uset , and
4Uset or more is recommended.
3) CT has lower secondary leakage reactance and higher excitation impedance.
4) Because the high impedance REF circuit has a stable resistance, it should be not shared with
other protections.
5) It is recommended to obtain these CT nameplate parameters: CT knee voltage, CT ratio, the

Date: 2021-08-01
excitation current corresponds to the knee voltage, CT secondary coil impedance, and CT
secondary circuit resistance.
3.12 RMS Overcurrent Protection (50/51R)

When the capacitive equipment such as a capacitor bank or the inductive equipment such as a
rotating electrical machine in the system has a serious fault, the fundamental component in the
fault current will be relatively low, and the higher harmonic components will be higher. The
conventional phase overcurrent protection uses filtering algorithms to filter out higher harmonics
and perform calculation based on the fundamental component, resulting in failure to truly reflect
the fault condition and the protection sensitivity is affected. The RMS overcurrent protection
3 calculates the full-current RMS value includes 2nd~11th harmonic components, which can
sensitively reflect the actual fault current, so the fault can be removed quickly and accurately.
The device can provide two stages of RMS overcurrent protection with independent logic. When
the fault current with more harmonic components is generated in the system, the amplitude is
larger than the current threshold of RMS overcurrent protection, the RMS overcurrent protection
will operate.
Each stage of RMS overcurrent protection can be independently set as definite-time

characteristics or inverse-time characteristics. The drop-out characteristics can be set as
instantaneous drop-out, definite-time drop-out or inverse-time drop-out. RMS overcurrent
protection can operate to trip or alarm, it can be enabled or blocked by the external binary input.
RMS overcurrent protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, the protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block RMS overcurrent protection. The
enabling and blocking logic of RMS overcurrent protection is shown in the figure below:
EN 50/51Rx.En &
50/51Rx.On
SIG 50/51Rx.Enable
&
SIG 50/51Rx.Block ≥1 50/51Rx.Blocked
SIG Fail_Device
&
50/51Rx.Valid
Figure 3.12-1 The enabling and blocking logic of RMS overcurrent protection
The logic diagram of the fault detector element of RMS overcurrent protection is as follows:

Date: 2021-08-01
SET IRMS >0.95*[50/51Rx.I_Set] & 50/51Rx.Pkp

0 500ms
&
SIG 50/51Rx.On &
FD.Pkp
SIG 50/51Rx.Valid
EN [50/51Rx.Opt_Trp/Alm]=Alm
Figure 3.12-2 Logic diagram of the fault detector element of RMS overcurrent protection
RMS overcurrent protection can operate without time delay or operate with a definite-time limit, it
can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and
3
ANSI C37.112 standards. RMS overcurrent protection can support definite-time limit, IEC & ANSI
standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51Rx.Opt_Curve] (x=1~6), the relationship between the value
of the setting and the curve is shown in the table below.
50/51Rx.Opt_Curve Time Characteristic k α c tr

Only when the setting [50/51Rx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Rx.K], [50/51Rx.C] and [50/51Rx.Alpha]
When IRMS>IRMSp, phase overcurrent protection operates immediately.
When IRMS>IRMSp, the protection operates with a time delay of top (i.e. the value of the setting
[50/51Rx.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2021-08-01
t 0p
3
IRMSp IRMS
Figure 3.12-3 Definite-time operation characteristic curve of RMS overcurrent protection
When IRMS>IRMSp, the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current IRMS. The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Rx.tmin]. The inverse-time
 k 
t= 
+ c   TMS
 ( I RMS / I RMSP ) − 1 
Where:
IRMSp is the current setting [50/51Rx.I_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51Rx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Rx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Rx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Px.Alpha];
IRMS is the measured current.

Date: 2021-08-01
t min 3
I RMSP ID I RMS
Figure 3.12-4 Inverse-time operation characteristic curve of RMS overcurrent protection
T0
1
 t(I
0 RMS )
dt = 1
Where:
t(IRMS) is the theoretical operating time when the current is IRMS.
3.12.1.2 Dropout Characteristic
The supported dropout characteristics of the RMS overcurrent protection include instantaneous
dropout, definite-time dropout and ANSI inverse-time dropout.

inverse-time characteristic, the dropout characteristic can only be selected as instantaneous
dropout or definite-time dropout, if inverse-time dropout is selected, the alarm signal
When the operating curve is selected as ANSI inverse-time characteristic, the dropout
characteristic can be selected as instantaneous dropout, definite-time dropout and ANSI
inverse-time dropout.
⚫ Instantaneous dropout
When I RMS <0.95* I RMSP , the protection drops out immediately.

Date: 2021-08-01
⚫ Definite-time dropout
When I RMS <0.95* I RMSP , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51Rx.t_DropOut]), and the dropout characteristic curve is shown in the following figure:
Start time
IRMS >Iset
3 Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.12-5 Definite-time dropout characteristic of RMS overcurrent protection
⚫ Inverse-time dropout
When IRMS>IRMSp, the inverse-time operating accumulator begins to accumulate, the accumulated
tp
1
I tp =  dt
0
t ( I RMS )
At this time, if IRMS<0.95*IRMSp, the protection element starts dropout, and the dropout
TR
1
I tp −  dt = 0
0
t R ( I RMS )
Where:

Date: 2021-08-01
T R is the dropout time;
tR( I RMS ) is the dropout characteristic equation
When IRMS<0.95*IRMSp, the inverse-time dropout characteristic equation is as follows:
 tr 
tR =  2 
 TMS
1 − ( I RMS / I RMSP ) 
Where:
IRMSp is the current setting [50/51Rx.I_Set]; 3

TMS is the inverse-time factor, i.e. the setting [50/51Rx.TMS];
tr is the dropout time coefficient, it is the dropout time required for the current to drop to 0 after the
protection operates.
IRMS is the measured current.
When 0.95*IRMSp <IRMS <IRMSp, the accumulator will neither accumulate nor drop out
The inverse time dropout characteristic curve is shown in the figure below.
tr
I RMSP I RMS
Figure 3.12-6 Inverse-time dropout characteristic curve of RMS overcurrent protection
inverse-time dropout characteristic is shown in the figure below:

Date: 2021-08-01
Start time
IRMS >IRMSp
Start
signal
Operating
signal
Protection
operate
Operating
counter
tr
Dropout time coefficient
Dropout time
Dropout time
Figure 3.12-7 Inverse-time dropout characteristic of RMS overcurrent protection
50/51R
50/51Rx.Enable 50/51Rx.On
50/51Rx.Blocked
50/51Rx.Block
50/51Rx.Valid
50/51Rx.St
50/51Rx.StA
50/51Rx.StB
50/51Rx.StC
50/51Rx.Op
50/51Rx.Op.PhA
50/51Rx.Op.PhB
50/51Rx.Op.PhC
50/51Rx.Alm
3.12.3 I/O Signal

Stage x of RMS overcurrent protection enabling input, it is triggered from binary
1 50/51Rx.Enable
input or programmable logic etc. (x=1~2)
2 50/51Rx.Block Stage x of RMS overcurrent protection blocking input, it is triggered from binary

Date: 2021-08-01

1 50/51Rx.On Stage x of RMS overcurrent protection is enabled
2 50/51Rx.Blocked Stage x of RMS overcurrent protection is blocked
3 50/51Rx.Valid Stage x of RMS overcurrent protection is valid
4 50/51Rx.St Stage x of RMS overcurrent protection starts
5 50/51Rx.StA Stage x of RMS overcurrent protection starts (Phase A)
6 50/51Rx.StB Stage x of RMS overcurrent protection starts (Phase B)
7 50/51Rx.StC Stage x of RMS overcurrent protection starts (Phase C)
8 50/51Rx.Op Stage x of RMS overcurrent protection operates
9 50/51Rx.Op.PhA Stage x of RMS overcurrent protection operates (Phase A) 3
10 50/51Rx.Op.PhB Stage x of RMS overcurrent protection operates (Phase B)
11 50/51Rx.Op.PhC Stage x of RMS overcurrent protection operates (Phase C)
12 50/51Rx.Alm Stage x of RMS overcurrent protection alarms
3.12.4 Logic
50/51Rx.St
SET IRMS >[50/51Rx.I_Set] & Timer

t
SIG 50/51Rx.Pkp
t &
50/51Rx.Op
SET [50/51Rx.Opt_Trp/Alm]=Trp
&
50/51Rx.Alm
SET [50/51Rx.Opt_Trp/Alm]=Alm
Figure 3.12-8 Logic diagram of RMS overcurrent protection
3.12.5 Settings
Access path: MainMenu  Settings  Protection Settings  RMS OC Settings

The current setting of
1 50/51R1.I_Set 0.05~200 15 A 0.001 stage 1 of RMS
The operating time
2 50/51R1.t_Op 0 ~100 0.1 s 0.001
RMS overcurrent
protection
The drop-out time
3 50/51R1.t_DropOut 0 ~100 0 s 0.001
RMS overcurrent
protection

Date: 2021-08-01

Disabled; enabling/disabling the
4 50/51R1.En Enabled - -
Enabled stage 1 of RMS
Enabling stage 1 of
RMS overcurrent
Trp; protection operate to
5 50/51R1.Opt_Trp/Alm Trp - -
Alm trip or alarm.

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
The setting for selecting
ANSILTV;
the inverse-time
ANSILT;
6 50/51R1.Opt_Curve IECDefTime - - operation characteristic
IECN;
curve of stage 1 of RMS
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
the inverse-time dropout
characteristic curve of
stage 1 of RMS
Inst; overcurrent protection
7 50/51R1.Opt_Curve_DropOut DefTime; Inst - - Inst: instantaneous
IDMT dropout
dropout
IDMT: inverse-time
dropout
The time multiplier
8 50/51R1.TMS 0.04~ 20 1 - 0.001
RMS overcurrent
protection

Date: 2021-08-01

time setting of stage 1
9 50/51R1.tmin 0 ~10 0.02 s 0.001
of RMS overcurrent
protection
customized
10 50/51R1.K 0.001~120 0.14 - 0.0001
characteristic of stage 1
of RMS overcurrent
protection
3
customized
11 50/51R1.Alpha 0.01 ~3 0.02 - 0.0001
of RMS overcurrent
protection
customized
12 50/51R1.C 0 ~1.2 0 - 0.0001
of RMS overcurrent
protection
The operating time
14 50/51R2.t_Op 0 ~100 0.1 s 0.001
RMS overcurrent
protection
The drop-out time
15 50/51R2.t_DropOut 0 ~100 0 s 0.001
RMS overcurrent
protection
Enabling stage 2 of
RMS overcurrent
Alm trip or alarm.

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
the inverse-time
ANSILT;
IECN;
3 IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
stage 2 of RMS
IDMT dropout
dropout
IDMT: inverse-time
dropout
The time multiplier
20 50/51R2.TMS 0.04~ 20 1 - 0.001
RMS overcurrent
protection
21 50/51R2.tmin 0 ~10 0.02 s 0.001
of RMS overcurrent
protection
customized
22 50/51R2.K 0.001~120 0.14 - 0.0001
of RMS overcurrent
protection

Date: 2021-08-01

customized
23 50/51R2.Alpha 0.01 ~3 0.02 - 0.0001
of RMS overcurrent
protection
customized
24 50/51R2.C 0 ~1.2 0 - 0.0001
of RMS overcurrent
3
protection
3.13 Phase Overvoltage Protection (59P)

Some abnormal conditions in the power system will generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.
The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, it is greater than the voltage threshold, phase overvoltage
protection will operate to remove the device from the system after a time delay. In addition, the
overvoltage protection also provides the alarm function, prompting the overvoltage of the system,
it allows users to find the cause timely, and preventing further deterioration of the fault. Each stage
of phase overvoltage protection can be independently set as definite-time characteristics or
inverse-time characteristics. The drop-out characteristics can be set as instantaneous drop-out
and definite-time drop-out.
Users can select phase voltage or phase-to-phase voltage for the protection calculation via the
setting [59P.Opt_Up/Upp]. If it is set as “Up”, phase voltage criterion is selected, and if it is set to
“Upp”, phase-to-phase voltage criterion is selected.
Users can select “1-out-of-3” or “3-out-of-3” logic for the protection criterion via the setting
[59P.Opt_1P/3P]. If it is set as “1P”, phase overvoltage protection can operate if any
phase/phase-to-phase voltage is greater than the voltage setting. If it is set as “3P”, phase
overvoltage protection cannot operate unless three phase/phase-to-phase voltages are greater
than the voltage setting.
Phase overvoltage protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, overvoltage protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overvoltage protection. In
addition, if the VT of the local side is out of service, phase overvoltage protection will be disabled.
The enabling and blocking logic of phase overvoltage protection is shown in the figure below:

Date: 2021-08-01
EN 59Px.En &
59Px.On
SIG 59Px.Enable
&
SIG 59Px.Block ≥1 59Px.Blocked
SIG Fail_Device
EN [En_VT] & &

59Px.Valid
SIG BI_En_VT
3
Figure 3.13-1 The enabling and blocking logic of phase overvoltage protection
The logic diagram of the fault detector element of phase overvoltage protection is as follows:
SET [59P.Opt_Up/Upp]=Upp
SET Uab>U_DropOut
>=1
SET Ubc>U_DropOut &
SET Uca>U_DropOut
SET [59P.Opt_1P/3P]=1P
&
SET [59P.Opt_1P/3P]=3P >=1
SET Uab>U_DropOut
&
&
SET Ubc>U_DropOut
SET Uca>U_DropOut
SET Ua>U_DropOut
>=1
SET Ub>U_DropOut &
SET Uc>U_DropOut
SET [59P.Opt_1P/3P]=3P >=1

SET Ua>U_DropOut
&
&
SET Ub>U_DropOut >=1
SET Uc>U_DropOut
& &
0 500ms &
SET [59P.Opt_Up/Upp]=Up 59Px.Pkp
SIG 59Px.On
SIG 59Px.Valid
&
FD.Pkp
SET [59Px.Opt_Trp/Alm]=Alm
Figure 3.13-2 Logic diagram of the fault detector element of phase overvoltage protection
Where:
U_DropOut: the drop-out voltage value, i.e. [59Px.K_DropOut]*[59Px.U_Set]

Date: 2021-08-01
Phase overvoltage protection can operate with a definite-time limit, it can also operate with an
inverse-time limit. Phase overvoltage protection can support definite-time limit, IEC & ANSI
standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [59Px.Opt_Curve] (x=1, 2), the relationship between the value of
59Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite Time - - -
IECDefTime IEC Definite Time - - -
UserDefine UserDefine 3
InvTime_U InvCrv_U 1 1 0
When the setting [59Px.Opt_Curve] is set as “InvTime_U”, the operation characteristic is the
corresponding selected operating curve type, and the settings [59Px.K], [59Px.C] and
[59Px.Alpha] are useless.
When the setting [59Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time
characteristic is selected, the inverse-time operating curve is determined by the settings [59Px.K],
[59Px.C] and [59Px.Alpha].
When the setting [59Px.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, it is definite-time

overvoltage protection.
When U > Up , the protection operates with a time delay of top (i.e. the value of the setting
[59Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
Up U
Figure 3.13-3 Definite-time operation characteristic curve of phase overvoltage protection
When U > Up , the inverse-time accumulator begins to accumulate, and the operating time is

Date: 2021-08-01
affected by the applied voltage U . The larger voltage is, the smaller the operating time is, but not
unlimited. When the voltage is large enough to a certain threshold ( Up ), the inverse-time
operating time will not continue to decrease, then the operation characteristic becomes the
definite-time characteristic, and the operating time is tmin , i.e. the setting [59Px.tmin]. The
 k 
t= 
+ c   TMS
 (U / U P ) − 1 
Where:
3 Up is the voltage setting [59Px.U_Set];
TMS is the inverse-time time multiplier, i.e. the setting [59Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [59Px.K];

c is the inverse-time coefficient C, i.e. the setting [59Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [59Px.Alpha];
U is the measured voltage.

t min
UP UD U
Figure 3.13-4 Inverse-time operation characteristic curve of phase overvoltage protection
When the applied voltage is not a fixed value, but changes with time, the operating behaviour of
T0
1
 t (U )dt
0
=1
Where:

Date: 2021-08-01
t (U ) is the theoretical operating time when the voltage is U .
The supported drop-out characteristics of the phase overvoltage protection include instantaneous
drop-out and definite-time drop-out.
When U <[ 59Px.K_DropOut]* Up , the protection drops out immediately.
3
When U <[59Px.K_DropOut]* Up , the protection drops out with a time delay of tdr (i.e. the value
of the setting [59Px.t_DropOut]), and the drop-out characteristic curve is shown in the following
figure:
Start time
U>Up
Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.13-5 Definite-time drop-out characteristic of phase overvoltage protection

Date: 2021-08-01
59P
59Px.Enable 59Px.On
59Px.Block 59Px.Blocked
59Px.Valid
59Px.St
59Px.StA
3 59Px.StB
59Px.StC
59Px.Op
59Px.Op.PhA
59Px.Op.PhB
59Px.Op.PhC
59Px.Alm
3.13.3 I/O Signal

Stage x of phase overvoltage protection enabling input, it is triggered from
1 59Px.Enable
Stage x of phase overvoltage protection blocking input, it is triggered from
2 59Px.Block
1 59Px.On Stage x of phase overvoltage protection is enabled
2 59Px.Blocked Stage x of phase overvoltage protection is blocked
3 59Px.Valid Stage x of phase overvoltage protection is valid
4 59Px.St Stage x of phase overvoltage protection starts
5 59Px.StA Stage x of phase overvoltage protection starts (Phase A or AB)
6 59Px.StB Stage x of phase overvoltage protection starts (Phase B or BC)
7 59Px.StC Stage x of phase overvoltage protection starts (Phase C or CA)
8 59Px.Op Stage x of phase overvoltage protection operates
9 59Px.Op.PhA Stage x of phase overvoltage protection operates (Phase A or AB)
10 59Px.Op.PhB Stage x of phase overvoltage protection operates (Phase B or BC)
11 59Px.Op.PhC Stage x of phase overvoltage protection operates (Phase C or CA)
12 59Px.Alm Stage x of phase overvoltage protection alarms

Date: 2021-08-01
3.13.4 Logic
SET Uab>[59Px.U_Set]
>=1
SET Ubc>[59Px.U_Set] &
SET Uca>[59Px.U_Set]
&
SET [59P.Opt_1P/3P]=3P >=1 >=1
SET Uab>[59Px.U_Set]
&
&
SET Ubc>[59Px.U_Set] 3
SET Uca>[59Px.U_Set]
SET [59P.Opt_Up/Upp]=Up
SET Ua>[59Px.U_Set]
>=1
SET Ub>[59Px.U_Set] &
SET Uc>[59Px.U_Set]
&
SET [59P.Opt_1P/3P]=3P >=1
SET Ua>[59Px.U_Set]
&
& 59Px.St
SET Ub>[59Px.U_Set]
& Timer
SET Uc>[59Px.U_Set] t
&
t
SIG 59Px.Pkp 59Px.Op
SET [59Px.Opt_Trp/Alm]=Trp
&
59Px.Alm
Figure 3.13-6 Logic diagram of phase overvoltage protection
3.13.5 Settings
Access path: MainMenu  Settings  Protection Settings  OV Settings

Option of phase-to-phase
voltage or phase voltage for
Up; overvoltage protection
1 59P.Opt_Up/Upp Upp - -
Upp Up: phase voltage
Upp: phase-to-phase
voltage

Date: 2021-08-01

Option of 1-out-of-3 mode or
3-out-of-3 mode for
3P;
2 59P.Opt_1P/3P 3P - - overvoltage protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The voltage setting of stage
3 59P1.U_Set 57.7~200 115 V 0.001 1 of phase overvoltage
protection
The drop-out coefficient of
3 4 59P1.K_DropOut 0.93 ~1.00 0.98 - 0.001 stage 1 of phase

5 59P1.t_Op 0.1 ~100 1 s 0.001 stage 1 of phase
6 59P1.t_DropOut 0 ~100 0 s 0.001 stage 1 of phase
7 59P1.En Enabled - -
Enabled 1 of phase overvoltage
protection
Trp;
8 59P1.Opt_Trp/Alm Trp - - operate to trip or alarm.
Alm
ANSIDefTime;
IECDefTime;
9 59P1.Opt_Curve IECDefTime - - characteristic curve of stage
UserDefine;
1 of phase overvoltage
InvTime_U
protection.
Inst; 1 of phase overvoltage
10 59P1.Opt_Curve_DropOut Inst - -
DefTime protection
Inst: instantaneous drop-out
drop-out
11 59P1.TMS 0.04~ 20 1 - 0.001 stage 1 of phase

Date: 2021-08-01

12 59P1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of phase
13 59P1.K 0.001~120 1 - 0.0001 operation characteristic of
stage 1 of phase
customized inverse-time 3
14 59P1.Alpha 0.01 ~3 1 - 0.0001 operation characteristic of
stage 1 of phase
15 59P1.C 0 ~1 0 - 0.0001 operation characteristic of
stage 1 of phase
protection
17 59P2.K_DropOut 0.93 ~1.00 0.98 - 0.001 stage 2 of phase
protection
Trp;
Alm

Date: 2021-08-01

ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
3 DefTime protection
drop-out
stage 2 of phase
stage 2 of phase
stage 2 of phase
3.14 Residual Overvoltage Protection (59G)

If an earth fault occurs in the feeder of a high-resistance grounding system, the residual current
changes little and is difficult to detect. However, the amplitude of the residual voltage changes
significantly and can be used as a criterion for earth fault. In addition, the neutral point gap of the
transformer is grounded, once a fault occurs, the residual voltage increases, and the residual
overvoltage protection can also be used as the backup protection of the transformer. The residual
voltage can be measured from the open-triangle side of the voltage transformer, and it can also be

Date: 2021-08-01
calculated internally by the protection device using three-phase voltage.
The device can provide two stages of residual overvoltage protection with independent logic.
When the residual voltage is greater than the voltage threshold, the residual overvoltage
protection will operate to remove the device from the system after a time delay. In addition, the
residual overvoltage protection also provides the alarm function, it prompt that there is an earth
fault leading to residual voltage generation, it allows users to find the cause timely, and preventing
further deterioration of the fault. The drop-out characteristics of residual overvoltage protection
can be set as instantaneous drop-out and definite-time drop-out.
Residual overvoltage protection can be enabled or disabled via the settings or binary input signals, 3
for some specific applications, residual overvoltage protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block residual
overvoltage protection. In addition, if the residual voltage used by residual overvoltage protection
is the calculated residual voltage, once the VT of the local side is out of service, residual
overvoltage protection will be disabled. The enabling and blocking logic of residual overvoltage
protection is shown in the figure below:
EN 59Gx.En &
59Gx.On
SIG 59Gx.Enable
&
SIG 59Gx.Block ≥1 59Gx.Blocked
SIG Fail_Device
EN [En_VT] & &

59Gx.Valid
SIG BI_En_VT
Figure 3.14-1 The enabling and blocking logic of residual overvoltage protection
The logic diagram of the fault detector element of residual overvoltage protection is as follows:

Date: 2021-08-01
SET 3U0_Cal> U_DropOut &
SET [59G.Opt_3U0]=Cal
≥1
SET 3U0_Ext> U_DropOut &
& 59Gx.Pkp
SET [59Gx.Opt_3U0]=Ext 0 500ms
&
SIG 59Gx.On &
FD.Pkp
SIG 59Gx.Valid
3
EN [59Gx.Opt_Trp/Alm]=Alm
Figure 3.14-2 Logic diagram of the fault detector element of residual overvoltage protection
Where:
U_DropOut: the drop-out voltage value, i.e. [59Gx.K_DropOut]*[59Gx.3U0_Set]
Residual overvoltage protection can operate with a settable time delay. When U 0 > U 0 p , the
protection operates with a time delay of top (i.e. the value of the setting [59Gx.t_Op]), and the
operation characteristic curve is shown in the following figure:
t op
U0p U0
Figure 3.14-3 Definite-time operation characteristic curve of residual overvoltage protection
The supported drop-out characteristics of the residual overvoltage protection include

instantaneous drop-out and definite-time drop-out.

Date: 2021-08-01
When U 0 <[59Gx.K_DropOut]* U 0 p , the protection drops out immediately.
When U 0 <[59Gx.K_DropOut]* U 0 p , the protection drops out with a time delay of tdr (i.e. the
value of the setting [59Gx.t_DropOut]), and the drop-out characteristic curve is shown in the
following figure:
Start time
U0>U0p 3
Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.14-4 Definite-time drop-out characteristic of residual overvoltage protection
59G
59Gx.Enable 59Gx.On
59Gx.Block 59Gx.Blocked
59Gx.Valid
59Gx.St
59Gx.Op
59Gx.Alm

Date: 2021-08-01
3.14.3 I/O Signal

Stage x of residual overvoltage protection enabling input, it is triggered from
1 59Gx.Enable
Stage x of residual overvoltage protection blocking input, it is triggered from
2 59Gx.Block
1 59Gx.On Stage x of residual overvoltage protection is enabled
2 59Gx.Blocked Stage x of residual overvoltage protection is blocked
3 3
4
59Gx.Valid
59Gx.St
Stage x of residual overvoltage protection is valid
Stage x of residual overvoltage protection starts
5 59Gx.Op Stage x of residual overvoltage protection operates
6 59Gx.Alm Stage x of residual overvoltage protection alarms
3.14.4 Logic
SET 3U0_Cal> [59Gx.3U0_Set] & 59Gx.St
SET [59G.Opt_3U0]=Cal
≥1 &
[59Gx.t_Op] [59Gx.t_DropOut]
SET 3U0_Ext> [59Gx.3U0_Set] & &
59Gx.Op
SET [59Gx.Opt_3U0]=Ext
SIG 59Gx.Pkp
SET [59Gx.Opt_Trp/Alm] = Trp

&
59Gx.Alm
SET [59Gx.Opt_Trp/Alm] = Alm
Figure 3.14-5 Logic diagram of residual overvoltage protection
3.14.5 Settings
Access path: MainMenu  Settings  Protection Settings  ROV Settings

Option of measured residual voltage or
calculated residual voltage for residual
Ext;
1 59G.Opt_3U0 Cal - - overvoltage protection
Cal
Ext: the measured residual voltage
Cal: the calculated residual voltage
The voltage setting of stage 1 of residual
2 59G1.3U0_Set 1~200 50 V 0.001
The drop-out coefficient of stage 1 of
3 59G1.K_DropOut 0.93 ~1 0.98 - 0.001
residual overvoltage protection
The operating time setting of stage 1 of
4 59G1.t_Op 0.1 ~100 1 s 0.001

Date: 2021-08-01

The drop-out time setting of stage 1 of
5 59G1.t_DropOut 0 ~100 0 s 0.001
Disabled; The logic setting for enabling/disabling the
6 59G1.En Enabled - -
Enabled stage 1 of residual overvoltage protection
Enabling stage 1 of residual overvoltage
Trp; protection operate to trip or alarm.
7 59G1.Opt_Trp/Alm Trp - -
8 59G2.3U0_Set 1~200 50 V 0.001
overvoltage protection 3
9 59G2.K_DropOut 0.93 ~1 0.98 - 0.001
10 59G2.t_Op 0.1 ~100 1 s 0.001
11 59G2.t_DropOut 0 ~100 0 s 0.001
3.15 Negative-sequence Overvoltage Protection (59Q)
When the system has a broken-conductor, reverse phase sequence or inter-phase voltage
imbalance, the negative-sequence voltage increases, and the negative-sequence overvoltage
protection can reflect the system imbalance fault. It is used to protect the equipment from
insulation breakdown or premature aging due to overvoltage. The negative-sequence overvoltage
protection can also be used to alarm for prompting users the system voltage state is abnormal at
this moment.
This device provides two stages of negative-sequence overvoltage protection. If the

negative-sequence voltage is larger than the predefined setting, this protection will operate. The
negative-sequence overvoltage protection can operate with a definite-time limit, and the
supported drop-out characteristics include instantaneous drop-out and definite-time drop-out.
Negative-sequence overvoltage protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, overvoltage protection needs to be blocked by the
external signal, so the device provides a function block input signal to be used to block
overvoltage protection. In addition, if the VT of the local side is out of service, negative-sequence
overvoltage protection will be disabled. The enabling and blocking logic of negative-sequence

Date: 2021-08-01
overvoltage protection is shown in the figure below:
EN 59Qx.En &
59Qx.On
SIG 59Qx.Enable
&
SIG 59Qx.Block ≥1 59Qx.Blocked
SIG Fail_Device
EN [En_VT] & &

3 SIG BI_En_VT
59Qx.Valid
Figure 3.15-1 Logic diagram of enabling/disabling negative-sequence overvoltage protection
When the negative-sequence overvoltage protection is enabled and no external blocking signal is
input, if the negative-sequence voltage is larger than the voltage setting multiplied by the drop-out
coefficient setting of the negative-sequence overvoltage protection, the negative-sequence
overvoltage protection will pick up.
The logic diagram of the fault detector of the negative-sequence overvoltage protection is shown
as below.
SET U2 >U2_DropOut & 59Qx.Pkp

0ms 500ms
&
SIG 59Qx.On & FD.Pkp
SIG 59Qx.Valid
EN [59Qx.Opt_Trp/Alm]=Alm
Figure 3.15-2 Logic diagram of the fault detector of negative-sequence overvoltage protection
Where:
U2_DropOut: the drop-out voltage value, i.e. [59Qx.K_DropOut]*[59Qx.U2_Set]
Negative-sequence overvoltage protection can operate with a definite-time limit.
When the negative-sequence voltage is larger than the voltage setting, the protection operates
with a time delay of top (i.e. the value of the setting [59Qx.t_Op]), and the operation
characteristic curve is shown in the following figure:

Date: 2021-08-01
t op
U2p U2
Figure 3.15-3 Operation characteristic curve of negative-sequence overvoltage protection
The supported drop-out characteristics of the negative-sequence overvoltage protection include

When U2 <[ 59Qx.K_DropOut]*[59Qx.U2_Set] (x: 1~2), the protection drops out immediately.
When U2 <[59Qx.K_DropOut]*[59Qx.U2_Set] (x: 1~2), the protection drops out with a time delay
of tdr (i.e. the value of the setting [59Qx.t_DropOut]), and the drop-out characteristic curve is
shown in the following figure:

Date: 2021-08-01
Start time
U 2> U2p
Start signal
Operating
3 signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.15-4 Definite-time drop-out characteristic of negative-sequence overvoltage protection
59Q
59Qx.Enable 59Qx.On
59Qx.Block 59Qx.Blocked
59Qx.Valid
59Qx.St
59Qx.Op
59Qx.Alm
3.15.3 I/O Signals

Stage x of negative-sequence overvoltage protection enabling input, it is
1 59Qx.Enable
Stage x of negative-sequence overvoltage protection blocking input, it is
2 59Qx.Block
1 59Qx.On Stage x of negative-sequence overvoltage protection is enabled
2 59Qx.Blocked Stage x of negative-sequence overvoltage protection is blocked

Date: 2021-08-01
3 59Qx.Valid Stage x of negative-sequence overvoltage protection is valid

4 59Qx.St Stage x of negative-sequence overvoltage protection starts
5 59Qx.Op Stage x of negative-sequence overvoltage protection operates
6 59Qx.Alm Stage x of negative-sequence overvoltage protection alarms
3.15.4 Logic
59Qx.St
SET U2 > [59Qx.U2_Set] &

[59Qx.t_Op] [59Qx.t_DropOut]
& 59Qx.Op
SIG 59Qx.Pkp
3
SET [59Qx.Opt_Trp/Alm] = Trp
& 59Qx.Alm
SET [59Qx.Opt_Trp/Alm] = Alm
Figure 3.15-5 Logic diagram of negative-sequence overvoltage protection
3.15.5 Settings
Access path: MainMenu  Settings  Protection Settings  NegOV Settings

The voltage setting of stage 1 of
1 59Q1.U2_Set 2~100 15 V 0.001
negative-sequence overvoltage protection
The drop-out coefficient setting of stage 1
2 59Q1.K_DropOut 0.93~1 0.98 - 0.001 of negative-sequence overvoltage
protection
The time setting of stage 1 of
3 59Q1.t_Op 0.1~100 1 s 0.001
4 59Q1.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of stage 1 of
5 59Q1.En Enabled - -
Enabled negative-sequence overvoltage protection
Enabling stage 1 of negative-sequence
Trp; overvoltage operate to trip or alarm.
6 59Q1.Opt_Trp/Alm Trp - -
7 59Q2.U2_Set 2~100 15 V 0.001
protection
9 59Q2.t_Op 0.1~100 1 s 0.001

Date: 2021-08-01

10 59Q2.t_DropOut 0~100 0 s 0.001
3.16 Positive-sequence Overvoltage Protection (59Pos)

3
This device provides one stage of positive-sequence overvoltage protection. If the

positive-sequence voltage is larger than the pre-defined setting, this protection will operate. The
positive-sequence overvoltage protection can operate with a definite-time limit, and the supported
drop-out characteristics include instantaneous drop-out and definite-time drop-out.
Positive-sequence overvoltage protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, overvoltage protection needs to be blocked by the
external signal, so the device provides a function block input signal to be used to block
overvoltage protection. In addition, if the VT of the local side is out of service, positive-sequence
overvoltage protection will be disabled. The enabling and blocking logic of positive-sequence
overvoltage protection is shown in the figure below:
The logic diagram of enabling/disabling positive-sequence overvoltage protection is shown as

below.
EN 59Pos.En &
59Pos.On
SIG 59Pos.Enable
&
SIG 59Pos.Block ≥1 59Pos.Blocked
SIG Fail_Device
EN [En_VT] & &

59Pos.Valid
SIG BI_En_VT
Figure 3.16-1 Logic diagram of enabling/disabling positive-sequence overvoltage protection
When the positive-sequence overvoltage protection is enabled and no external blocking signal is
input, if the positive-sequence voltage is larger than the voltage setting multiplied by the drop-out
coefficient setting of the positive-sequence overvoltage protection, the positive-sequence
overvoltage protection will pick up.

Date: 2021-08-01
The logic diagram of the fault detector of the positive-sequence overvoltage protection is shown
as below.
SET U1 >U1_DropOut & 59Pos.Pkp

0ms 500ms
&
SIG 59Pos.On & FD.Pkp
SIG 59Pos.Valid
EN [59Pos.Opt_Trp/Alm]=Alm
Figure 3.16-2 Logic diagram of the fault detector of positive-sequence overvoltage protection 3
Where:
U1: the positive-sequence voltage;
U1_DropOut: the drop-out voltage value, i.e. [59Pos.K_DropOut]*[59Pos.U1_Set].
Positive-sequence overvoltage protection can operate with a definite-time limit.
When the positive-sequence voltage is larger than the voltage setting, the protection operates
with a time delay of top (i.e. the value of the setting [59Pos.t_Op]), and the operation
t op
U 1p U1
Figure 3.16-3 Operation characteristic curve of positive-sequence overvoltage protection
The supported drop-out characteristics of the positive-sequence overvoltage protection include


Date: 2021-08-01
When U <[ 59Pos.K_DropOut]*[59Pos.U1_Set] (x: 1~2), the protection drops out immediately.
1
When U <[59Pos.K_DropOut]*[59Pos.U1_Set] (x: 1~2), the protection drops out with a time delay
1
of tdr (i.e. the value of the setting [59Pos.t_DropOut]), and the drop-out characteristic curve is
shown in the following figure:
Start time
3 U 1> U1p
Start signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.16-4 Definite-time drop-out characteristic of positive-sequence overvoltage protection
59Pos
59Pos.Enable 59Pos.On
59Pos.Block 59Pos.Blocked
59Pos.Valid
59Pos.St
59Pos.Op
59Pos.Alm

Date: 2021-08-01
3.16.3 I/O Signals

Positive-sequence overvoltage protection enabling input, it is triggered from
1 59Pos.Enable
binary input or programmable logic etc.
Positive-sequence overvoltage protection blocking input, it is triggered from
2 59Pos.Block
1 59Pos.On Positive-sequence overvoltage protection is enabled
2 59Pos.Blocked Positive-sequence overvoltage protection is blocked
3
4
59Pos.Valid
59Pos.St
Positive-sequence overvoltage protection is valid
Positive-sequence overvoltage protection starts
3
5 59Pos.Op Positive-sequence overvoltage protection operates
6 59Pos.Alm Positive-sequence overvoltage protection alarms
3.16.4 Logic
59Pos.St
SET U1 > [59Pos.U1_Set] &

[59Pos.t_Op] [59Pos.t_DropOut]
& 59Pos.Op
SIG 59Pos.Pkp
SET [59Pos.Opt_Trp/Alm] = Trp

& 59Pos.Alm
SET [59Pos.Opt_Trp/Alm] = Alm
Figure 3.16-5 Logic diagram of positive-sequence overvoltage protection
3.16.5 Settings
Access path: MainMenu  Settings  Protection Settings  PosOV Settings

The voltage setting of the
1 59Pos.U1_Set 2~100 60 V 0.001
positive-sequence overvoltage protection
The drop-out coefficient setting of the
2 59Pos.K_DropOut 0.93~1 0.98 - 0.001
The time setting of the positive-sequence
3 59Pos.t_Op 0.1~100 1 s 0.001
The drop-out time setting of the
4 59Pos.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of the positive-sequence
5 59Pos.En Enabled - -
Enabled overvoltage protection

Date: 2021-08-01
Enabling the positive-sequence

6 59Pos.Opt_Trp/Alm Trp - -
3.17 Phase Undervoltage Protection (27P)

Some abnormal conditions in the power system will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be removed from
the system in time. In addition, the voltage reduction may also be related to the shortage of
system reactive power. Reducing part of the reactive power load through the undervoltage
3 protection can help increase the voltage level of the system.
The device can provide two stages of phase undervoltage protection with independent logic.
When the voltage drops in the system and it is lower than the voltage threshold, phase
undervoltage protection will operate.
Taking into account that the role of undervoltage protection is to remove the running device from
the system, but in order to prevent that undervoltage protection is always operating when it is not
charged, the breaker closed position check criterion is added, users can choose to detect the
breaker position, current or no-check as the releasing condition for the protection.
In addition, the undervoltage protection also provides the alarm function, prompting the voltage
drop of the system, it allows users to find the cause timely, and preventing further deterioration of
the fault. Each stage of phase undervoltage protection can be independently set as definite-time
characteristics or inverse-time characteristics. The drop-out characteristics can be set as
Users can select phase voltage or phase-to-phase voltage for the protection calculation via the
setting [27P.Opt_Up/Upp]. If it is set as “Up”, phase voltage criterion is selected, and if it is set to
“Upp”, phase-to-phase voltage criterion is selected.
[27P.Opt_1P/3P]. If it is set as “1P”, phase undervoltage protection can operate if any
phase/phase-to-phase voltage is smaller than the voltage setting. If it is set as “3P”, phase
undervoltage protection cannot operate unless three phase/phase-to-phase voltages are smaller
than the voltage setting.
The breaker closed position check mode is configured via the setting [27P.Opt_LogicMode], it
includes:
[27P.Opt_LogicMode]=None: no-check;
[27P.Opt_LogicMode]=Curr: check the current;
[27P.Opt_LogicMode]=CBPos: check the breaker position;
[27P.Opt_LogicMode]=CurrAndCBPos: check the current and the breaker position;

Date: 2021-08-01
[27P.Opt_LogicMode]=CurrOrCBPos: check the current or the breaker position.
Undervoltage protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, undervoltage protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block undervoltage protection. In
addition, if the VT of the local side is out of service, undervoltage protection will be disabled. The
enabling and blocking logic of undervoltage protection is shown in the figure below:
EN 27Px.En &
27Px.On
SIG 27Px.Enable
3
&
SIG 27Px.Block ≥1 27Px.Blocked
SIG Fail_Device
EN [En_VT] & &

27Px.Valid
SIG BI_En_VT
Figure 3.17-1 The enabling and blocking logic of phase undervoltage protection
The logic diagram of the fault detector element of phase undervoltage protection is as follows:

Date: 2021-08-01
&
SET Uab<[U_DropOut]
&
SET Ubc<[U_DropOut]
SET Uca<[U_DropOut]
>=1
&
SET Uab<[U_DropOut]
>=1
3 SET Ubc<[U_DropOut]
SET Uca<[U_DropOut]
&
SET Ua<[U_DropOut]
&
SET Ub<[U_DropOut] >=1
>=1 Pickup voltage criterion
SET Uc<[U_DropOut]
&
SET Ua<[U_DropOut]
>=1
SET Ub<[U_DropOut]
SET Uc<[U_DropOut]
SET [27P.Opt_LogicMode]=None
SET [27P.Opt_LogicMode]=Curr & >=1

>=1
SIG Ia, Ib and Ic > 0.04In Auxiliary criterion
SET [27P.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1
SET [27P.Opt_LogicMode]=CurrOrCBPos
&
&
SET [27P.Opt_LogicMode]=CurrAndCBPos

Date: 2021-08-01
SIG Pickup voltage criterion

& 27Px.Pkp
SIG Auxiliary criterion 0 500ms &
&
SIG VTS.Alm & FD.Pkp
&
EN [27Px.En_VTS_Blk]
SIG 27Px.On
SIG 27Px.Valid
3
Figure 3.17-2 Logic diagram of the fault detector element of phase undervoltage protection
Where:
U_DropOut: the drop-out voltage value, i.e. [27Px.K_DropOut]*[27Px.U_Set]
Undervoltage protection can operate with a definite-time limit, it can also operate with an
inverse-time limit. Undervoltage protection can support definite-time limit, IEC & ANSI standard
inverse time limit and user-defined inverse-time limit, users can select the wanted operating curve
by the setting [27Px.Opt_Curve] (x=1 or 2), the relationship between the value of the setting and
the curve is shown in the table below.
27Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite Time - - -
IECDefTime IEC Definite Time - - -
UserDefine UserDefine
InvTime_U InvCrv_U 1 1 0
When the setting [27Px.Opt_Curve] is set as “InvTime_U”, the operation characteristic is the
corresponding selected operating curve type, and the settings [27Px.K], [27Px.C] and
[27Px.Alpha] are useless.
When the setting [27Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time
characteristic is selected, the inverse-time operating curve is determined by the settings [27Px.K],
[27Px.C] and [27Px.Alpha].
When the setting [27Px.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, it is definite-time

undervoltage protection.
When U < Up , the protection operates with a time delay of top (i.e. the value of the setting
[27Px.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2021-08-01
t op
3
Up U
Figure 3.17-3 Definite-time operation characteristic curve of phase undervoltage protection
When U < Up , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied voltage U . The lower voltage is, the smaller the operating time is, but not
unlimited. When the voltage is low enough to a certain threshold ( Up ), the inverse-time operating
time will not continue to decrease, then the operation characteristic becomes the definite-time
characteristic, and the operating time is tmin , i.e. the setting [27Px.tmin]. The inverse-time
 k 
t= 
+ c   TMS
1 − (U / U P ) 
Where:
Up is the voltage setting [27Px.U_Set];
TMS is the inverse-time time multiplier, i.e. the setting [27Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [27Px.K];

c is the inverse-time coefficient C, i.e. the setting [27Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [27Px.Alpha];
U is the measured voltage.


Date: 2021-08-01
t min 3
UD UP U
Figure 3.17-4 Inverse-time operation characteristic curve of phase undervoltage protection
When the applied voltage is not a fixed value, but changes with time, the operating behaviour of
T0
1
 t (U )dt
0
=1
Where:
t (U ) is the theoretical operating time when the voltage is U .
The supported drop-out characteristics of the undervoltage protection include instantaneous

drop-out and definite-time drop-out.
When U >[27Px.K_DropOut]* Up , the protection drops out immediately.
When U >[27Px.K_DropOut]* Up , the protection drops out with a time delay of tdr (i.e. the value
of the setting [27Px.t_DropOut]), and the drop-out characteristic curve is shown in the following
figure:

Date: 2021-08-01
Start time
U<Up
Start
signal
Operating
3 signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.17-5 Definite-time drop-out characteristic of undervoltage protection
27P
27Px.Enable 27Px.On
27Px.Block 27Px.Blocked
27Px.Valid
27Px.St
27Px.StA
27Px.StB
27Px.StC
27Px.Op
27Px.Op.PhA
27Px.Op.PhB
27Px.Op.PhC
27Px.Alm

Date: 2021-08-01
3.17.3 I/O Signal

Stage x of phase undervoltage protection enabling input, it is triggered from binary
1 27Px.Enable
Stage x of phase undervoltage protection blocking input, it is triggered from binary
2 27Px.Block
1 27Px.On Stage x of phase undervoltage protection is enabled
2 27Px.Blocked Stage x of phase undervoltage protection is blocked
3
4
27Px.Valid
27Px.St
Stage x of phase undervoltage protection is valid
Stage x of phase undervoltage protection starts
3
5 27Px.StA Stage x of phase undervoltage protection starts (Phase A or AB)
6 27Px.StB Stage x of phase undervoltage protection starts (Phase B or BC)
7 27Px.StC Stage x of phase undervoltage protection starts (Phase C or CA)
8 27Px.Op Stage x of phase undervoltage protection operates
9 27Px.Op.PhA Stage x of phase undervoltage protection operates (Phase A or AB)
10 27Px.Op.PhB Stage x of phase undervoltage protection operates (Phase B or BC)
11 27Px.Op.PhC Stage x of phase undervoltage protection operates (Phase C or CA)
12 27Px.Alm Stage x of undervoltage protection alarms

Date: 2021-08-01
3.17.4 Logic
&
SET Uab<[27Px.U_Set]
&
SET Ubc<[27Px.U_Set]
SET Uca<[27Px.U_Set]
>=1
&
3 SET Uab<[27Px.U_Set]
>=1
SET Ubc<[27Px.U_Set]
SET Uca<[27Px.U_Set]
&
SET Ua<[27Px.U_Set]
&
SET Ub<[27Px.U_Set] >=1
>=1 Voltage criterion
SET Uc<[27Px.U_Set]
&
SET Ua<[27Px.U_Set]
>=1
SET Ub<[27Px.U_Set]
SET Uc<[27Px.U_Set]
SIG Voltage criterion 27Px.St

&
SIG Auxiliary criterion & Timer
t
t
SIG VTS.Alm &
&
EN [27Px.En_VTS_Blk]
SIG 27Px.On
SIG 27Px.Pkp
&
27Px.Op
SET [27Px.Opt_Trp/Alm]=Trp
&
27Px.Alm
Figure 3.17-6 Logic diagram of phase undervoltage protection

Date: 2021-08-01
Where:
Auxiliary criterion: please refer to Figure 3.17-2.
3.17.5 Settings
Access path: MainMenu  Settings  Protection Settings  UV Settings

voltage or phase voltage
for stage x of
Up;
1 27P.Opt_Up/Upp
Upp
Upp - - undervoltage protection 3
Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode
or 3-out-of-3 mode for
3P; stage x of undervoltage
2 27P.Opt_1P/3P 3P - -
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
Breaker closed position
check mode
None: no check
Curr: check the current
None; CBPos: check the
Curr; normally open auxiliary
3 27P.Opt_LogicMode CBPos; Curr - - contact
CurrOrCBPos; CurrOrCBPos: check the
CurrAndCBPos current or normally open
auxiliary contact
CurrAndCBPos: check the
current and normally open
auxiliary contact
The voltage setting of
4 27P1.U_Set 5~120 80 V 0.001 stage 1 of phase
undervoltage protection
5 27P1.K_DropOut 1~1.2 1.03 - 0.001 stage 1 of phase
The operating time setting
6 27P1.t_Op 0.1 ~100 1 s 0.001 of stage 1 of phase

Date: 2021-08-01

The drop-out time setting
7 27P1.t_DropOut 0 ~100 0 s 0.001 of stage 1 of phase
Logic setting to determine
the behaviour of stage 1 of
phase undervoltage
supervision function is
Disabled;
8 27P1.En_VTS_Blk Disabled - - enabled and VT circuit
Enabled
3 failure happens.
Disabled: it is not affected
by VT circuit failure
Enabled: it will be blocked
by VT circuit failure signal
Enabled stage 1 of phase
Trp;
Alm
ANSIDefTime;
the inverse-time operation
IECDefTime;
11 27P1.Opt_Curve IECDefTime - - characteristic curve of
UserDefine;
stage 1 of phase
InvTime_U
the inverse-time drop-out
stage 1 of phase
Inst;
12 27P1.Opt_Curve_DropOut Inst - - undervoltage protection
DefTime
Inst: instantaneous
drop-out
drop-out
The time multiplier setting
13 27P1.TMS 0.04~ 20 1 - 0.001 of stage 1 of phase

Date: 2021-08-01

time setting of stage 1 of
14 27P1.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
15 27P1.K 0.001~120 0.14 - 0.0001 operation characteristic of
stage 1 of phase
The constant “α” of the 3
16 27P1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
stage 1 of phase
stage 1 of phase
phase undervoltage
Disabled;
Enabled
failure happens.

Date: 2021-08-01

Trp;
24 27P2.Opt_Trp/Alm Trp - operate to trip or alarm.
Alm
3 ANSIDefTime;
IECDefTime;
UserDefine;
stage 2 of phase
InvTime_U
stage 2 of phase
Inst;
DefTime
Inst: instantaneous
drop-out
drop-out
27 27P2.TMS 0.04~ 20 1 0.001 of stage 2 of phase
28 27P2.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
stage 2 of phase
stage 2 of phase

Date: 2021-08-01

stage 2 of phase
3.18 Overfrequency Protection (81O)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that 3
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
part of active power supplies from the system.
The device can provide six stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power
supplies from the system. Overfrequency protection is with independent definite-time
characteristics and with instantaneous drop-out characteristics.
Overfrequency protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, overfrequency protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overfrequency protection.
The enabling and blocking logic of overfrequency protection is shown in the figure below:
EN 81Ox.En & 81Ox.On
SIG 81Ox.Enable
& 81Ox.Blocked
SIG 81Ox.Block ≥1
SIG Fail_Device
& 81Ox.Valid
Figure 3.18-1 Logic diagram of enabling/disabling overfrequency protection
When the overfrequency protection is enabled and no external blocking signal is input, if the
system frequency is greater than the frequency setting of the overfrequency protection and all the
phase-to-phase voltages are greater than the setting of the voltage blocking element of the
overfrequency protection, the overfrequency protection will pick up.
The logic diagram of the fault detector of the overfrequency protection is shown in Figure 3.18-2.

Date: 2021-08-01
SET f>[81Ox.f_Set] &

&
SET Upp_min > [81.Upp_Blk] 0 500ms &
81Ox.Pkp
SIG 81Ox.On
SIG 81Ox.Valid
&
FD.Pkp
SET [81Ox.Opt_Trp/Alm]=Alm
3 Figure 3.18-2 Logic diagram of the fault detector of overfrequency protection
The overfrequency protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the system frequency is greater than the frequency setting [81Ox.f_Set] (x:
1~6), the overfrequency protection will operate after the time setting [81Ox.t_Op] (x: 1~6).
The operation characteristic curve of overfrequency protection is shown in Figure 3.18-3.
t op
fp f
Figure 3.18-3 Operation characteristic curve of overfrequency protection
The overfrequency protection is with instantaneous drop-out characteristic. If the system

frequency is less than the setting [81Ox.f_Set] (x: 1~6), the overfrequency protection will drop out
at once.

Date: 2021-08-01
81O
81Ox.Enable 81Ox.On
81Ox.Blocked
81Ox.Block
81Ox.Valid
81Ox.St
81Ox.Op
81Ox.Alm
3.18.3 I/O Signals 3

Stage x of overfrequency protection enabling input, it is triggered from binary
1 81Ox.Enable
Stage x of overfrequency protection blocking input, it is triggered from binary
2 81Ox.Block
1 81Ox.On Stage x of overfrequency protection is enabled.
2 81Ox.Blocked Stage x of overfrequency protection is blocked.
3 81Ox.Valid Stage x of overfrequency protection is valid.
4 81Ox.St Stage x of overfrequency protection starts.
5 81Ox.Op Stage x of overfrequency protection operates.
6 81Ox.Alm Stage x of overfrequency protection alarms.
3.18.4 Logic
81Ox.St
SET f>[81Ox.f_Set] &
&
SET Upp_min>[81.Upp_Blk] [81Ox.t_Op] 0
SIG 81Ox.Pkp &

81Ox.Op
SET [81Ox.Opt_Trp/Alm]=Trp
&
81Ox.Alm
SET [81Ox.Opt_Trp/Alm]=Alm
Figure 3.18-4 Logic diagram of overfrequency protection
3.18.5 Settings
Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

Date: 2021-08-01

The setting of the low voltage blocking
1 81.Upp_Blk 10~150 70 V 0.001 element of the frequency protection
(phase-to-phase voltage)
The frequency setting of stage 1 of
2 81O1.f_Set 50~65 52 Hz 0.001
overfrequency protection
The time setting of stage 1 of overfrequency
3 81O1.t_Op 0~100 0.3 s 0.001
protection
Disabled; The logic setting of stage 1 of overfrequency
4 81O1.En Enabled - -
Enabled protection
3 Enabling stage 1 of overfrequency protection

81O1.Opt_Trp/ Trp; operate to trip or alarm.
5 Trp - -
Alm Alm Trp: for tripping purpose
6 81O2.f_Set 50~65 52 Hz 0.001
7 81O2.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
Enabling stage 2 of overfrequency protection
9 Trp - -
10 81O3.f_Set 50~65 52 Hz 0.001
11 81O3.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
13 Trp - -
14 81O4.f_Set 50~65 52 Hz 0.001
15 81O4.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
17 Trp - -

Date: 2021-08-01

18 81O5.f_Set 50~65 52 Hz 0.001
19 81O5.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
21 Trp - -
22 81O6.f_Set 50~65 52 Hz 0.001

The frequency setting of stage 6 of 3
23 81O6.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
25 Trp - -
3.19 Underfrequency Protection (81U)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some
part of loads from the system.
This device provides six stages of underfrequency protection. If the system frequency is less than
the predefined setting, this protection will operate for shedding some part of loads from the system.
The underfrequency protection is with independent definite-time delay characteristic and with
instantaneous drop-out characteristic.
Underfrequency protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, underfrequency protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block underfrequency protection.
The enabling and blocking logic of underfrequency protection is shown in the figure below:

Date: 2021-08-01
EN 81Ux.En & 81Ux.On
SIG 81Ux.Enable
& 81Ux.Blocked
SIG 81Ux.Block ≥1
SIG Fail_Device
& 81Ux.Valid
3 Figure 3.19-1 Logic diagram of enabling/disabling underfrequency protection
When the underfrequency protection is enabled and no external blocking signal is input, if the
system frequency is less than the setting of the underfrequency protection and all the
phase-to-phase voltages are greater than the setting of the voltage blocking element of the
underfrequency protection, the underfrequency protection will pick up.
The logic diagram of the fault detector of the underfrequency protection is shown in Figure 3.19-2.
SET f<[81Ux.f_Set] &

&
81Ux.Pkp
SIG 81Ux.On
SIG 81Ux.Valid
&
FD.Pkp
SET [81Ux.Opt_Trp/Alm]=Alm
Figure 3.19-2 Logic diagram of the fault detector of underfrequency protection
The underfrequency protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the system frequency is less than the frequency setting [81Ux.f_Set] (x:
1~6), the underfrequency protection will operate after the time setting [81Ux.t_Op] (x: 1~6).
The operation characteristic curve of underfrequency protection is shown in Figure 3.19-3.

Date: 2021-08-01
t op
3
fp f
Figure 3.19-3 Operation characteristic curve of underfrequency protection
The underfrequency protection is with instantaneous drop-out characteristic. If the system

frequency is greater than the setting [81Ux.f_Set] (x: 1~6), the underfrequency protection will drop
out at once.
81U
81Ux.Enable 81Ux.On
81Ux.Blocked
81Ux.Block
81Ux.Valid
81Ux.St
81Ux.Op
81Ux.Alm
3.19.3 I/O Signals

Stage x of underfrequency protection enabling input, it is triggered from binary
1 81Ux.Enable
Stage x of underfrequency protection blocking input, it is triggered from binary
2 81Ux.Block
1 81Ux.On Stage x of underfrequency protection is enabled.
2 81Ux.Blocked Stage x of underfrequency protection is blocked.
3 81Ux.Valid Stage x of underfrequency protection is valid.
4 81Ux.St Stage x of underfrequency protection starts.

Date: 2021-08-01
5 81Ux.Op Stage x of underfrequency protection operates.

6 81Ux.Alm Stage x of underfrequency protection alarms.
3.19.4 Logic
81Ux.St
SET f<[81Ux.f_Set] &
&
SET Upp_min>[81.Upp_Blk] [81Ux.t_Op] 0
SIG 81Ux.Pkp &

81Ux.Op
3 SET [81Ux.Opt_Trp/Alm]=Trp
&
81Ux.Alm
SET [81Ux.Opt_Trp/Alm]=Alm
Figure 3.19-4 Logic diagram of underfrequency protection
3.19.5 Settings

2 81U1.f_Set 45~60 48 Hz 0.001
underfrequency protection
3 81U1.t_Op 0~100 0.3 s 0.001
4 81U1.En Enabled - -
Enabled underfrequency protection
Enabling stage 1 of underfrequency
81U1.Opt_Trp/ Trp; protection operate to trip or alarm.
5 Trp - -
6 81U2.f_Set 45~60 48 Hz 0.001
7 81U2.t_Op 0~100 0.3 s 0.001

Date: 2021-08-01

9 Trp - -
10 81U3.f_Set 45~60 48 Hz 0.001
11 81U3.t_Op 0~100 0.3 s 0.001
Enabling stage 3 of underfrequency 3
13 Trp - -
14 81U4.f_Set 45~60 48 Hz 0.001
15 81U4.t_Op 0~100 0.3 s 0.001
17 Trp - -
18 81U5.f_Set 45~60 48 Hz 0.001
19 81U5.t_Op 0~100 0.3 s 0.001
21 Trp - -
22 81U6.f_Set 45~60 48 Hz 0.001
23 81U6.t_Op 0~100 0.3 s 0.001
25 Trp - -

Date: 2021-08-01
3.20 Frequency Rate-of-change Protection (81R)
Frequency rate-of-change reflects the balance of the generator output power and the active power
of the load. It can reflect the increase of active load power and the decrease of frequency. When
the frequency changes too fast, it is generally considered that the system has a fault, and the
frequency rate-of-change protection can operate in such a situation.
This device provides six stages of frequency rate-of-change protection. If the system frequency
3 rate-of-change is greater than the predefined setting, this protection will operate. The frequency
rate-of-change protection is with independent definite-time delay characteristic and with
instantaneous drop-out characteristic.
The frequency rate-of-change protection protection can be enabled or disabled via the settings or
binary input signals, for some specific applications, frequency rate-of-change protection needs to
be blocked by the external signal, so the device provides a function block input signal to be used
to block frequency rate-of-change protection. The enabling and blocking logic of frequency
rate-of-change protection is shown in the figure below:
EN 81Rx.En & 81Rx.On
SIG 81Rx.Enable
& 81Rx.Blocked
SIG 81Rx.Block ≥1
SIG Fail_Device
& 81Rx.Valid
Figure 3.20-1 Logic diagram of enabling/disabling frequency rate-of-change protection
When the frequency rate-of-change protection is enabled and no external blocking signal is input,
if the absolute value of the system frequency rate-of-change is greater than the absolute value of
setting of the frequency rate-of-change protection, the frequency rate-of-change protection will
pick up.
The logic diagram of the fault detector of the frequency rate-of-change protection is shown in
Figure 3.20-2.

Date: 2021-08-01
[81Rx.df/dt_Set] > 0 &

SET
df/dt > [81Rx.df/dt_Set]
&
SET Upp_min > [81.Upp_Blk] >=1

[81Rx.df/dt_Set] < 0 &
SET
df/dt < [81Rx.df/dt_Set] &
&
81Rx.Pkp
SIG 81Rx.On
SIG 81Rx.Valid
&
FD.Pkp
SET [81Rx.Opt_Trp/Alm]=Alm 3
Figure 3.20-2 Logic diagram of the fault detector of frequency rate-of-change protection
The frequency rate-of-change protection has definite-time delay characteristic complied with IEC
60255-3 and ANSI C37.112. If the absolute value of the system frequency rate-of-change is
greater than the absolute value of setting [81Rx.df/dt_Set] (x: 1~6), the frequency rate-of-change
protection will operate after the time setting [81Rx.t_Op] (x: 1~6).
The operation characteristic curve of the frequency rate-of-change protection is shown in Figure
3.20-3.
top
-df/dtset df/dtset
-df/dt df/dt
Figure 3.20-3 Operation characteristic curve of frequency rate-of-change protection
The frequency rate-of-change protection is with instantaneous drop-out characteristic. If the

absolute value of the system frequency rate-of-change is less than the absolute value of setting
[81Rx.df/dt_Set] (x: 1~6), the frequency rate-of-change protection will drop out at once.

Date: 2021-08-01
81R
81Rx.Enable 81Rx.On
81Rx.Blocked
81Rx.Block
81Rx.Valid
81Rx.St
81Rx.Op
81Rx.Alm
3 3.20.3 I/O Signals

Stage x of frequency rate-of-change protection enabling input, it is triggered from
1 81Rx.Enable
Stage x of frequency rate-of-change protection blocking input, it is triggered from
2 81Rx.Block
1 81Rx.On Stage x of frequency rate-of-change protection is enabled.
2 81Rx.Blocked Stage x of frequency rate-of-change protection is blocked.
3 81Rx.Valid Stage x of frequency rate-of-change protection is valid.
4 81Rx.St Stage x of frequency rate-of-change protection starts.
5 81Rx.Op Stage x of frequency rate-of-change protection operates.
6 81Rx.Alm Stage x of frequency rate-of-change protection alarms.
3.20.4 Logic
[81Rx.df/dt_Set] > 0 &

SET
df/dt > [81Rx.df/dt_Set]
&
SET f>[81Rx.f_Set]
SET Upp_min > [81.Upp_Blk] >=1

[81Rx.df/dt_Set] < 0 &
SET
df/dt < [81Rx.df/dt_Set]
& 81Rx.St
SET f<[81Rx.f_Set]
&
[81Rx.t_Op] 0
SET Upp_min > [81.Upp_Blk]
SIG 81Rx.Pkp &

81Rx.Op
SET [81Rx.Opt_Trp/Alm]=Trp
&
81Rx.Alm
SET [81Rx.Opt_Trp/Alm]=Alm
Figure 3.20-4 Logic diagram of frequency rate-of-change protection

Date: 2021-08-01
3.20.5 Settings

The rate-of-change setting of stage 1 of
2 81R1.df/dt_Set -5~5 0.5 Hz/s 0.001
frequency rate-of-change protection
The time setting of stage 1 of frequency
3 81R1.t_Op 0.1~100 0.1 s 0.001
rate-of-change protection 3
The pickup frequency setting of stage 1 of
4 81R1.f_Pkp 45~65 50 Hz 0.001
Disabled; The logic setting of stage 1 of frequency
5 81R1.En Enabled - -
Enabled rate-of-change protection
Enabling stage 1 of frequency
rate-of-change protection operate to trip or
81R1.Opt_Trp/ Trp;
6 Trp - - alarm.
Alm Alm
7 81R2.df/dt_Set -5~5 0.5 Hz/s 0.001
8 81R2.t_Op 0.1~100 0.1 s 0.001
rate-of-change protection
9 81R2.f_Pkp 45~65 50 Hz 0.001
81R2.Opt_Trp/ Trp;
11 Trp - - alarm.
Alm Alm
12 81R3.df/dt_Set -5~5 0.5 Hz/s 0.001
13 81R3.t_Op 0.1~100 0.1 s 0.001
14 81R3.f_Pkp 45~65 50 Hz 0.001

Date: 2021-08-01

81R3.Opt_Trp/ Trp;
16 Trp - - alarm.
Alm Alm
17 81R4.df/dt_Set -5~5 0.5 Hz/s 0.001
18 81R4.t_Op 0.1~100 0.1 s 0.001
19 81R4.f_Pkp 45~65 50 Hz 0.001
3 frequency rate-of-change protection
81R4.Opt_Trp/ Trp;
21 Trp - - alarm.
Alm Alm
22 81R5.df/dt_Set -5~5 0.5 Hz/s 0.001
23 81R5.t_Op 0.1~100 0.1 s 0.001
24 81R5.f_Pkp 45~65 50 Hz 0.001
81R5.Opt_Trp/ Trp;
26 Trp - - alarm.
Alm Alm
27 81R6.df/dt_Set -5~5 0.5 Hz/s 0.001
28 81R6.t_Op 0.1~100 0.1 s 0.001
29 81R6.f_Pkp 45~65 50 Hz 0.001
81R6.Opt_Trp/ Trp;
31 Trp - - alarm.
Alm Alm

Date: 2021-08-01
3.21 Reverse Power Protection (32R)
If a power supply failure occurs on the feeder, the synchronous motors become generators due to
the inertia of their load and the induction motors become generators. The aim of the reverse
power protection is to detect the inverse flow of energy and to ensure that the motor does not feed
the fault which has appeared on the network.
This device provides two stages of reverse power protection. If the reverse power is detected and
it is greater than the predefined setting, the reverse power protection will operate. The reverse
power protection is with independent definite-time delay characteristic and with instantaneous
3
drop-out characteristic.
The reverse power protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, reverse power protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block reverse power
protection. The enabling and blocking logic of reverse power protection is shown in the figure
below:
EN 32Rx.En & 32Rx.On
SIG 32Rx.Enable
& 32Rx.Blocked
SIG 32Rx.Block ≥1
SIG Fail_Device
& 32Rx.Valid
Figure 3.21-1 Logic diagram of enabling/disabling reverse power protection
When the reverse power protection is enabled and no external blocking signal is input, if the
reverse power is greater than the power setting of the reverse power protection, the reverse
power protection will pick up.
The logic diagram of the fault detector of the reverse power protection is shown in Figure 3.21-2.

Date: 2021-08-01
SET |P| > 0.95*[32Rx.P_Set] &
SIG P<0
32Rx.Pkp
SET U1 < [32R.U1_VCE] & & 0ms 500ms

&
≥1 & FD.Pkp
SET I1 < [32R.I1_CCE]
SET U2 > [32R.U2_VCE]
SIG 32Rx.On
SIG 32Rx.Valid
3 EN [32Rx.Opt_Trp/Alm]=Alm
Figure 3.21-2 Logic diagram of the fault detector of reverse power protection
Where:
The power value is positive-sequence power, P1 = 3×U1×I1×cosθ (θ is the phase angle

between positive-sequence voltage and positive-sequence current).
[32Rx.P_Set] (x: 1~2) is the power setting of stage x of reverse power protection.
[32R.U1_VCE] is the setting of the positive-sequence voltage control element of the reverse
power protection.
[32R.I1_CCE] is the positive-sequence current setting of the current control element of the
reverse power protection.
[32R.U2_VCE] is the setting of the negative-sequence voltage control element of the reverse
power protection.
“I1” is the positive-sequence current.
“U1” is the positive-sequence voltage.
“U2” is the negative-sequence voltage.
The reverse power protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the power value is less than “0”, and the absolute power value is greater
than the power setting of the reverse power protection [32Rx.P_Set] (x: 1~2), the reverse power
protection will operate after the time setting [32Rx.t_Op] (x: 1~2).
The operation characteristic curve of reverse power protection is shown in Figure 3.21-3.

Date: 2021-08-01
top
3
P1 P1set
Figure 3.21-3 Operation characteristic curve of reverse power protection
The reverse power protection is with instantaneous drop-out characteristic. If the power is greater
than “0” or the power is less than the power setting [32Rx.P_Set] (x: 1~2) multiplied by 0.95, the
reverse power protection will drop out at once.
32R
32Rx.Enable 32Rx.On
32Rx.Block 32Rx.Blocked
32Rx.Valid
32Rx.St
32Rx.Op
32Rx.Alm
3.21.3 I/O Signals

Stage x of reverse power protection enabling input, it is triggered from binary
1 32Rx.Enable
Stage x of reverse power protection blocking input, it is triggered from binary
2 32Rx.Block
1 32Rx.On Stage x of reverse power protection is enabled.
2 32Rx.Blocked Stage x of reverse power protection is blocked.
3 32Rx.Valid Stage x of reverse power protection is valid.

Date: 2021-08-01
4 32Rx.St Stage x of reverse power protection picks up.

5 32Rx.Op Stage x of reverse power protection operates.
6 32Rx.Alm Stage x of reverse power protection alarms.
3.21.4 Logic
SET |P| > [32Rx.P_Set] &
SIG P<0
32Rx.St
SET U1 < [32R.U1_VCE] &
3 SET I1 < [32R.I1_CCE]
≥1
SET U2 > [32R.U2_VCE] &

[32Rx.t_Op] 0
& 32Rx.Op
SIG 32Rx.Pkp
SET [32Rx.Opt_Trp/Alm] = Trp

& 32Rx.Alm
SET [32Rx.Opt_Trp/Alm] = Alm
Figure 3.21-4 Logic diagram of reverse power protection
3.21.5 Settings
Access path: MainMenu  Settings  Protection Settings  RevPower Settings

1 32R.U1_VCE 5~60 5 V 0.001 positive-sequence voltage control element
of the reverse power protection
The positive-sequence current setting of
2 32R.I1_CCE 0.01~1 0.1 p.u. 0.001 the current control element of the reverse
power protection
3 32R.U2_VCE 8~60 8 V 0.001 negative-sequence voltage control element
The power setting of stage 1 of reverse
4 32R1.P_Set 0.1~10 0.15 p.u. 0.001
power protection
The time setting of stage 1 of reverse
5 32R1.t_Op 0.01~100 0.1 s 0.001
power protection
Disabled; The logic setting of stage 1 of reverse
Enabled power protection
Enabling stage 1 of reverse power
7 32R1.Opt_Trp/Alm Trp - -

Date: 2021-08-01

8 32R2.P_Set 0.1~10 0.15 p.u. 0.001
power protection
9 32R2.t_Op 0.01~100 0.1 s 0.001
power protection
3
3.22 Cold Load Pickup Logic (CLP)
The cold load pickup (CLP) logic which is included within this relay serves to either inhibit the
selected protective elements for an appointed duration, or to raise the settings of the selected
protective elements. Therefore, it allows the protection settings to be set closer to the load profile
by automatically increasing them following circuit energization. The CLP logic thus provides
stability, whilst maintaining protection during starting.
If the CLP logic operates, the CLP settings are enabled for the overcurrent protection and the
earth fault overcurrent protection respectively. After the drop-out time delay of the CLP logic has
elapsed, the normal protection settings are applied. And if a fast resetting signal is received, the
normal protection settings are applied after the pre-defined short resetting time delay.
CLP
CLP.in_init
CLP.in_shortRst
3.22.3 I/O Signals

1 CLP.in_init The input of the CLP initiation signal
2 CLP.in_ShortRst The input of the short resetting signal

Date: 2021-08-01
3.22.4 Logic
SIG CLP.Onload &
SET [CLP.Opt_LogicMode] = 0
≥1
SE T
EN CLP.En tCold 0ms
S Q
&
tRst 0ms
CLR
SIG CLP.BI_52b R Q
SET [CLP.Opt_LogicMode] = 1 ≥1
& &
tS hort Rst 0ms
SIG CLP.In_ShortRst
≥1
SIG CLP.St_50/51
3 SIG
EN
CLP.in_Init
CLP.En
&
CLP.Op
Figure 3.22-1 Logic diagram of cold load pickup logic
Where:
CLP.Onload is the signal denotes anyone of the phase currents is greater than 0.04In.
CLP.BI_52b is the binary input for inputting the normally closed contact of the circuit breaker.
CLP.St_50/51 is the binary signal which denotes anyone of the selected protective elements
picked up.
“tCold” is the setting [CLP.t_Cold], the time setting for ensuring the cold load condition is met.
“tRst” is the setting [CLP.t_Rst], the time setting for resetting the cold load pickup logic function.
“tShortRst” is the setting [CLP.t_ShortRst], the time setting for fast resetting the cold load pickup logic
function.
3.22.5 Settings
Access path: MainMenu  Settings  Protection Settings  CLP Settings

The setting for selecting the cold load
Curr;
1 CLP.Opt_LogicMode CBPos - - initiation condition.
CBPos
Curr: current; CBPos: CB position.
The time setting for ensuring the cold
2 CLP.t_Cold 0~4000 3 s 0.001
load condition is met
The time setting for resetting the cold
3 CLP.t_Rst 0~4000 3 s 0.001
load pickup logic
The time setting for fast resetting the cold
4 CLP.t_ShortRst 0~600 1 s 0.001
load pickup logic
Disabled; The logic setting of the cold load pickup
5 CLP.En Enabled - -
Enabled logic function

Date: 2021-08-01
The multiple setting of stage 1 of

6 50/51P1.CLP.IMult 1~10 1 - 0.001 overcurrent protection when CLP is
active
The time setting of stage 1 of overcurrent
7 50/51P1.CLP.t_Op 0~100 0.1 s 0.001
protection when CLP is active
The time multiplier setting of stage 1 of
8 50/51P1.CLP.TMS 0.05~100 1 s 0.001 IDMT overcurrent protection when CLP is
active
The multiple setting of stage 1 of earth
9 50/51G1.CLP.IMult 1~10 1 - 0.001 fault overcurrent protection when CLP is
active 3
The time setting of stage 1 of earth fault
10 50/51G1.CLP.t_Op 0~100 0.1 s 0.001 overcurrent protection when CLP is
active
11 50/51G1.CLP.TMS 0.05~100 1 s 0.001 IDMT earth fault overcurrent protection
when CLP is active
active
13 50/51P2.CLP.t_Op 0~100 0.1 s 0.001
active
active
active
when CLP is active
active
19 50/51P3.CLP.t_Op 0~100 0.1 s 0.001
active

Date: 2021-08-01

active
active
when CLP is active
3 24 50/51P4.CLP.IMult 1~10 1 - 0.001 overcurrent protection when CLP is

active
25 50/51P4.CLP.t_Op 0~100 0.1 s 0.001
active
active
active
when CLP is active
active
31 50/51P5.CLP.t_Op 0~100 0.1 s 0.001
active
active
active
when CLP is active

Date: 2021-08-01

active
37 50/51P6.CLP.t_Op 0~100 0.1 s 0.001
active
active 3
active
when CLP is active
3.23 Undercurrent Protection (37)
The undercurrent protection can remove the device from the system by detecting the smaller load
current when the load is lost, the capacitor is in loss of voltage and the motor is running without
any load.
The device can provide one stage of undercurrent protection for tripping purpose or alarm
purpose. For different protected equipment, the single-phase criterion or three-phase criterion can
be selected. The position of circuit breaker, the load current also can be taken as the enabling
conditions for the undercurrent protection. The undercurrent protection is with definite-time
operation characteristic and instantaneous drop-out characteristic. Undercurrent protection can
operate to trip or alarm, it can be enabled or blocked by the external binary input.
Undercurrent protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, undercurrent protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block undercurrent protection. The
enabling and blocking logic of undercurrent protection is shown in the figure below:

Date: 2021-08-01
EN 37.En & 37.On
SIG 37.Enable
& 37.Blocked
SIG 37.Block ≥1
SIG Fail_Device
& 37.Valid
3 Figure 3.23-1 Logic diagram of enabling/disabling undercurrent protection
When the undercurrent protection is enabled and no external blocking signal is input, if the
detected current is less than the current setting multiplied by 1.10 of the undercurrent protection,
the undercurrent protection will pick up.
[37.Opt_1P/3P]. If it is set as “1P”, undercurrent protection can operate if any phase current is
smaller than the current setting. If it is set as “3P”, undercurrent protection cannot operate unless
three phase currents are smaller than the current setting.
The circuit breaker position with/without the current condition can be used as an auxiliary criterion
for undercurrent protection, which can be configured via the setting [37.Opt_LogicMode].
The logic diagram of the fault detector of the undercurrent protection is shown as below.

Date: 2021-08-01
SIG Ia<1.10×[37.I_Set]
>=1
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]
>=1
Pickup current criterion
SET [37.Opt_1P/3P]=1P
SIG Ia<1.10×[37.I_Set]
&
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]
SET [37.Opt_1P/3P]=3P 3
SET [37.Opt_LogicMode]=None
SET [37.Opt_LogicMode]=Curr & >=1

>=1
SIG Ip>0.04In Auxiliary criterion
SET [37.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1
SET [37.Opt_LogicMode]=CurrOrCBPos
&
&
SET [37.Opt_LogicMode]=CurrAndCBPos
SIG Pickup current criterion

& 37.Pkp
SIG Auxiliary criterion 0 500ms &
SIG 37.On
&
FD.Pkp
SIG 37.Valid
SET [37.Opt_Trp/Alm]=Alm
Figure 3.23-2 Logic diagram of the fault detector of undercurrent protection
The undercurrent protection has definite-time operation characteristic complied with IEC 60255-3
and ANSI C37.112. If the load current is less than the current setting of the undercurrent
protection [37.I_Set], the undercurrent protection will operate after the time setting [37.t_Op].

Date: 2021-08-01
The operation characteristic curve of undercurrent protection is shown as below.
3 t op
Ip I
Figure 3.23-3 Operation characteristic curve of undercurrent protection
The undercurrent protection is with instantaneous drop-out characteristic. If the load current is
larger than the current setting [37.I_Set] multiplied by 1.10, the undercurrent protection will drop
out immediately.
37
37.Enable 37.On
37.Block 37.Blocked
37.Valid
37.St
37.StA
37.StB
37.StC
37.Op
37.Op.PhA
37.Op.PhB
37.Op.PhC
37.Alm

Date: 2021-08-01
3.23.3 I/O Signals

Undercurrent protection enabling input, it is triggered from binary input or
1 37.Enable
programmable logic etc.
Undercurrent protection blocking input, it is triggered from binary input or
2 37.Block
1 37.On Undercurrent protection is enabled.
2 37.Blocked Undercurrent protection is blocked.
3
4
37.Valid
37.St
Undercurrent protection is valid.
Undercurrent protection starts.
3
5 37.StA Undercurrent protection starts (Phase A)
6 37.StB Undercurrent protection starts (Phase B)
7 37.StC Undercurrent protection starts (Phase C)
8 37.Op Undercurrent protection operates.
9 37.Op.PhA Undercurrent protection operates (Phase A)
10 37.Op.PhB Undercurrent protection operates (Phase B)
11 37.Op.PhC Undercurrent protection operates (Phase C)
12 37.Alm Undercurrent protection alarms.

Date: 2021-08-01
3.23.4 Logic
SIG Ia<[37.I_Set]
>=1
SIG Ib<[37.I_Set] &
SIG Ic<[37.I_Set]
>=1
Current criterion
SIG Ia<[37.I_Set]
&
SIG Ib<[37.I_Set] &
3 SIG Ic<[37.I_Set]
SIG Current criterion

& 37.St
SIG Auxiliary criterion &
[37.t_Op] 0
SIG 37.On
SIG 37.Pkp
&
37.Op
SET [37.Opt_Trp/Alm]=Trp
&
37.Alm
SET [37.Opt_Trp/Alm]=Alm
Figure 3.23-4 Logic diagram of undercurrent protection
Where:
Auxiliary criterion: please refer to Figure 3.23-2.
3.23.5 Settings
Access path: MainMenu  Settings  Protection Settings  UC Settings

The current setting of the
1 37.I_Set 0.1~5 0.5 A 0.001
undercurrent protection
The time setting of the undercurrent
2 37.t_Op 0.1~100 0.1 s 0.001
protection
1P;
3 37.Opt_1P/3P 3P - - three-phase criterion (3P) or
3P
single-phase criterion (1P)

Date: 2021-08-01
None;
Curr;
CurrAnd The setting of the CB position check
4 37.Opt_LogicMode CBPos; - -
CBPos mode.
CurrAndCBPos;
CurrOrCBPos
Disabled; The logic setting of the undercurrent
5 37.En Enabled - -
Enabled protection
Enabling undercurrent protection
Trp; operate to trip or alarm.
6 37.Opt_Trp/Alm Trp - -
3
3.24 Breaker Failure Protection (50BF)
When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure
protection is adopted to issue a backup tripping command to trip adjacent circuit breakers, and
isolate the fault as requested by the device.
According to the tripping information from the device and the auxiliary information (the current and
the position) of target circuit breaker, breaker failure protection constitutes the criterion to
discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker failure
protection will operate to trip the target circuit breaker with the time delay [50BF.t_ReTrp], trip it
again with the time delay [50BF.t1_Op] and trip the adjacent circuit breakers with the time delay
[50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly isolate the
fault, reduce the affected range by the fault, keep system stability and prevent generators,
transformers and other primary equipment from seriously damaged.
For breaker failure protection, re-trip and two time delays are available.
3.24.1.1 Re-trip
When breaker failure protection receives initiating signal of tripping and phase overcurrent
element of any phase operates, the device will issue tripping command to re-trip the target circuit
breaker with the time delay [50BF.t_ReTrp]. In order to improve the sensitivity, both
zero-sequence overcurrent element and negative-sequence overcurrent element are added,
which can be enabled or disabled by the settings [50BF.En_3I0_3P] and [50BF.En_I2_3P].
3.24.1.2 First Time Delay
As similar as re-trip, the device will operate to re-trip the target circuit breaker again with the time
delay [50BF.t1_Op] when the relevant operating criterion is satisfied.

Date: 2021-08-01
3.24.1.3 Second Time delay
As similar as re-trip, the device will operate to trip the adjacent circuit breakers with the time delay
[50BF.t2_Op] when the relevant operating criterion is satisfied.
3.24.1.4 Current Criterion
1. Phase overcurrent element
𝐼𝜑 > [50𝐵𝐹. 𝐼_𝑆𝑒𝑡]
Where:
3 𝜑 = A, B or C
2. Zero-sequence overcurrent element
3I0 > [50𝐵𝐹. 3𝐼0_𝑆𝑒𝑡]
Where:
3I0⁡ is the calculated residual current
3. Negative-sequence overcurrent element
I2 > [50𝐵𝐹. 𝐼2_𝑆𝑒𝑡]
Where:
I2⁡ is the negative-sequence current
For some special faults (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal "50BF.ExTrp_WOI" is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact "50BF.52b" as an option criterion for breaker failure check.
When the initiating signal of breaker failure protection is energized for longer than 10s, an alarm
signal "50BF.Alm_Init" will be issued, and will drop out with a time delay of 10s.

Date: 2021-08-01
50BF
50BF.Enable 50BF.On
50BF.Block 50BF.Blocked
50BF.ExTrp3P 50BF.Valid
50BF.ExTrp_WOI 50BF.St
50BF.Op_ReTrp3P
50BF.Op_t1 3
50BF.Op_t2
50BF.Alm_Init
3.24.3 I/O Signals

Breaker failure protection enabling input, it is triggered from binary input or
1 50BF.Enable
Breaker failure protection blocking input, it is triggered from binary input or
2 50BF.Block
3 50BF.ExtTrp3P Input signal of initiating breaker failure protection (three-phases)
Input signal of initiating breaker failure protection with the position check of
4 50BF.ExtTrp_WOI
the circuit breaker
1 50BF.On Breaker failure protection is enabled.
2 50BF.Blocked Breaker failure protection is blocked.
3 50BF.Valid Breaker failure protection is valid.
4 50BF.St Breaker failure protection starts
5 50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phases circuit breaker.
6 50BF.Op_t1 Breaker failure protection operates with the time delay [50BF.t1_Op].
7 50BF.Op_t2 Breaker failure protection operates with the time delay [50BF.t2_Op].
8 50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently.

Date: 2021-08-01
3.24.4 Logic
EN [50BF.En] &
50BF.On
SIG 50BF.Enable
&
SIG 50BF.Block >=1 50BF.Blocked
SIG Fail_Device
&
50BF.Valid
3
Figure 3.24-1 Logic of enabling breaker failure protection
SIG 50BF.ExtTrp3P 10s 10s >=1
SIG 50BF.ExtTrp_WOI 10s 10s
&
EN [50BF.En_Alm_Init] 50BF.Alm_Init
SIG 50BF.Valid
Figure 3.24-2 Logic of breaker failure initiating signal abnormality
SIG IA>[50BF.I_Set]
>=1
SIG IB>[50BF.I_Set]
SIG IC>[50BF.I_Set]
&
EN [50BF.En_Curr]
&
EN [50BF.En_CBPos]
SIG 50BF.52b
&
SIG IA>[50BF.I_Set]
& >=1
>=1 >=1 Current/Contact check
SIG IB>[50BF.I_Set]
SIG IC>[50BF.I_Set] &

&
SIG 50BF.52b
Figure 3.24-3 Logic of current/contact check

Date: 2021-08-01
SIG 50BF.Valid &
SIG 50BF.Alm_Init
EN [50BF.En_ReTrp]
EN [50BF.En_Ip] &
[50BF.t_ReTrp] 0 50BF.Op_ReTrp3P
SIG Current/Contact check
&
SIG 50BF.ExtTrp3P
EN [50BF.En_3I0_3P] &
&
3
SET 3I0>[50BF.3I0_Set]
>=1 &
& >=1 [50BF.t1_Op] 0 50BF.Op_t1
EN [50BF.En_I2_3P] &
SET I2>[50BF.I2_Set]
SIG 50BF.ExtTrp_WOI
>=1
& 50BF.St
EN [50BF.En_CB_Ctrl]
SIG 50BF.52b
EN [50BF.En_t1]
&
[50BF.t2_Op] 0 50BF.Op_t2
EN [50BF.En_t2]
Figure 3.24-4 Logic of breaker failure protection
Where:
50BF.52b: Input signal of three-phase open position of circuit breaker.
3.24.5 Settings
Access path: MainMenu  Settings  Protection Settings  BFP Settings

The phase current setting of breaker
1 50BF.I_Set 0.05~200 1.000 A 0.001
failure protection
The zero-sequence current setting of
2 50BF.3I0_Set 0.05~200 1.000 A 0.001
breaker failure protection
The negative-sequence current setting of
3 50BF.I2_Set 0.05~200 1.000 A 0.001
The re-trip time delay of breaker failure
4 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
5 50BF.t1_Op 0~20 0.100 s 0.001
protection
The second time delay of breaker failure
6 50BF.t2_Op 0~20 0.200 s 0.001
protection

Date: 2021-08-01
Disabled Enabling/disabling breaker failure

7 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
8 50BF.En_ReTrp Enabled - -
Enabled breaker failure protection
Disabled Enabling/disabling the first time delay of
9 50BF.En_t1 Disabled - -
Disabled Enabling/disabling the second time delay
Enabled of breaker failure protection
Enabling/disabling phase overcurrent
Disabled
11 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
3 three-phases initiating signal
Enabling/disabling zero-sequence
Disabled overcurrent element of breaker failure
12 50BF.En_3I0_3P Disabled - -
Enabled protection via three-phases initiating
signal
Enabling/disabling negative-sequence
13 50BF.En_I2_3P Disabled - -
signal
Enabling/disabling breaker failure
Disabled
14 50BF.En_CB_Ctrl Disabled - - protection be initiated by normally closed
Enabled
contact of circuit breaker
Disabled Enabling/disabling abnormality check of
15 50BF.En_Alm_Init Disabled - -
Enabled breaker failure initiating signal
Disabled Enabling/disabling current check criterion
16 50BF.En_Curr Enabled - -
Disabled Enabling/disabling contact check criterion
17 50BF.En_CBPos Disabled - -
3.25 Switch-on-to-Fault Protection (SOTF)

When the line is put into operation or the power is restored, the circuit breaker is necessary to be
closed automatically, it is possible to switch on to a permanent fault. The conventional phase
overcurrent protection or earth fault overcurrent protection requires a time delay to operate and
isolate the fault, which will affect the power system seriously. Switch-on-to-fault (SOTF) protection
can quickly operate to remove the fault and reduce the impact of the fault on the system.
The device can provide one stage of phase overcurrent SOTF protection and one stage of earth
fault overcurrent SOTF protection. The SOTF protection is with definite-time delay characteristic
and instantaneous drop-out characteristic, it can be enabled or blocked by the external binary
input.
The SOTF protection can be enabled or disabled via the settings or binary input signals, for some
specific applications, the protection needs to be blocked by the external signal, so the device

Date: 2021-08-01
provides a function block input signal to be used to block RMS overcurrent protection. The
enabling and blocking logic of the SOTF protection is shown in the figure below:
EN 50PSOTF.En &
50PSOTF.On
SIG 50PSOTF.Enable
&
SIG 50PSOTF.Block ≥1 50PSOTF.Blocked
SIG Fail_Device
&
50PSOTF.Valid
3
EN 50GSOTF.En &
50GSOTF.On
SIG 50GSOTF.Enable
&
SIG 50GSOTF.Block ≥1 50GSOTF.Blocked
SIG Fail_Device
&
50GSOTF.Valid
Figure 3.25-1 The enabling and blocking logic of SOTF protection
The SOTF protection must be initiated by auto-reclosing signal or manual closing signal, the
initiating time can be set by the setting [STOF.t_En]. After the acceleration condition is satisfied,
the SOTF protection will operate with a time delay of [50PSOTF.t_Op]/[50GSOTF.t_Op_3P].
If the three-phase current changes from “no” to “have”, and the breaker position changes from
“open” to “closed”, it will be judged that the acceleration condition for manual closing is satisfied.
Then the manual closing signal will be kept for a certain time which is determined by the setting
[SOTF.t_En], and SOTF protection will be enabled.
When the SOTF protection is used for the transformer bay, large inrush current generated during
manual closing and auto-reclosing maybe lead to an undesired operation of SOTF protection.
Second harmonic blocking can be selected by the setting
[50PSOTF.En_Hm2_Blk]/[50GSOTF.En_Hm2_Blk] to prevent the mal-operation due to inrush
current. The harmonic blocking characteristic of the phase overcurrent SOTF protection is
consistent with that of phase overcurrent protection. The harmonic blocking characteristic of the
earth fault overcurrent SOTF protection is consistent with that of earth fault overcurrent protection.
In order to improve the reliability, phase overcurrent SOTF protection can select phase voltage
element, phase-to-phase voltage element, zero-sequence voltage element and

Date: 2021-08-01
negative-sequence voltage element as auxiliary criterion.
50PSOTF
50PSOTF.Enable 50PSOTF.On
50GSOTF
50PSOTF.Blocked
50PSOTF.Block
50PSOTF.Valid 50GSOTF.Enable 50GSOTF.On
SOTF.in_mancls 50PSOTF.Op
50GSOTF.Block 50GSOTF.Blocked
50PSOTF.St
3 50PSOTF.StA
SOTF.in_mancls 50GSOTF.Valid
50GSOTF.Op
50PSOTF.StB
50PSOTF.StC 50GSOTF.St
3.25.3 I/O Signals

Phase overcurrent SOTF protection enabling input, it is triggered from binary
1 50PSOTF.Enable
input or programmable logic etc.
Phase overcurrent SOTF protection blocking input, it is triggered from binary
2 50PSOTF.Block
input or programmable logic etc.
Earth fault overcurrent SOTF protection enabling input, it is triggered from
3 50GSOTF.Enable
Earth fault overcurrent SOTF protection blocking input, it is triggered from
4 50GSOTF.Block
Manual closing input signal, it is triggered from binary input or programmable
5 SOTF.in_mancls
logic etc.
1 50PSOTF.On Phase overcurrent SOTF protection is enabled.
2 50PSOTF.Blocked Phase overcurrent SOTF protection is blocked
3 50PSOTF.Valid Phase overcurrent SOTF protection is valid
4 50PSOTF.Op Phase overcurrent SOTF protection operates.
5 50PSOTF.St Phase overcurrent SOTF protection starts.
6 50PSOTF.StA Phase overcurrent SOTF protection starts (Phase A).
7 50PSOTF.StB Phase overcurrent SOTF protection starts (Phase B).
8 50PSOTF.StC Phase overcurrent SOTF protection starts (Phase C).
9 50GSOTF.On Earth fault overcurrent SOTF protection is enabled.
10 50GSOTF.Op Earth fault overcurrent SOTF protection operates.
11 50GSOTF.Blocked Earth fault overcurrent SOTF protection is blocked
12 50GSOTF.Valid Earth fault overcurrent SOTF protection is valid
13 50GSOTF.St Earth fault overcurrent SOTF protection starts.

Date: 2021-08-01
3.25.4 Logic
SIG 79.Close: 0->1 0 [SOTF.t_En] AR signal
Figure 3.25-2 Logic of auto-reclosing signal
SIG Breaker open position &
SIG FD.Pkp
&
SIG FD.Pkp &
SIG No current & 3

SET [SOTF.Opt_Mode_ManCls]=CBPos
SIG FD.Pkp &

& >=1
SIG SOTF.in_mancls 0 [SOTF.t_En] Manual closing signal
SET [SOTF.Opt_Mode_ManCls]=ManClsBI
>=1
&
/CBPos
Figure 3.25-3 Logic of manual closing signal
If three-phase current is not detected, and the breaker is open, it will be judged that the
acceleration condition for manual closing is satisfied.

Date: 2021-08-01
SIG AR signal >=1
SIG Manual closing signal
SET Ia>[50PSOTF.I_Set]
>=1
SET Ib>[50PSOTF.I_Set]
SET Ic>[50PSOTF.I_Set]
SIG I3P 2nd Hm Detect & &
EN [50PSOTF.En_Hm2_Blk]
SET Ua<[50PSOTF.Up_Set]
>=1
3 SET Ub<[50PSOTF.Up_Set]
SET Uc<[50PSOTF.Up_Set]
&
EN [50PSOTF.En_Up_UV]
SET Uab<[50PSOTF.Upp_Set]
>=1 >=1
SET Ubc<[50PSOTF.Upp_Set] &
SET Uca<[50PSOTF.Upp_Set]
EN [50PSOTF.En_Upp_UV]
SET U2>[50PSOTF.U2_Set] & >=1

>=1
EN [50PSOTF.En_U2_OV]
SET 3U0>[50PSOTF.3U0_Set] &
EN [50PSOTF.En_3U0_OV]
EN [50PSOTF.En_Up_UV]
>=1
EN [50PSOTF.En_Upp_UV]
EN [50PSOTF.En_U2_OV]
EN [50PSOTF.En_3U0_OV]
&
[50PSOTF.t_Op] 0 50PSOTF.Op
SIG 50PSOTF.Valid
50PSOTF.St
Figure 3.25-4 Logic of phase overcurrent SOTF protection
SIG I3P/I1P 2nd Hm Detect &
SET [50GSOTF.En_Hm2_Blk]
SIG AR signal >=1

50GSOTF.St
&
[50GSOTF.t_Op] 0 50GSOTF.Op
SET 3I0>[50GSOTF.3I0_Set]
SIG 50GSOTF.Valid
Figure 3.25-5 Logic of earth fault overcurrent SOTF protection

Date: 2021-08-01
3.25.5 Settings
Access path: MainMenu  Settings  Protection Settings  SOTF Settings

ManClsBI Logic setting for selecting the
SOTF.Opt_Mode_Man CBPos manual closing SOTF trigger mode:
1 CBPos - -
Cls ManClsBI/ circuit breaker position, manual
CBPos closing input, or either.
The initiating time for the SOTF
2 SOTF.t_En 0.2~100 3 s 0.001
protection
3 50PSOTF.I_Set 0.05~200 1 A 0.001

Current setting of phase overcurrent 3
SOTF protection
Voltage setting for phase
4 50PSOTF.Up_Set 0~200 1 V 0.001
undervoltage supervision logic
Voltage setting for phase-to-phase
5 50PSOTF.Upp_Set 0~200 1 V 0.001
Voltage setting for negative-sequence
6 50PSOTF.U2_Set 0~200 1 V 0.001
overvoltage supervision logic
Voltage setting for zero-sequence
7 50PSOTF.3U0_Set 0~200 1 V 0.001
Time delay for phase overcurrent
8 50PSOTF.t_Op 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling phase overcurrent
9 50PSOTF.En Enabled - -
Enabled SOTF protection
Enabling/disabling second harmonic
Disabled
10 50PSOTF.En_Hm2_Blk Enabled - - blocking for phase overcurrent SOTF
Enabled
protection
Enabling/disabling phase
Disabled
11 50PSOTF.En_Up_UV Enabled - - undervoltage supervision logic for
Enabled
phase overcurrent SOTF protection
Enabling/disabling phase-to-phase
Disabled
12 50PSOTF.En_Upp_UV Enabled - - undervoltage supervision logic for
Enabled
Enabling/disabling
Disabled negative-sequence overvoltage
13 50PSOTF.En_U2_OV Enabled - -
Enabled supervision logic for phase
overcurrent SOTF protection
Disabled
14 50PSOTF.En_3U0_OV Enabled - - overvoltage supervision logic for
Enabled

Date: 2021-08-01
The option of the residual current

used by earth fault overcurrent SOTF
Ext
15 50GSOTF.Opt_3I0 Cal - - protection
Cal
Ext: the measured residual current
Cal: the calculated residual current
Current setting of earth fault
16 50GSOTF.3I0_Set 0.05~200 1 A 0.001
Time delay for earth fault overcurrent
17 50GSOTF.t_Op_3P 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling earth fault
18 50GSOTF.En Enabled - -
3 Enabled overcurrent SOTF protection
Enabling/disabling earth fault
Disabled
19 50GSOTF.En_Hm2_Blk Disabled - - overcurrent SOTF protection blocked
Enabled
by harmonic
3.26 Thermal Overload Protection (49)
When the power equipment is overloaded, a large current may cause the temperature of the
equipment to rise. When the temperature is high, the internal insulation of the equipment may be
aged, thereby increasing the possibility of internal failure. Thermal overload protection considers
the continuous heating state of the device, the thermal model of the device is established based
on the measured current and the time constant.
The device provides two thermal overload calculation methods: 1) only calculated by current; 2)
for the scenario with oil temperature measurement function, calculate the temperature difference
between the equipment (such as transformer windings) and the oil, and then plus the oil
temperature measured by the sensor, to obtain the final temperature.
⚫ Method 1:
Two stages overload protection are available, one stage for alarm purpose and the other stage for
trip purpose. The two stages are timed separately. When the thermal overload calculation reaches
the alarm setting value, an alarm signal will be issued to remind the operating personnel. If the
temperature continues to rise to reach the tripping setting value, the thermal overload protection
operates to trip.
The operating time of thermal overload protection complies with the IEC60255-8 standard and it is
calculated via the fundamental current or 1st to 11th harmonic current.

Date: 2021-08-01
t Refer to IEC60255-8
Ip
P=—
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB I
3
Figure 3.26-1 The operation characteristic curve of thermal overload protection
There are two kinds of thermal overload calculation modes: cold start mode and hot start mode.
The calculation formulas for the two modes are as follows:
1) Cold start mode
I eq
t =   ln
I eq − (k  I B )
2) Hot start mode
I eq − I p
t =   ln
I eq − (k  I B )
Where:
t is the theoretical operating time for the corresponding current.
τ is the thermal time constant of the protected device, i.e. [49.Tau]. When the current Ieq is lower
than 0.04In, the thermal time constant adopts the value of [49.Tau]*[49.C_Disspt].
Ieq is the actual measured current.
IP is the steady-state load for a period of time before the overload. The result is that the
transformer is in a stable thermal equilibrium state (the duration needs to be several times longer
than the time constant τ), which is equivalent to the previous memoried current, the value is “0” for
the cold start mode.
ln is the natural logarithm.
IB is the reference current and it corresponds to the setting [49.Ib_Set].
k is the thermal overload factor, it corresponds to the setting [49.K_Trp] or [49.K_Alm].

Date: 2021-08-01
If the device adopts the hot start model, the device calculates the IP in real time through the
external input current, and users do not need to set the value of IP.
The tripping of the protection is controlled by the current. After the current disappears, the
protection will drop-out immediately even if the heat accumulation is still greater than the tripping
setting. The alarm of the protection is not controlled by the current, as long as the heat
accumulation is greater than the alarm setting, it will always be alarmed and it can be used to
block the automatic closing of the device.
⚫ Method 2:
The temperature of the equipment can be calculated from the actual measured oil temperature
3 (via the PT100 sensor) plus the temperature difference between the equipment and the oil.
T_Equipment = T_Oil + T_Diff
The temperature difference between the equipment and the oil can be calculated by actual
measurement and it will change with the device current. When the current changes from “0” to “1”,
the temperature can be calculated by the following formula.
α
I −t
T_Diff = [49. K_T_Diff] × ( ) × (1 − eTau )
[49. Ib_Set]
Finally, the steady-state temperature difference is as follows:

α
I
T_Diff = [49. K_T_Diff] × ( )
[49. Ib_Set]
Where:
I is the measured current;
α is the cooling factor, it usually takes 1.6 or 2;
t is the time;
Tau is the time constant;
Users can compare the calculated temperature with the set temperature and set the time delay
through logic programming, it can be selected to operate to trip or alarm.
The logic diagram of enabling/disabling thermal overload protection is shown as below:

Date: 2021-08-01
EN [49.En_Trp] >=1
EN [49.En_Alm] &
49.On
SIG 49.Enable
&
SIG 49.Block >=1 49.Blocked
SIG Fail_Device
&
49.Valid
3
Figure 3.26-2 Logic diagram of enabling/disabling thermal overload protection
The logic diagram of the fault detector of thermal overload protection is shown as below.
SIG 49.in_I3P
SET [49.Ib_Set] &

0 500ms &
49.Pkp
SIG 49.On
FD.Pkp
SIG 49.Valid
Figure 3.26-3 Logic diagram of the fault detector of thermal overload protection (method 1)

Date: 2021-08-01
49
49.Enable 49.Accu_A
49.Block 49.Accu_B
49.Accu_C
49.Clr
49.T_Diff_A
49.T_Diff_B
49.T_Diff_C
49.On
49.Blocked
3 49.Valid
49.St
49.St_A
49.St_B
49.St_C
49.Op
49.Op_A
49.Op_B
49.Op_C
49.Alm
3.26.3 I/O Signals

Thermal overload protection enabling input, it is triggered from binary input or
1 49.Enable
Thermal overload protection blocking input, it is triggered from binary input or
2 49.Block
3 49.Clr Clear thermal overload statistics
1 49.Accu_A Phase-A thermal state of thermal overload protection.
2 49.Accu_B Phase-B thermal state of thermal overload protection.
3 49.Accu_C Phase-C thermal state of thermal overload protection.
The calculated temperature difference of phase-A between winding temperature
4 49.T_Diff_A
and oil temperature.
The calculated temperature difference of phase-B between winding temperature
5 49.T_Diff_B
The calculated temperature difference of phase-C between winding temperature
6 49.T_Diff_C
7 49.On Thermal overload protection is enabled
8 49.Blocked Thermal overload protection is blocked
9 49.Valid Thermal overload protection is valid
10 49.St Thermal overload protection starts
11 49.StA Phase-A thermal overload protection starts.

Date: 2021-08-01
12 49.StB Phase-B thermal overload protection starts.

13 49.StC Phase-C thermal overload protection starts.
14 49.Op Thermal overload protection operates to trip.
15 49.Op.PhA Phase-A thermal overload protection operates to trip.
16 49.Op.PhB Phase-B thermal overload protection operates to trip.
17 49.Op.PhC Phase-C thermal overload protection operates to trip.
18 49.Alm Thermal overload protection operates to alarm.
3.26.4 Logic
SIG 49.Pkp
&
3
SIG 49.in_I3P 49.St
& Timer
SET [49.Ib_Set] t
49.Alm
t
EN [49.En_Alm]
& Timer
t
49.Op
t
EN [49.En_Trp]
SIG 49.Clr
Figure 3.26-4 Logic diagram of thermal overload protection (method 1)
3.26.5 Settings
Access path: MainMenu  Settings  Protection Settings  ThOvLd Settings

The reference current setting of thermal
1 49.Ib_Set 0.05~200 15 A 0.001
overload protection
The thermal overload factor setting for
2 49.K_Trp 1~3 1.2 - 0.001
tripping
3 49.K_Alm 1~3 1.1 - 0.001
alarm
The heat accumulation time constant of
4 49.t_Tau 0.1~100 1 min 0.001
thermal overload protection
The temperature constant of thermal
5 49.K_T_Diff 0~200 30 - 0.001
overload protection
The cooling factor of thermal overload
6 49.Alpha_Cold 1~2 2 - 0.001
protection
Heat dissipation time constant setting.
0.100~10 When the current Ieq is lower than 0.04In,
7 49.C_Disspt 1.000 - 0.001
.000 the thermal time constant adopts the value
of [49.Tau]*[49.C_Disspt].

Date: 2021-08-01
Disabled; Enabling/Disabling thermal overload

8 49.En_Trp Disabled - -
Enabled protection operate to trip
9 49.En_Alm Disabled - -
Enabled protection operate to alarm
3.27 Restricted Earth Fault Protection (64REF)

Restricted earth fault (REF) protection is meant to protect a single winding of a power transformer,
and the protected winding must be earthed. In the case of delta windings, the winding must be
earthed by an earthing transformer, which must be electrically placed between the winding and
the current transformers. REF protection can be applied to protect two-winding transformer,
3 three-winding transformer, auto-transformer and shut reactor.
REF protection is a kind of differential protection, so it calculates differential current and restrained
current. The differential current is a vector difference of the neutral current (i.e., current flowing in
the neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF protection operates on the fault current only, and is not
dependent on eventual load currents. This makes REF protection a very sensitive protection.
3.27.1.1 Overview
The difference between current differential protection and REF protection is that the first one is
based on adjusted phase current balance and the latter is based on balance of calculated residual
current and residual current from neutral point CT.
Each side of transformer can be equipped with one group of REF protection, i.e., for a
three-winding transformer, up to three groups of REF protection can be equipped, and this device
can support only one group of REF protection. REF protection is not affected by inrush current
and the tap of transformer. CT transient detection function based on the ratio of residual current to
positive current is adopted to eliminate the influence of difference of transient characteristic to
REF protection.
*
HV side I_H LV side

*
*
3I0Cal'
Magnitude compensation
REF at HV side INP

I'NP
*
Figure 3.27-1 Application for one side of a transformer
The protection function can provide 1 sets of three-phase current inputs and 1 neutral point

Date: 2021-08-01
current input.
Before REF protection is put into service on site, polarity of neutral point
CT must have been checked by a primary current injection test. Otherwise
an undesired operation may occur during an external earth fault.
3.27.1.2 Fault Detector
The pickup criterion of REF protection is:

3
I0d>[64REF.I_Biased] Equation 3.27-1
Where:
I0d is the residual differential current.
3.27.1.3 Amplitude Compensation
If CTs used for REF protection have different primary rated values, the device will automatically
adjust the currents with respective correction ratio shown as below.
I1n
Klph =  Klb / I 2n and K lb = min(
I1n _ max
,4) Equation 3.27-2
I1n _ max I1n _ min
Where:
K1ph is the correction coefficient of the calculated side.
I1n is CT primary rated value of the calculated side.
I2n is CT second rated value of the calculated side.
I1n_min is minimum primary rated value among all CTs for REF protection.
I1n_max is maximum primary rated value among all CTs for REF protection.
This calculation method is to take the minimum CT primary rated value of all calculated sides as
the reference side. If the multiple of maximum CT primary rated value to minimum CT primary
rated value is greater than 4, then reference side shall be taken as 4 and other sides shall be
calculated proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be
calculated proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient (Kco).

Date: 2021-08-01
When selecting CT, the primary currents for each side muse follow the
criterion: I1n _ max  128 , it is recommended that the ratio is smaller than 16.
I1n _ min
Theoretically, the ratio is preferred to be as small as it can be.
3.27.1.4 Calculate Differential and Restraint Current
The equation of calculating residual differential current is:
3 𝐼0𝑑 = 𝐾𝑐𝑜 3𝐼0_𝐶𝑎𝑙 + 𝐾𝑐𝑜𝑁𝑃 𝐼𝑁𝑃

The above equation can be simplified to the following:
𝐼0𝑑 = 3𝐼′0_𝐶𝑎𝑙 + 𝐼′𝑁𝑃 Equation 3.27-3
Where:
I0d is the residual differential current.
3I0_Cal is the secondary value of calculated residual current.
INP is the secondary current of neutral point.
I'0 is the secondary value of corrected calculated residual current.
I'NP is the the secondary corrected current of neutral point.
Kco is the correction coefficient of amplitude compensation.
KcoNP is the correction coefficient of amplitude compensation of neutral point.
The equation of calculating residual restraint current is:
𝐼0𝑟 = 𝑀𝑎𝑥(3𝐼′0_𝐶𝑎𝑙 , 𝐼′𝑁𝑃 ) Equation 3.27-4
Where:
I0r is the residual restraint current.
Ia
*
A
Ib
*
B
Ic
*
INP
*
3I0_Cal' =I'a+I'b+I'c
I'NP REF
Figure 3.27-2 REF protection principle

Date: 2021-08-01
1. Through-flowing current under undisturbed conditions or external fault:
I’NP flows into the protected zone from ground, 3I0_Cal' leaves the protected zone, i.e. I’NP is
negative according to the definition of signs in above figure, therefore I’NP =-3I0_Cal'.
I0d=|3I0_Cal'+ I’NP|=|3I0_Cal'–3I0_Cal'|=0
I0r=Max(|3I0_Cal'|, |I’NP|)=|3I0_Cal'|
No differential current, but restraint current corresponds to the through-flowing current, hence,
REF protection does not operate.
2. Internal short-circuit:
Assume that I’NP =3I0_Cal'

3
3I0d=|3I0_Cal'+ I’NP |=2x|3I0_Cal'|
3I0r=Max(|3I0_Cal'|, |I’NP|) =|3I0_Cal'|
Differential current are two times of restraint current, hence, REF protection operates.
3.27.1.5 Operation Criterion
The operation criteria of REF protection protection are as follows:
𝐼0𝑑 > [64𝑅𝐸𝐹. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑]⁡⁡⁡⁡⁡(𝐼0𝑟 ≤ [64𝑅𝐸𝐹. 𝐼_𝐾𝑛𝑒𝑒])
𝐼0𝑑 > [64𝑅𝐸𝐹. 𝑆𝑙𝑜𝑝𝑒] × (𝐼0𝑟 − [64𝑅𝐸𝐹. 𝐼_𝐾𝑛𝑒𝑒]) + [64𝑅𝐸𝐹. 𝐼_𝐵𝑖𝑎𝑠𝑒𝑑] Equation 3.27-5
I0d = |3İ0_Cal + İNP |

I0r = max{|3İ0_Cal |, |İNP |}
Where:
𝐼0𝑑 and 𝐼0𝑟 are the differential current and the restraint current respectively.
3İ0_Cal is the calculated residual currents.
İNP is the residual current from neutral point CT.

Date: 2021-08-01
Differential current
K=2
3
[64REF.Slope]
[64REF.I_Biased]
Restraint current
[64REF.I_Knee]
Figure 3.27-3 Operation characteristic of REF protection
3.27.1.7 Direction Criterion
In order to ensure the selectivity of restricted earth fault protection, direction criterion is also
available. The setting [64REF.En_Dir_Blk] is used to enable/disable the function of direction
criterion blocking REF protection. The direction criterion is based on the different direction
characteristic of neutral-point current INP and calculated residual current 3I0_Cal for an external
earth fault and an internal earth fault.
For an external earth fault, the neutral-point current INP and the calculated residual current
3I0_Cal have equal magnitude, but they are of approximately opposite directions.
For external fault
3I0_Cal
ROA (Relay Operate Angle)
3I0_NP
ROA
Figure 3.27-4 Currents at an external earth fault
For an internal earth fault, the magnitudes of the two currents INP and 3I0_Cal may be different,
but their relative directions are within a certain angle range. The operation angle setting

Date: 2021-08-01
[64REF.ROA] is equipped in the device, it will be judged as an internal earth fault and the direction
criterion will be released when the relative angle of the two currents is lower than the setting.
For internal fault
ROA
3I0_Cal
3I0_NP
ROA
3
Figure 3.27-5 Currents at an internal earth fault
Or when INP >K×3I0_Cal (K is an internal setting), it will also be judged as an internal earth fault
and the direction criterion will be released.
3.27.1.8 CT Transient Characteristic Difference Detection
Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead to
mal-operation of REF protection. Therefore, positive-sequence current restraint blocking criterion
is adopted to prevent REF protection from mal-operation for above mentioned conditions.
When the residual current of REF protection is greater than 0 times of positive-sequence current,
it is judged that zero-sequence current is caused by a fault and release REF protection.
Positive-sequence current restraint blocking criterion is shown below. This blocking criterion is
ignored when neutral point current is greater than the internal setting, whichever is greater.
I0>β0×I1 Equation 3.27-6
Where:
I0 is the zero-sequence current.
I1 is the corresponding positive-sequence current.
β0 is a proportional constant and the value is 0.6
3.27.1.9 CT Saturation Detection
CT saturation detection function based on 2 nd and 3rd harmonics is adopted to avoid

mal-operation of REF protection during an external fault.
The criterions of CT saturation detection in REF protection are as follows
I  _ 2 nd  K 2nd  I _1st Equation 3.27-7

Date: 2021-08-01
or
3I 0 _Cal _ 2 nd  K 2nd  3I0_Cal _1st
or
I  _ 3rd  K 3rd  I _1st
or
3I 0 _ Cal _ 3rd  K 3rd  3I 0 _ Cal _1st
Where:
I _1st is the fundamental component of one phase current, it won’t do CT saturation detection
3 unless the fundamental component is higher than the corresponding internal setting.
3I0_Cal _1st is the fundamental component of calculated residual current.
I  _ 2 nd is the secondary harmonic of the same phase current.
3I 0_Cal _ 2nd is the secondary harmonic of calculated residual current.
I  _ 3rd is the third harmonic of the same phase current.
3I 0 _ Cal _ 3rd is the third harmonic of calculated residual current.
K 2nd and K 3rd are fixed coefficients of secondary and third harmonics respectively.
If any one of the above criterion is met, it will be considered that it is CT saturation to cause this
differential current and restricted earth fault protection will be blocked.
3.27.1.10 CT Circuit Supervision
CT circuit supervision for REF protection is divided into two kinds: differential CT circuit
abnormality without the pickup of the fault detector and differential CT circuit failure with the
pickup of the fault detector.
⚫ CT Circuit Abnormality
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF protection will
be issued without blocking the protection.
The operation formula is as follows:
I0d>max(0.1×I0r, [64REF.I_Alm]) Equation 3.27-8
⚫ CT Circuit Failure
Please refer to Section 3.36 for details.

Date: 2021-08-01
64REF
64REF.in_I3P 64REF.3I0d
64REF.in_I1P 64REF.3I0r
64REF.Enable 64REF.I0_Th
64REF.Block 64REF.St
64REF.Op
64REF.On 3
64REF.Blocked
64REF.Valid
64REF.Alm_Diff
64REF.Alm_CTS
3.27.3 I/O Signals

1 64REF.in_I3P Three-phase current data input for REF protection
2 64REF.in_I1P Residual current data input for REF protection
Input signal of enabling REF protection. It is triggered from binary input or
3 64REF.Enable
Input signal of blocking REF protection. It is triggered from binary input or
4 64REF.Block
1 64REF.3I0d Residual differential current of REF protection
2 64REF.3I0r Residual restraint current of REF protection
3 64REF.3I0_Th Threshold of residual restraint current of REF protection
4 64REF.St REF protection starts.
5 64REF.Op REF protection operates.
6 64REF.On REF protection is enabled.
7 64REF.Blocked REF protection is blocked.
8 64REF.Valid REF protection is valid.
9 64REF.Alm_Diff Differential current of REF protection is abnormal.
10 64REF.Alm_CTS CT secondary circuit of REF protection is abnormal.

Date: 2021-08-01
3.27.4 Logic
EN [64REF.En] &
64REF.On
SIG 64REF.Enable
&
SIG 64REF.Block >=1 64REF.Blocked
SIG Fail_Device
&
64REF.Valid
3
Figure 3.27-6 Logic of enabling restricted earth fault protection
SET I0d>[64REF.I_Biased] &

0 500ms &
64REF.Pkp
SIG 64REF.On
FD.Pkp
SIG 64REF.Valid
Figure 3.27-7 Pickup logic of restricted earth fault protection
SIG Flag_64REF &
SIG I0>β0×I1
&
SIG CT saturation
SIG CT circuit failure &
EN [64REF.En_CTS_Blk] 64REF.St
SIG INP>0.04In >=1 &

[64REF.t_Op] 0ms 64REF.Op
EN [64REF.En_NPCurr]
SIG 64REF.Dir_op >=1
EN 64REF.En_Dir_Blk
SIG 64REF.Pkp
Figure 3.27-8 Logic diagram of restricted earth fault protection
Where:
“Flag_64REF” means that operation criterion of REF protection is satisfied.
INP is the measured residual current of neutral point.

Date: 2021-08-01
3.27.5 Settings
Access path: MainMenu  Settings  Protection Settings  REF Settings
No. Name Range Unit Default Description

1 64REF.I_Biased 0.050~5.000 In 0.500 Pickup current setting of REF protection
Current setting of REF protection
2 64REF.I_Alm 0.050~1.500 In 0.200
abnormality alarm
Knee point setting of REF protection,
3 64REF.I_Knee 0.100~4.000 In 0.500
0.5In is recommended.
Percentage restraint coefficient of REF
4 64REF.Slope 0.200~0.750 - 0.500
protection, 0.5 is recommended. 3
Operation angle setting of REF
5 64REF.ROA 45.000~90.000 deg 60.000
protection
Current setting of neutral-point on-load
6 64REF.I_NP_OnLoad 0.040~40.000 A 0.001
criterion.
Time delay for REF protection, the
7 64REF.t_Op 0.000~20.000 s 0.000
recommended value is 0.
Enabled, Logic setting for enabling/disabling
8 64REF.En - Disabled
Disabled REF protection
9 64REF.En_NPCurr - Disabled
Disabled neutral current criterion
Logic setting for enabling/disabling
Enabled,
10 64REF.En_CTS_Blk - Enabled blocking REF protection during CT
Disabled
circuit failure
Logic setting for enabling/disabling the
Enabled,
11 64REF.En_Dir_Blk - Disabled function of direction criterion blocking
Disabled
REF protection
3.28 Arc Flash Protection (50L/NL)
Arc protection is used to protect the medium and low voltage switchgear cabinet. Due to the
compact structure and narrow space of the switchgear cabinet, when two-phase or three-phase
short-circuit fault occurs, it is often accompanied by a strong arcing phenomenon. The arc flash
signal is acquired by an arc sensor installed in the switchgear cabinet, it is combined with the
auxiliary fault current criterion, then the arc flash protection can operate to trip to isolate the fault.
The device can support up to 4 channels of arc flash signals, each channel is composed of arc
sensor and optical fiber, and can be enabled/disabled by the setting [50L/NL.Map_En_Sensor].
The arc sensor type is point sensor, and the connector between the optical fiber and the device is
ST type connector. Because the arc energy for a busbar fault is mainly concentrated within the
ultraviolet light range of 300~400nm (namometer), the arc sensor of the device adopts ultraviolet
light sensor, the sensor can ensure the reliable detection of arc signal and effectively prevent the

Date: 2021-08-01
adverse effects of interference light (natural light and strong light flashlight).
The arc sensor couples the optical signal and transmits the optical signal to the arc module of the
device through the dedicated arc fiber. The protection device converts the optical signal into a
weak electric analog signal through the photoelectric conversion module, and then samples and
filters the signal, and finally outputs an arc signal analog quantity. Users can check the arc
increment of the arc channel via the device menu MainMenu→Measurements→Function
Values→ArcFlash Value to determine whether the arc measurement channel is intact.
The passive arc sensor takes the arc signal through the photosensitive material and transmits the
signal to the protection device through the transmission fiber. Since the sensor is in a relatively
3 closed environment, it is not easy to be found if the sensor is damaged or the transmission fiber is
broken, if a phase-to-phase fault occurs at this time, the protection device will not be able to
acquire an accurate arc signal and it can not operate correctly.
In order to solve this problem, the arc channel self-supervision function is provided to monitor the
channel in real time. The specific method is: the protection device transmits the pulse optical
signal whose amplitude and pulse width can be modulated in real time, and it is superimposed in
the arc transmission channel. The pulse optical signal is reflected by the sensor lens and returned
to the protection device via the transmission fiber, the protection device detects the pulse optical
signal that superimposed in the sensor sampling signal in real time. If the sensor or the fiber
channel is damaged, the protection device will not receive the returned pulse optical signal, then
the arc channel abnormality alarm signal “50L/NL.Alm_Sensor0x” (x=0~4) will be issued.
Sensor
Fibre Channel Arc flash Digital
Arc flash signal signal
acquisition processing
Arc flash sensor diagram
Sensor Pulse arc

Fibre Channel Arc flash Digital
Arc flash signal signal
acquisition processing
Arc flash sensor diagram with channel supervision
Figure 3.28-1 Arc flash sensor diagram
It is necessary to add an optical signal for testing via a dedicated test instrument. First, the tester
outputs a light intensity of 5 mW, and observes the corresponding channel coefficient in the menu
MainMenu→Measurements→Function Values→ArcFlash Value, and then inputs the
coefficient as the value of the arc flash protection setting [50L/NL.K_Calbr_Sensor0x] (x=0~4),

Date: 2021-08-01
then calibrates the output light intensity of the tester. If the channel coefficient is set correctly,
adjust the output light intensity of the tester, the “50L/NL.LgtIncr_Sensor0x” (x=0~4) displayed in
the menu MainMenu→Measurements→Function Values→ArcFlash Value of the device
should be equal to the output light intensity of the tester. The operation must be done before the
arc flash protection is put into service.
The adjustment factor guarantees the accuracy of the light intensity sampling. During the
operation, if arcing caused by a short-circuit fault occurs, once the light intensity exceeds the
threshold value, the arc flash protection will operate.
The device can set whether the arc flash protection is blocked by the fault current, and the current
criterion can be enabled/disabled via the setting [50L/NL.En_CCE].
3
The logic diagram of enabling/disabling arc flash protection is shown as below:
EN 50L/NL.En & 50L/NL.On
SIG 50L/NL.Enable
& 50L/NL.Blocked
SIG 50L/NL.Block ≥1
SIG Fail_Device
& 50L/NL.Valid
Figure 3.28-2 Logic diagram of enabling/disabling arc flash protection
The operating threshold of the arc sensor can be set, if the light increment is greater than the
threshold value, the arc sensor operates. In order to realize the function of fast busbar protection,
the device provides an external arc flash protection tripping binary input (50L/NL.ExTrp), which
can be used to trigger the arc flash protection of local device directly. So the arc flash protection of
the device can be triggered by the arc flash protection of other bays. The external arc flash
protection tripping binary input is “0” if it is not configured. The operating logic is as shown below:
LgtIncr>[50L/NL.LgtIncr_
SET
Set_Sensor0x] &
& 50L/NL.Op_Sensor0x
EN 50L/NL.Map_En_Sensor
50L/NL.Alm_Sensor0x
SIG
(x=1, 2, 3 or 4)
Figure 3.28-3 Logic diagram of the arc sensor
The logic diagram of the fault detector of arc flash protection is shown in Figure 3.29-3.

Date: 2021-08-01
SET Ia>0.95*[50L/NL.I_Set] ≥1
Ia.Pkp
SET ∆Ia>0.2In+Ith_Float
SET Ib>0.95*[50L/NL.I_Set] ≥1
Ib.Pkp
SET ∆Ib>0.2In+Ith_Float
SET Ic>0.95*[50L/NL.I_Set] ≥1
Ic.Pkp
SET ∆Ic>0.2In+Ith_Float
3 SIG Ia.Pkp ≥1
SIG Ib.Pkp ≥1
SIG Ic.Pkp
&
EN 50L/NL.En_CCE
SIG 50L/NL.Op_Sensor0x &

50L/NL.Map_En_Sensor
EN
_Trp ≥1
SIG 50L/NL.ExTrp
&
SIG 50L/NL.On 0ms 500ms
& 50L/NL.Pkp
SIG 50L/NL.Valid
FD.Pkp
SIG 50L/NL.Blocked
Figure 3.28-4 Logic diagram of the fault detector of arc flash protection
Where:
Ith_Float: the current floating threshold value.

Date: 2021-08-01
50L/NL
50L/NL.Enable 50L/NL.On
50L/NL.Block 50L/NL.Blocked
50L/NL.ExTrp 50L/NL.Valid
50L/NL.St
50L/NL.StA
50L/NL.StB
50L/NL.StC
50L/NL.Op 3
50L/NL.Op.PhA
50L/NL.Op.PhB
50L/NL.Op.PhC
50L/NL.Alm_Sensor01
50L/NL.Alm_Sensor02
50L/NL.Alm_Sensor03
50L/NL.Alm_Sensor04
3.28.3 I/O Signals

Arc flash protection enabling input, it is triggered from binary input or
1 50L/NL.Enable
Arc flash protection blocking input, it is triggered from binary input or
2 50L/NL.Block
The external arc flash protection tripping binary input, which can be used to
3 50L/NL.ExTrp
trigger the arc flash protection of local device directly.
1 50L/NL.On Arc flash protection is enabled
2 50L/NL.Blocked Arc flash protection is blocked
3 50L/NL.Valid Arc flash protection is valid
4 50L/NL.St Arc flash protection starts
5 50L/NL.StA Arc flash protection starts (Phase A)
6 50L/NL.StB Arc flash protection starts (Phase B)
7 50L/NL.StC Arc flash protection starts (Phase C)
8 50L/NL.Op Arc flash protection operates
9 50L/NL.Op.PhA Arc flash protection operates (Phase A)
10 50L/NL.Op.PhB Arc flash protection operates (Phase B)
11 50L/NL.Op.PhC Arc flash protection operates (Phase C)
12 50L/NL.Alm_Sensor01 Arc sensor 01 channel abnormality alarm signal

Date: 2021-08-01
3.28.4 Logic
SIG Ia.Pkp ≥1
SIG Ib.Pkp ≥1
SIG Ic.Pkp
EN 50L/NL.En_CCE
&
SIG 50L/NL.Op_Sensor0x [50L/NL.t_Op] 50L/NL.Op
SIG 50L/NL.Pkp
3 Figure 3.28-5 Logic diagram of arc flash protection
3.28.5 Settings
Access path: MainMenu  Settings  Protection Settings  ArcFlash Settings

The light increment operating setting
50L/NL.LgtIncr_Set 2
1 5~30 8 mW/cm 0.1 of the arc sensor 01 of arc flash
_Sensor01
protection
_Sensor02
protection
50L/NL.LgtIncr_Set
3 5~30 8 mW/cm2 0.1 of the arc sensor 03 of arc flash
_Sensor03
protection
50L/NL.LgtIncr_Set
4 5~30 8 mW/cm2 0.1 of the arc sensor 04 of arc flash
_Sensor04
protection
50L/NL.K_Calbr_Se The channel coefficient of the arc
5 1~30000 3300 - 1
nsor01 sensor 01 of arc flash protection
6 1~30000 3300 - 1
7 1~30000 3300 - 1
8 1~30000 3300 - 1
This setting is used to enable/disable
each arc sensor, it is set by bit, a total
of 4 bits, from low to high,
50L/NL.Map.En_Se
9 0X0~0XF 0XF - - corresponds to the arc channel 1, 2,
nsor
3, 4 respectively. If any bit is “1”, the
corresponding arc channel is
enabled.

Date: 2021-08-01
The current setting of arc flash

10 50L/NL.I_Set 0.05~200 6 A 0.001
protection
The time delay setting of arc flash
11 50L/NL.t_Op 0~1 0 s 0.001
protection
Disabled; The logic setting for
12 50L/NL.En Disabled - -
Enabled enabling/disabling arc flash protection
Disabled;
13 50L/NL.En_CCE Disabled - - enabling/disabling the current
Enabled
criterion of arc flash protection
the tripping of each arc sensor, it is 3
set by bit, a total of 4 bits, from low to
50L/NL.Map.En_Se
14 0X0~0XF 0XF - - high, corresponds to the arc channel
nsor_Trp
1, 2, 3, 4 respectively. If any bit is “1”,
the tripping of corresponding arc
channel is enabled.
3.29 Current Unbalance Protection (60/50)
The current unbalance protection is adopted for the internal fault of capacitor bank with
double-star connection. The fault causes the capacitance reactance of a phase branch to be
changed, makes three phase reactance unequal and the unbalance current will be generated at
neutral point.
The application of the current unbalance protection in the capacitor bank with double-star
connection is shown in following figure.
52 52 52
Br1 Br2 Br1 Br2 Br1 Br2
1CT
60/50
*
Figure 3.29-1 Application of the current unbalance protection

Date: 2021-08-01
This device provides two stages of current unbalance protection. If the unbalance current is
greater than the predefined setting, this protection will operate. The current unbalance protection
is with independent definite-time delay characteristic and with instantaneous drop-out
characteristic.
The current unbalance protection protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, current unbalance protection needs to be blocked by
the external signal, so the device provides a function block input signal to be used to block current
unbalance protection. The enabling and blocking logic of current unbalance protection is shown in
3 the figure below:
EN 60/50-x.En & 60/50-x.On
SIG 60/50-x.Enable
& 60/50-x.Blocked
SIG 60/50-x.Block ≥1
SIG Fail_Device
& 60/50-x.Valid
Figure 3.29-2 Logic diagram of enabling/disabling current unbalance protection
When the current unbalance protection is enabled and no external blocking signal is input, if the
unbalance current is greater than the current setting multiplied by 0.95 of the current unbalance
protection, the current unbalance protection will pick up.
The logic diagram of the fault detector of current unbalance protection is shown in Figure 3.29-3.
SET Iu > [60/50-x.I_Set] × 0.95 & 60/50-x.Pkp

0ms 500ms
&
SIG 60/50-x.On & FD.Pkp
SIG 60/50-x.Valid
EN [60/50-x.Opt_Trp/Alm]=Alm
Figure 3.29-3 Logic diagram of the fault detector of current unbalance protection
The current unbalance protection has definite-time delay characteristic complied with IEC
60255-3 and ANSI C37.112. If the unbalance current is greater than the current setting of the
current unbalance protection [60/50-x.I_Set] (x: 1~2), the current unbalance protection will
operate after the time setting [60/50-x.t_Op] (x: 1~2).
The operation characteristic curve of current unbalance protection is shown in Figure 3.29-4.

Date: 2021-08-01
t op
I u_set Iu
Figure 3.29-4 Operation characteristic curve of current unbalance protection
The current unbalance protection is with instantaneous drop-out characteristic. If the unbalance
current is less than the current setting [60/50-x.I_Set] (x: 1~2) multiplied by 0.95, the current
unbalance protection will drop out at once.
60/50
60/50-x.Enable 60/50-x.On
60/50-x.Block 60/50-x.Blocked
60/50-x.Valid
60/50-x.St
60/50-x.Op
60/50-x.Alm
3.29.3 I/O Signals

Stage x of current unbalance protection enabling input, it is triggered from binary
1 60/50-x.Enable
Stage x of current unbalance protection blocking input, it is triggered from binary
2 60/50-x.Block
1 60/50-x.On Stage x of current unbalance protection is enabled.
2 60/50-x.Blocked Stage x of current unbalance protection is blocked.
3 60/50-x.Valid Stage x of current unbalance protection is valid.
4 60/50-x.St Stage x of current unbalance protection picks up.

Date: 2021-08-01
5 60/50-x.Op Stage x of current unbalance protection operates.

6 60/50-x.Alm Stage x of current unbalance protection alarms.
3.29.4 Logic
60/50-x.St
SET Iu > [60/50-x.I_Set] &

[60/50-x.t_Op] 0 & 60/50-x.Op
SIG 60/50-x.Pkp
3 SET [60/50-x.Opt_Trp/Alm] = Trp

& 60/50-x.Alm
SET [60/50-x.Opt_Trp/Alm] = Alm
Figure 3.29-5 Logic diagram of current unbalance protection
3.29.5 Settings
Access path: MainMenu  Settings  Protection Settings  UnbalCurr Settings

The current setting of stage 1 of current
1 60/50-1.I_Set 0.02~200 1 A 0.001
unbalance protection
2 60/50-1.t_Op 0.05~100 0.1 s 0.001
current unbalance protection
Disabled; The logic setting for enabling/disabling
3 60/50-1.En Enabled - -
Enabled stage 1 of current unbalance protection
Enabling stage 1 of current unbalance
4 60/50-1.Opt_Trp/Alm Trp - -
5 60/50-2.I_Set 0.02~200 1 A 0.001
6 60/50-2.t_Op 0.05~100 0.1 s 0.001
7 60/50-2.En Enabled - -
3.30 Voltage Unbalance Protection (60/59)
The voltage unbalance protection is adopted for the internal fault of capacitor bank with

Date: 2021-08-01
double-star connection. The fault causes the capacitance reactance of a phase branch to be
changed, makes three phase reactance unequal and the unbalance voltage will be generated at
neutral point.
The application of the voltage unbalance protection for a capacitor bank with double-star
connection is shown in following figure.
60/59N
Figure 3.30-1 Application of the voltage unbalance protection
This device supports two stages of voltage unbalance protection. If the unbalance voltage is
greater than the predefined setting, this protection will operate. The voltage unbalance protection
is with independent definite-time delay characteristic and with instantaneous drop-out
characteristic. In order to adapt to different applications, voltage unbalance protection can operate
to trip or alarm, it can be enabled or blocked by the external binary input.
Voltage unbalance protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, voltage unbalance protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block voltage unbalance
protection. The enabling and blocking logic of voltage unbalance protection is shown in the figure
below:

Date: 2021-08-01
EN 60/59-x.En & 60/59-x.On
SIG 60/59-x.Enable
& 60/59-x.Blocked
SIG 60/59-x.Block ≥1
SIG Fail_Device
& 60/59-x.Valid
3 Figure 3.30-2 Logic diagram of enabling/disabling voltage unbalance protection
When the voltage unbalance protection is enabled and no external blocking signal is input, if the
unbalance voltage is greater than the voltage setting multiplied by 0.95, the voltage unbalance
protection will pick up.
The logic diagram of the fault detector of voltage unbalance protection is shown as below.
SET Uu > [60/59-x.U_Set]×0.95 & 60/59-x.Pkp

0ms 500ms
&
SIG 60/59-x.On & FD.Pkp
SIG 60/59-x.Valid
EN [60/59-x.Opt_Trp/Alm]=Alm
Figure 3.30-3 Logic diagram of the fault detector of voltage unbalance protection
The voltage unbalance protection can operate with a definite-time limit.
When the unbalance voltage (Uub) is larger than the voltage setting, the protection operates with a
time delay of top (i.e. the value of the setting [60/59-x.U_Set] (x=1~2)), and the operation

Date: 2021-08-01
t op
Uu_set Uu
Figure 3.30-4 Operation characteristic curve of voltage unbalance protection
The voltage unbalance protection is with instantaneous drop-out characteristic. If the unbalance
voltage is less than the voltage setting multiplied by 0.95, the voltage unbalance protection will
drop out immediately.
60/59
60/59-x.Enable 60/59-x.On
60/59-x.Block 60/59-x.Blocked
60/59-x.Valid
60/59-x.St
60/59-x.Op
60/59-x.Alm
3.30.3 I/O Signals

Stage x of voltage unbalance protection enabling input, it is triggered from
1 60/59-x.Enable
Stage x of voltage unbalance protection blocking input, it is triggered from binary
2 60/59-x.Block
1 60/59-x.On Stage x of voltage unbalance protection is enabled.
2 60/59-x.Blocked Stage x of voltage unbalance protection is blocked.
3 60/59-x.Valid Stage x of voltage unbalance protection is valid.
4 60/59-x.St Stage x of voltage unbalance protection starts

Date: 2021-08-01
5 60/59-x.Op Stage x of voltage unbalance protection operates.

6 60/59-x.Alm Stage x of voltage unbalance protection alarms.
3.30.4 Logic
60/59-x.St
SET Uu > [60/59-x.U_Set] &

[60/59-x.t_Op] 0 & 60/59-x.Op
SIG 60/59-x.Pkp
3 SET [60/59-x.Opt_Trp/Alm] = Trp

& 60/59-x.Alm
SET [60/59-x.Opt_Trp/Alm] = Alm
Figure 3.30-5 Logic diagram of voltage unbalance protection
3.30.5 Settings
Access path: MainMenu  Settings  Protection Settings  UnbalVolt Settings

The voltage setting of stage 1 of voltage
1 60/59-1.U_Set 1~63.5 50 V 0.001
The time setting of stage 1 of voltage
2 60/59-1.t_Op 0.1~100 1 s 0.001
3 60/59-1.En Enabled - -
Enabled stage 1 of voltage unbalance protection
Enabling stage 1 of voltage unbalance
5 60/59-2.U_Set 1~63.5 50 V 0.001
6 60/59-2.t_Op 0.1~100 1 s 0.001
7 60/59-2.En Enabled - -
3.31 Automatic Reclosure (79)

To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by

Date: 2021-08-01
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. AR are installed to restore the faulted section of the
transmission system once the fault is extinguished (providing it is a transient fault). For certain
transmission systems, AR is used to improve system stability by restoring critical transmission
paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and AR is not initiated after faulty feeder is tripped. For some
mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines, etc., it is
required to ensure that AR is only initiated for faults overhead line section, or make a choice
according to the situation. 3
AR can be used with either integrated device or external device. When AR is used with integrated
device, the internal protection logic can initiate AR, moreover, a tripping contact from external
device can be connected to the device via input signal to initiate integrated AR.
When AR is used as an independent device, it can be initiated by operating signal of protections.

The device can output some configurable output signals (such as, contact signals or digital signal,
for example, GOOSE signal) to initiate external AR or block external AR. The contact signals
includes tripping signal, blocking AR signal and protection operating signal, etc,. According to
requirement, these contacts can be selectively connected to external AR and the device can be
set as one-shot or multi-shot AR.
3.31.1.1 Enable AR
When the setting [79.Opt_Enable] is set as "Setting&Config", AR is determined whether it is

enabled or disabled by the external input signal and the internal setting. Otherwise, it is only
determined by the internal setting. When AR is enabled, the device outputs the signal "79.On",
otherwise the device outputs the signal "79.Off".
The logic of enabling AR is:
EN [79.En] &
>=1
SET [79.Opt_Enable]=Setting 79.On
SET [79.Opt_Enable]=Setting&Config & 79.Off
SIG 79.Enable
&
SIG 79.Block
Figure 3.31-1 Logic of enabling AR
3.31.1.2 Synchronism Check for AR
When the synchronism check mode of auto-reclosing is independent of that of manual closing, the

Date: 2021-08-01
device provides dedicated settings used by synchronism check for AR. The synchronism check
mode can be determined by the settings or configuration signals. When the setting
[79.Opt_RSYN_ValidMode] is set as "Setting", the synchronism check mode for AR is determined
by the settings, [79.En_SynChk], [79.En_SynDd_RefDd], [79.En_SynLv_RefDd],
[79.En_SynDd_RefLv] and [79.En_NoChk]. When the setting [79.Opt_RSYN_ValidMode] is set
as "Config", the synchronism check mode for AR is determined by configuration signals,
"79.Sel_SynChk", "79.Sel_SynDd_RefDd", "79.Sel_SynLv_RefDd", "79.Sel_SynDd_RefLv"
and "79.Sel_NoChk".
1
EN [79.En_SynChk]
3 SIG 79.Sel_SynChk
79.On_SynChk
0
1
EN [79.En_SynDd_RefDd]
79.On_SynDd_RefDd
SIG 79.Sel_SynDd_RefDd
0
1
EN [79.En_SynLv_RefDd]
79.On_SynLv_RefDd
SIG 79.Sel_SynLv_RefDd
0
1
EN [79.En_SynDd_RefLv]
79.On_SynDd_RefLv
SIG 79.Sel_SynDd_RefLv
0
1
EN [79.En_NoChk]
79.On_NoChk
SIG 79.Sel_NoChk
0
EN [79.Opt_RSYN_ValidMode]
Figure 3.31-2 Logic of synchronism check mode selection for AR
Based on the chosen synchronism check mode for AR, the device judges whether the
synchronism condition is satisfied, and then implement reclosing. When none of the synchronism
check modes for AR is selected, the device will issue an alarm "79.Alm_RSYN_Mode".
3.31.1.3 AR Ready
AR must be ready to operate before performing reclosing. The output signal [79.Ready] means
that the auto-reclosure can perform at least one time of reclosing function, i.e., breaker
open-close-open.
When the device is energized or after the settings are modified, AR cannot be ready unless the
following conditions are met:
1. AR is enabled.
2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.

Date: 2021-08-01
3. The duration of the circuit breaker in closed position pre-fault is greater than the setting
[79.t_CBClsd].
4. There is no the signal of blocking AR.
After AR operates, it must reset, i.e. [79.Active]=0, in addition to the above conditions for reclosing
again.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After the fault is cleared, the tripping signal will drop out immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [79.t_PersistTrp], AR will be blocked, as shown in following figure
The input signal [79.CB_Healthy] must be energized before AR gets ready. Because most circuit
3
breakers can finish one complete process: open-closed-open, it is necessary that circuit breaker
has enough energy before reclosing. When the time delay of AR is exhausted, AR will be blocked
if the input signal [79.CB_Healthy] is still not energized within time delay [79.t_CBReady]. If this
function is not required, the input signal [79.CB_Healthy] can be not to configure, and its state will
be thought as “1” by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input signal of blocking AR, when the circuit breaker is open by manually and there is CB
position input under normal conditions, AR will be blocked with the time delay of 100ms if AR is
not initiated and no any trip signal.
SIG Any tripping signal [79.t_PersistTrp] 0 >=1

0 [79.t_DDO_Blk] 79.Blocked
SIG 79.LockOut
Figure 3.31-3 Logic of AR block
When AR is disabled, AR fails, synchronism check fails or last shot is reached, or when the
internal blocking condition of AR is met. AR will be discharged immediately and next AR will be
disabled. When the input signal [79.LockOut] is energized, AR will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, AR will be blocked immediately. The logic of AR ready is shown as
below
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop out with a time delay [79.t_DDO_Blk] after blocking signal disappears.

Date: 2021-08-01
>=1
SIG CB closed position [79.t_CBClsd] 100ms &
SIG 79.Active >=1
SIG Any tripping signal

& &
2s 0 79.Ready
SIG 79.Inprog
BI [79.CB_Healthy] 0 [79.t_CBReady] &
3 SIG 79.Blocked >=1

>=1
SIG 79.Lockout &
SIG 79.Failed
>=1
SIG 79.Fail_Chk
SIG Last shot is made
SIG 79.On
Figure 3.31-4 Logic of AR ready
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop out (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
3.31.1.4 AR Initiation
AR can be initiated by the tripping signal of line protection or CB state.
1. AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from
internal trip signal or external trip signal.
When AR is ready to reclosing (“79.Ready”=1) and the tripping signal is received, this tripping
signal will be kept in the device, and AR will be initiated after the tripping signal drops out. The
tripping signal kept in the device will be cleared after the completion of AR sequence (Reset
Command). Its logic is shown as below.
SIG Reset Command &

>=1
SIG Trip Signal
& AR Initiation
SIG 79.Ready
Figure 3.31-5 Tripping initiating AR

Date: 2021-08-01
2. AR initiated by CB state
AR can be initiated by CB state by setting the setting [79.En_CBInit]. Under normal conditions,
when AR is ready to reclose (“79.Ready”=1), AR will be initiated if circuit breaker is open and
corresponding phase current is nil. AR initiated by CB state logic is shown as below. Usually
normally closed contact of circuit breaker is used to reflect CB state.
SIG CB open
&
EN [79.En_CBInit] & AR Initiation
SIG 79.Ready
3
Figure 3.31-6 CB state initiating AR
3.31.1.5 AR Reclosing
When the dead time delay of AR expires after AR is initiated, if the synchronism check is enabled,
the release of reclosing signal shall be subject to the result of synchronism check.
After the dead time delay of AR expires, if the synchronism check is still unsuccessful within the
time delay [79.t_wait_Chk], the signal of synchronism check failure ("79.Fail_Chk") will be output
and the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of synchronism
check success ("25.RSYN_OK") will always be established. And the signal of synchronism check
success ("25.RSYN_OK") from the synchronism check logic can be applied by AR inside the
device or outside the device.
[79.t_Dd_3PS1] 0 & AR Pulse

If 79.Inhibit_AR operates,
SIG 79.Inhibit_AR then circuit of time delay
will be interrupted. >=1
& [79.t_Wait_Chk] 0 79.Fail_Chk
SIG 3-pole AR Initiation
SIG 79.Ok_Chk
Figure 3.31-7 One-shot AR
Reclosing pulse length may be set through the setting [79.t_PW]. For the circuit breaker without
anti-pump interlock, the setting [79.En_CutPulse] is available to control the reclosing pulse. When
this function is enabled, if the device operates to trip during reclosing, the reclosing pulse will drop
out immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing signal is
issued, AR will drop out with time delay [79.t_Reclaim], and can carry out next reclosing.
The reclaim timer is started when the CB closing signal is given. The reclaim timer defines a time
from the issue of the reclosing command, after which the reclosing function resets. Should a new
trip occur during this time, it is treated as a continuation of the first fault.

Date: 2021-08-01
SIG AR Pulse 0ms [79.t_PW]
& 79.Out
SIG Three - phase Trip
&
EN [ 79.En _ CutPulse ]
>=1
&
SIG 79.Out [79.t_ Reclaim] 0ms Reset Command
3
Figure 3.31-8 Reclosing output logic
3.31.1.6 Reclosing Failure and Success
For line fault, the fault will be cleared after the device operates to trip. When the following cases
appear, the reclosing is unsuccessful.
1. If any protection element operates to trip when AR is enabled ("79.On"=1) and AR is not
ready ("79.Ready"=0), the device will output the signal "79.Failed".
2. For one-shot AR, if the tripping signal is received again within reclaim time after the reclosing
pulse is issued, the reclosing shall be considered as unsuccessful.
3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping signal is received again after the last reclosing pulse is issued, the reclosing shall be
considered as unsuccessful.
4. The setting [79.En_FailCheck] is available to judge whether the reclosing is successful by CB

state, when it is set as “Enabled”. If CB is still in open position with a time delay [79.t_Fail]
after the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this
case, the device will issue a signal "79.Failed" to indicate that the reclosing is unsuccessful,
and this signal will drop out after (Reset Command). AR will be blocked if the reclosing shall
be considered as unsuccessful.
After unsuccessful AR is confirmed, AR will be blocked.

Date: 2021-08-01
SIG 79.On
&
SIG 79.Ready
SIG Any tripping command

& >=1
0 100ms
>=1
SIG Last shot is made 79.Failed
SIG 79.Inprog
&
SIG 79.Blocked
>=1
3
SIG AR Pulse &
[79.t_Fail ] 0
&
SIG CB closed
EN [79.En_ FailCheck ]
&
79.Succeeded
&
0 [79.t_Fail ]
SIG Reset Command 0s 2s 79.Completed
Figure 3.31-9 Reclosing failure and success
3.31.1.7 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.Num], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
⚫ [79.Num]=1
It means one-shot reclosing. Line protection device will operate to trip when a transient fault
occurs on the line and AR will be initiated. After the dead time delay for AR is expired, the device
will send reclosing pulse, and then AR will drop out after the time delay [79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and the device will output the signal of reclosing failure "79.Failed".
⚫ [79.Num]>1
It means multi-shot reclosing. For multi-shot reclosing, line protection device will operate to trip
when a transient fault occurs on the line and AR will be initiated. After the dead time delay of the
first reclosing is expired, the device will send reclosing pulse, and then AR will drop out after the
time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will
operate to trip again after the reclosing is performed, and then AR is initiated after the tripping
contact drops off. After the time delay for AR is expired, the device will send reclosing pulse. The
sequence is repeated until the reclosing is successful or the maximum permit reclosing number
[79.Num] is reached.
3.31.1.8 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and

Date: 2021-08-01
permanent fault respectively.
Signal
Fault
Trip
CB 52b
Open [79.t_Reclaim]
3 79.t_Reclaim
79.Active
79.Inprog [79.t_Dd_3PS1]
79.Inprog_3P [79.t_Dd_3PS1]
79.Ok_Chk
AR Out [79.t_PW]
79.Perm_Trp3P
79.Failed
Time
Figure 3.31-10 Transient fault

Date: 2021-08-01
Signal
Fault
Trip
Open Open
52b
[79.t_Reclaim]
79.t_Reclaim
79.Active
79.Inprog
3
79.Inprog_3P1 [79.t_Dd_3PS1]
79.Inprog_3PS2 [79.t_Dd_3PS2]
79.Ok_Chk
AR Out [79.t_PW] [79.t_PW]
79.Perm_Trp3P
79.Failed 200ms
Time
Figure 3.31-11 Permanent fault ([79.Num]=2)

Date: 2021-08-01
79
79. Enable 79.On
79.Block 79.Off
79.Trp3P 79. Close
79. Lockout 79. Ready
79.CB_ Healthy 79.AR_Blkd
3 79.Clr_ Counter 79. Active
79. Inprog
79. Inprog_3P
79.Inprog _ 3PS1
79.Inprog _ 3PS2
79.Inprog _ 3PS3
79.Inprog _ 3PS4
79. Rcls_ Status
79.Failed
79.Succeeded
79.Completed
79.Fail_Chk
3.31.3 I/O Signals

Input signal of enabling AR, it is triggered from binary input or programmable logic
1 79.Enable
etc.
Input signal of blocking AR, it is triggered from binary input or programmable logic
2 79.Block
etc.
3 79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the operating signals
4 79.Lockout of definite-time protection, transformer protection and busbar differential
protection, etc.
The input for indicating whether circuit breaker has enough energy to perform the
5 79.CB_Healthy
close function
6 79.Clr_Counter Clear the reclosing counter
1 79.On AR is enabled.
2 79.Off AR is disabled.

Date: 2021-08-01
3 79.Close AR operates.
4 79.Ready AR have been ready for reclosing cycle.
5 79.Blocked AR is blocked.
6 79.Active AR logic is active.
7 79.Inprog AR cycle is in progress
8 79.Inprog_3P 3-pole AR cycle is in progress
9 79.Inprog_3PS1 First 3-pole AR cycle is in progress
10 79.Inprog_3PS2 Second 3-pole AR cycle is in progress
11 79.Inprog_3PS3 Third 3-pole AR cycle is in progress
12 79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
AR status 3
0: AR is preprocessed
13 79.Status 1: AR is ready.
2: AR is in progress.
3: AR is successful.
14 79.Failed Auto-reclosing fails
15 79.Succeeded Auto-reclosing is successful
16 79.Fail_Chk Synchro-check for AR fails
17 79.Completed AR is completed.
3.31.4 Settings
Access path: MainMenu  Settings  Protection Settings  AR Settings

Maximum number of reclosing
1 79.Num 1~4 1 - 1
attempts
Dead time of first shot 3-pole
2 79.t_Dd_3PS1 0~600 0.600 s 0.001
reclosing
Dead time of second shot 3-pole
3 79.t_Dd_3PS2 0~600 0.600 s 0.001
reclosing
Dead time of third shot 3-pole
4 79.t_Dd_3PS3 0~600 0.600 s 0.001
reclosing
Dead time of fourth shot 3-pole
5 79.t_Dd_3PS4 0~600 0.600 s 0.001
reclosing
Time delay of circuit breaker in
6 79.t_CBClsd 0~600 5.000 s 0.001
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
signal [79.CB_Healthy] is
7 79.t_CBReady 0~600 5.000 s 0.001
de-energized and if it is not
energized within this time delay, AR
will be blocked.
Maximum wait time for synchronism
8 79.t_Wait_Chk 0~600 10.000 s 0.001
check

Date: 2021-08-01
9 79.t_Reclaim 0~600 15.000 s 0.001 Reclaim time of AR
Drop-out time delay of blocking AR,

when blocking signal for AR
10 79.t_DDO_Blk 0~600 5.000 s 0.001
disappears, AR blocking condition
drops out after this time delay
Time delay of excessive trip signal
11 79.t_PersistTrp 0~600 0.200 s 0.001
to block AR
Time delay allow for CB status
12 79.t_Fail 0~600 0.200 s 0.001 change to conform reclosing
3 successful
13 79.t_PW 0~600 0.120 s 0.001 Pulse width of AR closing signal
Enabling/disabling confirm whether

Disabled
14 79.En_FailCheck Disabled - - AR is successful by checking CB
Enabled
state
Disabled Enabling/disabling adjust the length
15 79.En_CutPulse Disabled - -
Enabled of reclosing pulse
Disabled
16 79.En Enabled - - Enabling/disabling auto-reclosing
Enabled
Enabling/disabling AR by external
input signal besides logic setting
Setting [79.En]
17 79.Opt_Enable Setting - -
Setting&Config Setting: only the setting
Setting&Config: the setting and
configuration signal
Disabled Enabling/disabling AR be initiated
18 79.En_CBInit Disabled - -
Enabled by open state of circuit breaker
Selection of decision mode for AR
synchronism check
79.Opt_RSYN_Valid Setting;
19 Setting - - Setting: determined by the setting
Mode Config
Config: determined by the
Enabling/disabling synchro-check
Disabled of AR (valid only if the setting
20 79.En_SynChk Disabled - -
Enabled [79.Opt_RSYN_ValidMode] =
Setting)
Enabling/disabling dead check for
both the reference side and the
Disabled synchronization side (valid only if
21 79.En_SynDd_RefDd Disabled - -
Enabled the setting
[79.Opt_RSYN_ValidMode] =
Setting)

Date: 2021-08-01

Enabling/disabling live check for
synchronization side and dead
Disabled check for reference side (valid only
22 79.En_SynLv_RefDd Disabled - -
Enabled if the setting
Setting)
synchronization side and live check
Disabled
23 79.En_SynDd_RefLv Disabled - - for reference side (valid only if the
Enabled
setting [79.Opt_RSYN_ValidMode]
= Setting)
3
Enabling/disabling AR without any
Disabled check (valid only if the setting
24 79.En_NoChk Enabled - -
Setting)
3.32 Another Group of Phase Overcurrent Protection (S2.50/51P)

Sometimes there are two branches on the low-voltage side of a transformer. The currents of each
branch can be connected to two devices to achieve redundancy, and two groups of CTs are
connected in series. A grounding transformer is connected to the low-voltage side of the main
transformer at the same time, the three-phase current of the grounding transformer needs to be
connected to one of the two devices. Therefore, the current input of another group of overcurrent
protection can be either the second group of three-phase CTs or the sum current of the two
groups of CTs. Another group of phase overcurrent protection can only be enabled if the
NR6641-8I4U module is configured.
The device can provide six stages of another group of phase overcurrent protection with
independent logic. Each stage can be independently set as definite-time characteristics or
inverse-time characteristics. The drop-out characteristics can be set as instantaneous drop-out,
definite-time drop-out or inverse-time drop-out. Another group of phase overcurrent protection
picks up when the current exceeds the current threshold value, and operates after a certain time
delay, once the fault disappears, another group of phase overcurrent protection will drop-out.
Another group of phase overcurrent protection can be enabled or disabled via the settings or
binary input signals, for some specific applications, overcurrent protection needs to be blocked by
the external signal, so the device provides a function block input signal to be used to block
another group of phase overcurrent protection. The enabling and blocking logic of another group
of phase overcurrent protection is shown in the figure below:

Date: 2021-08-01
EN S2.50/51Px.En &
S2.50/51Px.On
SIG S2.50/51Px.Enable
&
SIG S2.50/51Px.Block 1 S2.50/51Px.Blocked
SIG Fail_Device
&
S2.50/51Px.Valid
3 Figure 3.32-1 The enabling and blocking logic of another group of phase overcurrent protection
The logic diagram of the fault detector element of another group of phase overcurrent protection is
as follows:
SET Ia>0.95×[S2.50/51Px.I_Set]
>=1
SET Ib>0.95×[S2.50/51Px.I_Set] &
0 500ms &
SET Ic>0.95×[S2.50/51Px.I_Set]
S2.50/51Px.Pkp
SIG S2.50/51Px.On
SIG S2.50/51Px.Valid
&
FD.Pkp
SET [S2.50/51Px.Opt_Trp/Alm]=Alm
Figure 3.32-2 Logic diagram of the fault detector element of another group of phase overcurrent
protection
Another group of phase overcurrent protection can operate without time delay or operate with a
definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets the
IEC60255-3 and ANSI C37.112 standards. Another group of phase overcurrent protection can
support definite-time limit, IEC & ANSI standard inverse time limit and user-defined inverse-time
limit, users can select the wanted operating curve by the setting [S2.50/51Px.Opt_Curve] (x=1~6),
the relationship between the value of the setting and the curve is shown in the table below.
S2.50/51Px.Opt_Curve Time Characteristic k α c tr


Date: 2021-08-01
S2.50/51Px.Opt_Curve Time Characteristic k α c tr

Only when the setting [S2.50/51Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
3
inverse-time characteristic is selected, the settings [S2.50/51Px.K], [S2.50/51Px.C] and
[S2.50/51Px.Alpha] are useful, the inverse-time operating curve is determined by the three
settings.
When I > Ip , another group of phase overcurrent protection operates immediately.
When I > Ip , the protection operates with a time delay of top (i.e. the value of the setting
[S2.50/51Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
IP I
Figure 3.32-3 Definite-time operation characteristic curve of another group of phase overcurrent
protection

Date: 2021-08-01
When I > Ip , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [S2.50/51Px.tmin] (x=1~6). The
 k 
t= 
+ c   TMS
 ( I / I P ) − 1 
Where:
Ip is the current setting [S2.50/51Px.I_Set];

3 TMS is the inverse-time time multiplier, i.e. the setting [S2.50/51Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [S2.50/51Px.K];

c is the inverse-time coefficient C, i.e. the setting [S2.50/51Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [S2.50/51Px.Alpha];

t min
IP ID I
Figure 3.32-4 Inverse-time operation characteristic curve of another group of phase overcurrent
protection
T0
1
 t ( I )dt
0
=1

Date: 2021-08-01
Where:
t(I) is the theoretical operating time when the current is I.
The supported drop-out characteristics of another group of phase overcurrent protection include

drop-out or definite-time drop-out, if inverse-time drop-out is selected, the alarm signal 3
When I <0.95* Ip , the protection drops out immediately.
When I <0.95* Ip , the protection drops out with a time delay of tdr (i.e. the value of the setting
[S2.50/51Px.t_DropOut]), and the drop-out characteristic curve is shown in the following figure:

Date: 2021-08-01
Start time
I>Ip
Start
signal
Operating
3 signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.32-5 Definite-time drop-out characteristic of another group of phase overcurrent protection
When I > Ip , the inverse-time operating accumulator begins to accumulate, the accumulated
tp
1
I tp =  dt
0
t(I )
At this time, if I <0.95* Ip , the protection element starts drop-out, and the drop-out
TR
1
I tp − t
0 R (I )
dt = 0
Where:


Date: 2021-08-01
When I <0.95* Ip , the inverse-time drop-out characteristic equation is as follows:
 tr 
tR =  2
 TMS
1 − ( I / I P ) 
Where:
Ip is the current setting [S2.50/51Px.I_Set];
TMS is the inverse-time factor, i.e. the setting [S2.50/51Px.TMS];
tr is the drop-out time coefficient, it is the drop-out time required for the current to drop to 0 after 3
When 0.95* Ip < I < Ip , the accumulator will neither accumulate nor drop out
tr
IP I
Figure 3.32-6 Inverse-time drop-out characteristic curve of another group of phase overcurrent protection

Date: 2021-08-01
Start time
I>Ip
Start
signal
Operating
signal
Protection
operate
Operating
counter

Dropout time
Dropout time
Figure 3.32-7 Inverse-time drop-out characteristic of another group of phase overcurrent protection
50/51P
S2.50/51Px.Enable S2.50/51Px.On
S2.50/51Px.Block S2.50/51Px.Blocked
S2.50/51Px.Valid
S2.50/51Px.St
S2.50/51Px.StA
S2.50/51Px.StB
S2.50/51Px.StC
S2.50/51Px.Op
S2.50/51Px.Op.PhA
S2.50/51Px.Op.PhB
S2.50/51Px.Op.PhC
S2.50/51Px.Alm

Date: 2021-08-01
3.32.3 I/O Signal

Stage x of another group of phase overcurrent protection enabling input, it
1 S2.50/51Px.Enable
Stage x of another group of phase overcurrent protection blocking input, it is
2 S2.50/51Px.Block
1 S2.50/51Px.On Stage x of another group of phase overcurrent protection is enabled
2 S2.50/51Px.Blocked Stage x of another group of phase overcurrent protection is blocked
3
4
S2.50/51Px.Valid
S2.50/51Px.St
Stage x of another group of phase overcurrent protection is valid
Stage x of another group of phase overcurrent protection starts
3
5 S2.50/51Px.StA Stage x of another group of phase overcurrent protection starts (Phase A)
6 S2.50/51Px.StB Stage x of another group of phase overcurrent protection starts (Phase B)
7 S2.50/51Px.StC Stage x of another group of phase overcurrent protection starts (Phase C)
8 S2.50/51Px.Op Stage x of another group of phase overcurrent protection operates
Stage x of another group of phase overcurrent protection operates (Phase
9 S2.50/51Px.Op.PhA
A)
10 S2.50/51Px.Op.PhB
B)
11 S2.50/51Px.Op.PhC
C)
12 S2.50/51Px.Alm Stage x of another group of phase overcurrent protection alarms

Date: 2021-08-01
3.32.4 Logic
S2.50/51Px.StA
SET Ia>[S2.50/51Px.I_Set] & Timer

t
&
t S2.50/51Px.Op.PhA
SIG S2.50/51Px.Pkp
SET [S2.50/51Px.Opt_Trp/Alm]=Trp
&
S2.50/51Px.Alm.PhA
SET [S2.50/51Px.Opt_Trp/Alm]=Alm
3 SIG S2.50/51Px.StA
>=1
SIG S2.50/51Px.StB S2.50/51Px.St
SIG S2.50/51Px.StC
SIG S2.50/51Px.Op.PhA
>=1
SIG S2.50/51Px.Op.PhB S2.50/51Px.Op
SIG S2.50/51Px.Op.PhC
SIG S2.50/51Px.Alm.PhA
>=1
SIG S2.50/51Px.Alm.PhB S2.50/51Px.Alm
SIG S2.50/51Px.Alm.PhC
Figure 3.32-8 Logic diagram of another group of phase overcurrent protection
3.32.5 Settings
Access path: MainMenu  Settings  Protection Settings  OC2 Settings

1 S2.50/51P1.I_Set 0.05~200 15 A 0.001 another group of phase
2 S2.50/51P1.t_Op 0 ~100 0.1 s 0.001 stage 1 of another group of
S2.50/51P1.t_Drop
3 0 ~100 0 s 0.001 stage 1 of another group of
Out
Disabled; enabling/disabling the stage 1 of
4 S2.50/51P1.En Enabled - -
Enabled another group of phase

Date: 2021-08-01

group of phase overcurrent
S2.50/51P1.Opt_Tr Trp; protection operate to trip or
5 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
3
ANSILTE;
ANSILTV;
S2.50/51P1.Opt_Cu ANSILT;
6 IECDefTime - - characteristic curve of stage 1 of
rve IECN;
another group of phase
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
characteristic curve of stage 1 of
Inst;
S2.50/51P1.Opt_Cu another group of phase
7 DefTime; Inst - -
rve_DropOut overcurrent protection
IDMT
8 S2.50/51P1.TMS 0.04~ 20 1 - 0.001 stage 1 of another group of
9 S2.50/51P1.tmin 0 ~10 0.02 s 0.001
protection
0.000
10 S2.50/51P1.K 0.001~120 0.14 - operation characteristic of stage
1
1 of another group of phase

Date: 2021-08-01

0.000
11 S2.50/51P1.Alpha 0.01 ~3 0.02 - operation characteristic of stage
1
0.000
12 S2.50/51P1.C 0 ~1.2 0 - operation characteristic of stage
1
S2.50/51P2.t_Drop
Out
16 S2.50/51P2.En Enabled - -
17 Trp - -
p/Alm Alm alarm.

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
overcurrent protection. 3
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
19 DefTime; Inst - -
IDMT
21 S2.50/51P2.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1

Date: 2021-08-01

0.000
1
3 26 S2.50/51P3.t_Op 0 ~100 0.1 s 0.001 stage 3 of another group of

S2.50/51P3.t_Drop
Out
28 S2.50/51P3.En Enabled - -
29 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

Inst;
IDMT
3
33 S2.50/51P3.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1
0.000
1
S2.50/51P4.t_Drop
Out
40 S2.50/51P4.En Enabled - -

Date: 2021-08-01

41 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
3 ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
45 S2.50/51P4.tmin 0 ~10 0.02 s 0.001
protection
0.000
1

Date: 2021-08-01

0.000
1
0.000
1
3
S2.50/51P5.t_Drop
Out
52 S2.50/51P5.En Enabled - -
53 Trp - -
p/Alm Alm alarm.

Date: 2021-08-01

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
3 IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
57 S2.50/51P5.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1

Date: 2021-08-01

0.000
1
62 S2.50/51P6.t_Op 0 ~100 0.1 s 0.001 stage 6 of another group of 3
S2.50/51P6.t_Drop
Out
64 S2.50/51P6.En Enabled - -
65 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01

Inst;
IDMT
3 68 S2.50/51P6.TMS 0.04~ 20 1 - 0.001 stage 6 of another group of

69 S2.50/51P6.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1
0.000
1
3.33 Distance Protection (21L)
The distance protection function is designed to meet the requirement for the application of
transmission line or underground cable. The reach of distance protection is definite, and distance
protection is easy to coordinate with protections of the adjacent equipment.
Distance protection includes three independent phase-to-phase measuring loops and three
independent phase-to-ground measuring loops. Both mho and quadrilateral characteristics are
available for different application. In addition, load encroachment, power swing blocking and
releasing, and faulty phase selection functions are also provided.

Date: 2021-08-01
3.33.1 Functions Description
Up to 6 zones distance protection with settable direction are supplied. Each zone includes three
independent phase-to-phase measuring loops as well as three independent phase-to-ground
measuring loops. Phase-to-ground distance element should be compensated by zero-sequence
current of local line. Each zone can select forward direction, reverse direction and non direction.
Load encroachment can distinguish effectively between heavily loaded line and faulty line, and the
risk of encroachment of the load impedance into the tripping characteristics of the distance
protection can be excluded.
Power swing blocking and releasing can prevent distance protection from undesired operation
during power swing, even if measured impedance reaches into the operation area of distance 3
protection. Moreover, distance protection can operate reliably when a fault occurs during power
swing.
Based on distance protection characteristics, faulty phase can be identified correctly.
3.33.1.1 Faulter Detector
The current amplitude is calculated based on the injected analogue quantities. The fault detector
continuously detects the change of phase-to-phase power frequency current and the calculated
zero-sequence and negative-sequence currents. The fault detector includes:
1. Fault detector based on DPFC current: DPFC current is greater than the setting value
2. Fault detector based on zero-sequence current: Zero-sequence current is greater than the
setting value
3. Fault detector based on negative-sequence current: Negative-sequence current is greater

than the setting value
If any of the above conditions is satisfied, the fault detector will operate to start distance protection
calculation.
⚫ Fault Detector Based on DPFC Current
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from

that of a cycle before.
∆I = I(k) − I(k − 24)
I(k) is the current sampling point.
I(k-24) is the value of the sampling point before a cycle, 24 is the sampling points cycle.

Date: 2021-08-01
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
3 -50
-100
0 20 40 60 80 100 120
DPFC current
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection. It is used to determine
whether this pickup condition is met according to Equation 3.33-1.
For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to
ensure the pickup of protection device. For usual single phase to earth fault, it also has
sufficient sensitivity to pick up except the earth fault with very large fault resistance. Under
this condition, DPFC current may be very small and the sensitivity is reduced, however,
zero-sequence current is used to remedy the reduction of the sensitivity.
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steady under normal or power swing
condition, the adaptive floating threshold with the ΔI Set is higher than the change of current
under these conditions and hence maintains the element stability.
The criterion is:
ΔIΦΦMAX>1.25ΔITh+ΔISet Equation 3.33-1
Where:
ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC,
CA)
ΔISet: The fixed threshold value (i.e. the setting [21L.FD.DPFC.I_Set])
ΔITh: The floating threshold value
The coefficient, 1.25, is an empirical value which ensures that the threshold is always higher
than the unbalance current of the system.
If operation condition is satisfied, the fault detector based on DPFC current will operate. The
pickup signal will maintain 5s after the fault detector based on DPFC current drops off.
⚫ Fault Detector Based on Zero-sequence Current
The operation condition will be satisfied when zero-sequence current (3I0) is greater than the

Date: 2021-08-01
setting [21L.FD.ROC.3I0_Set]. The fault detector based on zero-sequence current is always

in service. (3I0: zero-sequence current is calculated from the vector sum of Ia, Ib and Ic)
If operation condition is satisfied, the fault detector based on zero-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on zero-sequence
current drops off.
⚫ Fault Detector Based on Negative-sequence Current
The operation condition will be satisfied when negative-sequence current (I2) is greater than
the setting [21L.FD.NOC.I2_Set].
If operation condition is satisfied, the fault detector based on negative-sequence current will
operate. The pickup signal will maintain 5s after the fault detector based on
3
negative-sequence current drops off.
3.33.1.2 Quadrilateral Distance Protection
For forward direction or reverse direction close-in fault, the voltage of faulty phase is 0, the
measured impedance of faulty phase is located in the origin of R-X plane, so it cann’t be
distinguished as forward direction or reverse direction fault if not handled.
For solving the problem, the positive-sequence voltage is used as polarized voltage to distinguish
between forward direction fault and reverse direction fault. As shown in Figure 3.33-1 and Figure
3.33-2, line OA and line OE are named direction line which has good direction characteristics with
positive-sequence voltage as the polarized voltage.
Phase comparison equation of forward direction distance element is:
U̇1
−β ≤ Arg ≤ 90° + α
İ
Phase comparison equation of reverse direction distance element is:
U̇1
180° − β ≤ Arg ≤ 270° + α
İ
Where:
⚫ For phase-to-ground distance element, taking phase-A as an example
U̇1 is positive-sequence voltage, U̇1 = U̇A1
İ is phase current compensated by zero-sequence current, İ = İA + K 0 × 3İ0
K0 is zero-sequence compensation coefficient.
⚫ For phase-to-phase distance element, taking phase-AB as an example
U̇1 is positive-sequence voltage, U̇1 = U̇AB1
İ is phase current compensated by zero-sequence current, İ = İAB

Date: 2021-08-01
jX
B Z_Set
θ D
C
Dꞌ
A
α
φ φ
R
R_Offset O β R_Set
3 E
Figure 3.33-1 Quadrilateral forward direction distance element
jX
E
R_Set β O R_Offset
R
φ φ
α
A
Dꞌ C
θ
B
D Z_Set
Figure 3.33-2 Quadrilateral reverse direction distance element
jX
B Z_Set
D
C
φ φ φ
R
R_Offset R
φ O
A
Z_Offset E
Figure 3.33-3 Quadrilateral non direction distance element

Date: 2021-08-01
Where:
Z_Set is the impedance setting.
R_Set is the resistance setting.
Z_Set is the offset impedance setting.
R_Set is the offset resistance setting.
α is the angle of directional line OA in the second quadrant.
β is the angle of directional line OE in the fourth quadrant.
θ is downward offset angle of the reactance line, which is used to prevent distance protection from 3
overreaching.
φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance

element and phase-to-phase distance element.
For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
almost 0, so the dead zone of distance protection for a close-in three-phase fault must be
eliminated. Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage.
When the memory fades out, the operating characteristics will be shifted toward forward direction
or reverse direction, as shown in Figure 3.33-4 and Figure 3.33-5.
The shift impedance setting is fixed as ZShift=Z_Set/8 by default, 4ohm<ZShift<10ohm.
jX
B Z_Set
θ D
C
Dꞌ
A α
φ φ
O R
R_Offset β R_Set
ZShift
E
Figure 3.33-4 Shift impedance characteristics of forward direction

Date: 2021-08-01
jX
B Z_Set
θ D
C
A
Dꞌ
α ZShift
E φ
R_Offset φ R
β R_Set
O
3
Figure 3.33-5 Shift impedance characteristics of reverse direction
For reverse direction distance element, the similar treatment as forward direction distance
element can be adopted, by rotating the operation characteristics of forward direction distance
element 180°, the operating characteristics of reverse direction distance element can be gained.
3.33.1.3 Mho Distance Protection
For forward direction or reverse direction close-in fault, the voltage of faulty phase is almost 0, and
the measured impedance of faulty phase is located in the origin of R-X plane. Positive-sequence
voltage is used as polarized voltage to distinguish between forward direction fault and reverse
direction fault.
Phase comparison equation of forward direction distance element and reverse direction distance
element is:
U̇OP∅
−90° ≤ Arg ≤ 90°
U̇P∅
Where:
U̇P∅ is the polarized positive-sequence voltage, i.e., U̇P∅ = −U̇1∅
U̇OP∅ is the operating voltage.
⚫ For forward direction characteristics: U̇OP∅ = U̇ − İ × Z
1) For phase-to-ground distance element:
U̇ is phase voltage.
İ is phase current compensated by zero-sequence current.
Taking phase-A as an example: U̇OPA = U̇A − (İA + K 0 × 3İ0 ) × Z
2) For phase-to-phase distance element:
U̇ is phase-to-phase voltage.
İ is phase-to-phase current.

Date: 2021-08-01
Taking phase-AB as an example: U̇OPAB = U̇AB − İAB × Z
⚫ For reverse direction characteristics: U̇OP∅ = U̇ + İ × Z
Taking phase-A as an example: U̇OPA = U̇A + (İA + K 0 × 3İ0 ) × Z
U̇ is phase-to-phase voltage. 3
Taking phase-AB as an example: U̇OPAB = U̇AB + İAB × Z
⚫ For non-direction characteristics U̇P∅ = U̇ + İ × ZOFFSET
Taking phase-A as an example: U̇PA = U̇A + (İA + K 0 × 3İ0 ) × ZOFFSET
U̇ is phase-to-phase voltage.
Taking phase-AB as an example: U̇PAB = U̇AB + İAB × ZOFFSET
Non direction distance element adopts offset characteristics and does not use
positive-sequence voltage as polarized voltage, and operation voltage is as same as that of
forward direction distance element.
jX
Z
θ
C
D
R
O
Figure 3.33-6 Mho forward direction distance element

Date: 2021-08-01
jX
φ R
θ
Z
3
Figure 3.33-7 Mho reverse direction distance element
jX
Z_Set
R
φ O
Z_Offset
Figure 3.33-8 Mho non direction distance element
Where:
Z_Offset is the offset impedance setting.
θ is downward offset angle of the reactance line, which is used to prevent distance protection from
overreaching.
φ is line positive-sequence characteristic angle, which is shared by phase-to-ground distance

element and phase-to-phase distance element.
For the fault in forward direction, the operating characteristics of phase-to-ground distance
element is shown in Figure 3.33-9. Operating characteristics on R-X plane is a circle with line
connecting ends of Z_Set and -2ZS/3 as the diameter. The origin is enclosed in the circle.

Date: 2021-08-01
jX
Z_Set
R
O
-2Zs/3
3
Figure 3.33-9 Phase-to-ground operating characteristics for forward fault
Where:
ZS is total impedance between local system and protective device location
φ is positive-sequence sensitive angle.
For the fault in forward direction, the operating characteristics of phase-to-phase distance element
is shown in Figure 3.33-10. Operating characteristics on R-X plane is a circle with line connecting
ends of Z_Set and -ZS/2 as the diameter. The origin is enclosed in the circle.
jX
Z_Set
R
O
-Zs/2
Figure 3.33-10 Phase-to-phase operating characteristics for forward fault
For the fault in reverse direction, the operating characteristics is shown in Figure 3.33-11. This
characteristics is a circle with line connecting ends of Z_Set and Z'S as the diameter.

Date: 2021-08-01
ZꞋs
jX
Z_Set
3 O
Figure 3.33-11 Operating characteristics for reverse fault
Where:
Z'S is total impedance between remote system and protective device location.
For reverse direction distance element, its operating characteristics can be gained by rotating the
operating characteristics of forward direction distance element 180°.
For forward direction or reverse direction close-in three-phase fault, positive-sequence voltage is
also 0, so the dead zone of distance protection for a close-in three-phase fault must be eliminated.
Memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positive-sequence voltage. When the memory fades out, the
operating characteristics will be shifted toward forward direction or reverse direction.
For the fault in forward direction, as shown in Figure 3.33-12, C1 is the operating characteristics
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is enclosed in the impedance circle.
jX
Z_Set
φ
O
R
C2
Zs C1
Figure 3.33-12 Operating characteristics of three-phase close-in fault
For the fault in reverse direction, as shown in Figure 3.33-13, C1 is the operating characteristics

Date: 2021-08-01
before the memory fades out, and C2 is the operating characteristics after the memory fades out.
Whether the memory fades out or not, the origin always is not enclosed in the impedance circle.
ZꞋs
jX
C1
Z_Set
C2 3
φ
O
R
Figure 3.33-13 Operating characteristics of three-phase close-in fault
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close-in fault occurs. It also has favourable directivity and will not operate for a reverse
three-phase fault at busbar.
3.33.1.4 Zero-sequence Current Compensation
For three-phase transmission line, the faulty phase is affected by the current of non-faulty phase
due to the mutual inductance among phase-to-phase conductors.
ZL
ZM
IA
IB ZM
IC
UC UB UA
Figure 3.33-14 Phase-to-phase mutual inductance
Where:
ZL is line impedance
ZM is line mutual impedance
For metallic fault:
U̇A = İA × ZL + İB × ZM + İC × ZM = İA × (ZL − ZM ) + (İA + İB + İC ) × ZM

Date: 2021-08-01
For three-phase symmetric line:
ZL1 = ZL − ZM
ZL0 = ZL + 2ZM
ZL1 is line positive-sequence impedance
ZL0 is line zero-sequence impedance
ZL0 − ZL1
ZM =
3
3 Z −Z ZL0 −ZL1
Hen ce , U̇A = İA × ZL1 + (İA + İB + İC ) × L0 3 L1 = (İA + 3İ0 × 3×Z
L1
) × ZL1
Zero-sequence compensation coefficient K 0
ZL0 − ZL1
K0 =
3 × ZL1
U̇A = (İA + K 0 × 3İ0 ) × ZL1
The device provides zero-sequence compensation coefficient to fulfill zero-sequence current

compensation.
For parallel double-circuit lines, due to mutual inductance of zero-sequence current from the
adjacent line, phase-to-ground characteristics of distance protection will be affected.
ZL1
Z
I
3I0I ZM0
II
3I0II
Figure 3.33-15 Zero-sequence mutual inductance for double-circuit lines
Where:
3I0I is residual current of line I.
3I0II is residual current of line II.
ZM0 is mutual zeros-sequence current between line I and line II.
When phase-A earth fault happens to line I , phase-A voltage is:
U̇A = (İA + K 0 × 3İ0 ) × ZL1 + 3İ0II × ZM0
Due to mutual inductance of zero-sequence current from the adjacent line, the error item

Date: 2021-08-01
3İ0II × ZM0 is imported. According to the actual application, K 0 and the setting range of distance
protection shall be adjusted reasonably to avoid undesired operation.
3.33.1.5 Load Encroachment
When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristics of the distance protection may exist. A load
encroachment characteristics for all zones is used to exclude the risk of unwanted fault detected
by distance protection during heavy load flow. As shown in Figure 3.33-16, if the measured
impedance locate in the load area, distance protection will be blocked.
jX 3
Z
φLoad φLoad
Load Area Load Area
R
O
RLoad RLoad
Figure 3.33-16 Distance element with load encroachment
Two settings are equipped to exclude the encroachment of the load impedance:
RLoad: the minimum load resistance
φLoad: the load area angle
These values are common for all zones.
3.33.1.6 Power Swing Blocking and Releasing
When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the
distance element. The distance measuring element may operate due to the power swing occurs at
many points of interconnected power systems. To keep the stability of whole power system,
tripping due to operation of the distance measuring element during a power swing is generally not
allowed. Distance protection adopts power swing blocking releasing to avoid maloperation
resulting from power swing. In another word, distance protection is blocked all along under the
normal condition and power swing when the respective logic settings are enabled. Only when fault
(internal fault or power swing with internal fault) is detected, power swing blocking for distance
protection is released by PSBR element.
Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone element has respective setting for selection this function.
⚫ Fault detector PSBR element (FD PSBR)

Date: 2021-08-01
⚫ Unsymmetrical fault PSBR element (UF PSBR)
⚫ Symmetrical fault PSBR element (SF PSBR)
1. Fault detector PSBR element
If any of the following condition is matched, FD PSBR will operate for 160ms.
Positive sequence current is lower than the setting [21L.I_PSBR] before general fault
detector element operates.
As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
3 [21L.I_PSBR], it means FD operates between point 1 and point 2 if operation condition for FD
PSBR mentioned above is fulfilled (point 3 as an example), and then FD PSBR will operate
for 160ms.
[21.I_PSBR]
FD
Normal load
impedance
Point 1
Point 2
Point 3
2. Unsymmetrical fault PSBR element
The operation criterion:
I0+I2>m×I1
The “m”, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing
or power swing with external fault.
This decision mainly utilizes the "discrepancy" that there is no negative-sequence or

zero-sequence current during power swing, and there are negative-sequence and
zero-sequence currents in case of asymmetric fault. In addition, value of m is used to
differentiate internal asymmetric fault and external asymmetric fault in case of power swing.
⚫ In case of power swing or both power swing and external fault, asymmetric fault
discriminating element will not operate and distance protection will be blocked:
In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large.
Asymmetric fault discriminating element will not operate.
In case of both power swing and external fault, if center of power swing is in scope of
protection, both phase-to-phase and grounding impedance relays may operate. At this
time, selection of value of m is used to ensure no operation of asymmetric fault
discriminating element, blocking of distance protection, and no incorrect operation

Date: 2021-08-01
without selectivity. If power swing center is not on this line, distance protection will not
operate incorrectly without selectivity due to power swing.
⚫ In case of internal asymmetric fault, asymmetric fault discriminating element operates

and distance protection will be release to clear internal fault:
In case of both power swing and internal fault, if at the instant of short circuit, system
electric potential angle is not laid out, asymmetric fault discriminating element will
operate at once. If at the instant of short circuit, system electric potential angle is laid out,
asymmetric fault discriminating element will operate when system angle gradually
decreases, or local side tripping may be activated after immediate operation of opposite
side asymmetric fault discriminating element and releasing of distance protection tripping.
In case of normal internal asymmetric phase-to-phase or grounding fault in the system,
3
relatively large zero-sequence or negative-sequence component will exist. At this time,
the above equation is true and distance protection will be released.
3. Symmetrical fault PSBR element
If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD
PSBR nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is
provided for this case specially. This detection is based on measuring the voltage at power
swing center, during power swing, U1cosΦ will constantly change periodically.
UOS=U1×COSΦ
Where:
Φ: the angle between positive sequence voltage and current
U1: the positive sequence voltage
As shown in the figure below, assume system connection impedance angle of 90°, current
vector will be perpendicular to the line connecting E M and EN, and have the same phase as
power swing center voltage. During normal operation of system or power swing, U1cosΦ just
reflects positive-sequence voltage of power swing center. In case of 3-phase short circuit,
U1cosΦ is voltage drop on arc resistor, transition resistance is arc resistance, and voltage
drop on arc resistor is less than 5%UN. In actual system, line impedance angle is not 90°.
Through compensation of angle Φ, power swing center voltage can be measured accurately.
After compensation, power swing center voltage is U1cos(Φ＋90o－ΦL), where ΦL is line
impedance angle.
I
EM U EN
UOS
During power swing, power swing center voltage U1cosΦ has the following characteristics:

Date: 2021-08-01
When electric potential phase angle difference between power supplies at two sides is 180 o,
U1cosΦ＝0 and change rate dU1cosΦ/dt is the maximum. When this phase angle difference
is near 0o, power swing center voltage change rate dU1cosΦ/dt is the minimum. During short
circuit, U1cosΦ remains unchanged and dU 1cosΦ/dt＝0. However, in early stage of short
circuit when normal state enters short circuit state, dU 1cosΦ/dt is very large. Therefore, use
of dU1cosΦ/dt solely to differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing
center voltage U1cosΦ is less than a setting and after a short delay can be used as symmetric
fault discriminating element. This element can accurately differentiate power swing and
3-phase short circuit fault, and constitute a complete power swing blocking scheme with other
3 elements. The element to open distance protection if U 1cosΦ is less than a certain setting
and after a delay is easy to realize and has short delay, and can trip fault more quickly and
accurately trip 3-phase short circuit fault during power swing.
The criterion of SF PSBR element comprises the following two parts:
⚫ when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.
⚫ when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.
The second criterion is a backup of the first criterion allowing longer monitoring period of
voltage variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of
voltage at power swing center is also used which can release SF PSBR element quickly for
the fault occurred during power swing. The typical release time is less than 60ms.
3.33.1.7 Faulty Phase Selection
The realization of phase-segregated tripping and fault location depends on the faulty phase
selection. Each zone of distance protection contains three phase-to-ground measuring elements
and three phase-to-phase measuring elements, so non-faulty phase maybe operates when there
is a fault. For example, for near-end phase A fault, phase A distance element operates, while
phase AB and phase CA distance element are also possible to operate. Therefore, the faulty
phase selection of distance protection cannot only depend on the operating phase of distance
protection.
For single-phase fault, three phase-to-ground distance elements, three phase-to-phase distance
elements and the angle relation between I0 and I2A can effectively distinguish faulty phase. As
shown in Figure 3.33-17,
I
⚫ −60° < 𝐴𝑟𝑔 I 0 < 60° region A is selected
2A
I
⚫ 60° < 𝐴𝑟𝑔 I 0 < 180° , region B is selected
2A
I
⚫ 180° < 𝐴𝑟𝑔 I 0 < 300° , region C is selected
2A

Date: 2021-08-01
Region A
60° -60°
Region B Region C
180°
Figure 3.33-17 Faulty phase selection based on I0 and I2A

3
Zero-sequence current is used to distinguish between earth fault and phase-to-phase fault. For
earth fault, associating the angle relation between I0 and I2A, the operating phase of distance
protection can determine faulty phase. For phase-to-phase fault, the faulty phase is detected by
comparing the relative relationship of distance protection operating.
3.33.1.8 Time Delay Characteristics
For each distance protection zone, the three phase-to-ground distance elements share the same
time relay, and the three phase-to-phase distance elements share the same time relay.
When there is a transferring fault, operating time of distance protection with time delay is subject
to the beginning of the first fault. For example:
T=0ms: there is phase A earth fault in the range of zone 2.
T=100ms: phase A earth fault is transferred into phase B earth fault.
T=150ms: the circuit breaker of phase A is open.
If the time delay of zone 2 of phase-to-ground distance element is set as 400ms, zone 2 of
phase-to-ground distance element will operate at T=400ms not T=500ms. However, time delay of
each distance protection zone is independent.
21L.FD
21L.FD.in_U3p 21L.FD.Pkp
21L.FD.in_I3p 21L.FD.DPFC.Pkp
21L.FD.ROC.Pkp
21L.FD.NOC.Pkp
21L.FD.Alm_Pkp

Date: 2021-08-01
ZONEPREPCOMM
21L.Enable 21L.On
21L.Block 21L.Blocked
21L.FwdDir_ZeroSeq 21L.Valid
21L.RevDir_ZeroSeq
21L.FwdDir_NegSeq
21L.RevDir_NegSeq
3
21Lx
21Lx.Enable 21Lx.On
21Lx.Block 21Lx.Op
21Lx.ZG.Enable 21Lx.Op.PhA
21Lx.ZG.Block 21Lx.Op.PhB
21Lx.ZP.Enable 21Lx.Op.PhC
21Lx.ZP.Block 21Lx.ZG.LoadEnch.St
21Lx.Enable_PSBR 21Lx.ZG.LoadEnch.StA
21Lx.Block_PSBR 21Lx.ZG.LoadEnch.StB
21Lx.ZG.LoadEnch.StC
21Lx.ZP.LoadEnch.St
21Lx.ZP.LoadEnch.StAB
21Lx.ZP.LoadEnch.StBC
21Lx.ZP.LoadEnch.StCA
3.33.3 I/O Signals

Three-phase current data input for fault detector element of distance
1 21L.FD.in_I3p
protection
Three-phase voltage data input for fault detector element of distance
2 21L.FD.in_U3p
protection
3 21L.Enable Input signal of enabling side x of distance protection
4 21L.Block Input signal of blocking side x of distance protection
5 21L.FwdDir_ZeroSeq Input signal of forward direction element of 50/51G
6 21L.RevDir_ZeroSeq Input signal of reverse direction element of 50/51G
7 21L.FwdDir_NegSeq Input signal of forward direction element of 50/51Q
8 21L.RevDir_NegSeq Input signal of reverse direction element of 50/51Q

Date: 2021-08-01
9 21Lx.Enable Input signal of enabling zone x of distance protection (x=1~4)

10 21Lx.Block Input signal of blocking zone x of distance protection (x=1~4)
Input signal of enabling zone x of phase-to-ground distance element
11 21Lx.ZG.Enable
(x=1~4)
Input signal of blocking zone x of phase-to-ground distance element
12 21Lx.ZG.Block
(x=1~4)
13 21Lx.ZP.Enable Input signal of enabling zone x of phase-to-phase distance element (x=1~4)
14 21Lx.ZP.Block Input signal of blocking zone x of phase-to-phase distance element (x=1~4)
Input signal of enabling power swing blocking releasing for zone x of
15 21Lx.Enable_PSBR
distance protection (x=1~4)
16 21Lx.Block_PSBR
Input signal of blocking power swing blocking releasing for zone x of 3
1 21L.FD.Pkp The device picks up
2 21L.FD.DPFC.Pkp DPFC current fault detector element operates.
3 21L.FD.ROC.Pkp Zero-sequence current fault detector element operates.
4 21L.FD.NOC.Pkp Negative-sequence fault detector element operates.
5 21L.FD.Alm_Pkp Fault detector element operates for more than 50s.
6 21L.On Side x of distance protection is enabled.
7 21L.Blocked Side x of distance protection is blocked.
8 21L.Valid Side x of distance protection is valid.
9 21Lx.On Zone x of distance protection is enabled. (x=1~4)
10 21Lx.Op Zone x of distance protection operates (x=1~4)
11 21Lx.Op_PhA Zone x of distance protection operates (Phase A, x=1~4)
12 21Lx.Op_PhB Zone x of distance protection operates (Phase B, x=1~4)
13 21Lx.Op_PhC Zone x of distance protection operates (Phase C, x=1~4)
14 21Lx.ZG.LoadEnch.St Zone x of distance protection starts. (x=1~4)
15 21Lx.ZG.LoadEnch.StA Zone x of distance protection starts. (Phase A, x=1~4)
16 21Lx.ZG.LoadEnch.StB Zone x of distance protection starts. (Phase B, x=1~4)
17 21Lx.ZG.LoadEnch.StC Zone x of distance protection starts. (Phase C, x=1~4)
18 21Lx.ZP.LoadEnch.St Zone x of distance protection starts. (x=1~4)
19 21Lx.ZP.LoadEnch.StAB Zone x of distance protection starts. (Phase AB, x=1~4)
20 21Lx.ZP.LoadEnch.StBC Zone x of distance protection starts. (Phase BC, x=1~4)
21 21Lx.ZP.LoadEnch.StAC Zone x of distance protection starts. (Phase AC, x=1~4)

Date: 2021-08-01
3.33.4 Logic
SIG Ia Calculate DPFC phase-to- ΔIab>[21L.FD.DPFC.I_Set]

phase current: >=1
ΔIab=Δ(Ia-Ib)
SIG Ib ΔIbc>[21L.FD.DPFC.I_Set] 21L.FD.DPFC.Pkp
ΔIbc=Δ(Ib-Ic)
ΔIca=Δ(Ic-Ia)
SIG Ic ΔIca>[21L.FD.DPFC.I_Set] >=1
0s 5s 21L.FD.Pkp
FD.Pkp
Calculate residual current:

3I0>[21L.FD.ROC.3I0_Set] 21L.FD.ROC.Pkp
3I0=Ia+Ib+Ic
3 Calculate negative-
sequence current: I2
I2>[21L.FD.NOC.I2_Set] 21L.FD.NOC.Pkp
SIG 21L.FD.Pkp 50s 10s 21L.FD.Alm_Pkp
Figure 3.33-18 Logic of fault detector
SIG 21L.Enable 21L.On

&
SIG 21L.Block >=1 21L.Blocked
SIG Fail_Device
&
SIG 21L.Valid 21L.Valid
&
SIG 21Lx.Enable
SIG 21Lx.Block
EN [21Lx.ZG.En]
& &
& 21Lx.ZG.Enabled
SIG 21Lx.ZG.Enable
SIG 21Lx.ZG.Block >=1

& 21Lx.On
EN [21Lx.ZP.En]
&
SIG 21Lx.ZP.Enable
SIG 21Lx.ZP.Block
SIG VTS.Alm
&
>=1 21Lx.ZP.Enabled
SIG BI_En_VT &
EN [En_VT]
Figure 3.33-19 Logic of enabling distance protection (x=1~4)

Date: 2021-08-01
SIG 21Lx.ZG.Enabled
&
SIG 21L.FD.Pkp 21Lx.Flag.ZG
EN [21Lx.ZG.En_3I0] >=1
SET 3I0>[FD.ROC.3I0_Set]
EN [21Lx.ZG.En_NeuDir_Blk]
SET [21Lx.DirMode]=Forward
&
& & 21Lx.Flg_PSBR_ZG
>=1
SIG 50/51G.DIR.Rev
SET [21Lx.DirMode]=Reverse
3
&
SIG 50/51G.DIR.Fwd
EN [21Lx.ZG.En_NegDir_Blk]
&
SET [21Lx.DirMode]=Forward & &
>=1
SIG 50/51Q.DIR.Rev
SET [21Lx.DirMode]=Reverse &
SIG 50/51Q.DIR.Fwd
SIG 21Lx.ZG.StA
&
SET Ia>0.04In
SIG 21L.LoadEnchPG.StA
SIG 21Lx.ZG.StB
& >=1
SET Ib>0.04In
SIG 21L.LoadEnchPG.StB
SIG 21Lx.ZG.StC
&
SET Ic>0.04In
SIG 21L.LoadEnchPG.StC
Figure 3.33-20 Logic of distance protection (phase-to-ground, x=1~4)
"21Lx.ZG.StA" means that zone x of phase-to-ground distance element starts (phase A).
"21Lx.ZG.StB" means that zone x of phase-to-ground distance element starts (phase B).
"21Lx.ZG.StC" means that zone x of phase-to-ground distance element starts (phase C).
"21Lx.Flag.ZG" means that measured impedance of zone x of phase-to-ground distance element

is inside the operation area.

Date: 2021-08-01
SIG 21Lx.ZP.Enabled
&
SIG 21L.FD.Pkp 21Lx.Flag.ZP
EN [21Lx.ZP.En_NegDir_Blk]
SET [21Lx.DirMode]=Forward & &

>=1 &
SIG 50/51Q.DIR.Rev 21Lx.Flg_PSBR_ZP
SET [21Lx.DirMode]=Reverse &
SIG 50/51Q.DIR.Fwd
3 SIG 21Lx.ZP.StAB
&
SET Iab>0.04In
SIG 21L.LoadEnchPP.StAB
SIG 21Lx.ZP.StBC
& >=1
SET Ibc>0.04In
SIG 21L.LoadEnchPP.StBC
SIG 21Lx.ZP.StCA
&
SET Ica>0.04In
SIG 21L.LoadEnchPP.StCA
Figure 3.33-21 Logic of distance protection (phase-to-phase, x=1~4)
"21Lx.ZP.StAB" means that zone x of phase-to-phase distance element starts (phase AB).
"21Lx.ZP.StBC" means that zone x of phase-to-phase distance element starts (phase BC).
"21Lx.ZP.StCA" means that zone x of phase-to-phase distance element starts (phase CA).
"21Lx.Flag.ZP" means that measured impedance of zone x of phase-to-phase distance element

is inside the operation area.
SIG 21Lx.Rls_PSBR &

[21Lx.ZG.t_Op] 0 21Lx.ZG.Op
SIG 21Lx.Flag.ZG
>=1
21Lx.Op
&
[21Lx.ZP.t_Op] 0 21Lx.ZP.Op
SIG 21Lx.Flag.ZP
Figure 3.33-22 Logic of distance protection operating (zone x, x=1~4)

Date: 2021-08-01
SIG 21Lx.Flg_PSBR_ZG >=1

21Lx.Flg_PSBR
SIG 21Lx.Flg_PSBR_ZP
SIG 21Lx.En_PSBR &

21Lx.Enable_PSBR
SIG 21Lx.Blk_PSBR
SIG 21L.FD.Pkp &
SIG 21Lx.Flg_PSBR
SIG 21Lx.Enable_PSBR &
EN [21Lx.En_PSBR]
>=1
3
SIG -0.03Un<U1cosΦ<0.08Un 150ms 0 &
>=1 21Lx.Rls_PSBR
SIG -0.1Un<U1cosΦ<0.25Un 500ms 0
>=1
&
SIG |I0|+|I2|>m×I1
SIG 21Lx.Flg_PSBR
SET I1>[21L.I_PSBR] 0 3s & &

0 160ms >=1
SIG 21L.FD.Pkp
Figure 3.33-23 Logic of PSBR (x=1~4)
"21Lx.Rls_PSBR" is the releasing signal of power swing blocking element for zone x of distance
protection.
"21Lx.Flg_PSBR_ZG" is the operating condition of power swing blocking element for zone x of
phase-to-ground distance element.
"21Lx.Flg_PSBR_ZP" is the operating condition of power swing blocking element for zone x of
phase-to-phase distance element.
3.33.5 Settings
Access path: MainMenu  Settings  Protection Settings  DistProt Settings

Current setting of DPFC current
1 21L.FD.DPFC.I_Set (0.050~40.000)×In A 0.100
fault detector element
Current setting of residual current
2 21L.FD.ROC.3I0_Set (0.050~40.000)×In A 0.100
Current setting of
3 21L.FD.NOC.I2_Set (0.050~40.000)×In A 0.100 negative-sequence current fault
detector element

Date: 2021-08-01

The angle of directional line in the
4 21L.Ang_Alpha 5~30 ° 15 second quadrant for quadrilateral
phase-to-ground distance element
5 21L.Ang_Beta 5~30 ° 15 fourth quadrant for quadrilateral
Angle setting of load trapezoid
characteristics, it should be set
6 21L.LoadEnch.phi 5~50 ° 12 according to the maximum load
3 area angle (φLoad_Max), φLoad_Max+5°

is recommended.
Resistance setting of load trapezoid
7 21L.LoadEnch.R_Set (0.000~4Unn)/In Ω 40.000 according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Current setting for power swing
8 21L.I_PSBR (0.050~30.000)×In A 1.000
blocking releasing
Mho Characteristics option of
9 21L.ZG.Opt_Characteristic - Mho
Quad phase-to-ground distance element
10 21L.ZP.Opt_Characteristic - Mho
Quad phase-to-phase distance element
Forward
Direction option for zone x of
11 21Lx.DirMode Reverse - Forward
Non_Directional
Real component of zero-sequence
12 21Lx.Real_K0 -4.000~4.000 - 0.660 compensation coefficient for zone x
of distance protection (x=1~4)
Imaginary component of
zero-sequence compensation
13 21Lx.Imag_K0 -4.000~4.000 - 0.000
coefficient for zone x of distance
protection (x=1~4)
Phase angle of positive-sequence
14 21Lx.phi1_Reach 30~89 ° 78 impedance for zone x of distance
protection (x=1~4)
Downward offset angle of the
reactance line for zone x of
15 21Lx.ZG.RCA 0~45 ° 12
(x=1~4)
Impedance setting of zone x of
16 21Lx.ZG.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(x=1~4)
17 21Lx.ZG.Z_Offset (0.000~4Unn)/In Ω 10.000 Shift impedance setting of zone x of

Date: 2021-08-01

(x=1~4)
Resistance setting of zone x of
18 21Lx.ZG.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-ground
distance element (x=1~4)
Shift resistance setting of zone x of
19 21Lx.ZG.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(x=1~4)
Time delay of zone x of
20 21Lx.ZG.t_Op 0.000~10.000 s 0.200 phase-to-ground distance element 3
(x=1~4)
Enabling/disabling zone x of
Disabled
21 21Lx.ZG.En - Enabled phase-to-ground distance element
Enabled
(x=1~4)
Disabled phase-to-ground distance element
22 21Lx.ZG.En_3I0 - Disabled
Enabled controlled by residual current fault
detector element (x=1~4)
Disabled
23 21Lx.ZG.En_NeuDir_Blk - Enabled blocked by direction control
Enabled
element of earth fault protection
(x=1~4)
Disabled
24 21Lx.ZG.En_NegDir_Blk - Enabled blocked by direction control
Enabled
overcurrent protection (x=1~4)
25 21Lx.ZP.RCA 0~45 ° 12
phase-to-phase distance element
(x=1~4)
26 21Lx.ZP.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(x=1~4)
Shift impedance setting of zone x of
27 21Lx.ZP.Z_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(x=1~4)
28 21Lx.ZP.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-phase
29 21Lx.ZP.R_Offset (0.000~4Unn)/In Ω 10.000

Date: 2021-08-01

(x=1~4)
30 21Lx.ZP.t_Op 0.000~10.000 s 0.200 phase-to-phase distance element
(x=1~4)
Disabled
31 21Lx.ZP.En - Enabled phase-to-phase distance element
Enabled
(x=1~4)
Disabled
3 32 21Lx.ZP.En_NegDir_Blk
Enabled
- Enabled blocked by direction control
Enabling/disabling load trapezoid
Disabled
33 21Lx.LoadEnch.En - Enabled characteristics for zone x of
Enabled
Disabled
34 21Lx.En_PSBR - Enabled distance protection controlled by
Enabled
PSBR (x=1~4)
Disabled
35 21Lx.En_ReacLine - Disabled distance protection controlled by
Enabled
the reactance line (x=1~4)
3.34 Distance SOTF Protection (21SOTF)
When the circuit breaker is closed manually or automatically, it is possible to switch on to a

permanent fault. When the circuit breaker is switched onto the fault, the influence on power
system can be effectively decreased if main protection or fast protection can isolate the fault
timely.
This is especially critical if the fault occurs in the remote end of transmission line, since main
protection would not clear the fault until the time delay of backup protection have elapsed. In this
situation, however, the fastest possible clearance is required. Distance SOTF (switch onto fault)
protection is a complementary function to distance protection. With distance SOTF protection, a
fast trip is achieved for a fault on the whole line, when the line is being energized. It shall be
responsive to all types of faults anywhere within the protected line.
Distance SOTF protection shares pickup signal as initiation condition with distance protection. It is
selectable among zone 2, 3 or 4 of distance protection which is accelerated to trip by manual
closing or auto-reclosing, and they can enable or disable be controlled by power swing blocking.
Distance SOTF protection equips with independent time delay.

Date: 2021-08-01
21SOTF
21SOTF.Enable 21SOTF.On
21SOTF.Block 21SOTF.Blocked
21SOTF.Valid
21SOTF.Op
3.34.3 I/O Signals 3

1 21SOTF.Enable Input signal of enabling distance SOTF protection
2 21SOTF.Block Input signal of blocking distance SOTF protection
1 21SOTF.On Distance SOTF protection is enabled.
2 21SOTF.Blocked Distance SOTF protection is blocked.
3 21SOTF.Valid Distance SOTF protection is valid
Distance SOTF protection operates when manual closing or auto-reclosing to
4 21SOTF.Op
fault.
3.34.4 Logic
SIG 21SOTF.Enable &

21SOTF.On
EN [21SOTF.En]
&
SIG 21SOTF.Block >=1 21SOTF.Blocked
SIG Fail_Device
&
21SOTF.Valid
Figure 3.34-1 Logic of enabling distance SOTF protection

Date: 2021-08-01
SIG Breaker open position &
SIG FD.Pkp
&
SIG FD.Pkp &
SIG No current &
SET [SOTF.Opt_Mode_ManCls]=CBPos
SIG FD.Pkp &

& >=1
SIG SOTF.in_mancls 0 [SOTF.t_En] Manual closing signal
3 SET [SOTF.Opt_Mode_ManCls]=ManClsBI
>=1
&
/CBPos
Figure 3.34-2 Logic of manual closing signal
Distance SOTF protection can be initiated by several cases, including manual closing signal and
3-pole reclosing conditions.
The device provides a variety of accelerated tripping modes by manual closing signal, which can
choose circuit breaker position or external binary signal of manual closing.
1. Circuit breaker position (The setting [SOTF.Opt_Mode_ManCls] shall be set as "CBPos")
When the circuit breaker is in open position while the device does not pick up, then manual
closing signal will be kept for a certain time which is determined by the setting [SOTF.t_En], and
distance SOTF protection will be enabled.
2. External binary signal of manual closing (The setting [SOTF.Opt_Mode_ManCls] shall be set
as "ManClsBI")
When external binary input of manual closing is energized, then manual closing signal will be kept
for a certain time which is determined by the setting [SOTF.t_En], and distance SOTF protection
will be enabled.
SIG 79.Close (3P) 0 [SOTF.t_En] 3-pole reclosing signal
Figure 3.34-3 Logic of auto-reclosing signal

Date: 2021-08-01
SIG 21SOTF.Valid &
SIG FD.Pkp
&
& [21SOTF.t_ManCls] 0 21SOTF.Op_ManCls
EN [21SOTF.Zx.En_ManCls] &
SIG 21Lx.Flg_PSBR
Figure 3.34-4 Logic of distance SOTF protection by manual closing signal

3
SIG FD.Pkp &
&
SIG 21SOTF.Valid [21SOTF.t_3PAR] 0 21SOTF.Op_AR
SIG 3-pole reclosing signal
EN [21SOTF.Zx.En_3PAR]
& &
SIG 21Lx.Flg_PSBR >=1
EN [21SOTF.Zx.En_PSBR]
&
SIG 21Lx.Rls_PSBR
Figure 3.34-5 Logic of distance SOTF protection by 3-pole AR
SIG 21SOTF.Op_ManCls >=1

21SOTF.Op
SIG 21SOTF.Op_AR
Figure 3.34-6 Logic of distance SOTF protection
x=2~4
3.34.5 Settings

Time delay of enabling SOTF
protection (shared by distance
SOTF protection, phase
1 SOTF.t_En 0.200~100.000 0.400 s 0.001
and earth fault overcurrent
SOTF protection)
Time delay of distance
2 21SOTF.t_ManCls 0.000~100.000 0.025 s 0.001 protection accelerating to trip
when manual closing

Date: 2021-08-01

Time delay of distance
3 21SOTF.t_3PAR 0.000~100.000 0.025 s 0.001 protection accelerating to trip
when 3-pole reclosing
Disabled Enabling/disabling distance
4 21SOTF.En Enabled - -
Enabling/disabling zone 2 of
Disabled
5 21SOTF.Z2.En_ManCls Enabled - - distance SOTF protection for
Enabled
manual closing
Disabled
3 6 21SOTF.Z3.En_ManCls
Enabled
Disabled - - distance SOTF protection for
manual closing
Disabled
7 21SOTF.Z4.En_ManCls Disabled - - distance SOTF protection for
Enabled
manual closing
Disabled
8 21SOTF.Z2.En_3PAR Enabled - - distance SOTF protection for
Enabled
3-pole reclosing
Disabled
9 21SOTF.Z3.En_3PAR Disabled - - distance SOTF protection for
Enabled
3-pole reclosing
Disabled
10 21SOTF.Z4.En_3PAR Disabled - - distance SOTF protection for
Enabled
3-pole reclosing
Enabling/disabling zone 2
Disabled controlled by PSB of distance
11 21SOTF.Z2.En_PSBR Enabled - -
Enabled SOTF protection for 3-pole
reclosing
reclosing
reclosing
Undervoltage setting of
14 SOTF.U_Ddl 0.000~100.000 30.000 - -
deadline detection
Time delay of deadline
15 SOTF.t_Ddl 0.200~100.000 15.000 - -
detection

Date: 2021-08-01

Option of manual SOTF mode
ManClsBI: initiated by input
ManClsBI signal of manual closing
16 SOTF.Opt_Mode_ManCls CBPos CBPos - - CBPos: initiated by CB position
ManClsBI/CBPos ManClsBI/CBPos: initiated by
either input signal of manual
closing or CB position
3.35 VT Circuit Supervision (VTS)

3.35.1 General Application 3
The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when measurement from VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
⚫ Line VT is used as protection VT and the protected line is out of service.
⚫ Only current protection functions are enabled and VT is not connected to the device.
⚫ The specific current protection has picked up before the satisfaction of conditions of VT circuit
failure alarm.
VT circuit supervision can detect failure of single-phase, two-phase and three-phase on VT. Under
normal condition, the device continuously supervises input voltage from VT. The VT circuit failure
alarm will be issued with configurable time delay if residual voltage exceeds or negative-sequence
voltage exceeds the threshold value or positive-sequence voltage is less than the threshold value.
If a specific current protection (such as breaker failure protection) operates to pick up, the time
delay count-down will be paused until the protection returns to normal state.
Under normal conditions, the device detects residual voltage that is greater than the setting
[VTS.3U0_Set] or negative-sequence voltage that is greater than the setting [VTS.U2_Set] to
distinguish a single-phase or two-phase VT circuit failure, and detects positive-sequence voltage
that is less than the setting [VTS.U1_Set] to distinguish a three-phase VT circuit failure. Upon
detecting abnormality on VT circuit, an alarm will come up after a time delay of [VTS.t_DPU] and
drop-off with a time delay of [VTS.t_DDO] after that VT is restored to normal. Upon abnormality
detection on VT circuit, an instant alarm will be issued after a time delay of 25ms and drop-off
without time delay.
VT (secondary circuit) MCB auxiliary contact can be connected to the binary input circuit of the
device as a binary signal. If the MCB has been opened (i.e. "VTS.MCB_VT" is energized), the
device will consider that the VT circuit is in a bad condition and issue an alarm without a time

Date: 2021-08-01
delay. If the auxiliary contact is not connected to the device, VT circuit supervision will be issued
with time delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm shall be not issued if the logic setting [En_VT]
is set as "Disabled". However, the alarm is still issued if the binary input "VTS.MCB_VT" is
energized, no matter that the logic setting [En_VT] is set as "Disabled" or "Enabled".
3.35.3 Function Block
VTS
3 VTS.Enable VTS.Alm
VTS.Block VTS.InstAlm
VTS.MCB_VT
VTS.in_52b
3.35.4 I/O Signals

VT circuit supervision enabling input, it is triggered from binary input or
1 VTS.Enable
VT circuit supervision blocking input, it is triggered from binary input or
2 VTS.Block
3 VTS.MCB_VT Binary input for VT MCB auxiliary contact
4 VTS.in_52b Phase A opening position input of circuit breaker
1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTS.InstAlm Instantaneous alarm signal to indicate VT circuit failure
3.35.5 Logic
SIG Pickup of specific current prot.
SET 3U0>[VTS.3U0_Set]
>=1
SET U2>[VTS.U2_Set]
SET U1<[VTS.U1_Set] &

>=1 If specific current prot. picks up, the
time delay count-down will be paused.
SET [VTS.Opt_VT]=Bay &
[VTS.t_DPU] [VTS.t_DDO] &
SIG 52b (three phase) >=1
SIG Ip > 0.04In >=1
[En_VT]
&
EN VTS.Alm
BI VTS.MCB_VT
EN [VTS.En]
&
SIG VTS.Enable
SIG VTS.Block
Figure 3.35-1 VT circuit supervision logic diagram

Date: 2021-08-01
SIG Pickup of specific current prot.
SET 3U0>[VTS.3U0_Set]
>=1
SET U2>[VTS.U2_Set]
SET U1<[VTS.U1_Set] &

>=1 If specific current prot. picks up, the
time delay count-down will be paused.
SET [VTS.Opt_VT]=Bay &
25ms 0ms &
SIG 52b (three phase) >=1
SIG Ip > 0.04In >=1
[En_VT]
&
EN VTS.InstAlm
BI VTS.MCB_VT
EN [VTS.En]
&
SIG
SIG
VTS.Enable
VTS.Block
3
Figure 3.35-2 Instantaneous VT circuit supervision logic diagram
Where:
Ip is any measured single-phase current;
In is the rated phase current;
In this device, the specific current protection refers to phase overcurrent protection, earth fault
overcurrent protection and breaker failure protection.
⚫ If the specific protection picks up firstly and then an abnormality on VT circuit is detected. The
VT circuit failure alarm should not be issued before the specific protection returns to normal
state;
⚫ If an abnormality on VT circuit is detected firstly and then the specific protection operates to
pick up. The time delay count-down of VT circuit failure alarm shall be paused until the
protection return to normal state.
⚫ If the specific protection operates and VT circuit failure alarm has been issued, the alarm will
be maintained.
3.35.6 Settings
Access path: MainMenu  Settings  Global Settings  Superv Settings
No. Setting Default Range Step Unit Description

Positive-sequence voltage threshold for
1 VTS.U1_Set 30.00 0~100 0.01 V
VT circuit supervision
Zero-sequence voltage (calculated)
2 VTS.3U0_Set 8.00 0~100 0.01 V
threshold for VT circuit supervision
Negative-sequence voltage setting of VT
3 VTS.U2_Set 8.00 0~100 0.01 V
circuit supervision function.
Delay pickup setting for the alarm of VT
4 VTS.t_DPU 1.500 0.2~30 0.001 s
circuit supervision
5 VTS.t_DDO 10.000 0.2~30 0.001 s Delay drop off setting for the alarm of VT

Date: 2021-08-01

circuit supervision
Disabled or Logic setting for alarm function of VT
6 VTS.En Enabled - -
Enabled circuit supervision
7 VTS.Opt_VT Bus Bus or Bay - - Selection of Bay VT or Bus VT
Positive-sequence voltage threshold for
8 Bus2.VTS.U1_Set 30.00 0~100 0.01 V
VT circuit supervision of Bus2
Zero-sequence voltage (calculated)
9 Bus2.VTS.3U0_Set 8.00 0~100 0.01 V
threshold for VT circuit supervision of Bus2
Negative-sequence voltage setting of VT
10 Bus2.VTS.U2_Set 8.00 0~100 0.01 V
3 circuit supervision function of Bus2.
Delay pickup setting for the alarm of VT
11 Bus2.VTS.t_DPU 1.500 0.2~30 0.001 s
circuit supervision of Bus2
Delay drop off setting for the alarm of VT
12 Bus2.VTS.t_DDO 10.000 0.2~30 0.001 s
Disabled or Logic setting for alarm function of VT
13 Bus2.VTS.En Enabled - -
Enabled circuit supervision of Bus2
14 Bus2.VTS.Opt_VT Bus Bus or Bay - - Selection of Bay VT or Bus2 VT
3.36 CT Circuit Supervision (CTS)

The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.
When CT secondary circuit is abnormal, the current acquired by the device is not accurate, which
will affect protection functions related to the current. Therefore, it is necessary to monitor the CT
abnormal condition. When CT abnormality is detected, the device shall issue an alarm signal and
block the relevant protection functions.

Under normal conditions, CT secondary signal is continuously supervised by detecting the
residual current and voltage. If residual current is larger than [CTS.3I0_Set] whereas residual
voltage is less than [CTS.3U0_Set], and any phase current is less than 0.04In, CT circuit failure is
considered. The concerned protection functions are blocked and an alarm is issued with a time
delay of [CTS.t_DPU] and drop off with a time delay of [CTS.t_DDO] after CT circuit is restored to
normal condition.
CTS
CTS.Enable CTS.On
CTS.Block CTS.Blocked
CTS.Valid
CTS.Alm

Date: 2021-08-01
3.36.3 I/O Signals

CT circuit supervision enabling input, it is triggered from binary input or
1 CTS.Enable
CT circuit supervision blocking input, it is triggered from binary input or
2 CTS.Block
1 CTS.Alm Alarm signal to indicate CT circuit fails
2 CTS.On CT circuit supervision is enabled.
3
4
CTS.Blocked
CTS.Valid
CT circuit supervision is blocked.
CT circuit supervision is valid.
3
3.36.4 Logics
EN [CTS.En] &
CTS.On
SIG CTS.Enable
&
SIG CTS.Block >=1 CTS.Blocked
SIG Fail_Device
&
CTS.Valid
SIG CTS.Valid &

[CTS.t_DPU] [CTS.t_DDO] CTS.Alm
SET 3I0>[CTS.3I0_Set]
&
SET 3U0<[CTS.3U0_Set]
SIG IA<0.04In
>=1
SIG IB<0.04In
SIG IC<0.04In
Figure 3.36-1 Logic of CT circuit failure
3.36.5 Settings
No. Settings Range Default Unit Step Remark

The calculated residual current setting
1 CTS.3I0_Set 0.00~200.00 0.1 A 0.001
of CT circuit supervision function.
The calculated residual voltage setting
2 CTS.3U0_Set 0.00~200.00 30 V 0.001
of CT circuit supervision function.
Delay pick-up time setting for CT
3 CTS.t_DPU 0.000~100.000 1.25 s 0.001
circuit failure
Delay drop-out time setting for CT
4 CTS.t_DPO 0.000~100.000 10 s 0.001
circuit failure

Date: 2021-08-01

Disabled Enabling/disabling CT circuit
5 CTS.En Disabled - -
Enabled supervision function.
3.37 Fault Location (FL)
The main objective of feeder protection is fast, selective and reliable operation for faults on the
protected line. Besides this, fault location information is very important for those involved in
operation and maintenance. Reliable fault location information greatly decreases the outage of
the protected line and increases the total availability of a power system. This fault location function
3 cannot be used for the transmission line with series compensation.
For a permanent fault, it is necessary to find out and eliminate the fault point as soon as possible,
so to reduce the time of power off. Therefore, accurate fault location is very important.
Single-end fault location function is available for the device. Fault location element picks up after
the device operates to trip when there is a fault in the line. Fault location element can be activated
only after the distance protection, phase overcurrent protection or earth fault overcurrent
protection operates to trip. Once any of phase overcurrent protection or earth fault overcurrent
protection operates, fault distance calculation starts after 25ms. The premise of fault location is to
select the faulty phase. After selecting the fault phase, calculate the fault distance according to the
fault type.
3.37.1.1 Fault Location Algorithm
The device adopts single-end fault location elemnent, which only uses the measured value of the
voltage and the current of one end. The error is mainly due to the fault resistance of fault point and
the infeed current from power source of the opposite end.
When a short-circuit fault with fault resistance occurs, additional voltage will be generated in the
fault resistance by infeed current from power source of the opposite end, which will have a great
impact to the fault location measured result. Generally, the larger the fault resistance is, the larger
the impact will be.
UM UN
EM ZM ZF ZL-ZF ZN EN
IM IN
Bus M Bus N
IF RF
Figure 3.37-1 Equivalent circuit of single-phase fault with fault resistance
Where:
U̇M is busbar voltage of side M.

Date: 2021-08-01
İM is line phase current of side M.
İ0 is line zero-sequence current of side M.
İF is the fault current of fault resistance.
K 0 is zero-sequence compensation coefficient
R F is fault resistance.
U̇M = (İM + K 0 × 3İ0 ) × ZF1 + İF × R F

3İ0
İF =
CM0
ZN0 + ZL0 − ZF0
3
CM0 = Equation 3.37-1
ZM0 + ZN0 + ZL0
ZF0 − ZF1
K0 =
3ZF1
CM0 is zero-sequence distribution coefficient of side M.
ZM0 is zero-sequence impedance of side M.
ZN0 is zero-sequence impedance of side N.
ZL0 is line zero-sequence impedance.
ZF1 is the line positive-sequence impedance from side M to fault point.
ZF0 is the line zero-sequence impedance from side M to fault point.
U̇M, İM and İ0 can be measured. Because the parameters of zero-sequence impedance circuit
between the system of both sides are generally similar. CM0 can be approximately thought as a
real number. Therefore, ZF1 can be calculated according to Equation 3.37-1.
3İ0
U̇M = (İM + K 0 × 3İ0 ) × ZF1 + × RF Equation 3.37-2
CM0
The two ends are multiplied by conjugate complex number of İ0.
3|I0 |2
I0′ × U̇M = (İM + K 0 × 3İ0 ) × I0′ × ZF1 + × RF Equation 3.37-3
CM0
Take the imaginary part of Equation 3.37-3,
Im[I0′ × U̇M ] = Im[(İM + K 0 × 3İ0 ) × I0′ × ZF1 ] Equation 3.37-4
The result of fault location can be obtained directly by solving ZF1 .
The distance from the location of the device to the fault point (i.e., Fault Location) is:
Im[ZF1 ]
Fault⁡Location = × Line⁡Length⁡(km)
X1L

Date: 2021-08-01
Fault⁡Location
Fault⁡Location⁡(Percent) = × 100%
Line⁡Length
Where:
ZF1 is the measured impedance from the location of the device to the fault point.
X1L is line positive-sequence impedance.
Line Length is the length of the feeder line (km)
3 FL
Fault_Location
3.37.3 I/O Signals

1 Fault_Location The result of fault location
3.37.4 Settings
Access path: MainMenu  Settings  Protection Settings  Line Settings

Positive-sequence reactance of the whole
1 X1L 0~600 10 Ω 0.001
line (secondary value)
Positive-sequence resistance of the whole
2 R1L 0~600 1 Ω 0.001
Zero-sequence reactance of the whole
3 X0L 0~600 20 Ω 0.001
Zero-sequence resistance of the whole
4 R0L 0~600 3 Ω 0.001
5 LineLength 0~500 30 km 0.01 Length of the whole line

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4 Control Functions
Table of Contents
4.1 Switchgear Control .......................................................................................... 4-1

4.1.1 Functional Description .......................................................................................................... 4-1
4.1.2 Operation Theory.................................................................................................................. 4-2
4.1.4 I/O Signals ............................................................................................................................ 4-5
4.1.5 Logics ................................................................................................................................... 4-7

4
4.1.6 Settings ............................................................................................................................... 4-10
4.2 Manual Closing Synchronism Check ........................................................... 4-12

4.2.1 Operation Theory................................................................................................................ 4-12
4.2.3 I/O Signals .......................................................................................................................... 4-14
4.2.4 Logics ................................................................................................................................. 4-16
4.2.5 Settings ............................................................................................................................... 4-18
4.3 Voltage Selection ........................................................................................... 4-20

4.3.3 I/O Signals .......................................................................................................................... 4-22
4.3.4 Logics ................................................................................................................................. 4-23
List of Figures
Figure 4.1-1 Logic diagram of switchgear closing operation ................................................. 4-8
Figure 4.1-2 Logic diagram of switchgear opening operation ............................................... 4-8
Figure 4.1-3 Logic diagram of DPS synthesis .......................................................................... 4-9
Figure 4.1-4 Logic diagram of DPS alarm ................................................................................. 4-9
Figure 4.1-5 Logic diagram of trip counter triggering ............................................................. 4-9
Figure 4.1-6 Logic diagram of Interlocking ............................................................................ 4-10
Figure 4.1-7 Logic diagram of manual control ....................................................................... 4-10

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Figure 4.2-1 Relationship between reference and synchronous voltages ......................... 4-12
Figure 4.2-2 Synchronism check logic.................................................................................... 4-16
Figure 4.2-3 Synchro-check logic ............................................................................................ 4-16
Figure 4.2-4 Dead charge check logic ..................................................................................... 4-18
Figure 4.3-1 Voltage connection for double busbars arrangement ..................................... 4-21
Figure 4.3-2 Voltage connection for double busbars arrangement ..................................... 4-21
Figure 4.3-3 Voltage selection for double busbar (Three phase voltage of busbars) ....... 4-23
List of Tables
Table 4.1-1 Remote/Local control mode switch logic.............................................................. 4-2

4

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4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be
divided into remote control and local control according to the control source location. A remote
control mainly refers to remote control commands from substation automation system (SAS) or
network control center (NCC). However, a control triggered manually from the device LCD, by a
terminal contact or by a panel handle is a local control. The switchgear control function is closely
related to interlocking, double point status (DPS), remote/local control mode switching and trip
counter.
4.1.1 Functional Description
A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure 4
that the control operation can be safely and reliably implemented. In addition, the device has a
hardware self-checking and blocking function to prevent hardware damage from mal-operation
output.
When the device is in the remote-control mode, the control command may be sent via
communication protocol; when it is in the local control mode, the local operation may be
performed on the device LCD or panel handle.
A complete control process is:
1. Protocol module sends a selection command;
2. Control module responds the success or failure result of selection;
3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;
4. Control module responds the success or failure result of execution;
5. The control operation may be open/close or up/down/stop.
When the device is in the maintenance status, it can still respond to local control commands.
The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.
This device supports the following functional control module:
Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated

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Module Description
XSWI Synthesis of DS/ES position
SXCBR/SCSWI Trip counter of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
CHKPOS Position verification for switchgear control
4.1.2 Operation Theory
The initiation of a control command may be sent to the device by the SCADA or the NCC through
communication protocol. It may also be the operation of the device LCD or the manual triggering
through configured signal. The command is sent by the CPU to the control module for processing,
and a control record is made on the CPU module according to the control result.
4 4.1.2.1 Remote/Local Control Mode Switch
Since the source of a control command may be SAS or NCC, or may be triggered by the device
LCD or terminal contact, it is necessary to provide a remote/local control mode switch function.
The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module
determines the current control authority to be remote or local according to the input value. By
default, if the input is not configured, any control operation is blocked.
Table 4.1-1 Remote/Local control mode switch logic
in_Remote in_Local Remote Control Local Control

NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable
4.1.2.2 Double Point Status
A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".

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DPS Bit0 = 0 Bit0 = 1

Bit1 = 0 DPS_INT DPS_OFF
Bit1 = 1 DPS_ON DPS_BAD
For the convenient use in user-defined logic programming, this functional module derives four
single-bit outputs to indicate each DSP state.
Indication Signal
DPS State
DPS_ON DPS_OFF DPS_INT DPS_BAD
ON 1 0 0 0
OFF 0 1 0 0
INT 0 0 1 0
BAD 0 0 0 1
This unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
4
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated
positions, while the XSWI is used DS or ES position synthesis.
4.1.2.3 Trip Counter
The trip counter function takes the DPS of switchgear position as input count the trip times. For
CB, this device supports phase-segregated and general trip counter. The trip counter function is
triggered by DPS change. The counting result is stored in non-volatile memory for power-off
holding.
Use the clear command from the menu in local LCD or customized binary signal to reset trip
counter.
4.1.2.4 Interlocking
The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.
The interlocking function is very important for the control operation of switchgears. During the
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could
detect the interlocking logic depending on the message within the command; for local control
through device LCD or terminal contact, please use the corresponding logic setting to
enable/disable the interlocking function.
4.1.2.5 Manual Control
The switchgear control function supports manual control function that can be configured with a
terminal contact or binary signal to trigger the control operation.

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The manual control function supports the control input configuration of selection and open/close.
When the control object selection input is configured, the signal "1" indicates that the current
control object has to be selected before a control operation; if the control object selection input is
not configured, the control command can be directly issued without judgment of selection.
4.1.2.6 Switchgear Position Verification
The position verification function is provided during switchgear control process. In a control
function block of circuit breaker, disconnector or earthing switch, if the input “in_CheckPos_En” is
set as 1, the CB/DS/ES position shall be verified when receiving a remote or local control
command.
The verification logic complies with IEC 61850 standard is:
⚫ A control object only permits to be opened when its DPS is CLOSE;
⚫ A control object only permits to be closed when its DPS is OPEN;

4
⚫ The device shall respond control command failed with the cause of failure when its DPS is
INT, BAD or opposite (i.e. OPEN while opening or CLOSE while closing).
4.1.2.7 Direct Control
For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.
The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.

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XCBR: circuit breaker; XSWI: disconnector switch or earthing switch
4.1.4 I/O Signals
The prefix CB** for circuit breaker and DS** for disconnector switch in the
following lists are hidden since their description (if valid) are similar.

1 in_en Enabling function
2 In_blk Disabling function
3 in_Remote Remote control mode

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4 in_Local Local control mode

5 in_Pos_NO Normally opened contact input for DPS opening position
6 in_Pos_NC Normally closed contact input for DPS closing position
7 in_Pos_A_NO Phase A normally opened contact input for DPS opening position
8 in_Pos_A_NC Phase A normally closed contact input for DPS closing position
9 in_Pos_B_NO Phase B normally opened contact input for DPS opening position
10 in_Pos_B_NC Phase B normally closed contact input for DPS closing position
11 in_Pos_C_NO Phase C normally opened contact input for DPS opening position
12 in_Pos_C_NC Phase C normally closed contact input for DPS closing position
13 in_N_Trp Opening command for trip counter
14 in_N_Trp_A Phase A opening command for trip counter
15 in_N_Trp_B Phase B opening command for trip counter
16 in_N_Trp_C Phase C opening command for trip counter
17 in_Clr_Cnt Clear trip counters
4 18 in_Rsyn Structure pointer of synchronism check element
19 in_EnaOpn Opening permission for interlocking
20 in_EnaCls Closing permission for interlocking
21 in_CILO_Bypass Bypass for interlocking
22 in_Manual_Sel Selection for manual control
23 in_Manual_Opn Opening for manual control
24 in_Manual_Cls Closing for manual control
25 in_CheckPos_En Input signal of enabling of position verification function for switchgear control
1 NO_DPS DPS opening position
2 NC_DPS DPS closing position
3 NO_DPS_A Phase A DPS opening position
4 NC_DPS_A Phase A DPS closing position
5 NO_DPS_B Phase B DPS opening position
6 NC_DPS_B Phase B DPS closing position
7 NO_DPS_C Phase C DPS opening position
8 NC_DPS_C Phase C DPS closing position
9 DPS Synthetic DPS for switchgear position
10 DPS_A Synthetic DPS for switchgear phase A position
11 DPS_B Synthetic DPS for switchgear phase B position
12 DPS_C Synthetic DPS for switchgear phase C position
13 N_Trp Trip counter
14 N_Trp_A Phase A trip counter
15 N_Trp_B Phase B trip counter
16 N_Trp_C Phase C trip counter
17 Opn_Enabled Permission of opening operation
18 Cls_Enabled Permission of closing operation
19 Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
20 Opn_Exec Opening operation

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21 Cls_Exec Closing operation

22 Opn_Sel Opening selection
23 Cls_Sel Closing selection
24 DPS.Alm Alarm signal when DPS status is BAD or INT
25 Cmd_ManSel Selection command for manual control
26 Cmd_ManOpn Opening command for manual control
27 Cmd_ManCls Closing command for manual control
28 RSYN_ChkInprog Synchronism check is in progress
29 DPS_ON Single-bit DPS state indication of ON
30 DPS_OFF Single-bit DPS state indication of OFF
31 DPS_INT Single-bit DPS state indication of INT
32 DPS_BAD Single-bit DPS state indication of BAD
33 DPS_A_ON Phase A single-bit DPS state indication of ON
34 DPS_A_OFF Phase A single-bit DPS state indication of OFF
35 DPS_A_INT Phase A single-bit DPS state indication of INT 4
36 DPS_A_BAD Phase A single-bit DPS state indication of BAD
37 DPS_B_ON Phase B single-bit DPS state indication of ON
38 DPS_B_OFF Phase B single-bit DPS state indication of OFF
39 DPS_B_INT Phase B single-bit DPS state indication of INT
40 DPS_B_BAD Phase B single-bit DPS state indication of BAD
41 DPS_C_ON Phase C single-bit DPS state indication of ON
42 DPS_C_OFF Phase C single-bit DPS state indication of OFF
43 DPS_C_INT Phase C single-bit DPS state indication of INT
44 DPS_C_BAD Phase C single-bit DPS state indication of BAD
In above table, the prefix can be “CB” or “DS01”~“DS04”.
4.1.5 Logics
The prefix CB** for circuit breaker and DS** for disconnector switch in the
following diagrams are hidden since their logics (if valid) are similar.

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EN [CB.En_CILO_Cls] >=1
SIG CB.Cls_Enabled
SIG CB Control Mode = Remote

&
SIG CB.Cls_Exec_Man >=1 >=1 &
0 [CB.t_PW_Cls] CB.Cls_Exec
CB closing cmd. from device local HMI
&
CB closing cmd. from SCADA/Gateway
SIG CB.25.RSYN_OK
>=1
SIG CB.25.SynChk_Enabled &
SIG CB.25.DdChk_Enabled
4
EN [DS**.En_CILO_Cls] >=1
SIG DS**.Cls_Enabled
SIG DS** Control Mode = Remote & &

>=1 0 [DS**.t_PW_Cls] DS**.Cls_Exec
SIG DS**.Cls_Exec_Man >=1
DS** closing cmd. from device local HMI &
DS** closing cmd. from SCADA/Gateway
Figure 4.1-1 Logic diagram of switchgear closing operation
EN [XXXX.En_CILO_Opn] >=1
SIG XXXX.Opn_Enabled
SIG XXXX Control Mode = Remote & &

>=1 0 [XXXX.t_PW_Opn] XXXX.Opn_Exec
SIG XXXX.Opn_Exec_Man >=1
XXXX opening cmd. from device local HMI &
XXXX opening cmd. from SCADA/Gateway
Figure 4.1-2 Logic diagram of switchgear opening operation

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SIG XXXX.DPS_A = OFF

&
SIG XXXX.DPS_B = OFF XXXX.DPS = OFF
SIG XXXX.DPS_C = OFF
SIG XXXX.DPS_A = ON
&
SIG XXXX.DPS_B = ON XXXX.DPS = ON
SIG XXXX.DPS_C = ON
SIG XXXX.DPS_A = INT

&
SIG XXXX.DPS_B = INT XXXX.DPS = INT
SIG XXXX.DPS_C = INT
SIG XXXX.DPS_A = BAD

&
SIG XXXX.DPS_B = BAD XXXX.DPS = BAD 4
SIG XXXX.DPS_C = BAD
Figure 4.1-3 Logic diagram of DPS synthesis
SIG XXXX.DPS=BAD >=1

&
SIG XXXX.DPS= INT [XXXX.DPS.t_Alm] [XXXX.DPS.t_Alm] XXXX.Alm_DPS
EN [XXXX.DPS.En_Alm]
Figure 4.1-4 Logic diagram of DPS alarm
SIG Rasing edge of in_N_Trp_A & N_Trp_A + 1
SIG DPS_A change form ON to OFF
SIG Rasing edge of in_N_Trp_B & &

N_Trp_B + 1
>=1 N_Trp + 1
SIG DPS_B change form ON to OFF
SIG Rasing edge of in_N_Trp_C & N_Trp_C + 1
SIG DPS_B change form ON to OFF
SIG Rasing edge of in_N_Trp &
SIG DPS change form ON to OFF
Figure 4.1-5 Logic diagram of trip counter triggering

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From SCADA/Gateway with

"Interlocking"
Remote control
>=1
The interlocking logic of
Local control
XXXX is activated
From device HMI with "InterlockChk"
>=1
From energized contact via binary input &
SIG Manual control
EN [XXXX.En_CILO_Opn] >=1
EN [XXXX.En_CILO_Cls]
Figure 4.1-6 Logic diagram of Interlocking
SIG in_Manual_Sel = NUL &

4 >=1
SIG in_Manual_Opn
SIG in_Manual_Sel &
SIG in_Manual_Opn
&
SIG Opn_Enabled Opn_Exec_Man
SIG Control mode = Local
SIG in_Manual_Sel = NUL &
SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &
SIG in_Manual_Cls
&
SIG Cls_Enabled Cls_Exec_Man
SIG Control mode = Local
Figure 4.1-7 Logic diagram of manual control
4.1.6 Settings
4.1.6.1 Double Point Status Settings
Access path: Main Menu  Settings  Meas Control Settings  DPS Settings

Delay Pick Up (DPU) time, i.e.
1 CB.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of the circuit
breaker
2 CB.DPS.En_Alm Disabled Disabled or - - Logic setting for DPS alarm of the

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Enabled circuit breaker
Operation time delay of DPS alarm of
3 CB.DPS.t_Alm 500 0~60000 1 ms
the circuit breaker
Delay Pick Up (DPU) time, i.e.
4 DS**.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of
disconnector switch ** (**=01~09)
Logic setting for DPS alarm of the
Disabled or
5 DS**.DPS.En_Alm Disabled - - circuit breaker of disconnector switch
Enabled
** (**=01~09)
6 DS**.DPS.t_Alm 500 0~60000 1 ms the circuit breaker of disconnector
switch ** (**=01~09)
4.1.6.1 Control Settings

4
Access path: Main Menu  Settings  Meas Control Settings  Control Settings

Pulse Width (PW), i.e. holding time,
1 CB.t_PW_Opn 500 0~60000 1 ms for opening output of the circuit
breaker
2 CB.t_PW_Cls 500 0~60000 1 ms for closing output of the circuit
breaker
3 DS**.t_PW_Opn 500 0~60000 1 ms for direct opening output of
4 DS**.t_PW_Cls 500 0~60000 1 ms for direct closing output of
5 DirCtrl**.t_PW_Opn 500 0~60000 1 ms
for direct opening output
6 DirCtrl**.t_PW_Cls 500 0~60000 1 ms
for direct closing output
4.1.6.2 Interlocking Logic Settings
Access path: Main Menu  Settings  Meas Control Settings  Interlock Settings

Logic setting for interlocking logic
Disabled or
1 CB.En_CILO_Opn Disabled - - control of closing output of the circuit
Enabled
breaker
Disabled or
2 CB.En_CILO_Cls Disabled - - control of opening output of the circuit
Enabled
breaker

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Disabled or
3 DS**.En_CILO_Opn Disabled - - control of direct closing output of
Enabled
Disabled or
4 DS**.En_CILO_Cls Disabled - - control of direct opening output of
Enabled
Disabled or Logic setting for interlocking logic
5 DirCtrl**.En_CILO_Opn Disabled - -
Enabled control of direct opening output.
Disabled or Logic setting for interlocking logic
6 DirCtrl**.En_CILO_Cls Disabled - -
Enabled control of direct closing output.
4.2 Manual Closing Synchronism Check
4 The purpose of synchronism check is to ensure two systems are synchronous before they are
going to be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus, closing operation is
applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.
4.2.1 Operation Theory

4.2.1.1 Synchro-check
The comparative relationship between the reference side voltage and the synchronous side
voltage for synchro-check is as follow. Furthermore, the measured three-phase voltages for
synchro-check should not exceed the overvoltage threshold [25.U_OV] or lag the undervoltage
threshold [25.U_UV].
U_Ref
U_Syn
Figure 4.2-1 Relationship between reference and synchronous voltages
This figure shows the characteristics of synchro-check element used for CB closing if both
reference and synchronous sides are live. The element operates if the voltage difference,
frequency difference, slip frequency difference and phase angle difference are all within their
setting ranges.

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⚫ The voltage difference between the reference side and the synchronous side is checked by
the following equation
[25.U_UV] ≤ U_Ref ≤ [25.U_OV]
[25.U_UV] ≤ U_Syn ≤ [25.U_OV]
|U_Ref - U_Syn| ≤ [25.U_Diff_Set]
⚫ The frequency difference between the reference side and the synchronization side is
checked by the following equation
[25.f_UF] ≤ f(U_Ref) ≤ [25.f_OF]
[25.f_UF] ≤ f(U_Syn) ≤ [25.f_OF]
|f(U_Ref) - f(U_Syn)| ≤ [25.f_Diff_Set] 4

⚫ The slip frequency variation is checked by the following equation
df/dt ≤ [25.df/dt_Set]
⚫ The phase difference between the reference side voltage and the synchronous side voltage
is checked by the following equation
∆δ ≤ [25.phi_Diff_Set]
4.2.1.2 Dead Charge Check
The dead charge check mode checks either the reference side or the synchronous side voltage.
Several dead charge check modes are supported in using the setting [25.Opt_Mode_DdChk]. The
device compares the reference side and the synchronous side voltages at both ends of a circuit
breaker with the settings [25.U_LvChk] and [25.U_DdChk]. When the voltage is higher than
[25.U_LvChk], the corresponding side is regarded as live. When the voltage is lower than
[25.U_DdChk], the corresponding side is regarded as dead.
4.2.1.3 Voltage Input Channel
The synchronism check function is suitable for several applications. According to different
application scenarios, user needs to configure different voltage input channel. For both the
reference side and the synchronous side, the voltage input channel may be single phase or
three-phase.
While configuring through the PCS-Studio software, user can configure three phase or single
phase voltage channel for reference and synchronous sides inputs.
In the meantime, the voltage selection logic can be adopted for the synchronism check input
channel, please refer to the following section.

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For synchronism check voltage input channel configuration, please MAKE

SURE that the voltage source to connect to the inputs "in_ref" and
"in_syn" should be the same with that used in measurement function,
such as BayMMXU and UMMXN. Otherwise, the alarm "25.Alm_Cfg_Ch"
will be issued.
4.2.1.4 Enabling Logic
If one of the following conditions is met, the synchro-check for CB closing is enabled.
⚫ [25.Opt_ValidMode] = Setting, [25.En_SynChk] = Enabled;
⚫ [25.Opt_ValidMode] = Config, “25.in_syn_chk” = 1.
4 If one of the following conditions is met, the dead charge check for CB closing is enabled.
⚫ [25.Opt_ValidMode] = Setting, [25.En_DdChk] = Enabled;
⚫ [25.Opt_ValidMode] = Config, “25.in_vol_chk” = 1.
If none of synchro-check and dead charge check is enabled, the synchronism check for CB
closing is disabled.
4.2.3 I/O Signals

1 in_en Enabling function
2 In_blk Disabling function
3 in_ref_A Reference voltage channel (phase A or single phase)
4 in_ref_B Reference voltage channel (phase B)

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5 in_ref_C Reference voltage channel (phase C)

6 in_syn_A Synchronization voltage channel (phase A or single phase)
7 in_syn_B Synchronization voltage channel (phase B)
8 in_syn_C Synchronization voltage channel (phase C)
9 in_25_Blk Signal to block synchronism check logic
10 in_Dd_Blk Signal to block dead charge logic
11 in_Lv_Blk Signal to block live check logic
12 in_SYN_Blk Signal to block synchro-check logic
13 in_25_Bypass Signal to temporarily bypass synchronism check logic
14 in_syn_chk Activate synchro-check (valid only if the setting [25.Opt_ValidMode] = Config)
15 in_vol_chk Activate dead charge check (valid only if the setting [25.Opt_ValidMode] = Config)
1 25.RSYN Pointer to struct of synchronism check element
2 25.U_Ref_Sec Reference side voltage secondary value 4

3 25.U_Ref_Pri Reference side voltage primary value
4 25.f_Ref Reference side frequency
5 25.U_Syn_Sec Synchronous side voltage secondary value
6 25.U_Syn_Pri Synchronous side voltage primary value
7 25.f_Syn Synchronous side frequency
8 25.U_Diff_Sec Voltage difference secondary value
9 25.U_Diff_Pri Voltage difference primary value
10 25.phi_Diff Phase angle difference
11 25.f_Diff Frequency difference
12 25.df/dt Frequency rate-of-change
13 25.SynChk_OK Satisfaction of synchro-check logic
14 25.DdChk_OK Satisfaction of dead charge check logic
15 25.RSYN_OK Satisfaction of synchronism check logic, i.e. SynChk_OK or DdChk_OK
16 25.Alm_Cfg_Ch Channel configuration for reference or synchronization is not correct.
17 25.SynChk_Enabled Synchro-check is enabled
18 25.DdChk_Enabled Dead charge check is enabled
19 25.U_Diff_OK Voltage difference within setting range
20 25.f_Diff_OK Frequency difference within setting range
21 25.df/dt_OK Frequency variation difference within setting range
22 25.phi_Diff_OK Phase difference within setting range
23 25.RefDd The reference side is dead.
24 25.RefLv The reference side is live.
25 25.SynDd The synchronous side is dead.
26 25.SynLv The synchronous side is live.

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4.2.4 Logics
EN [25.Opt_Vali dMode] = Setting &

1
EN [25.En_SynChk] 25.SynChk_Ena bled
EN [25.Opt_Vali dMode] = Config &
SIG 25.in_syn_chk
EN [25.Opt_Vali dMode] = Setting &

1
EN [25.En_DdChk] 25.DdChk_Ena bled
EN [25.Opt_Vali dMode] = Config &
SIG 25.in_vol_chk
4 SIG 25.SynChk_Ena bled &

Synchroni sm che ck for CB closing is disa bled
SIG 25.DdChk_Ena bled
Figure 4.2-2 Synchronism check logic
SIG in_25_Bypass
SIG in_25_Blk
SIG in_SYN_Blk
SET df/dt ≤ [25.df/dt_Set]
≥1
SET [25.En_df/dt_Chk] = Disa bled
SET ΔU ≤ [25.U_Diff_Set]
SET Δf ≤ [25.f_Diff_Set]
≥1
SET [25.En_f_Diff_Chk] = Disa bled
& ≥1 25.SynChk_OK
SET Δδ ≤ [25.phi_Diff_Set]
SET U_Ref ≤ [25.U_UV]
SET U_Ref ≥ [25.U_OV]
≥1
SET U_Syn ≤ [25.U_UV]
SET U_Syn ≥ [25.U_OV]
SET f_Ref ≤ [25.f_UF]

SET f_Ref ≥ [25.f_OF]
≥1
SET f_Syn ≤ [25.f_UF]
SET f_Syn ≥ [25.f_OF]
SIG Cmd without synchro-check

SIG 25.SynChk_OK
SET [25.Opt_Vali dMode] = Setting ≥1 SynChk Success
&
EN [25.En_SynChk]
≥1 &
SET [25.Opt_Vali dMode] = Config
&
SIG in_syn_chk
SIG Cmd with synchro-check
Figure 4.2-3 Synchro-check logic

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4 Control Functions
SIG Ua_Ref < [25.U_DdChk]
SIG Ub_Ref < [25.U_DdChk]

&
SIG Uc_Ref < [25.U_DdChk]
>=1
SIG U_Ref is three-phase voltage 25.RefDd
SIG U_Ref < [25.U_DdChk] &
SIG U_Ref is single-phase voltage
SIG Ua_Syn < [25.U_DdChk]
SIG Ub_Syn < [25.U_DdChk]

&
SIG Uc_Syn < [25.U_DdChk]
>=1
SIG U_Syn is three-phase voltage 25.SynDd 4
SIG U_Syn < [25.U_DdChk] &
SIG U_Syn is single-phase voltage
SIG Ua_Ref > [25.U_LvChk]
SIG Ub_Ref > [25.U_LvChk]

&
SIG Uc_Ref > [25.U_LvChk]
>=1
SIG U_Ref is three-phase voltage 25.RefLv
SIG U_Ref > [25.U_LvChk] &
SIG U_Ref is single-phase voltage
SIG Ua_Syn > [25.U_LvChk]
SIG Ub_Syn > [25.U_LvChk]

&
SIG Uc_Syn > [25.U_LvChk]
>=1
SIG U_Syn is three-phase voltage 25.SynLv
SIG U_Syn > [25.U_LvChk] &
SIG U_Syn is single-phase voltage

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4 Control Functions
SIG in_25_Bypass >=1

25.DdChk_OK
SIG in_25_Blk
SET [25.Opt_Mode_DdChk]
SIG 25.RefDd &

&
SIG in_Dd_Blk
&
crite ria sel ection

Dead check
SIG 25.SynDd
SIG 25.RefLv &
SIG in_Lv_Blk
4 &
SIG 25.SynLv
SIG Cmd. without dead charge check

>=1
SIG 25.DdChk_Ok
& DdChk Success
SIG 25.DdChk_Enabled
SIG Cmd. with dead charge check
Figure 4.2-4 Dead charge check logic
4.2.5 Settings
Access path: Main Menu  Settings  Meas Control Settings  Syn Settings

Selection of decision
1 25.Opt_ValidMode Setting Setting or Config - - mode for synchronism
check
Logic setting for
synchro-check (valid
2 25.En_SynChk Enabled Disabled or Enabled - - only if the setting
[25.Opt_ValidMode] =
Setting)
Logic setting for dead
charge check (valid
3 25.En_DdChk Enabled Disabled or Enabled - - only if the setting
[25.Opt_ValidMode] =
Setting)
4 25.U_UV 80.00 0~100 0.01 % Percentage threshold

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4 Control Functions

of under voltage for
CB closing blocking
Percentage threshold
5 25.U_OV 170.00 100~170 0.01 % of over voltage for CB
closing blocking
6 25.f_UF 45.000 45~65 0.001 Hz of under frequency for
CB closing blocking
7 25.f_OF 65.000 45~65 0.001 Hz of over frequency for
CB closing blocking
Selection of voltage
8 25.Opt_U_SynChk Ua Ua, Ub, Uc, Uab, Ubc, Uca - -
for synchronism check
Threshold of voltage 4
9 25.U_Diff_Set 10.00 0~100 0.01 V difference for
synchronism check
Logic setting for
10 25.En_f_Diff_Chk Enabled Disabled or Enabled - - frequency difference
check
Threshold of
11 25.f_Diff_Set 0.50 0~2 0.01 Hz frequency difference
for synchronism check
Logic setting for
12 25.En_df/dt_Chk Enabled Disabled or Enabled - - frequency variation
difference check
Threshold of
13 25.df/dt_Set 1.00 0~2 0.01 Hz/s frequency variation for
synchronism check.
Threshold of phase
14 25.phi_Diff_Set 15.00 0~180 0.01 ° difference for
synchronism check
Compensation angle
15 25.phi_Comp 0.00 0~360 0.01 ° of phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead
16 25.Opt_Mode_DdChk AnySideDd RefDd - -
charge check mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage
17 25.U_DdChk 17.32 0~100 0.01 V
dead check

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4 Control Functions

Threshold for voltage
18 25.U_LvChk 34.64 0~100 0.01 V
live check
Threshold of duration
19 25.t_Reset 5 0~60 1 s
for synchro-check
Circuit breaker closing
time. It is the time
from receiving closing
20 25.t_Close_CB 20 0~2000 1 ms
command pulse till the
CB is completely
closed.
⚫ 25.Opt_Mode_DdChk
No. Setting Value Dead charge check mode

4 1 SynDdRefDd Dead check for both the reference and the synchronization sides
2 SynLvRefDd Live check for synchronization side and dead check for reference side
3 SynDdRefLv Dead check for synchronization side and live check for reference side
4 RefDd Dead check for reference side
5 SynDd Dead check for synchronization side
6 SynLvRefDd/SynDdRefLv Option 2 or 3
7 AnySideDd Option 1, 2 or 3
4.3 Voltage Selection

The voltage selection function can be used to switch the reference and synchronization voltages
of synchronism check in double busbars application scenarios, or to switch three-phase voltages
of both busbars for the use in protection calculation or measurement.
By default, the device adopts the principle of proximity in built-in voltage selection logic. Moreover,
it supports customized selection logic. The default voltage selection logic is automatically disabled
if the customized voltage selection logic is correctly configured.
The customized selection result may be derived from any source binary signals, such as binary
inputs, isolators status and programmable logic output signals.
If voltage selection logic fails, the alarm "VoltSel.Alm_Invalid_Sel" will be issued and the
selection output remains unchanged.
The voltage selection module is used in the following scenario:
⚫ For some double busbars, three-phases voltages from Bus1 VT and Bus2 VT via switching is
used for protection calculations or measurements and meanwhile used as the reference
voltage of synchronism check. Single-phase voltage from line VT is used as the
synchronization voltage. Selection approach is as follows.

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4 Control Functions
Bus2
Bus1
DS1 DS2
Ua
UB1 Ub
Uc
Ua
UB2 Ub
Uc
CB
DS1.DPS
DS2.DPS
4
UL1
Line
Figure 4.3-1 Voltage connection for double busbars arrangement
⚫ For other busbar arrangements, single-phase voltages from Bus1 VT and Bus2 VT via
switching is used for protection calculations or measurements and meanwhile used as the
reference voltage of synchronism check. Three-phase voltage from line VT is used as the
synchronization voltage. Selection approach is as follows.
Bus2
Bus1
DS1 DS2
UB1
UB2
DS1.DPS
CB
DS2.DPS

UL1
Ua
Ub
Line
Uc
Figure 4.3-2 Voltage connection for double busbars arrangement

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4 Control Functions
4.3.3 I/O Signals

1 in_UB1_A_Chn Voltage input for Bus1 (phase A)
2 in_UB1_B_Chn Voltage input for Bus1 (phase B)
3 in_UB1_C_Chn Voltage input for Bus1 (phase C)
4 in_UB2_A_Chn Voltage input for Bus2 (phase A)
5 in_UB2_B_Chn Voltage input for Bus2 (phase B)
6 in_UB2_C_Chn Voltage input for Bus2 (phase C)
7 in_UL1_A_Chn Voltage input for Line1 (phase A)
8 in_UL1_B_Chn Voltage input for Line1 (phase B)
9 in_UL1_C_Chn Voltage input for Line1 (phase C)
10 in_UL2_A_Chn Voltage input for Line2 (phase A)
11 in_UL2_B_Chn Voltage input for Line2 (phase B)
12 in_UL2_C_Chn Voltage input for Line2 (phase C)
13 in_Bus1_CB DPS position for the Bus 1 side CB in one-and-half arrangement
14 in_Tie_CB DPS position for the tie CB in one-and-half arrangement
15 in_Bus2_CB DPS position for the Bus 2 side CB in one-and-half arrangement
DPS position for the Line 1 in one-and-half or Busbar1 in double busbars
16 in_DS1
arrangement
DPS position for the Line 2 in one-and-half or Busbar2 in double busbars
17 in_DS2
arrangement
18 in_bus1_sel Bus1-selected input for customized programmable voltage selection logic

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4 Control Functions
19 in_bus2_sel Bus2-selected input for customized programmable voltage selection logic

20 in_line1_sel Line1-selected input for customized programmable voltage selection logic
21 in_line2_sel Line2-selected input for customized programmable voltage selection logic
1 VoltSel.Ref_Chn_A Reference voltage channel (Phase A)
2 VoltSel.Ref_Chn_B Reference voltage channel (Phase B)
3 VoltSel.Ref_Chn_C Reference voltage channel (Phase C)
4 VoltSel.Syn_Chn_A Synchronization voltage channel (Phase A)
5 VoltSel.Syn_Chn_B Synchronization voltage channel (Phase B)
6 VoltSel.Syn_Chn_C Synchronization voltage channel (Phase C)
7 VoltSel.Bus1_Sel Bus1 voltage channel for customized programmable voltage selection logic
8 VoltSel.Line1_Sel Line1 voltage channel for customized programmable voltage selection logic
9 VoltSel.Line2_Sel Line2 voltage channel for customized programmable voltage selection logic
10 VoltSel.Bus2_Sel Bus2 voltage channel for customized programmable voltage selection logic
11 VoltSel.Alm_Invalid_Sel Voltage selection is invalid. 4
4.3.4 Logics
SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF
SIG DS1.DPS=OFF &

UB2_Sel
SIG DS2.DPS=ON
&
Alm_Invalid_Sel
UB1 U_Ref
Three-phase voltage of busbars for reference side
UB2
Figure 4.3-3 Voltage selection for double busbar (Three phase voltage of busbars)

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4 Control Functions
SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF
SIG DS1.DPS=OFF &

UB2_Sel
SIG DS2.DPS=ON
&
Alm_Invalid_Sel
UB1 U_Syn
Single-phase voltage of busbars for
synchronization side
UB2
Figure 4.3-4 Voltage selection for double busbars (Single-phase voltage of busbars)
4

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5 Measurement
5 Measurement
Table of Contents
5.1 Primary Values ................................................................................................. 5-1

5.1.1 General Values ..................................................................................................................... 5-1
5.1.2 Angle Values ......................................................................................................................... 5-1
5.1.3 Sequence Components Values ............................................................................................ 5-2
5.1.4 Power Values........................................................................................................................ 5-3
5.1.5 Harmonics ............................................................................................................................ 5-3
5.2 Secondary Values ............................................................................................ 5-4

5.2.1 General Values ..................................................................................................................... 5-4
5.2.2 Angle Values ......................................................................................................................... 5-5 5

5.2.3 Sequence Components Values ............................................................................................ 5-6
5.2.4 Power Values........................................................................................................................ 5-6
5.2.5 Harmonics ............................................................................................................................ 5-7
5.3 Function Values ............................................................................................... 5-7

5.3.1 Synchro-check...................................................................................................................... 5-7
5.3.2 Thermal Overload ................................................................................................................. 5-8
5.3.3 Arc Flash............................................................................................................................... 5-8
5.3.4 Current Summation .............................................................................................................. 5-9
5.4 Energy Metering............................................................................................... 5-9

5.5 Power Quality................................................................................................... 5-9
5.6 Synchrophasor Measurement ...................................................................... 5-10
5.6.2 PMU Values ........................................................................................................................ 5-12
5.6.3 PMU Status ........................................................................................................................ 5-14
5.6.4 PMU Settings...................................................................................................................... 5-15
5.7 DC Analogue Outputs.................................................................................... 5-18


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5 Measurement
5.7.3 I/O Signals .......................................................................................................................... 5-19
5.7.4 Settings ............................................................................................................................... 5-20

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5 Measurement
5.1 Primary Values

Access path: MainMenu  “Measurements”  “Primary Values”
5.1.1 General Values
No. Symbol Definition Unit
1 Ia_Pri Phase-A current A
2 Ib_Pri Phase-B current A
3 Ic_Pri Phase-C current A
4 Ua_Pri Phase-A protection voltage kV
5 Ub_Pri Phase-B protection voltage kV
6 Uc_Pri Phase-C protection voltage kV
7 Uab_Pri Phase-AB protection voltage kV
8 Ubc_Pri Phase-BC protection voltage kV
9 Uca_Pri Phase-CA protection voltage kV
10 f Frequency of protection voltage Hz
11 Neu.I_Pri External measured residual current A

5
12 SEF.I_Pri The sensitive residual current measured from the high-precision CT A
13 Neu2.I_Pri Another group of residual current A
14 60/50.I_Pri Unbalance current A
15 Delt.U_Pri External measured residual voltage kV
16 Syn.U_Pri Voltage for synchronism check kV
17 60/59.U_Pri Unbalance voltage kV
18 S2.Ia_Pri Phase-A current (another group of three-phase current) A
19 S2.Ib_Pri Phase-B current (another group of three-phase current) A
20 S2.Ic_Pri Phase-C current (another group of three-phase current) A
5.1.2 Angle Values
1 Ang (Ua-Ia) Phase angle between phase-A voltage and phase-A current °
2 Ang (Ub-Ib) Phase angle between phase-B voltage and phase-B current °
3 Ang (Uc-Ic) Phase angle between phase-C voltage and phase-C current °
4 Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °
5 Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °
6 Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °
7 Ang (Ia-Ib) Phase angle between phase-A current and phase-B current °
8 Ang (Ib-Ic) Phase angle between phase-B current and phase-C current °

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5 Measurement
9 Ang (Ic-Ia) Phase angle between phase-C current and phase-A current °
Phase angle between phase-A voltage and the referenced angle,

currently, the angle of the positive voltage is used as the referenced angle
10 Ang (Ua) °
(if voltage is not connected, the angle of the positive current is used as
the referenced angle).
11 Ang (Ub) Phase angle between phase-B voltage and the referenced angle °
12 Ang (Uc) Phase angle between phase-C voltage and the referenced angle °
13 Ang (Ia) Phase angle between phase-A current and the referenced angle °
14 Ang (Ib) Phase angle between phase-B current and the referenced angle °
15 Ang (Ic) Phase angle between phase-C current and the referenced angle °
Phase angle between the external measured residual current and the
16 Neu.Ang (I) °
referenced angle
17 SEF.Ang (I) °
referenced angle
Phase angle between another group of external measured residual

5 18 Neu2.Ang (I)
current and the referenced angle
°
19 60/50.Ang (I) Phase angle between the unbalance current and the referenced angle °
Phase angle between the external measured residual voltage and the
20 Delt.Ang (U) °
referenced angle
Phase angle between the synchronism check used voltage and the
21 Syn.Ang (U) °
referenced angle
22 60/59.Ang (U) Phase angle between the unbalance voltage and the referenced angle °
Phase angle between phase-A current and phase-B current (another

23 S2.Ang (Ia-Ib) °
group of three-phase current)
Phase angle between phase-B current and phase-C current (another

24 S2.Ang (Ib-Ic) °
Phase angle between phase-C current and phase-A current (another

25 S2.Ang (Ic-Ia) °
Phase angle between phase-A current and the referenced angle (another
26 S2.Ang (Ia) °
Phase angle between phase-B current and the referenced angle (another
27 S2.Ang (Ib) °
Phase angle between phase-C current and the referenced angle (another
28 S2.Ang (Ic) °
5.1.3 Sequence Components Values
1 I1_Pri The positive-sequence current A

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5 Measurement
2 I2_Pri The negative-sequence current A
3 3I0_Pri Residual current A
4 U1_Pri The positive-sequence voltage kV
5 U2_Pri The negative-sequence voltage kV
6 3U0_Pri The calculated residual voltage kV
7 S2.I1_Pri The positive-sequence current (another group of three-phase current) A
8 S2.I2_Pri The negative-sequence current (another group of three-phase current) A
9 S2.3I0_Pri Residual current (another group of three-phase current) A
5.1.4 Power Values
No. Sign Description Unit
1 Pa_Pri
2 Pb_Pri The primary values of three-phases active powers. MW
3 Pc_Pri
4 Qa_Pri 5
5 Qb_Pri The primary values of three-phases reactive powers. MVAr
6 Qc_Pri
7 Sa_Pri
8 Sb_Pri The primary values of three-phases apparent powers. MVA
9 Sc_Pri
10 P_Pri The primary value of active power. MW
11 Q_Pri The primary value of reactive power. MVAr
12 S_Pri The primary value of apparent power. MVA
13 Cosa
14 Cosb Three-phases power factors. -
15 Cosc
16 Cos Power factor -
5.1.5 Harmonics
1 Ua_Hm01_Pri kV
2 Ua_Hm02_Pri kV
3 Ua_Hm03_Pri kV
The primary value of the 1st~15th voltage harmonic
4 Ua_Hm04_Pri kV
5 Ua_Hm05_Pri kV
6 Ua_Hm06_Pri kV

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5 Measurement
7 Ua_Hm07_Pri kV
8 Ua_Hm08_Pri kV
9 Ua_Hm09_Pri kV
10 Ua_Hm10_Pri kV
11 Ua_Hm11_Pri kV
12 Ua_Hm12_Pri kV
13 Ua_Hm13_Pri kV
14 Ua_Hm14_Pri kV
15 Ua_Hm15_Pri kV
5.2 Secondary Values

Access path: MainMenu  “Measurements”  “Secondary Values”
5.2.1 General Values
5 1 Ia_Sec Phase-A current A
2 Ib_Sec Phase-B current A
3 Ic_Sec Phase-C current A
4 Ua_Sec Phase-A protection voltage V
5 Ub_Sec Phase-B protection voltage V
6 Uc_Sec Phase-C protection voltage V
7 Uab_Sec Phase-AB protection voltage V
8 Ubc_Sec Phase-BC protection voltage V
9 Uca_Sec Phase-CA protection voltage V
10 f Frequency of protection voltage Hz
11 Neu.I_Sec External measured residual current A
12 SEF.I_Sec The sensitive residual current measured from the high-precision CT A
13 Neu2.I_Sec Another group of residual current A
14 60/50.I_Sec Unbalance current A
15 Delt.U_Sec External measured residual voltage V
16 Syn.U_Sec Voltage for synchronism check V
17 60/59.U_Sec Unbalance voltage V
18 S2.Ia_Sec Phase-A current (another group of three-phase current) A
19 S2.Ib_Sec Phase-B current (another group of three-phase current) A
20 S2.Ic_Sec Phase-C current (another group of three-phase current) A

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5 Measurement
5.2.2 Angle Values
1 Ang (Ua-Ia) Phase angle between phase-A voltage and phase-A current °
2 Ang (Ub-Ib) Phase angle between phase-B voltage and phase-B current °
3 Ang (Uc-Ic) Phase angle between phase-C voltage and phase-C current °
4 Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °
5 Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °
6 Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °
7 Ang (Ia-Ib) Phase angle between phase-A current and phase-B current °
8 Ang (Ib-Ic) Phase angle between phase-B current and phase-C current °
9 Ang (Ic-Ia) Phase angle between phase-C current and phase-A current °
Phase angle between phase-A voltage and the referenced angle,

currently, the angle of the positive voltage is used as the referenced angle
10 Ang (Ua) °
(if voltage is not connected, the angle of the positive current is used as
the referenced angle).
11 Ang (Ub) Phase angle between phase-B voltage and the referenced angle ° 5
12 Ang (Uc) Phase angle between phase-C voltage and the referenced angle °
13 Ang (Ia) Phase angle between phase-A current and the referenced angle °
14 Ang (Ib) Phase angle between phase-B current and the referenced angle °
15 Ang (Ic) Phase angle between phase-C current and the referenced angle °
16 Neu.Ang (I) °
referenced angle
17 SEF.Ang (I) °
referenced angle
Phase angle between another group of external measured residual

18 Neu2.Ang (I) °
current and the referenced angle
19 60/50.Ang (I) Phase angle between the unbalance current and the referenced angle °
Phase angle between the external measured residual voltage and the
20 Delt.Ang (U) °
referenced angle
Phase angle between the synchronism check used voltage and the
21 Syn.Ang (U) °
referenced angle
22 60/59.Ang (U) Phase angle between the unbalance voltage and the referenced angle °
Phase angle between phase-A current and phase-B current (another

23 S2.Ang (Ia-Ib) °
Phase angle between phase-B current and phase-C current (another

24 S2.Ang (Ib-Ic) °
Phase angle between phase-C current and phase-A current (another

25 S2.Ang (Ic-Ia) °

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5 Measurement
Phase angle between phase-A current and the referenced angle (another
26 S2.Ang (Ia) °
Phase angle between phase-B current and the referenced angle (another
27 S2.Ang (Ib) °
Phase angle between phase-C current and the referenced angle (another
28 S2.Ang (Ic) °
5.2.3 Sequence Components Values
1 I1_Sec The positive-sequence current A
2 I2_Sec The negative-sequence current A
3 3I0_Sec Residual current A
4 U1_Sec The positive-sequence voltage V
5 U2_Sec The negative-sequence voltage V
6 3U0_Sec The calculated residual voltage V

5 7 S2.I1_Sec The positive-sequence current (another group of three-phase current) A
8 S2.I2_Sec The negative-sequence current (another group of three-phase current) A
9 S2.3I0_Sec Residual current (another group of three-phase current) A
5.2.4 Power Values
1 Pa_Sec
2 Pb_Sec The secondary values of three-phases active powers. W
3 Pc_Sec
4 Qa_Sec
5 Qb_Sec The secondary values of three-phases reactive powers. Var
6 Qc_Sec
7 Sa_Sec
8 Sb_Sec The secondary values of three-phases apparent powers. VA
9 Sc_Sec
10 P_Sec The primary value of active power. W
11 Q_Sec The primary value of reactive power. Var
12 S_Sec The primary value of apparent power. VA
13 Cosa
14 Cosb Three-phases power factors. -
15 Cosc

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5 Measurement
16 Cos Power factor -
5.2.5 Harmonics
1 Ua_Hm01_Sec V
2 Ua_Hm02_Sec V
3 Ua_Hm03_Sec V
4 Ua_Hm04_Sec V
5 Ua_Hm05_Sec V
6 Ua_Hm06_Sec V
7 Ua_Hm07_Sec V
8 Ua_Hm08_Sec The secondary value of the 1st~15th voltage harmonic V
9 Ua_Hm09_Sec V
10 Ua_Hm10_Sec V
11 Ua_Hm11_Sec V 5
12 Ua_Hm12_Sec V
13 Ua_Hm13_Sec V
14 Ua_Hm14_Sec V
15 Ua_Hm15_Sec V
5.3 Function Values

Access path: MainMenu  “Measurements”  “Function Values”
5.3.1 Synchro-check
Access path: MainMenu  “Measurements”  “Function Values”  “Synchronism Check”
1 25.U_Ref_Sec Secondary voltage of reference side V
2 25.U_Ref_Pri Primary voltage of reference side kV
3 25.f_Ref Frequency of reference side Hz
4 25.U_Syn_Sec Secondary voltage of synchronization side V
5 25.U_Syn_Pri Primary voltage of synchronization side kV
6 25.f_Syn Synchronization side frequency Hz
7 25.U_Diff_Sec Secondary voltage difference for CB synchronism check V
8 25.U_Diff_Pri Primary voltage difference for CB synchronism check kV
9 25.phi_Diff Phase angle difference for CB synchronism check deg
10 25.f_Diff Frequency difference for CB synchronism check Hz

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5 Measurement
11 25.df/dt Frequency variation difference for CB synchronism check Hz/s
12 25.RSYN_OK Synchronism check is passed. -
13 25.SynChk_OK Synchro-check is passed. -
14 25.DdChk_OK Dead charge check is passed. -
15 25.U_Diff_OK Voltage difference criteria is satisfied. -
16 25.f_Diff_OK Frequency difference criteria is satisfied. -
17 25.df/dt_OK Frequency variation difference criteria is satisfied. -
18 25.phi_Diff_OK Phase difference criteria is satisfied. -
19 25.RefDd Dead check of reference side is passed. -
20 25.RefLv Live check of reference side is passed. -
21 25.SynDd Dead check of synchronization side is passed. -
22 25.SynLv Live check of synchronization side is passed. -
5.3.2 Thermal Overload
5 Access path: MainMenu  “Measurements”  “Function Values”  “ThOvLd Values”
1 49.Accu_A Phase-A thermal state of thermal overload protection -
2 49.Accu_B Phase-B thermal state of thermal overload protection -
3 49.Accu_C Phase-C thermal state of thermal overload protection -
The calculated temperature difference of phase-A between the

4 49.T_Diff_A ℃
equipment and the oil.
The calculated temperature difference of phase-B between the

5 49.T_Diff_B ℃
The calculated temperature difference of phase-C between the

6 49.T_Diff_C ℃
5.3.3 Arc Flash
Access path: MainMenu  “Measurements”  “Function Values”  “ArcFlash Values”
1 50L/NL.LgtIncr_Sensor01 The light intensity of the sensor 01 mW
5 50L/NL.K_Calbr_Sensor01 The channel calibration coefficient of the sensor 01 -

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5.3.4 Current Summation
Access path: MainMenu  “Measurements”  “Function Values”  “Sum Values”
1 Sum.Ia_Sec Secondary phase-A current summation A
2 Sum.Ib_Sec Secondary phase-B current summation A
3 Sum.Ic_Sec Secondary phase-C current summation A
4 Sum.Ia_Pri Primary phase-A current summation A
5 Sum.Ib_Pri Primary phase-B current summation A
6 Sum.Ic_Pri Primary phase-C current summation A
5.4 Energy Metering

Access path: MainMenu  “Measurements”  “Energy Metering”

5
1 EA_Accu_Fwd Positive active energy kWh
2 EA_Accu_Rev Negative active energy kWh
3 ER_Accu_Fwd Positive reactive energy kVarh
4 ER_Accu_Rev Negative reactive energy kVarh
5 EA_Accu_Fwd_X Positive active energy for phase X (X=A,B,C) kWh
6 EA_Accu_Rev_X Negative active energy for phase X (X=A,B,C) kWh
7 ER_Accu_Fwd_X Positive reactive energy for phase X (X=A,B,C) kVArh
8 ER_Accu_Rev_X Negative reactive energy for phase X (X=A,B,C) kVArh
5.5 Power Quality

Access path: MainMenu  “Measurements”  “Power Quality”
U a  3 − U nn
1 Ua_Devn Deviation of phase A voltage = %
U nn
U b  3 − U nn
2 Ub_Devn Deviation of phase B voltage = %
U nn

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U c  3 − U nn
3 Uc_Devn Deviation of phase C voltage = %
U nn
4 f_Devn Deviation of frequency = f_meas - fn Hz
5 UnbalRate_U2 Unbalance rate of negative-sequence voltage = U2/U1 %
6 UnbalRate_3U0 Unbalance rate of zero-sequence voltage (calculated) = 3U0/U1 %
√∑15 2
𝑖=2 𝑈𝑎 𝐻𝑚_𝑖
7 THD_Ua Total Harmonic Distortion (THD) of phase A voltage 𝑇𝐻𝐷 = %
𝑈𝑎𝐻𝑚_1
√∑15 2
𝑖=2 𝑈𝑏 𝐻𝑚_𝑖
8 THD_Ub Total Harmonic Distortion (THD) of phase B voltage 𝑇𝐻𝐷 = %
𝑈𝑏𝐻𝑚_1
√∑15 2
𝑖=2 𝑈𝑐 𝐻𝑚_𝑖
9 THD_Uc Total Harmonic Distortion (THD) of phase C voltage 𝑇𝐻𝐷 = %
𝑈𝑐𝐻𝑚_1
10 UnbalRate_I2 Unbalance rate of negative-sequence current = I2/I1 %
11 UnbalRate_3I0 Unbalance rate of zero-sequence current (calculated) = 3I0/I1 %
√∑15 2
5 12 THD_Ia Total Harmonic Distortion (THD) of phase A current 𝑇𝐻𝐷 =

𝑖=2 𝐼𝑎 𝐻𝑚_𝑖
𝐼𝑎𝐻𝑚_1
%
√∑15 2
𝑖=2 𝐼𝑏 𝐻𝑚_𝑖
13 THD_Ib Total Harmonic Distortion (THD) of phase B current 𝑇𝐻𝐷 = %
𝐼𝑏𝐻𝑚_1
√∑15 2
𝑖=2 𝐼𝑐 𝐻𝑚_𝑖
14 THD_Ic Total Harmonic Distortion (THD) of phase C current 𝑇𝐻𝐷 = %
𝐼𝑐𝐻𝑚_1
Unbalance rate of negative-sequence current (another group of three-phase

15 S2.UnbalRate_I2 %
current) = I2/I1
Unbalance rate of calculated zero-sequence current (another group of

16 S2.UnbalRate_3I0 %
three-phase current) = 3I0/I1
Total Harmonic Distortion (THD) of phase A current (another group of

17 S2.THD_Ia √∑15 2 %
𝑖=2 𝐼𝑎 𝐻𝑚_𝑖
three-phase current) 𝑇𝐻𝐷 =
𝐼𝑎𝐻𝑚_1
Total Harmonic Distortion (THD) of phase B current (another group of

18 S2.THD_Ib √∑15 2 %
𝑖=2 𝐼𝑏 𝐻𝑚_𝑖
three-phase current) 𝑇𝐻𝐷 = 𝐼𝑏𝐻𝑚_1
Total Harmonic Distortion (THD) of phase C current (another group of

19 S2.THD_Ic √∑15 2 %
𝑖=2 𝐼𝑐 𝐻𝑚_𝑖
three-phase current) 𝑇𝐻𝐷 =
𝐼𝑐𝐻𝑚_1
5.6 Synchrophasor Measurement

The integrated Phasor Measurement Unit (PMU) function of synchrophasor measurement
receives raw data from the common A/D module. It is applied to measure synchrophasor of
busbar, line or transformer in substation and power plant, to calculate frequency and
active/reactive power, and to send real-time data to local Phasor Data Concentrators (PDC) in

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substation or to super PDC of upper level.
The PMU function adopts phasor measurement model recommended in C37.118.1-2011 to

achieve high measurement accuracy. The typical processing steps performed within the function
are:
Three-phase
voltage LP Single-
ADC LP
Three-phase Filter phase
Filter
current phasors
sin cos
Synchronized Quadrature
UTC signal
Clock Oscillator
Figure 5.6-1 Single-phase section of PMU phasor signal processing model
This model is the same for both P class and M class algorithms. It assumes fixed frequency
sampling synchronized to an absolute time reference, followed by complex multiplication with the
nominal frequency carrier. The low-pass (LP) filtering can be applied individually to the real and
imaginary outputs of the complex demodulator.
5
The complete PMU signal processing model is as follows, in which all processing shown are at
the A/D sampling rate. The reporting rate is produced by resampling at the system output.
Single-phase
Va(t)
phasor section
Measuring point
Single-phase Single-phase phasors

Vb(t) (Ua, Ub, Uc, Ia, Ib, Ic)
phasor section
Single-phase
Vc(t)
phasor section
Phasor calculation
(positive-sequence/ Sequence component phasors
negative-sequence/ (I1, I2, I0)
zero-sequence)
Deviation of phase angle Frequency (f)
Rate-Of-Change Of Frequency
Time synchronization Deviation of frequency (ROCOF)
Decimator
Figure 5.6-2 Complete PMU signal processing model
The normal positive sequence is calculated using the symmetrical component transformation. The
system frequency is calculated from the rate of change of phase angle, and the rate-of-change of
frequency (ROCOF) is then calculated.

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The calculation equations for the total active and reactive power are as follows.
𝑃 = 𝑟𝑒𝑎𝑙(𝑈̇𝑎 ∗ 𝐼 ̇𝑎 + 𝑈̇𝑏 ∗ 𝐼 ̇𝑏 + 𝑈̇𝑐 ∗ 𝐼 ̇𝑐), 𝑄 = 𝑖𝑚𝑎𝑔(𝑈̇𝑎 ∗ 𝐼 ̇𝑎 + 𝑈̇𝑏 ∗ 𝐼 ̇𝑏 + 𝑈̇𝑐 ∗ 𝐼 ̇𝑐)
Where:
𝑃 is three-phase active power.

𝑄 is three-phase reactive power.
𝑈̇𝑎 , 𝑈̇𝑏 , 𝑈̇𝑐 are three phase voltage phasors.
𝐼𝑎̇ , 𝐼𝑏̇ , 𝐼𝑐̇ are three phase current phasors.

Multiply symbol * means the voltage phasor multiplies the conjugated current phasor.
5.6.2 PMU Values

Access path: Main Menu  Measurements  PMU Values
5.6.2.1 PMU Phasor Values
5 The description names of the following quantities are their default value.
The description name is the combination of two kinds of settings value,
which are [Name_PMUBay] in the submenu PMUBay Settings and
[Name_Amp_XXXX] in the submenu PMU Label Settings.
No. Item Definition Unit
1 STN-Bay01-UAV Amplitude of phase A voltage phasor kV
2 STN-Bay01-UBV Amplitude of phase B voltage phasor kV
3 STN-Bay01-UCV Amplitude of phase C voltage phasor kV
4 STN-Bay01-U1V Amplitude of positive sequence voltage phasor kV
5 STN-Bay01-U2V Amplitude of negative sequence voltage phasor kV
6 STN-Bay01-U0V Amplitude of zero sequence voltage phasor kV
7 STN-Bay01-IAV Amplitude of phase A current phasor A
8 STN-Bay01-IBV Amplitude of phase B current phasor A
9 STN-Bay01-ICV Amplitude of phase C current phasor A
10 STN-Bay01-I1V Amplitude of positive sequence current phasor A
11 STN-Bay01-I2V Amplitude of negative sequence current phasor A
12 STN-Bay01-I0V Amplitude of zero sequence current phasor A
13 STN-Bay01-UAP Angle of phase A voltage phasor deg
14 STN-Bay01-UBP Angle of phase B voltage phasor deg
15 STN-Bay01-UCP Angle of phase C voltage phasor deg
16 STN-Bay01-U1P Angle of positive sequence voltage phasor deg
17 STN-Bay01-U2P Angle of negative sequence voltage phasor deg

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18 STN-Bay01-U0P Angle of zero sequence voltage phasor deg
19 STN-Bay01-IAP Angle of phase A current phasor deg
20 STN-Bay01-IBP Angle of phase B current phasor deg
21 STN-Bay01-ICP Angle of phase C current phasor deg
22 STN-Bay01-I1P Angle of positive sequence current phasor deg
23 STN-Bay01-I2P Angle of negative sequence current phasor deg
24 STN-Bay01-I0P Angle of zero sequence current phasor deg
5.6.2.2 PMU Analog Values
The description names of the following quantities are their default value.
The description name is the combination of two kinds of settings value,
which are [Name_PMUBay] in the submenu PMU Bay Settings and
[Name_Amp_XXXX] in the submenu PMU Label Settings.

5
1 STN-Bay01-FRQ Frequency Hz
2 STN-Bay01-DFT Rate-of-change of frequency Hz/s
3 STN-Bay01-00P Active power MW
4 STN-Bay01-00Q Reactive power MVAr
5.6.2.3 PMU Digital Values
The description names of the following quantities are their default value.
The description name is determined by the setting value of [Name_BI_**]
in the submenu PMU BI Settings.
1 STN-Digital** Binary status **
5.6.2.4 PMU Miscellaneous Values
1 STAT Bit mapped status, defined in IEEE C37.118 standard
2 f System frequency Hz
3 f_Diff System frequency deviation Hz
4 df/dt Rate-of-change of system frequency Hz/s

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5.6.3 PMU Status
Access path: Main Menu  Status  PMU Status
5.6.3.1 PMU Clock Synchronisation Status
1 Sig_TimeSyn_OK Flag of time synchronization
2 TQ_IRIG-B Time quality of IRIG-B signal
3 Sig_TimeKeep Flag of time keeping
4 Quality_TimeKeep Quality bit of time keeping
5 Flg_LeapSecond Flag of leap second
5.6.3.2 PDC Communication Status
1 PDC**.Name Name of PDC**
2 PDC**.Connected Connection status with PDC
5 3 PDC**.DataRate Transmission data rate fps
4 PDC**.N_Phasor Number of transmitted phasors
5 PDC**.N_Analog Number of transmitted analog quantities
6 PDC**.N_BI Number of transmitted digital status
7 PDC**.DataRate_CFG2 Transmission data rate in CFG2 fps
8 PDC**.N_SendCFG1 Number of CFG1 retrieval times
9 PDC**.N_SendCFG2 Number of CFG2 retrieval times
10 PDC**.N_TurnOnData Number of turning on real-time data
5.6.3.3 PMU CFG1 Status
1 N_Phasor_CFG1 Number of phasors in CFG1
2 N_Analog_CFG1 Number of analog quantities in CFG1
3 N_BI_CFG1 Number of digital status in CFG1 fps
5.6.3.4 PMU Supervision Status
1 Alm_Phasor_Config Error of phasor configuration
2 Alm_Analog_Config Error of analog input configuration
3 Alm_BI_Config Error of digital status configuration
4 PDC**.Alm_Invalid_IDCODE PDC**_IDCODE is invalid
5 Alm_TimeSyn Error of time synchronization

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6 XXXX.Alm_VTS Error of VT circuit
7 XXXX.Alm_CTS Error of CT circuit
5.6.4 PMU Settings
5.6.4.1 PMU Global Settings
Access path: Main Menu  Settings  PMU Settings  PMU Global Settings
No. Setting Default Range Step Unit Remark

Disabled or Enabling/Disabling PMU function for
1 En_PMU Enabled - -
Enabled synchrophasor measurement
Performance class option of the
measured values for the use in
P_Class or calculation
2 Opt_Class_PMU M_Class - -
M_Class P class: faster response time
M class: higher measurement
precision
3 DataRate 50 10~120 1 fps Data transmission rate (to PDC)
5
Max. 16
4 Substation_PMU NR_Station1 - - Name of PMU substation
characters
Times of change of CFG
To inform the updated version number
5 N_Chgd_CFG 1 0~65535 1 - which should be increased if any
configuration or setting has been
modified
6 Port_TCP 4712 0~65535 1 - PMU port TCP address
7 Port_UDP 4713 1024~65535 1 - PMU port UDP address
5.6.4.2 PMU Comm Settings
Access path: Main Menu  Settings  PMU Settings  PMU Comm Settings  PDC**
Settings

1 PDC**.Name PDC** - - - Connected PDC name
000.000.000.000~ IP address of connected
2 PDC**.IP_TCP 198.120.0.20 - -
255.255.255.255 PDC
000.000.000.000~
3 PDC**.IP_UDP_Dest 198.120.0.20 - - Destination IP address
255.255.255.255
Multicast source IP
000.000.000.000~
4 PDC**.IP_MulticastSrc 198.120.0.1 - - address, valid for multicast
255.255.255.255
mode using UDP
5 PDC**.Opt_Protocol None None, - - Option of PDC

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TCP, communication protocol
UDP, None: no communication
TCP-UDP between PDC and PMU
TCP: TCP for the
transmission of
configuration frame,
command frame and data
frame.
UDP: UDP for the
transmission of
frame.
TCP-UDP: TCP for the
transmission of
configuration frame and
command frame; UDP for
5 the transmission of data
frame.
Unicast,
Option of UDP broadcast
6 PDC**.Opt_UDP Multicast Broadcast, - -
mode
Multicast
7 PDC**.IDCODE 1 1~65534 - - Connected PDC IDCODE
5.6.4.3 PMU Bay Settings
Access path: Main Menu  Settings  PMU Settings  PMU Bay Settings

Max. 12
1 Name_PMUBay STN-Bay** - - Configurable PMU bay name
characters
None,
Bay,
2 XXXX.Opt_UnitType Bay 1 - Bay application scenario
Bus(U_3P),
Bus(U_1P)
U1,
Ua, Option of base voltage for
3 XXXX.Opt_U_MeasFreq U1 1 -
Ub, frequency measurement
Uc
Enabling/Disabling disturbance
Disabled or
4 XXXX.En_TrigDFR Enabled - - fault recording function in case
Enabled
any following over limit situation
5 XXXX.Up_UpLmt 1.200 0.010~2.000 0.001 Un Upper limit of phase voltage

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Upper limit of positive sequence
6 XXXX.U1_UpLmt 1.200 0.010~2.000 0.001 Un
voltage
Upper limit of negative sequence
7 XXXX.U2_UpLmt 0.200 0.010~2.000 0.001 Un
voltage
Upper limit of zero sequence
8 XXXX.U0_UpLmt 0.200 0.010~2.000 0.001 Un
voltage
9 XXXX.Up_LowLmt 0.900 0.010~2.000 0.001 Un Lower limit of phase voltage
Lower limit of positive sequence
10 XXXX.U1_LowLmt 0.900 0.010~2.000 0.001 Un
voltage
11 XXXX.Ip_UpLmt 1.200 0.010~2.000 0.001 In Upper limit of phase current
12 XXXX.I1_UpLmt 1.200 0.010~2.000 0.001 In
current
13 XXXX.I2_UpLmt 0.200 0.010~2.000 0.001 In
current
14 XXXX.I0_UpLmt 0.200 0.010~2.000 0.001 In
current
15 XXXX.f_Diff_Lmt 0.50 0.01~10.00 0.01 Hz Limit of frequency deviation
Limit of rate-of-change of
5
16 XXXX.df/dt_Lmt 1.00 0.01~50.00 0.01 Hz/s
frequency
5.6.4.4 PMU BI Settings
Access path: Main Menu  Settings  PMU Settings  PMU BI Settings

Max. 16
1 Name_BI_** STN-Digital** - - Configurable PMU binary signal name
charactors
Enabling/Disabling disturbance fault
Disabled or
2 Link_BI_TrigDFR Enabled - - recording function in case state change
Enabled
of any PMU binary signal
Disabled or
3 BI_**.En_TrigDFR Enabled - - recording function in case state change
Enabled
of the PMU binary signal BI_**
5.6.4.5 PMU Label Settings
Access path: Main Menu  Settings  PMU Settings  PMU Label Settings

1 Name_Amp_Ua -UAV - - - Label for amplitude of phase A voltage phasor
2 Name_Amp_Ub -UBV - - - Label for amplitude of phase B voltage phasor
3 Name_Amp_Uc -UCV - - - Label for amplitude of phase C voltage phasor
4 Name_Amp_U0 -U0V - - - Label for amplitude of zero sequence voltage phasor
5 Name_Amp_U1 -U1V - - - Label for amplitude of positive sequence voltage

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phasor
Label for amplitude of negative sequence voltage
6 Name_Amp_U2 -U2V - - -
phasor
7 Name_Amp_Ia -IAV - - - Label for amplitude of phase A current phasor
8 Name_Amp_Ib -IBV - - - Label for amplitude of phase B current phasor
9 Name_Amp_Ic -ICV - - - Label for amplitude of phase C current phasor
10 Name_Amp_I0 -I0V - - - Label for amplitude of zero sequence current phasor
Label for amplitude of positive sequence current
11 Name_Amp_I1 -I1V - - -
phasor
Label for amplitude of negative sequence current
phasor
13 Name_Ang_Ua -UAP - - - Label for angle of phase A voltage phasor
14 Name_Ang_Ub -UBP - - - Label for angle of phase B voltage phasor
15 Name_Ang_Uc -UCP - - - Label for angle of phase C voltage phasor
16 Name_Ang_U0 -U0P - - - Label for angle of zero sequence voltage phasor
17 Name_Ang_U1 -U1P - - - Label for angle of positive sequence voltage phasor
5 18 Name_Ang_U2 -U2P - - - Label for angle of negative sequence voltage phasor
19 Name_Ang_Ia -IAP - - - Label for angle of phase A current phasor
20 Name_Ang_Ib -IBP - - - Label for angle of phase B current phasor
21 Name_Ang_Ic -ICP - - - Label for angle of phase C current phasor
22 Name_Ang_I0 -I0P - - - Label for angle of zero sequence current phasor
23 Name_Ang_I1 -I1P - - - Label for angle of positive sequence current phasor
24 Name_Ang_I2 -I2P - - - Label for angle of negative sequence current phasor
25 Name_f -FRQ - - - Label for bay frequency
26 Name_df/dt -DFT - - - Label for bay rate-of-change of frequency
27 Name_P -00P - - - Label for bay active power
28 Name_Q -00Q - - - Label for bay reactive power
29 Name_phi_diff -FAI - - - Label for bay phase difference
5.7 DC Analogue Outputs

The DC analogue output function outputs several channels of voltage or current rated at
configurable range: 4~20mA, 0~10V, 0~5V or 0~20mA. 4 or 8 (depending on the subtype) outputs
are available in one DC AO module, which can be plugged into a plug-in module slot. Typically,
the DC analogue output is connected to Distributed Control System (DCS) in power plant.

The DC analogue output function provides the regulation mode and the monitoring mode.
⚫ Regulation mode
Regulation command from remote control centre or local station control could be transmitted

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to the device and be converted to DC analogue output to regulate an object such as

active/reactive power output of generator.
⚫ Monitoring mode
A measured or calculated value input terminal of DC analog such as active/reactive power or

temperature, could be converted to DC analogue output and sent to DCS system for real-time
monitoring.
User may define the maximal and the minimal values of each DC analogue output channel to
create a characteristic curve that connects the physical quantities to DC analogue output values.
So as to simply the physical signification understanding. The following figure shows an example.
Output (mA)
20mA
P
DC output value
4mA
Regulation value
5
0
Min. Object Max.
Figure 5.7-1 Characteristic curve of DC analogue output
In the example, the output range is defined as 4~20mA. The lower limit 4mA is related to the
minimal regulation value which is defined by the setting [B**.DCAO**.Min_Regu] while the upper
limit 20mA is related to the maximal regulation value which is defined by the setting
[B**.DCAO**.Max_Regu]. Thus, the regulation value can be converted into a corresponding DC
analogue output value between 4~20mA for the object point P.
DCAO
in_en
in_blk
in_remote
in_local
input
5.7.3 I/O Signals

1 B**.DCAO**.input Object regulation value

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2 B**.DCAO**.in_Remote Remote regulation mode
3 B**.DCAO**.in_Local Local regulation mode
Access path: Main Menu  Measurements  Function Values 
1 B**.DCAO**.Output_Raw DCAO_Values
Raw value of DC analogue channel **
Access path: Main Menu  Measurements  Function Values 
DCAO_Values
2 B**.DCAO**.Output
Converted output value (physical quantity, 4~20mA, 0~10V, 0~5V or
0~20mA) of DC analogue channel **
5.7.4 Settings
Access path: Main Menu  Settings  Meas Control Settings  DCAO Settings

4~20mA
0~10V Option of DC analogue
5 1 B**.DCAO**.Opt_Type_Regu 4~20mA
0~5V
- -
output range
0~20mA
The minimal converted
2 B**.DCAO**.Min_Regu 0 -60000~60000 0.01 -
physical quantity value
The maximal
3 B**.DCAO**.Max_Regu 10 -60000~60000 0.01 - converted physical
quantity value

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6 Supervision
Table of Contents
6.1 Overview........................................................................................................... 6-1

6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-2
6.2.2 Hardware Status Supervision ............................................................................................... 6-2
6.2.3 Hardware Configuration Supervision ................................................................................... 6-3
6.2.4 Device Firmware Supervision .............................................................................................. 6-3
6.2.5 CPU Process and Module Supervision ................................................................................ 6-3
6.3 Analog Input Supervision ............................................................................... 6-3

6.4 Secondary Circuit Supervision....................................................................... 6-4
6.5 Binary Input Supervision ................................................................................ 6-5
6.5.1 Debounce Time .................................................................................................................... 6-5
6.5.2 Jitter Processing ................................................................................................................... 6-7

6
6.6 Tripping Counter Statistics ............................................................................. 6-9
6.7 Supervision Alarms and Handling Suggestion ............................................. 6-9
List of Figures
Figure 6.4-1 Principle of the TCS function with two binary inputs ........................................ 6-4
Figure 6.5-1 Sequence chart of debounce technique ............................................................. 6-5
Figure 6.5-2 Debounce time configuration page...................................................................... 6-6
Figure 6.5-3 Sequence chart of jitter processing..................................................................... 6-8
List of Tables
Table 6.7-1 Alarm description..................................................................................................... 6-10
Table 6.7-2 Alarm handling suggestion .................................................................................... 6-17

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6.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device needs to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed if required.
6.2 Device Hardware Supervision
All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For
peripherals, it can monitor the status of the interface module, check the input and output data,
send the communication interface and receive self-loop detection. Memory self-check is used to
detect unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.
The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is detected
whether the interface work is abnormal.
The hardware supervision also includes the power supply status monitoring. The voltage
monitoring chip is used by all the power supplies. The reset voltage threshold is pre-set to the
reset monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will
output the reset signal to control CPU to be in the reset state and avoid the wrong operation.

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6.2.1 Hardware Resource Consumption Supervision

1. Logic component total execution time monitoring
In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the
PCS-Studio automatically calculates the time required for the theoretical execution of the
configured components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.
2. Module data exchange monitoring
During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.
3. Configuration file size monitoring
The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the
PCS-Studio prompts the configuration error.
6.2.2 Hardware Status Supervision

6 1. Memory ECC and parity functions.
The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and
eliminate the logic abnormity caused by memory errors.
2. Memory error monitoring in code area and constant data area
In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device
hardware, only at the moment and not restart.
3. Binary output relay drive monitoring
The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from mal-operation when the device is not given a
tripping order and the binary output relay driver is detected in the effective state.
4. CPU temperature monitoring
The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature

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monitored by CPU.
6.2.3 Hardware Configuration Supervision
The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre-configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.
6.2.4 Device Firmware Supervision
1. Each hardware module configuration check code needs to be consistent with CPU module.
The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.
2. The hardware modules and process interface versions need to be consistent with the CPU
module.
If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.
3. Configuration text is correct.
The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not. 6
4. Whether any setting is over the range, whether it needs to confirm the settings.
If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.
6.2.5 CPU Process and Module Supervision

1. Monitor the heartbeat of the module.
In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.
2. Check whether the settings of other modules are consistent with the CPU module.
The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".
6.3 Analog Input Supervision
The sampling circuit of this device is designed as dual-design scheme. Each analog sampling

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channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal “Alm_Sample“,
and the protection function related to the sampling channel is disabled at the same time. When
the sampling circuit returns to normal state, the related protection is not blocked after 10s.
6.4 Secondary Circuit Supervision
The secondary circuit supervision function includes current transformer supervision (CTS),
voltage transformer supervision (VTS) and tripping/closing circuit supervision.
⚫ CTS function
The purpose of the CTS function is to detect whether the current transformer circuit is failed. In
some cases, if the CT is failed (broken-conductor, short-circuit), related protective element should
be blocked for preventing this device from mal-operation.
See further details about the CTS function, please refer Chapter 3.
⚫ VTS function
The purpose of the VTS function is to detect whether the VT analog input is normal. Because
some function, such as synchronism check, will be influenced by a voltage input failure.
The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit
6 fault, poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and
then issue an alarm signal and block relevant function.
See further details about the VTS function, please refer to Chapter 3.
⚫ Tripping circuit supervision function
The tripping circuit supervision function can be realized by program the logic function of this
device through the PCS-Studio according to the practical application experience of the user. In
this manual, a scheme which uses two independent binary inputs to supervise the tripping circuit
is recommended.
The following figure show the recommended scheme for tripping circuit supervision and the logic
diagram of the TCS function.
DC+ DC-
52a TC
BTJ
52b
Protection Device Circuit Breaker

[BI_01]
& 600ms [Alm_TCS]
[BI_02]
Figure 6.4-1 Principle of the TCS function with two binary inputs
Where:

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“BTJ” is the protection tripping output contact;
“TC” is the tripping coil of the circuit breaker;
[BI_01] is the binary input which is parallel connected with “BTJ”;
[BI_02] is the binary input which is serial connected with the “52b” contact.
6.5 Binary Input Supervision

6.5.1 Debounce Time
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.5-1.
Binary input
state
SOE report SOE report

timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1
Debounce time of Debounce time of 6

delayed pickup delayed dropout
Time
Figure 6.5-1 Sequence chart of debounce technique
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.
In order to meet flexible configurable requirement for different project field, all binary inputs
provided by the device are configurable. Through the configuration tool, this device provides two
parameters to setup debounce time of delayed pickup and drop-out based on specific binary
signal.

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Figure 6.5-2 Debounce time configuration page
The configurable binary signals can be classified as follows:
1. Type 1
This type of binary inputs includes enable/disable of protection functions, AR mode selection,
“BI_RstTarg”, “BI_Maintenance”, disconnector position, settings group switch, open and
close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They are on the premise of reliability, and the
debounce time of delayed pickup and delayed drop-out is recommended to set as 100ms at
least.
6 2. Type 2
This type of binary inputs include breaker failure initiating binary inputs,
“CSWIxx.Cmd_LocCtrl”, “CSWIxx.Cmd_RmtCtrl” and so on.
Debounce time
BI Input Signal.X1 t1 t2 &

Time delay Output
SIG Operation condition
⚫ Time delay is equal to 0
The debounce time of delayed pickup and delayed drop-out is recommended to set as
15ms, in order to prevent binary signals from mal-operation due to mixed connection of
AC system and DC system.
⚫ Time delay is not equal to 0
The debounce time of delayed pickup and delayed drop-out is recommended to set as
(-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from mal-operation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed drop-out.
3. Type 3

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This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed drop-out is recommended to set as 5ms.
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.
6.5.2 Jitter Processing
This device can handle repetitive signal or so-called jitter via binary input module with the following
settings:
[Mon_Window_Jitter] T, monitoring window of binary input jitter processing
[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter
[Blk_Window_Jitter] T', blocking window of binary input status change due to jitter
[Num_Reblk_Jitter] N', times threshold to initiate immediately another blocking

window of binary input status change due to continuous jitter
For a binary input voltage variation, if the jitter processing function is enabled, its handling
principle is:
1. During the T,
⚫ If the actual jitter times < N, the block will not be initiated and the status change of this
6
binary input will be considered.
⚫ If the actual jitter times ≥ N, the T' is initiated, and the status change of binary input will
be ignored during the T'.
2. During the T',
⚫ If the actual jitter times < N', the block window will expire. The final status of this binary
input will be compared to the original one before T', so as to determine whether there is a
change or not.
⚫ If the actual jitter times ≥ N', the T' will be initiated again immediately (i.e. restart the
timer), and the status change of binary input will be ignored during the next T'.
An example of jitter processing is shown in the following sequence chart:

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Debounce time Input voltage level

(falling edge)
Debounce time
(rising edge)
Jitter blocking flag

n=N
initiate jitter block
Signal after
debounce & jitter
n=6<N=7
n=N processing
Prolong blocking
window
T
T t7 t8
t5 t6
T T T
t1 t2 t3 t4 t9 t10 t
Figure 6.5-3 Sequence chart of jitter processing
①Red line Voltage variation of binary input
②Green line Blocking signal of binary input status change due to jitter
6
③Blue line Binary input status after debounce and jitter processing
n Actual jitter times
We take N = 7 and N' = 5 in this example.
1. T = t2 - t1
⚫ n=6<N
⚫ No blocking, ② stays at 0 and ③ is tracing the voltage variation to create SOE.
2. T = t4 - t3, at t5
⚫ n=7=N
⚫ The processing initiates the blocking immediately due to jitter
⚫ Jitter blocking, no more SOE event, ② changes its status to 1 and ③ stops the tracing.
3. T' = t6 - t5
⚫ At t7, n = 5 =N', the processing prolongs the blocking immediately due to jitter

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⚫ Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
4. T'= t8 - t7
⚫ At t9, n = 5 =N', the processing prolongs the blocking immediately due to jitter.
⚫ Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
5. T'= t10 - t9
⚫ n = 2 < N'
⚫ At t10, jitter unblocking, ② changes its status to 0, the blocking window expires and ③
restart to trace the voltage varation immediately. At this point, no debounce time takes
effect and SOE can be created since then.
6.6 Tripping Counter Statistics
The tripping counter statistics function supports statistics of the tripping operation, such as circuit
breakers, disconnectors and so on. For phase separation circuit breaker, when the position of
phase A, B, and C is detected from close state to open state, the total position tripping counter is
added, and the tripping counter is added once when the position of the disconnector is detected
from close state to open state.
6
In addition, the statistics of the number of state change of circuit breakers and disconnectors are
also provided. The state change counter will add one when the position is detected from close
state to open state or from open state to close state.
6.7 Supervision Alarms and Handling Suggestion
Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
If the device is blocked or alarm signal is sent during operation, please do find out its reason with
the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.

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Table 6.7-1 Alarm description
Running Status LED

No. Item Description
HEALTHY ALARM Modifiable
Fail Signals (Device will be blocked)

This signal will be issued if
any fail signal picks up and it
1 Fail_Device OFF OFF NO
will drop off when all fail
signals drop off.
any hardware or software
failure, or serious
2 Fail_DeviceInit OFF OFF NO
configuration error is
detected in the device
initialization process.
This signal will be issued due
to mismatch between the
configuration of plug-in
3 Fail_BoardConfig OFF OFF NO
modules and the designing
drawing of an
applied-specific project.
6 the CCD process level
configure file is parsed
4 Fail_ProcLevelConfig OFF OFF NO
wrongly or the type in the file
is inconsistent with the actual
device.
After configuration file is
updated, settings of the file
and settings saved on the
device are not matched. This
5 Fail_SettingItem_Chgd OFF OFF NO signal will be issued
instantaneously and will be
latched unless the
recommended handling
suggestion is adopted.
The value of any setting is
out of scope. This signal will
be issued instantaneously
6 Fail_Setting_OvRange OFF OFF NO
and will be latched unless
the recommended handling
The alarm signal will be
7 Fail_Memory OFF OFF NO
issued instantaneously when

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Running Status LED

an error is found during

checking memory data, and
usually, it will automatically
drop out.
The board fails to register the
variable, because of
8 Fail_BoardRegister OFF OFF NO abnormal board, insufficient
memory space, or incorrect
configuration.
The configuration process
9 Fail_ProcessConfig OFF OFF NO
does not run properly.
The board fails to be
initialized, because of
10 Fail_BoardInit OFF OFF NO abnormal board, insufficient
memory space, or incorrect
configuration.
Error is found during
checking settings. It means
inappropriate or incorrect
settings for some application
scenarios are checked.
6
11 Fail_Settings OFF OFF NO
This signal will be issued
instantaneously and will be
latched unless the
recommended handling
A/D sampling data push
error, the possible cause is
12 Fail_Sample OFF OFF NO that the data verification fails
or no data is sampled by A/D
converter.
The output module is
13 Fail_Output OFF OFF NO
abnormal
An abnormality is detected
14 Bx.Fail_Board OFF OFF NO during self-check of No. x
board of this device.
The PWR module is
15 P1.Fail_Board OFF OFF NO
abnormal.
Alarm Signals (Device will not be blocked)
The device is abnormal. This
16 Alm_Device ON ON NO
signal will be issued if any

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Running Status LED

alarm signal picks up and it

will drop off when all alarm
signals drop off.
any hardware or software
17 Alm_DeviceInit ON OFF NO configuration wrong is
detected in the device
The error is found during
checking the version of
software downloaded to the
18 Alm_Version ON ON NO
device. This signal will be
issued instantaneously and
will drop off instantaneously.
Alarm signal indicating that
the equipment is in
maintenance state (the
19 Alm_Maintenance ON ON YES
binary input
[BI_Maintenance] is
6 energized.
The device is in the
communication test mode.
20 Alm_CommTest ON ON NO This signal will be issued
instantaneously and will drop
off instantaneously.
The device is in the GOOSE
test mode. This signal will be
21 Alm_GOOSETest ON OFF NO
Management procedure will
upload and check the
parameters and settings of
each protection plug-in
22 Alm_Settings_MON ON ON NO
module regularly, if the
parameters and settings are
inconsistent, the alarm signal
will be issued.
The active group set by
settings in device and that
23 Alm_BI_SettingGrp ON OFF NO
set by binary input are not
matched. This signal will be

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Running Status LED


The time synchronization
24 Alm_TimeSyn ON ON YES
abnormality alarm.
The memory of CPU plug-in
25 Alm_Insuf_Memory ON ON NO
module is insufficient.
The configuration file of
IEC103 is detected to be not
26 Alm_CfgFile_IEC103 ON ON NO correct when this file is
parsed in the device
CPU module detects that
some module is reset due to
27 Alm_Board ON OFF NO
the abnormality during the
device operating.
An abnormality is detected
28 Bx.Alm_Board ON ON NO during the module
self-check.
No sufficient NOR flash
29 Alm_Insuf_NORflash ON OFF NO space used to store the
program in CPU module
6
The settings which are
stored in CPU module are
30 Alm_Settings ON ON NO different with the settings
which are used by other
modules.
Disturbance fault recording
31 Alm_Settings_DFR ON OFF NO
settings are set wrongly
The network mode is
inconsistent, such as the
32 Alm_NetMode_Unmatched ON OFF NO setting is set as HSR mode,
but the actual operation
mode is PRP mode.
The device's master process
33 Alm_master ON ON NO is abnormal and it is blocked
for more than 1 minute.
Error is detected in the FPGA
34 Alm_CfgFile_FPGA ON OFF NO
configuration file.
Error is detected in internal
35 Alm_DSP_HTM_Comm ON ON NO
communication.
36 Alm_CRC_ProcLevel ON OFF NO Error is detected in the

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Running Status LED

configuration file of process

level by CRC.
The configuration file of DNP
37 Alm_CfgFile_TCP1_DNP ON OFF NO
client 1 is incorrect.
The device is in the binary
41 Alm_BOTest ON OFF NO
output test mode.
the sampled values from the
dual A/D converters are
inconsistent or the sampled
42 Alm_Sample ON ON NO
value contains a large DC
component during the self or
mutual supervision of
6 sampling channels.
The quality of sampled data
43 Alm_Quality ON ON NO
is abnormal.
DPS abnormality signal, if
the circuit breaker position is
intermediate or bad, this
alarm will be issued.
44 CB.DPS.Alm ON OFF YES
This signal will pick up and
drop off with a time delay
defined by
[CSWI**.DPS.t_Alm].
DPS abnormality signal, if
the switch 0x position is
intermediate or bad, this
DS0x.DPS.Alm alarm will be issued.
45 ON OFF YES
(x=1~9) This signal will pick up and
drop off with a time delay
defined by
[CSWI**.DPS.t_Alm].
The initiating signal of
46 50BF.Alm_Init ON ON YES breaker failure protection is
energized consistently.

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Running Status LED

CT circuit fails.
This signal will pick-up with a
47 CTS.Alm ON ON YES time delay of [CTS.t_DPU]
and will drop-out with a time
delay of [CTS.t_DDO].
VT circuit fails.
This signal will pick-up with a
48 VTS.Alm ON ON YES time delay of [VTS.t_DPU]
and will drop-out with a time
delay of [VTS.t_DDO].
GOOSE alarm signals (Device will not be blocked)
The GOOSE communication
is abnormal.
It is an overall alarm signal
and will be issued if any
49 GAlm_Overall ON ON NO
GOOSE alarm signal picks
up and it will drop-out when
all these alarm signals
drop-out.
50 GAlm_CfgFile ON ON NO
GOOSE
indicating
alarm
that GOOSE
signal
6
configuration file is incorrect.
For GOOSE link, the
incoming data with test=true
& validity=good &
51 GAlm_Maint_Unmatched ON ON NO
operatorBlocked=false, but
the quality status (q) of the
device equals to "on".
Network A of corresponding
GOOSE link is disconnected
@Bx.Name_n_GCommLink. (No GOOSE message is
52 ON ON NO
GAlm_ADisc received within two times
TAL from corresponding
GOOSE link)
Network B of corresponding
GOOSE link is disconnected
@Bx.Name_n_GCommLink. (No GOOSE message is
53 ON ON NO
GAlm_BDisc received within two times
TAL from corresponding
GOOSE link)
54 @Bx.Name_n_GCommLink. ON ON NO The GOOSE control blocks

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Running Status LED

GAlm_CfgUnmatched received on network and the

GOOSE control blocks
defined in GOOSE
configuration file are
unmatched (Including config
version, number of data sets
and data type).
The SV communication is
abnormal.
It is an overall alarm signal
55 SVAlm_Overall ON ON NO and will be issued if any SV
alarm signal picks up and it
will drop-out when all these
alarm signals drop-out.
Error is detected in the SV
56 SVAlm_CfgFile ON ON NO
configuration file.
For SV link, the incoming
data with test=true &
validity=good &
57 SVAlm_Maint_Unmatched ON ON NO
6 operatorBlocked=false,
the quality status (q) of the
but
device equals to "on".

Network A of corresponding
SV link is disconnected.
@Bx.Name_n_SVCommLink
58 ON ON NO (Including data timeout,
.SVAlm_ADisc
decoding error, or sampling
counter error)
Network B of corresponding
SV link is disconnected.
59 ON ON NO (Including data timeout,
.SVAlm_BDisc
decoding error, or sampling
counter error)
Interpolation error of
60 ON ON NO sampling data in the
.SVAlm_Data
corresponding SV link
@Bx.Name_n_SVCommLink Loss of synchronization in
61 ON ON NO
.SVAlm_SmplSynLoss the corresponding SV link
@Bx.Name_n_SVCommLink Invalid sampling data in the
62 ON ON NO
.SVAlm_InvalidSample corresponding SV link
@Bx.Name_n_SVCommLink Jittering error of sampling
63 ON ON NO
.SVAlm_Jitter_Ch data in the corresponding SV

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Running Status LED

link
The channel delay of the
64 ON ON NO corresponding SV link
.SVAlm_tdrChgd_Ch
changes.
The channel delay of the
65 ON ON NO corresponding SV link
.SVAlm_tdrOvRange_Ch
exceeds the limit.
@Bx.Name_n_SVCommLink The corresponding SV link is
66 ON ON NO
.SVAlm_Maintenance in maintenance state
Table 6.7-2 Alarm handling suggestion
No. Item Handling suggestion
Fail Signals (Device will be blocked)

The signal is issued with other specific fail signals, and please refer to the
1 Fail_Device
handling suggestion other specific alarm signals.
2 Fail_DeviceInit Please inform the manufacturer or the agent for repair.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig 2. For the abnormality board, if the board is not used, then remove, and if 6
the board is used, then check whether the board is installed properly and
work normally.
Check whether the CCD process level configuration file of this device is
4 Fail_ProcLevelConfig existed and whether the file content is correct. May need to download and
update the correct CCD process level configuration file.
Please check the settings mentioned in the prompt message on the LCD,
5 Fail_SettingItem_Chgd and go to the menu “Settings” and select “Confirm_Settings” item to
confirm settings. Then, the device will restore to normal operation stage.
Please reset setting values according to the range described in the
6 Fail_Setting_OvRange instruction manual, then re-power or reboot the device and the device will
restore to normal operation state.
7 Fail_Memory
Please inform the manufacturer or the agent for repair.
8 Fail_BoardRegister
9 Fail_ProcessConfig View the menu "Initialization Error" to check the detailed reason, and
10 Fail_BoardInit send the reason to the manufacturer or the agent.
11 Fail_Settings Please check the settings and set them correctly
12 Fail_Sample Please check the connection of CPU plug-in module.
Put the protective device out of service at once. Inform the manufacturer
13 Fail_Output
or the agent to maintain it.
14 Bx.Fail_Board Please inform the manufacturer or the agent to deal with it.

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15 P1.Fail_Board Please inform the manufacturer or the agent to deal with it.
Alarm Signals (Device will not be blocked)
The signal is issued with other specific alarm signals, and please refer to
16 Alm_Device
the handling suggestion other specific alarm signals.
17 Alm_DeviceInit Please inform the manufacturer or the agent to deal with it.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package file
(including correct version checksum file) provided by R&D engineer to
18 Alm_Version make the alarm signal disappear. Then users get the correct software
version. It is not allowed that the alarm signal is issued on the device
already has been put into service. The devices having being put into
service so that the alarm signal disappears.
19 Alm_Maintenance Check the binary input [BI_Maintenance].
20 Alm_CommTest No special treatment is needed, and disable the communication test
21 Alm_GOOSETest function after the completion of the test.
Put the protective device out of service at once. Inform the manufacturer
22 Alm_Settings_MON
or the agent to maintain it.
Please check the value of setting [Active_Grp] and binary input of
indicating active group, and make them matched. Then the “ALARM”
23 Alm_BI_SettingGrp
6 LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
1. Check whether the selected clock synchronization mode matches the
clock synchronization source;
2. Check whether the wiring connection between the device and the clock
synchronization source is correct
3. Check whether the setting for selecting clock synchronization (i.e.
24 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization,
please set the setting [Opt_TimeSyn] as “No TimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
25 Alm_Insuf_Memory Please inform the manufacturer or the agent to deal with it.
26 Alm_CfgFile_IEC103 Please inform the manufacturer or the agent to deal with it.
27 Alm_Board
28 Bx.Alm_Board
Please inform the manufacturer or the agent to deal with it.
29 Alm_Insuf_NORflash
30 Alm_Settings
Please refer to the fault recording configuration related contents, i.e.
31 Alm_Settings_DFR
Section 7.4.
Check the setting of network mode, or upload the device log and confirm
32 Alm_NetMode_Unmatched
with the manufacturer or agent whether the network mode is supported.

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33 Alm_master Please check the load of the device.

34 Alm_CfgFile_FPGA Please inform the manufacturer or the agent for repair.
35 Alm_DSP_HTM_Comm Please inform the manufacturer or the agent for repair.
36 Alm_CRC_ProcLevel Please check the configuration and network of the process level.
37 Alm_CfgFile_TCP1_DNP
38 Alm_CfgFile_TCP2_DNP Please contact the configuration engineer to check and confirm the
39 Alm_CfgFile_TCP3_DNP contents of DNP configuration file.
40 Alm_CfgFile_TCP4_DNP
No special treatment is needed, and disable the binary output test
41 Alm_BOTest
function after the completion of the test.
42 Alm_Sample Please check the connection of AC AI module and CPU module.
43 Alm_Quality Please check SV quality if adopting IED 61850-9-2.
44 CB.DPS.Alm
DS0x.DPS.Alm Check the corresponding DPS signal
45
(x=1~9)
46 50BF.Alm_Init Check the initiating contact of breaker failure protection
Please check the corresponding CT secondary circuit. After the
47 CTS.Alm
abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit. After the
48 VTS.Alm
abnormality is eliminated, the device returns to normal operation state. 6
GOOSE alarm signals (Device will not be blocked)
The signal is issued with other specific GOOSE alarm signals, and please
49 GAlm_Overall
refer to the handling suggestion of them.
50 GAlm_CfgFile Inform commissioning personnel to check the GOOSE configuration file.
51 GAlm_Maint_Unmatched Please check the quality status (q) of the incoming data and the device.
@Bx.Name_n_GCommLink.
52
GAlm_ADisc
53 Please check the GOOSE network and GOOSE configuration file.
GAlm_BDisc
54
GAlm_CfgUnmatched
SV alarm signals (Device will not be blocked)
The signal is issued with other specific SV alarm signals, and please refer
55 SVAlm_Overall
to the handling suggestion of them.
56 SVAlm_CfgFile Please check SV configuration file.
57 SVAlm_Maint_Unmatched Please check the quality status (q) of the incoming data and the device.
@Bx.Name_n_SVCommLin
58
k.SVAlm_ADisc
@Bx.Name_n_SVCommLin Please check the SV network and the SV configuration file.
59
k.SVAlm_BDisc
60 @Bx.Name_n_SVCommLin

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6 Supervision
k.SVAlm_Data
61 Please check the synchronization clock of the corresponding SV link.
k.SVAlm_SmplSynLoss
@Bx.Name_n_SVCommLin Please check the validity of quality type definition in the corresponding
62
k.SVAlm_InvalidSample SV link.
63 Please check the sending interval of the corresponding SV link.
k.SVAlm_Jitter_Ch
64 Please check the channel delay of the corresponding SV link
k.SVAlm_tdrChgd_Ch
65 Please check the channel delay of the corresponding SV link
k.SVAlm_tdrOvRange_Ch
66 Please check the quality status (q) of the corresponding SV link via MU
k.SVAlm_Maintenance
Where:
@Bx.Name_n_GCommLink is the set value of the label setting of [Bx.Name_n_GCommLink]

(n=00~63)
@Bx.Name_n_SVCommLink is the set value of the label setting of [Bx.Name_n_SVCommLink]

(n=00~03)
6

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7 System Functions
7 System Functions
Table of Contents
7.1 Clock Synchronization .................................................................................... 7-1

7.1.1 Clock Synchronization Mode ................................................................................................ 7-1
7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1
7.1.3 Clock Synchronization Priority ............................................................................................. 7-1
7.1.4 SNTP Setup.......................................................................................................................... 7-1
7.2 State Information ............................................................................................. 7-2

7.2.1 Overview............................................................................................................................... 7-2
7.2.2 Access Method ..................................................................................................................... 7-2
7.3 Event Recording .............................................................................................. 7-3

7.3.1 Overview............................................................................................................................... 7-3
7.3.2 Disturbance Records ............................................................................................................ 7-3
7.3.3 Supervision Events............................................................................................................... 7-4
7.3.4 Binary Events ....................................................................................................................... 7-4
7.3.5 Device Logs .......................................................................................................................... 7-4 7

7.3.6 Control Logs ......................................................................................................................... 7-4
7.3.7 High-frequency Recording ................................................................................................... 7-4
7.3.8 Access Method ..................................................................................................................... 7-5
7.4 Fault Recording ............................................................................................... 7-5

7.4.1 Overview............................................................................................................................... 7-5
7.4.2 Fault Report .......................................................................................................................... 7-6
7.4.3 Fault Waveform .................................................................................................................... 7-6
7.4.4 Access Method ..................................................................................................................... 7-7
7.5 Maintenance State ........................................................................................... 7-7

7.6 Communication Test ....................................................................................... 7-8
7.7 Output Test ....................................................................................................... 7-8
7.8 Target Reset ..................................................................................................... 7-9

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7 System Functions
7.9 Switch Setting Groups .................................................................................... 7-9

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7 System Functions
7.1 Clock Synchronization
7.1.1 Clock Synchronization Mode
The device supports both hardware-based and software-based clock synchronization modes.
1. Hardware-based clock synchronization ([Opt_TimeSyn]=Conventional)
⚫ IRIG-B: IRIG-B via RS-485 differential level, TTL level, BNC or optical fibre interface
⚫ PPS: Pulse per second (PPS) via RS-485 differential level or binary input
⚫ IEEE 1588: Clock message based on IEEE 1588 via Ethernet network
2. Software-based clock synchronization ([Opt_TimeSyn]=SAS)
⚫ SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
⚫ Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol
7.1.2 Clock Synchronization Abnormality
The device provides an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source. But if the setting [Opt_TimeSyn] is set as
"NoTimeSyn" and no clock synchronization signal is inputted, the device will not issue the alarm
signal.
7.1.3 Clock Synchronization Priority
The device provides a priority-based adaptive clock synchronization scheme, which means that it 7
can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of clock synchronization sources.
Clock synchronization Input signal The Highest priority

Software-based
SNTP + Clock message SNTP
([Opt_TimeSyn]=SAS)
Hardware-based IRIG-B + PPS + IEEE 1588 IRIG-B
([Opt_TimeSyn]=Conventional,
PPS + IEEE 1588 PPS
[En_ConvModeSNTP]=Disabled)
Hardware-based + SNTP IRIG-B + PPS + IEEE 1588 + SNTP IRIG-B
([Opt_TimeSyn]=Conventional, PPS + IEEE 1588 + SNTP PPS
[En_ConvModeSNTP]=Enabled) IEEE 1588 + SNTP IEEE 1588
7.1.4 SNTP Setup
When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.
[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing

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7 System Functions
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the

device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP
synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.
7.2 State Information
7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary
measurement value, secondary measurement value, metering value and so on) and status
7 quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the
device is healthy.
7.2.2 Access Method
7.2.2.1 Access by Local HMI (Human Machine Interface)
These state information can be gained via local HMI. The menu path is:
1. Analog quantities
⚫ MainMenu  "Measurements"  "Primary Values"
⚫ MainMenu  "Measurements"  "Secondary Values"
⚫ MainMenu  "Measurements"  "Function Values"  "Synchronism Check"
⚫ MainMenu  "Measurements"  "Energy Metering"
⚫ MainMenu  "Measurements"  "Power Quality"
⚫ MainMenu  "Measurements"  "PMU Values"

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7 System Functions
⚫ MainMenu  "Measurements"  "UserDef Values"  "UserDef Values1/2"
2. Status quantities
⚫ MainMenu  "Status"  "Inputs"
⚫ MainMenu  "Status"  "Outputs"
⚫ MainMenu  "Status"  "PMU Status"
⚫ MainMenu  "Status"  "Superv Status"
⚫ MainMenu  "Status"  "Logic Links Status"
⚫ MainMenu  "Status"  "Running Status"
⚫ MainMenu  "Status"  "UserDef Status"  "UserDef Status1/2"
7.2.2.2 Access by Virtual HMI
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
7.2.2.3 Access by Communication Client
Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.
7.2.2.4 Access by Printer
The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:
MainMenu  "Print"  "Device Status"

7
7.3 Event Recording
7.3.1 Overview
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped
binary events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024
time-stamped device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.
7.3.2 Disturbance Records
When any protection element operates or drops out, such as fault detector, distance protection
etc., they will be logged in event records. Disturbance records include signal name, its value
before and after changing, and the time precision is up to 1ms.

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7 System Functions
7.3.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records. Supervision events include signal name, its value before and after changing, and the
time precision is up to 1ms.
7.3.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records. Binary events include signal name, its value
7.3.5 Device Logs
If an operator executes some operations on the device, such as reboot protective device, modify
setting, etc., they will be logged in event records. Device logs include signal name, its value
7.3.6 Control Logs
When an operator executes a control command via local LCD, PCS-Studio or communication
client, it will be logged in control logs. Control logs include time stamp, controlled object, control
origination, control position, operation condition ,interlocking condition, control command and
operation result.
7.3.7 High-frequency Recording

The high-frequency recording is available by PCS-Studio. By switching the option "Disabled" or
"Enabled" to enable or disable the function in the following path through the PCS-Studio
7 configuration tool: Project Node → Device Node → Device Setup → Global Config → System
Config.
When high-frequency recording is enabled, a high-frequency waveforms record (9.6kHz sampling)

can also be gained besides the normal disturbance waveforms record (1.2kHz sampling). The
difference between high-frequency waveforms records and normal disturbance waveforms
records is only the sampling rate. This kind of high-resolution records is convenient to perform
post-fault system and device operation analysis.

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7 System Functions
7.3.8 Access Method

7.3.8.1 Access by Local HMI
The device provides corresponding menus to view event recorders. The menu path is:
MainMenu  "Test"  "Disturb Records"
MainMenu  "Records"  "Superv Events"
MainMenu  "Records"  "IO Events"
MainMenu  "Records"  "Device Logs"
MainMenu  "Records"  "Control Logs"
MainMenu  "Records"  "HighFreqRecords"
as local LCD.
Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3).
The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Superv Events"

7
MainMenu  "Print"  "IO Events"
7.4 Fault Recording
7.4.1 Overview
Fault recorder can be used to have a better understanding of the behaviour of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.
The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal “BI_TrigDFR”.
The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most
recent recordings are always stored safely. The maximum number of recordings is 64.

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7 System Functions
7.4.2 Fault Report

For each fault report, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The date and time are recorded when a system fault is detected. The time resolution is 1ms.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.
4. Fault information
Including faulty phase, fault location and protection elements
7.4.3 Fault Waveform
A fault waveform contains all analog and digital quantities related to protection such as currents,
voltages, differential current, alarm elements, binary inputs and etc.
The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording
parameter, these components can be individually set. The pre-trigger waveform recorded duration
is configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
7 recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].
4. [MaxRecDur_PostTrigDFR]
1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]
Trigger point
Total recording time
1. Pre-trigger recording time
Use the setting [RecDur_PreTrigDFR] to set this time.
2. Pickup recording time
The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).
3. Post-fault recording time

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7 System Functions
The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.
4. Maximal post-trigger recording time
Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the
post-trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].
7.4.4 Access Method
7.4.4.1 Access by Local HMI
The device provides corresponding menus to check fault recording. The menu path is:
MainMenu  "Records"  "Disturb Records"
as local LCD.
Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3).
The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Disturb Records"

7
7.5 Maintenance State
The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized,
which is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and
binary outputs, maintenance state has no influence on protection logics. For binary inputs and
binary outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.
For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in
the application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality

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7 System Functions
attribute set as "1". For DNP3 and ModBus protocol, they are not affected.
7.6 Communication Test
The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During
communication test, protection functions are not affected, the signals generated by
communication test are recorded in relevant reports, and event recording and fault recording will
not stop recording disturbance information. The alarm signal "Alm_CommTest" will be issued to
indicate the operator when activating Test Mode and exiting Test Mode.
Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:
⚫ Events Simulation
Main Menu  "Test"  "Device Test"  "Disturb Events"
Main Menu  "Test"  "Device Test"  "Superv Events"
Main Menu  "Test"  "Device Test"  "IO Events"
⚫ Forced Measurements
Main Menu  "Test"  "Device Test"  "Measurements"
Forced measurement ONLY affects the values modified and transmitted to

7 station control or control center. Primary circuit, secondary circuit and
device local logic will not be influenced. Forced value will remain during the
test until the exit of this menu.
If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7.7 Output Test

The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.
Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:
⚫ Contacts Outputs

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7 System Functions
Main Menu  "Test"  "Device Test"  "Contact Outputs"
⚫ GOOSE Outputs
Main Menu  "Test"  "Device Test"  "GOOSE Outputs"
Dismantle the wiring connection if any influence on relevant primary

equipment is undesired. The output test will cause operation of relay
contacts through secondary circuit and GOOSE link.
7.8 Target Reset
The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.
1. Reset via local HMI
⚫ Access menu path: MainMenu  "Local Cmd"  "Reset Target"
⚫ Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface
⚫ Press the command pushbutton " TARGET RESET" on operation panel of the device
2. Reset via virtual HMI
Access menu path: MainMenu  "Local Cmd"  "Reset Target"

7
3. Reset via binary input
Energize the binary input "BI_RstTarg"
4. Reset via IEC61870-5-103
Use ASDU20, INF19 of IEC61870-5-103 protocol
5. Reset via remote control
Use standard remote service of corresponding protocol
7.9 Switch Setting Groups
For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 20 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.
The device will be temporarily blocked during switching setting groups. During temporary device

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7 System Functions
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.
1. Switch via local HMI
⚫ Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

change the value of the setting [Active_Grp]
⚫ Press the command pushbutton “MENU” under main interface (password is required)
2. Switch via virtual HMI
Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

modify the setting [Active_Grp]
3. Switch via communication client
The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.
⚫ Use "General Service" of IEC61870-5-103 protocol to modify the setting [Active_Grp]
⚫ Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.
4. Switch via binary signals
The device also provides an available function by configuring associated binary signals via
PCS-Studio to switch setting group, which can be external binary inputs or internal logic
signals. By default, no binary signals are configured, so the function is invalid. (The specificed
confiuration method can refer to the application manual).
Each input signal is coded with a sequence number that corresponds to a setting group.
7 When the associated input signal changes, the device scans all input signals and selects the
input with the smallest sequence number as the valid input. The device switches to the
setting range corresponding to the input signal. The device can switch up to 20 setting
groups.

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8 Hardware
8 Hardware
Table of Contents
8.1 Overview........................................................................................................... 8-1

8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirement ............................................................................................... 8-7
8.4 Plug-in Module Description ............................................................................ 8-9
8.4.1 Human-machine Interface Module (NR6855/NR6856) ........................................................ 8-9
8.4.2 Power Supply Module (NR6305/NR6310/NR6311) ............................................................. 8-9
8.4.3 CPU Module (NR6106) ...................................................................................................... 8-12
8.4.4 Analog Input Module (NR6641) .......................................................................................... 8-16
8.4.5 Binary Input Module (NR6601/NR6604/NR6610/NR6611) ................................................ 8-20
8.4.6 Binary Output Module (NR6651/NR6652/NR6660/NR6663)............................................. 8-28
8.4.7 DC Analogue Output Module (NR6632) ............................................................................. 8-33
8.4.8 Binary Input/Output Module (NR6661)............................................................................... 8-35
8.4.9 Arc Flash Module (NR6621A) ............................................................................................ 8-36
List of Figures
Figure 8.1-1 Hardware diagram.................................................................................................. 8-1
Figure 8.1-2 Front view of this device.......................................................................................... 8-3 8

Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules) ............................ 8-3
Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules) ........................... 8-4
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules) ......................... 8-4
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules)...................................................... 8-5
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules)........................ 8-6
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules) .................................................... 8-7
Figure 8.4-1 View of power supply module ............................................................................... 8-10
Figure 8.4-2 View of CPU module .............................................................................................. 8-14
Figure 8.4-3 Connection of communication terminal ............................................................ 8-16

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8 Hardware
Figure 8.4-4 Jumpers of printer/RS-485 port .......................................................................... 8-16
Figure 8.4-5 Schematic diagram of CT circuit automatically closed ................................... 8-17
Figure 8.4-6 Terminal definition of analog input module ...................................................... 8-18
Figure 8.4-7 Current connection examples ............................................................................ 8-19
Figure 8.4-8 Voltage connection examples............................................................................. 8-20
Figure 8.4-9 Voltage dependence for binary inputs............................................................... 8-21
Figure 8.4-10 View of binary input module (NR6601A) ......................................................... 8-22
Figure 8.4-11 View of binary input module (NR6604A).......................................................... 8-23
Figure 8.4-12 View of binary input module (NR6610A) ......................................................... 8-25
Figure 8.4-13 View of binary input module (NR6611A) .......................................................... 8-27
Figure 8.4-14 View of binary output module NR6651A ......................................................... 8-29
Figure 8.4-15 View of binary output module NR6651B ......................................................... 8-30
Figure 8.4-16 View of binary output module NR6652A ......................................................... 8-31
Figure 8.4-17 View of binary output module (NR6660A) ....................................................... 8-32
Figure 8.4-18 View of binary output module (NR6663A) ....................................................... 8-33
Figure 8.4-19 View of DC analogue output module (NR6632A) ............................................ 8-34
Figure 8.4-20 View of binary input/output module (NR6661A) ............................................. 8-35
Figure 8.4-21 View of arc flash module ..................................................................................... 8-37
List of Tables
8 Table 8.4-1 Terminal definition of power supply module (ring-ferrule-terminal) ..................... 8-10
Table 8.4-2 Terminal definition of power supply module (pin-ferrule-terminal)....................... 8-11
Table 8.4-3 Configuration and terminal definition of CPU module........................................... 8-14
Table 8.4-4 Terminal definition and description of binary input module (NR6601A)............... 8-22
Table 8.4-5 Terminal definition and description of binary input module (NR6604A)............... 8-24
Table 8.4-6 Terminal definition and description of binary input module (NR6610A) .............. 8-25
Table 8.4-7 Terminal definition and description of binary input module (NR6611A) .............. 8-27
Table 8.4-8 Terminal definition and description of NR6661A ................................................... 8-35
Table 8.4-9 Technical data of arc flash module ......................................................................... 8-36

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8 Hardware
8.1 Overview
The modular design of this device allows this device to be easily upgraded or repaired by a
qualified service person. The faceplate is hinged to allow easy access to the configurable
modules, and back-plugging structure design makes it easy to repair or replace any module.
This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 8.1-1 for the hardware diagram.
External
Binary Input
Conventional CT/VT A/D

Output
ARM1
Relay
A/D
Pickup
ECVT Relay
ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45
Keypad
PRINT
Figure 8.1-1 Hardware diagram

8
The working process of the device is shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signals are
sent to the device without small signal and A/D conversion). The ARM1 core carries out fault
detector, protection logic calculation, tripping output, and the ARM2 core performs SOE
(sequence of event) record, waveform recording, printing, communication between the device and
SAS and communication between HMI and CPU. When the fault detector detects a fault and picks
up, the positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS S series based on microcomputer
are classified into standard and optional modules.

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Table 8.1-1 Module configuration of this device
Module ID Module description Remark

NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/6310/NR6311 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
NR6641 Analog input module (AI module) Mandatory
NR6601/NR6604/NR6610/NR6611 Binary input module (BI module) Mandatory
NR6651/NR6652/NR6660/NR6663 Binary output module (BO module) Mandatory
NR6632 DC analogue output module (DC AO module) Optional
NR6661 Binary Input/output module (BI/BO module) Mandatory
NR6621 Arc flash module (ARC module) Optional
⚫ HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
⚫ PWR module converts AC100V/110V/115V/120V/127V/220V/230V/240V/250V or

DC24V/30V/48V/60V/110V/125V/220V/250V into various DC voltage levels for modules of
the device.
⚫ CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.
⚫ AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
⚫ BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V/48V/110V/125V/220V/250V (configurable).
⚫ BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
8 ⚫ DC AO module provides DC analogue output channels in the range of 0~20mA or 0~10Vdc.
⚫ BI/BO module not only provides binary inputs via opto-couplers with rating voltage among
AC110V/220V or DC24V~250V (configurable), but also provides output contacts for tripping,
and signal output contact for annunciation signal, remote signal, fault and disturbance signal,
operation abnormal signal, etc.
⚫ ARC module provides arc flash sampling channels with channel self-supervision function.
Following figures show front and rear views of this device respectively.

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Figure 8.1-2 Front view of this device
Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules)

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Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules)
8.2 Typical Wiring
B01 B02 & B03 B04 B05 B06 P1 B01 B02 & B03 B04 P1
NR6106AA NR6641-63I02U Option Option Option NR6310A NR6106AA NR6641-63I02U Option NR6310A
BI_01+ 01 BI_01+ 01
01 Ia Ian 02 01 Ia Ian 02
BI_01- 02 BI_01- 02
03 Ib Ibn 04 BI_02+ 03 03 Ib Ibn 04 BI_02+ 03
BI_02- 04 BI_02- 04
NET 05 Ic Icn 06 BI_COM 05 NET 05 Ic Icn 06 BI_COM 05
BI_03 06 BI_03 06
LC 07 3I0 3I0n 08 LC 07 3I0 3I0n 08
BI_04 07 BI_04 07
LC BI_05 08 LC BI_05 08
09 3I02 3I02n 10 09 3I02 3I02n 10
BI_06 09 BI_06 09
11 Isef Isefn 12 BI_07 10 11 Isef Isefn 12 BI_07 10
BI_08 11 BI_08 11
13 14 BI_09 12 13 14 BI_09 12
13 13
15 3U0 3U0n 16 BO_01 15 3U0 3U0n 16 BO_01
8 17 Usyn Usynn 18 BO_02

14
15
16
17 Usyn Usynn 18 BO_02
14
15
16
01 1A 19 Ua Uan 20 17 01 1A 19 Ua Uan 20 17
BO_03 BO_03
02 1B 18 02 1B 18
03 SG ND 21 Ub Ubn 22 19 03 SGND 21 Ub Ubn 22 19
BO_04 BO_04
04 2A 20 04 2A 20
23 Uc Ucn 24 23 Uc Ucn 24
05 2B 21 05 2B 21
06 SG ND BO_05 06 SGND
BO_05
22 22
07 SYN+ 07 SYN+
23 23
08 SYN- BO_Fail 08 SYN- BO_Fail
24 24
09 SGND 09 SGND
PWR+ 25 PWR+ 25
10 SYN-TTL 10 SYN-TTL
PWR- 26 PWR- 26
CONSOLE Ground CONSOLE Ground
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

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Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 Ia
0202
SGND 0103
0203
485-2A 0104 Ib
COM
0204
485-2B 0105
0205
SGND 0106
Ic
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 3I0
0208
TTL 0110
0209
3I02
Multiplex RJ45 0210
0211
AI plug-in module
Isef
P101 + BI_01 0212
0213
P102 -
0214
- P103 + BI_02
0215
P104 - 3U0
0216
P106 + BI_03 0217
Usyn
0218
P107 + BI_04 0219
Ua
0220
PWR plug-in module
…
0221
P112 + BI_09 Ub
0222
P105 0223
P113 Uc
BO_01 0224
P114
P115
P116 BO_02
…
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
External DC power Power
supply
PWR- P126 Supply
8
Grounding Bus
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules)

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B01 B02 & B03 B04 B05 B06 P1 B01 B02 & B03 B04 P1
NR6106AA NR6641-63I02U Option Option Option NR6305A NR6106AA NR6641-63I02U Option NR6305A
01 Ia Ian 02 01 BI_01+ BI_01- 02 01 Ia Ian 02 01 BI_01+ BI_01- 02
03 Ib Ibn 04 03 BI_02+ BI_02- 04 03 Ib Ibn 04 03 BI_02+ BI_02- 04
NET 05 Ic Icn 06 05 BI_COM BI_03 06 NET 05 Ic Icn 06 05 BI_COM BI_03 06
LC 07 3I0 3I0n 08 07 BI_04 BI_05 08 LC 07 3I0 3I0n 08 07 BI_04 BI_05 08
LC LC
09 3I02 3I02n 10 09 BI_06 BI_07 10 09 3I02 3I02n 10 09 BI_06 BI_07 10
11 Isef Isefn 12 11 BI_08 BI_09 12 11 Isef Isefn 12 11 BI_08 BI_09 12
13 14 13 BO_01 14 13 14 13 BO_01 14
15 3U0 3U0n 16 15 BO_02 16 15 3U0 3U0n 16 15 BO_02 16
17 Usyn Usynn 18 17 BO_03 18 17 Usyn Usynn 18 17 BO_03 18
01 1A 19 Ua Uan 20 19 BO_04 20 01 1A 19 Ua Uan 20 19 BO_04 20

02 1B 02 1B
03 SGND
21 Ub Ubn 22 21 BO_05 22 03 SGND 21 Ub Ubn 22 21 BO_05 22
04 2A 04 2A
23 Uc Ucn 24 23 BO_Fail 24 23 Uc Ucn 24 23 BO_Fail 24
05 2B 05 2B
06 SGND 06 SGND
25 PWR+ PWR- 26 25 PWR+ PWR- 26
07 SYN+ 07 SYN+
08 SYN- 08 SYN-
09 SGND 09 SGND
10 SYN-TTL 10 SYN-TTL
CONSOLE CONSOLE
Ground Ground
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

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Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 Ia
0202
SGND 0103
0203
485-2A 0104 Ib
COM
0204
485-2B 0105
0205
SGND 0106
Ic
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 3I0
0208
TTL 0110
0209
3I02
Multiplex RJ45 0210
0211
AI plug-in module
Isef
P101 + BI_01 0212
0213
P102 -
0214
- P103 + BI_02
0215
P104 - 3U0
0216
P106 + BI_03 0217
Usyn
0218
P107 + BI_04 0219
Ua
0220
PWR plug-in module
…
0221
P112 + BI_09 Ub
0222
P105 0223
P113 Uc
BO_01 0224
P114
P115
P116 BO_02
…
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
External DC power Power
supply
PWR- P126 Supply
8
Grounding Bus
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules)
8.3 CT Requirement
⚫ CT Requirement
Generally, CT saturation will cause a certain time delay to the operation of a protection, which is
obvious for inverse-time overcurrent protection. When the maximum fault current is far greater
than the current seting, the operating time delay generated at this time can be ignored. If the
maximum fault current is slightly greater than the current setting, the operating time delay
generated at this time is equivalent to the primary time constant of the system. When there is an
upper-lower coordination relationship, the effect of this time delay needs to be considered.

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Generally, the requirements for CT are as follows:
𝐸𝑠𝑙′ < 𝐸𝐴𝐿𝐹
In where:
𝐸𝑠𝑙′ is the secondary electromotive force required for the maximum prospective fault current
According to the operating characteristics, the phase overcurrent protection and earth fault
overcurrent protection are divided into the following two situations:
For instantaneous overcurrent protection, definite-time overcurrent protection and earth fault
overcurrent protection:
𝐸𝑠𝑙′ = 𝐼𝑝𝑐𝑓 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏′ )/𝐼𝑝𝑟
For inverse-time overcurrent protection and earth fault overcurrent protection:
𝐸𝑠𝑙′ = 20 × 𝐼𝑠𝑒𝑡 × (𝑅𝑐𝑡 + 𝑅𝑏′ )
𝐼𝑠𝑒𝑡 is the the inverse-time reference current setting or 1.1 times of the maximum load current.
For the directional overcurrent protection and earth fault overcurrent protection, try to choose the
low remanence or no remanence CT.
The parameters are defined as follows:
𝐼𝑝𝑐𝑓 Maximum primary fault current (amps)
𝐼𝑝𝑟 Rated primary current (amps)
Actual secondary load resistance
𝑅𝑏′ = 𝑅𝑟 + 2 × 𝑅𝐿
𝑅𝑏′
𝑅𝑟 : Protection device phase current input impedance, it takes 0.01ohm
𝑅𝐿 : The resistance from protection device to CT single wire

8 Inverse-time reference current setting or 1.1 times of the maximum load current
𝐼𝑠𝑒𝑡
(amps)
⚫ Example
The parameters are as follows:
5P30, 𝐼𝑝𝑟 =2000A, 𝐼𝑠𝑟 =5A,⁡𝑅𝑐𝑡 = 1.0ohm, 𝑆𝑟 =60VA,⁡𝐼𝑝𝑐𝑓 =40000A,⁡𝑅𝐿 =0.5ohm,⁡𝑅𝑟 =0.01ohm, the
primary time constant of the system is 80ms, calculate that whether the CT can meet the
requirements of definite-time overcurrent protection.
𝐸𝐴𝐿𝐹 = 𝐴𝐿𝐹 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑍𝑏 ) = 30 ∗ 5 ∗ (1.0 + 60/(5 ∗ 5)) = 510V
𝐸𝑠𝑙′ = 𝐼𝑝𝑐𝑓 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏′ )/𝐼𝑝𝑟 = 40000 ∗ 5 ∗ (1.0 + (0.01 + 2 ∗ 0.5))/2000 = 201V
𝐸𝑠𝑙′ < 𝐸𝐴𝐿𝐹 , it can meet the requirements of definite-time overcurrent protection.

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8.4 Plug-in Module Description

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO module, DC analog output module and arc flash module. Terminal definitions and
application of each plug-in module are introduced as follows.
8.4.1 Human-machine Interface Module (NR6855/NR6856)

The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the
user.
8.4.2 Power Supply Module (NR6305/NR6310/NR6311)

The power supply module is a DC/DC converter with electrical insulation between input and
output. It has an input voltage range as described in Chapter 2 Technical Data. The standardized
output voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously
monitored.
The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.

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Figure 8.4-1 View of power supply module
Four types of power supply modules are provided: NR6305A, NR6305B, NR6310A and NR6311A.
The NR6305B is same as the NR6305A except that the NR6305B can support at least 500ms
power supply interruption. The terminal definition of NR6311A is same as that of NR6310A except
that the input voltage of NR6311A is 18~72Vdc.
⚫ NR6305A & NR6305B
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
8 binary output. A 26-pin connector is fixed on the power supply module. The terminal definition of
the connector is described as below.
Table 8.4-1 Terminal definition of power supply module (ring-ferrule-terminal)
Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_03 to BI_09
06 BI_03 The No.3 programmable binary input

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13
BO_01 The No.1 programmable binary output
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
⚫ NR6310A & NR6311A
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 22-pin connector and a 4-pin connector are fixed on the power supply module.
The terminal definition of the connector is described as below.
Table 8.4-2 Terminal definition of power supply module (pin-ferrule-terminal)

01 BI_01+
02 BI_01-
03 BI_02+
8
04 BI_02-
05 BI_COM The common negative connection of the BI_03 to BI_09
22-pin
13
14
15
16

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8 Hardware
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
The standard rated voltage of the PWR module is self-adaptive to

18~72Vdc (NR6311), 88~300Vdc (NR6310) or 88~275Vac (NR6305). For
a non-standard rated voltage power supply module please specify when
place order, and check whether the rated voltage of power supply module
is the same as the voltage of power source before the device being put into
service.
The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent

EMI, so effective grounding must be ensured before the device is put into
service.
8.4.3 CPU Module (NR6106)

8 The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provides
accurate current time for this device.
The main functional details of the CPU module are listed as below:
⚫ Protection calculation and logical judgment function
The CPU module can calculate protective elements (such as overcurrent element) on the
basis of the analog sampled values (voltages and currents) and binary inputs, then it does
logical judgment function and decides whether the device needs to trip or close.

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⚫ Communication function
The CPU module can effectively manage all communication procedures, and reliably send
out some useful information through its various communication interfaces. These interfaces
are used to communicate with a SAS or a RTU. It also can communicate with the human
machine interface module. If an event occurs (such as SOE, protective tripping event etc.),
this module will send out the relevant event information through these interfaces, and make it
be easily observed by the user.
⚫ Support of Protocols
MMS, GOOSE or SV independent networking
MMS, GOOSE and SV hybrid networking
⚫ Auxiliary calculation
Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.
⚫ Human-machine interface function
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.
⚫ Time synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B
signal. Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on
the IRIG-B signal, this module can synchronize local clock with the standard clock.

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8 Hardware
Figure 8.4-2 View of CPU module
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.

8 The configuration and terminal definition of the CPU modules are listed in following table.
Table 8.4-3 Configuration and terminal definition of CPU module
Sampling Terminal
Module ID Interface Usage Physical Layer
channel No.
2 RJ45
Ethernet
- - Ethernet communication Twisted pair wire
2 SFP
Ethernet
NR6106AA 16 01 A
RS-485 02 B To SCADA Twisted pair wire
03 SGND
04 A
RS-485 To SCADA or printer Twisted pair wire
05 B

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06 SGND
07 SYN+
RS-485 08 SYN- Cable
To clock synchronization
09 SGND
TTL 10 TTL Cable
1 RJ45
- - For debugging Twisted pair wire
Ethernet
4 SFP
Ethernet
1 ST To clock synchronization Optical fiber
NR6106AH 16 - -
connector (PPS/IRIG-B) (multi-mode)
1 RJ45
Ethernet
2 RJ45
Ethernet
2 SFP
Ethernet
01 A
RS-485 02 B To SCADA Twisted pair wire
NR6106AP 16 03 SGND
04 A
RS-485 05 B To SCADA or printer Twisted pair wire
06 SGND
1 BNC - - To clock synchronization
1 RJ45
Ethernet
The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. 8

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Twisted pair wire

A
COM
B
SGND
cable with single point earthing

To the screen of other coaxial
Twisted pair wire
SYN+
Clock SYN
SYN-
SGND
Cable
RTS
PRINT
TXD
SGND
Figure 8.4-3 Connection of communication terminal
Figure 8.4-4 Jumpers of printer/RS-485 port

8
The 2nd RS-485 port also can be configured as a printer port through the
jumpers “J10” and “J11”.
Jumper RS-485 Printer

J10 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
J11 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
8.4.4 Analog Input Module (NR6641)

The analog input module is applicable for power plant or substation with conventional VT and CT,
and it can transform high AC input values to relevant low AC output value, which are suited to the
analog inputs of the CPU module. The transformers are used both to step-down the currents and
voltages to levels appropriate to the device’s electronic circuitry and to provide effective isolation

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8 Hardware
between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analog AC input signal.
For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.
Plug
Socket
In
Out
plug is not put in the socket
In
Out
Put the plug in the socket
Figure 8.4-5 Schematic diagram of CT circuit automatically closed
There are several types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current 8
converter is 40In.
⚫ NR6641-4I4U: 4CT+4VT
⚫ NR6641-6I5U: 6CT+5VT
⚫ NR6641-4I7U: 4CT+7VT
⚫ NR6641-8I4U: 8CT+4VT
If synchronism check voltage selection function is needed, the NR6641-4I7U module must be
selected. This AI module supports two voltage selection mode:
Three-phase voltage selection: The voltage selection function can be used to switch between
Ua1/Ub1/Uc1 and Ua2/Ub2/Uc2.
Single-phase voltage selection: The voltage selection function can be used to switch between

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8 Hardware
UL1 and UL2.
If two groups of phase overcurrent protection are configured, the NR6641-8I4U module must
be selected.
The terminal definition of the analog input module is shown as below.
NR6641-6I5U NR6641-4I4U NR6641-4I7U NR6641-8I4U

01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02
03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04
05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06
07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08
09 I5 I5n 10 09 10 09 10 09 I5 I5n 10
11 Isef Isefn 12 11 12 11 U1 U1n 12 11 I6 I6n 12
13 14 13 14 13 U2 U2n 14 13 I7 I7n 14
15 U1 U1n 16 15 16 15 U3 U3n 16 15 I8 I8n 16
17 U2 U2n 18 17 U1 U1n 18 17 U4 U4n 18 17 U1 U1n 18
19 U3 U3n 20 19 U2 U2n 20 19 U5 U5n 20 19 U2 U2n 20
21 U4 U4n 22 21 U3 U3n 22 21 U6 U6n 22 21 U3 U3n 22
23 U5 U5n 24 23 U4 U4n 24 23 U7 U7n 24 23 U4 U4n 24
Figure 8.4-6 Terminal definition of analog input module
NEVER allow the current transformer (CT) secondary circuit connected to

this device to be opened while the primary system is energized. The
8 opened CT secondary circuit will produce a dangerously high voltage. If
this safety precaution is disregarded, personal death, severe personal
injury or considerable equipment damage will occur.
Each analog input channel can be configured according to practical

application through PCS-Studio.
Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.
1. Current connections examples

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8 Hardware
A B C A B C
Ia Ia
Ian Ian
Ib Ib
Ibn Ibn
Ic Ic
Icn Icn
I01
I01n I01
(1) I01n
A B C (3)
Ia
Ian
Ib I0s
Ibn I0sn
Ic
(4)
Icn
I01 I02
I01n I02n
(2) (5)
Figure 8.4-7 Current connection examples
Where:
(1) Current connections to three current transformers with a star-point connection for ground
current (zero-sequence current or residual current).
(2) Current connections to three current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer).
(3) Current connections to two current transformers with a separate ground current 8
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.
(4) Current connection to a core balance neutral current transformer for sensitive ground
fault detection, only for ungrounded or compensated networks.
(5) Current connection to a separate ground current transformer (summation current

transformer or core balance current transformer) for the No.2 zero-sequence current
input of this relay.
2. Voltage connections examples

Date: 2021-08-01
8 Hardware
A B C A B C
Ux
52 52 52 Ux 52 52 52
Uxn
Uxn
Ua Ua
Ub Ub
Uc Uc
Un Un
U0 U0
U0n U0n
(1) (2)
Figure 8.4-8 Voltage connection examples
Where:
(1) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase voltage (for synchronism check).
(2) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase-to-phase voltage (for synchronism check).
8.4.5 Binary Input Module (NR6601/NR6604/NR6610/NR6611)

The binary input module contains some binary inputs which are used to monitor the contact
positions of the corresponding bay, and all the binary inputs are configurable through PCS-Studio
according to practical application.
There are four kinds of BI modules available, NR6601A, NR6604A, NR6610A and NR6611A. The
binary input module can respectively provide 25, 13, 32 or 14 binary inputs.
8
The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc,
125V, 220V, 110Vac or 220Vac (@50Hz), which must be specified when
placed order. It is necessary to check whether the rated voltage of binary
input module complies with site DC power supply rating before put this
device in service.

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8 Hardware
Voltage
300
157.5
138.6
125
110
78.75
69.3
62.5
55 Operation
30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V
Figure 8.4-9 Voltage dependence for binary inputs
⚫ NR6601A
Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and drop-out voltages of the binary
inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from 8
50%Un to 80%Un.

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8 Hardware
01 BI_01 BI_02 02
03 BI_03 BI_04 04
05 BI_05 BI_06 06
07 BI_07 BI_08 08
09 BI_09 BI_10 10
11 BI_11 BI_12 12
13 BI_13 BI_14 14
15 BI_15 BI_16 16
17 BI_17 BI_18 18
19 BI_19 BI_20 20
21 BI_21 BI_22 22
23 BI_23 BI_24 24
25 BI_25 BI_COM 26
Figure 8.4-10 View of binary input module (NR6601A)
Table 8.4-4 Terminal definition and description of binary input module (NR6601A)

8 04 BI_04 The No.4 programmable binary input

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8 Hardware

26 BI_COM The common negative connection of the BI_01 to BI_25.
⚫ NR6604A
Each BI module is with a 26-pin connector for 13 binary inputs, each binary input has independent
negative power input and is configurable. The pickup voltages and drop-out voltages of the binary
inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from
50%Un to 80%Un.
01 BI_01 Opto01- 02
03 BI_02 Opto02- 04
05 BI_03 Opto03- 06
07 BI_04 Opto04- 08
09 BI_05 Opto05- 10
11 BI_06 Opto06- 12
13 BI_07 Opto07- 14
15 BI_08 Opto08- 16
17 BI_09 Opto09- 18 8
19 BI_10 Opto10- 20
21 BI_11 Opto11- 22
23 BI_12 Opto12- 24
25 BI_13 Opto13- 26

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8 Hardware

01 BI_01 Configurable binary input 1
02 Opto01- Negative pole of power supply of configurable binary input 1
8 ⚫ NR6610A
Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and drop-out voltages of the
binary inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from
50%Un to 80%Un.

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8 Hardware
01 BI_01 19 BI_17
02 BI_02 20 BI_18
03 BI_03 21 BI_19
04 BI_04 22 BI_20
05 BI_05 23 BI_21
06 BI_06 24 BI_22
07 BI_07 25 BI_23
08 BI_08 26 BI_24
09 BI_09 27 BI_25
10 BI_10 28 BI_26
11 BI_11 29 BI_27
12 BI_12 30 BI_28
13 BI_13 31 BI_29
14 BI_14 32 BI_30
15 BI_15 33 BI_31
16 BI_16 34 BI_32
17 BI_COM 35 BI_COM
18 BI_COM 36 BI_COM
Pin Pin No. Symbol Description

8
18-pin

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8 Hardware
17
BI_COM The common negative connection of the BI_01 to BI_16.
18
18-pin
35
BI_COM The common negative connection of the BI_17 to BI_32.
36
⚫ NR6611A
Each BI module is with two 18-pin connectors for 14 binary inputs, each binary input has
independent negative power input and is configurable. The pickup voltages and drop-out voltages
of the binary inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range
is from 50%Un to 80%Un.

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8 Hardware
01 19
02 20
03 BI_01 21 BI_08
04 Opto01- 22 Opto08-
05 BI_02 23 BI_09
06 Opto02- 24 Opto09-
07 BI_03 25 BI_10
08 Opto03- 26 Opto10-
09 BI_04 27 BI_11
10 Opto04- 28 Opto11-
11 BI_05 29 BI_12
12 Opto05- 30 Opto12-
13 BI_06 31 BI_13
14 Opto06- 32 Opto13-
15 BI_07 33 BI_14
16 Opto07- 34 Opto14-
17 35
18 36

01 Blank -
02 Blank -
8
18-pin

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8 Hardware
17 Blank -
18 Blank -
19 Blank -
20 Blank -
18-pin
35 Blank -
36 Blank -
8.4.6 Binary Output Module (NR6651/NR6652/NR6660/NR6663)

The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal
outputs. It can receive tripping commands or closing commands from the CPU module, and then
executes these commands. It also can output some alarm signals from the CPU module.
The device can provide five types of binary output modules: NR6651A, NR6651B, NR6652A,
NR6660A and NR6663A.
8 ⚫ NR6651A
The NR6651A provides 13 normal open contacts (NOC).
A 26-pin connector is fixed on the binary input module.
The terminal definition of the connector is shown as below.

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8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-14 View of binary output module NR6651A
⚫ NR6651B
The NR6651B provides 11 normal open contacts (NOC, the first 11 contacts) and 2 normal close
contacts (NCC, the last 2 contacts).
The terminal definition of the connector is shown in as below.

8

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8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-15 View of binary output module NR6651B
⚫ NR6652A
The NR6652A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).
8 The terminal definition of the connector is shown in as below.

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8 Hardware
BO_01 01 02
03 04
BO_02 05 06
07 08
BO_03 09 10
11 12
BO_04 13 14
15 16
17 18
BO_05 19 20
BO_06 21 22
BO_07 23 24
BO_08 25 26
Figure 8.4-16 View of binary output module NR6652A
⚫ NR6660A
The NR6660A provides 17 normally open contacts (NOC, the first 17 contacts) and 2 normally
close contacts (NCC, the 16th and the 17th contacts).
Two 18-pin connectors are fixed on the binary input module.
The terminal definition of the connector is shown in Figure 8.4-17.

8

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8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
BO_14 27 28
BO_15 29 30
BO_16 32
31
BO_16 33
BO_17 35
34
BO_17 36
Figure 8.4-17 View of binary output module (NR6660A)
⚫ NR6663A
The NR6663A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).
Two 18-pin connectors are fixed on the binary input module.
8 The terminal definition of the connector is shown as below.

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8 Hardware
01 02
03 04
BO_01
Heavy-capacity tripping contact

05 06
07 08
BO_02
09 10
11 12
BO_03
13 14
15 16
BO_04
17 18
19 20
21 22
General tripping/signaling contact

BO_05
23 24
25 26
BO_06
27 28
29 30
BO_07
31 32
33 34
BO_08
35 36
Figure 8.4-18 View of binary output module (NR6663A)
Each binary output can be set as a specified tripping output contact or a

signal output contact through PCS-Studio according to practical
application.
8.4.7 DC Analogue Output Module (NR6632)

8
The DC analogue output module can provide 0~20mA or 0~10V output channels.
The NR6632A provides 4 channels of outputs. All channels can be set as 4~20mA, 0~10V,
0~20mA or 0~5V DC analogue outputs respectively through the related settings
[DCAO**.Opt_Type_Regu].

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8 Hardware
Figure 8.4-19 View of DC analogue output module (NR6632A)
Two 18-pin connectors are fixed on the DC analogue output module, but only the upper 18-pin
connector is valid. The terminal definition of the upper 18-pin connector on the module NR6632A
is listed as below.

01 IOUT1 Current output for the No.1 DC analogue output channel
02 AGND1- Grounding terminal for the No.1 DC analogue output channel
8 03 VOUT1 Voltage output for the No.1 DC analogue output channel
04 Blank
07 VOUT2 Voltage output for the No.2 DC analogue output channel
08 Blank
18-pin
12 Blank
16 Blank

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8 Hardware

17
18
8.4.8 Binary Input/Output Module (NR6661)

NR6661A module provides both binary inputs and binary outputs.
Two 18-pin connectors are fixed on the NR6661A module:
The upper 18-pin connector provides 16 binary inputs, the supported rated voltages of binary
inputs are listed in Chapter 2 Technical Data.
The lower 18-pin connector provides 6 normally open contacts (NOC) and 2 normally open
contacts & normally closed contacts (NOC/NCC).
01 BI_01
02 BI_02
03 BI_03
04 BI_04
05 BI_05 BO_01 19 20
06 BI_06 BO_02 21 22
07 BI_07 BO_03 23 24
08 BI_08 BO_04 25 26
09 BI_09 BO_05 27 28
10 BI_10 BO_06 29 30
11 BI_11 BO_07_NO 32
31
12 BI_12 BO_07_NC 33
13 BI_13 BO_08_NO 35
34
14 BI_14 BO_08_NC 36
15 BI_15
8
16 BI_16
COM-
17 (01-16)
COM-
18 (01-16)
Figure 8.4-20 View of binary input/output module (NR6661A)
The terminal definition of NR6661A is described as below.
Table 8.4-8 Terminal definition and description of NR6661A

18-pin

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8 Hardware

17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
19 The No.01 binary output contact. It is a normally open contact
BO_01
20 (NOC).
21
BO_02 The No.02 binary output contact. It is a normally open contact.
22
23
24
25
26
27
18-pin BO_05 The No.05 binary output contact. It is a normally open contact.
28
29
30
31
The No.07 binary output contact. It can be selected as a normally
32 BO_07
open contact or a normally closed contact (NCC).
33
8 34
The No.08 binary output contact. It can be selected as a normally
35 BO_08
open contact or a normally closed contact.
36
8.4.9 Arc Flash Module (NR6621A)

The NR6621A module is the arc flash sampling module, it provides up to 4 arc flash sampling
channels with channel self-supervision function, it is dedicated for arc flash protection.
Table 8.4-9 Technical data of arc flash module
Arc flash channel Up to 4 channels (ST connector)

Arc receiving wavelength 350nm~1100nm
Visible light: 2kLux~40kLux/0.28mW/cm2~5.86mW/cm2 (@555nm)
Light sampling range (10m pigtail)
Ultraviolet light: 2mW/cm2~30mW/cm2
Sampling resolution (10m pigtail) Visible light: 0.1kLux

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8 Hardware
Ultraviolet light: 0.1mW/cm2
Figure 8.4-21 View of arc flash module

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8 Hardware

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9 Settings
9 Settings
Table of Contents
9.1 Global Settings ................................................................................................ 9-1

9.1.1 System Settings.................................................................................................................... 9-1
9.1.2 Device Settings..................................................................................................................... 9-3
9.1.3 Communication Settings ...................................................................................................... 9-4
9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-19
9.1.5 Label Settings ..................................................................................................................... 9-20
9.1.6 Clock Synchronization Settings.......................................................................................... 9-20
9.1.7 OutMap Settings ................................................................................................................. 9-22
9.1.8 Supervision Settings........................................................................................................... 9-23
9.2 Protection Settings ........................................................................................ 9-24

9.2.1 Phase Overcurrent Protection Settings.............................................................................. 9-24
9.2.2 Earth Fault Overcurrent Protection Settings ...................................................................... 9-39
9.2.3 Another Group of Earth Fault Overcurrent Protection Settings ......................................... 9-55
9.2.4 Negative-sequence Overcurrent Protection Settings......................................................... 9-67
9.2.5 Broken Conductor Protection (46BC) ................................................................................ 9-72
9.2.6 Sensitive Earth Fault Protection Settings........................................................................... 9-72
9.2.7 RMS Overcurrent Protection Settings ................................................................................ 9-83
9.2.8 Phase Overvoltage Protection Settings ............................................................................. 9-87
9.2.9 Residual Overvoltage Protection Settings ......................................................................... 9-90

9
9.2.10 Negative-sequence Overvoltage Protection Settings ...................................................... 9-91
9.2.11 Positive-sequence Overvoltage Protection Settings ........................................................ 9-92
9.2.12 Phase Undervoltage Protection Settings ......................................................................... 9-92
9.2.13 Frequency Protection Settings ......................................................................................... 9-96
9.2.14 Reverse Power Protection Settings ............................................................................... 9-101
9.2.15 Cold Load Pickup Logic Settings ................................................................................... 9-102
9.2.16 Undercurrent Settings .................................................................................................... 9-105

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9 Settings
9.2.17 Breaker Failure Protection Settings ............................................................................... 9-105
9.2.18 Switch-on-to-Fault ProtectionSettings............................................................................ 9-106
9.2.19 Thermal Overload Protection Settings ........................................................................... 9-108
9.2.20 Fault Location Settings ................................................................................................... 9-109
9.2.21 Restricted Earth Fault Protection Settings ..................................................................... 9-109
9.2.22 Arc Flash Protection Settings ......................................................................................... 9-110
9.2.23 Current Unbalance Protection Settings ........................................................................... 9-111
9.2.24 Voltage Unbalance Protection Settings ........................................................................... 9-111
9.2.25 Automatic Reclosure Settings ........................................................................................ 9-112
9.2.26 Another Group of Phase Overcurrent Protection Settings ............................................. 9-114
9.2.27 Distance Protection Settings .......................................................................................... 9-124
9.3 Measurement and Control Settings ........................................................... 9-127

9.3.1 Function Settings .............................................................................................................. 9-127
9.3.2 Synchronism Check Settings ........................................................................................... 9-128
9.3.3 Double Point Status Settings ........................................................................................... 9-130
9.3.4 Control Settings ................................................................................................................ 9-131
9.3.5 Interlocking Logic Settings ............................................................................................... 9-133
9.3.6 DC Analogue Output Settings .......................................................................................... 9-134
9.4 PMU Settings ............................................................................................... 9-134

9.4.1 PMU Global Settings ........................................................................................................ 9-134
9.4.2 PMU Comm Settings ........................................................................................................ 9-135
9.4.3 PMU Bay Settings ............................................................................................................ 9-136
9.4.4 PMU BI Settings ............................................................................................................... 9-137

9 9.4.5 PMU Label Settings.......................................................................................................... 9-137
9.5 Logic Links ................................................................................................... 9-138

9.5.1 Function Links .................................................................................................................. 9-138
9.5.2 GOOSE Sending Links..................................................................................................... 9-138
9.5.3 GOOSE Receiving Links .................................................................................................. 9-138
9.5.4 SV Links ........................................................................................................................... 9-139

Date: 2021-08-01
9 Settings
9.1 Global Settings

9.1.1 System Settings

The number of active setting group,
several setting groups can be configured
1 Active_Grp 1~20 1 - 1
for protection settings, and only one is
active at a time.
Name of the protected primary
Max 20
2 PrimaryEquip_Name - - - equipment, such as feeder, transformer,
characters
etc.
3 Opt_SysFreq 50, 60 50Hz Hz The system frequency.
Rated primary value of protection phase
4 Prot.I1n 0~9999 1000 A 1
CT
Rated secondary value of protection
5 Prot.I2n 1, 5 1 A -
phase CT
Rated primary value of the No.1
6 Neu.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of the No.1
7 Neu.I2n 1, 5 1 A -
zero-sequence CT
Rated primary value of the No.2
8 Neu2.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of the No.2
9 Neu2.I2n 1, 5 1 A -
zero-sequence CT
Rated primary value of sensitive
10 SEF.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of sensitive
11 SEF.I2n 1 1 A -
zero-sequence CT
12 60/50.I1n 0~9999 1000 A 1 Rated primary value of unbalance CT
13 60/50.I2n 1, 5 1 A - Rated secondary value of unbalance CT
Rated primary value of another group of
14 S2.I1n 0~9999 1000 A 1
three-phase CT 9
Rated secondary value of another group
15 S2.I2n 1, 5 1 A -
of three-phase CT
16 Prot.U1n 0~1100 10 kV 0.01 Rated primary value of protection VT
17 Prot.U2n 1~200 100 V 0.01 Rated secondary value of protection VT
18 Syn.U1n 0~1100 10 kV 0.01 Rated primary value of synchro-check VT
Rated secondary value of synchro-check
19 Syn.U2n 1~200 100 V 0.01
VT
20 Delt.U1n 0~1100 10 kV 0.01 Rated primary value of zero-sequence VT
21 Delt.U2n 1~200 100 V 0.01 Rated secondary value of zero-sequence

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9 Settings

VT
22 60/59.U1n 0~1100 10 kV 0.01 Rated primary value of the unbalance VT
Rated secondary value of the unbalance
23 60/59.U2n 1~200 100 V 0.01
VT
The logic setting determines that whether
the CT polarity of the three-phase
Disabled;
24 Prot.En_RevCT Disabled - - protection CT is reversed.
Enabled
Enabled: The CT polarity is reversed
Disabled: The CT polarity is not reversed
the CT polarity of the No.1
Disabled;
25 Neu.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the No.2
Disabled;
26 Neu2.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the sensitive
Disabled;
27 SEF.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the unbalance CT is
Disabled;
28 60/50.En_RevCT Disabled - - reversed.
Enabled
the CT polarity of another group of
Disabled;
29 S2.En_RevCT Disabled - - three-phase CT is reversed.
Enabled
9 Enabled: The CT polarity is reversed
This setting informs the device of the
actual system phase sequence, either
ABC; ABC or ACB. CT and VT inputs on the
30 Opt_PhSeq ABC - -
ACB device, labelled as A, B and C, must be
connected to system phase A, B and C
for correct operation.
Disabled;
31 En_VT Enabled - - Logic setting to put VT into service
Enabled

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9 Settings
9.1.2 Device Settings

Access path: MainMenu  Settings  Global Settings  Device Settings

Logic setting to enable/disable the
Disabled debugging port. Used for debugging
1 En_DebugPort Enabled - -
Enabled tool connection, program download,
variable debugging, etc.
Disabled Logic setting to enable/disable the
2 En_TelnetPort Disabled - -
Enabled Telnet port.
Enabled: Connecting to the device
via the software Teldevice is
Disabled supported
3 En_VirtualLCDPort Enabled - -
Enabled Disabled: Connecting to the device
via the software Teldevice is not
supported
4 Ctrl_Password 000~999 111 - - The control password via local LCD.
Disabled Override control password via local
5 En_NoCtrlPwd Enabled - -
Enabled LCD
Enabled: all the events (including
disturbance records, supervision
events, IO events, control events)
will not pop up automatically in the
Disabled main graph of local LCD, they can
6 En_PopupRecord_Blkd Disabled - -
Enabled only be viewed by entering
corresponding menus.
Disabled: these events can pop up
in the main graph of local LCD
automatically.
This setting is used to set the
7 Un_BinaryInput 24~250 220 V 1 voltage level of the binary input
module.
DC
Power supply mode of binary input
8 Opt_Pwr_BI AC50Hz
AC60Hz
DC - -
module 9
This setting is used to set pickup
9 U_Pickup_BI 50%Un~80%Un 63 % 0.1
voltage of the binary input module.
This setting is used to set drop-off
10 U_Dropoff_BI 50%Un~80%Un 55 % 0.1
voltage of the binary input module.
Monitoring window of binary input
11 Mon_Window_Jitter 0.000~500.000 1 s 0.001
jitter processing
Times threshold to block binary
12 Num_Blk_Jitter 2~500000 10 - 1
input status change due to jitter
13 Blk_Window_Jitter 0.000~500.000 1 s 0.001 Blocking window of binary input

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9 Settings

status change due to jitter
Times threshold to initiate
immediately another blocking
14 Num_Reblk_Jitter 1~500000 10 - 1
window of binary input status
change due to continuous jitter
The logic setting to enable/disable
Disabled
15 En_Jitter_Blk Disabled - - the jitter processing function in case
Enabled
of binary input voltage variation
Enabled: Conducting mode by high
power with constant current drain of
binary inputs is enabled. Now the
binary input will be considered to be
energized only when the
instantaneous active power rises to
a certain value together with
constant current drain during this
mode, so as to avoid mistaken
signal.
Disabled: Conducting mode by high
binary inputs is disabled. Now the
binary input will be considered to be
Disabled
16 En_BICheckInstP Disabled - - energized with constant current
Enabled
drain without checking the
instantaneous active power.
The conducting mode by high
binary inputs is only available in the
device equipped with some certain
modules (e.g.: NR6604A,
NR6611A). If these modules are not
equipped, this conducting mode will
9 be unavailable, so this setting will

be hidden.
This setting cooperates with the BI
debouncing time configuration of
this device.
9.1.3 Communication Settings

9.1.3.1 General Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  General Comm
Settings

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9 Settings

0.0.0.0~
1 IP_LAN1 172.16.0.100 - - IP address of Ethernet port A
255.255.255.255
0.0.0.0~
2 Mask_LAN1 255.255.0.0 - - Subnet mask of Ethernet port A
255.255.255.255
Disabled
3 En_LAN1 Enabled - - Put Ethernet port A into service
Enabled
0.0.0.0~
4 IP_LAN2 172.17.0.100 - - IP address of Ethernet port B
255.255.255.255
0.0.0.0~
5 Mask_LAN2 255.255.0.0 - - Subnet mask of Ethernet port B
255.255.255.255
Disabled
6 En_LAN2 Enabled - - Put Ethernet port B into service
Enabled
0.0.0.0~
7 IP_LAN3 172.18.0.100 - - IP address of Ethernet port C
255.255.255.255
0.0.0.0~
8 Mask_LAN3 255.255.0.0 - - Subnet mask of Ethernet port C
255.255.255.255
Disabled
9 En_LAN3 Disabled - - Put Ethernet port C into service
Enabled
0.0.0.0~
10 IP_LAN4 172.19.0.100 - - IP address of Ethernet port D
255.255.255.255
0.0.0.0~
11 Mask_LAN4 255.255.0.0 - - Subnet mask of Ethernet port D
255.255.255.255
Disabled
12 En_LAN4 Disabled - - Put Ethernet port D into service
Enabled
0.0.0.0~ IP address of the gateway
13 Gateway 0.0.0.0 - -
255.255.255.255 (router)
4800
9600
19200
14 Baud_Printer 19200 bps - Baud rate of printer port
38400
57600
115200
15 En_AutoPrint
Disabled
Disabled - -
Enable/disable automatic 9
Enabled printing function
Communication protocol of rear
RS-485 serial port 1.
IEC103
16 Protocol_RS485-1 IEC103 - - IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
Communication protocol of rear
IEC103 RS-485 serial port 2.
17 Protocol_RS485-2 IEC103 - -
Modbus IEC103: IEC60870-5-103
protocol

Date: 2021-08-01
9 Settings

Modbus: Modbus protocol
4800
9600
19200 Baud rate of rear RS-485 serial
18 Baud_RS485-1 19200 bps -
38400 port 1.
57600
115200
4800
9600
19200 Baud rate of rear RS-485 serial
19 Baud_RS485-2 19200 bps -
38400 port 2.
57600
115200
Communication address
between the device and the
20 Addr_RS485-1 1~254 100 - 1
SCADA or RTU via RS-485
serial port 1.
Communication address
between the device and the
21 Addr_RS485-2 1~254 100 - 1
SCADA or RTU via RS-485
serial port 2.
The setting is used to set IP
address of syslog server 01,
and the device can upload
audit log to syslog server. The
setting is invalid unless cyber
0.0.0.0~
22 IP_SyslogServer01 0.0.0.0 - - security is configured in the
255.255.255.255
device.
Syslog is a communication
protocol for message logging,
it is used for security auditing
in this device.
9 The setting is used to set IP

0.0.0.0~
255.255.255.255
device.
in this device.

Date: 2021-08-01
9 Settings

0.0.0.0~
255.255.255.255
device.
in this device.
0.0.0.0~
255.255.255.255
device.
in this device.
The setting is used to set the
26 Cfg_NetPorts_Bond 0~255 0 - - Ethernet ports that are used
as hot standby each other.
A whitelist is a list of IP
addresses that are granted
access to a certain system or
protocol. When a whitelist is
Disabled used, all IP addresses are
27 En_IP_Whitelist Disabled - -
Enabled denied access, except those
included in the whitelist.
This setting
enable/disable
is
the
used
whitelist
to
9
function of this device.
No.** IP address of the
whitelist. (**=01...16) This
0.0.0.0~
28 IP**_Whitelist 0.0.0.0 - - setting is effective only when
255.255.255.255
the setting [En_IP_Whitelist] is
enabled.
Normal; The network method of the
29 B01.Opt_NetMode 1-2:Normal,3-4:HSR; Normal - - CPU module located in slot
1-2:Normal,3-4:PRP; No.1

Date: 2021-08-01
9 Settings

1-2:Normal,3-4:RSTP;
1-2:PRP, 3-4:PRP
1. [Cfg_NetPorts_Bond]
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device supports a bond between any two
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.
Ethernet port 1
Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 0 1 1 0011 3 1 0 0 1 1001 9
Ethernet port 2
0 1 0 1 0101 5 0 1 1 0 0110 6
Ethernet port 3
1 0 1 0 1010 10 1 1 0 0 1100 12
Ethernet port 4
CPU Module
9 The switching logic is as below.
⚫ After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.
⚫ When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.
⚫ When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.
⚫ When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal.

Date: 2021-08-01
9 Settings
9.1.3.2 IEC61850 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC61850

Settings

It is used to set the change detection
threshold for suddenly sending
1 Pcnt_Deadband 0~100.00 1 % 0.01 measurement value to the SCADA via
the device's Ethernet port using IEC
61850 protocol
Measurement values zero drift
2 Threshold_ZeroDrift 0.001~0.5 0.02 - 0.001
suppression threshold
If users need to support the quality
Disabled
3 En_Send_MMS_Qual_Chg Disabled - - change upload function, this parameter
Enabled
should be set as “Enabled”
It is used to select the network mode of
MMS network for the communication
with SCADA
IEC61850
4 Opt_DualNetMode_MMS IEC61850 - - IEC61850: Network mode with IEC
GB32890
61850 protocol.
GB32890: Network mode with GB32890
standard.
The identification of the IED in IEC
61850 protocol.
It cannot be an empty string and shall
be unique within an SCL file. IEDNAME
should be less than 20 characters
5 IEDNAME - TEMPLATE - -
comprising letters or digits or underline
( _ ), and it is case sensitive.
If this setting is modified, the IED name
in ".cid" file will be changed
simultaneously and vice versa.
Disabled The logic setting to enable/disable TCP
6 En_IEC62351_TCP_Port Disabled - -
Enabled
Disabled
port in IEC62351 protocol
The logic setting to enable/disable TCP
9
7 En_IEC61850_TCP_Port Enabled - -
Enabled port in IEC61850 protocol
9.1.3.3 DNP Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  DNP Settings

The logic setting to
Disabled
1 En_TCP1_DNP Disabled - - enable/disable the No.1
Enabled
network DNP client

Date: 2021-08-01
9 Settings

The local address of the
2 Addr_Slave_TCP1_DNP 0~65519 2 - 1
No.1 network DNP client
The master address of the
3 Addr_Master_TCP1_DNP 0~65519 1 - 1
The IP address of the
0.0.0.0~
4 IP_Master_TCP1_DNP 0.0.0.0 - - master of the No.1 network
255.255.255.255
DNP client
The communication map
5 Opt_Map_TCP1_DNP 0~4 0 - 1 of the No.1 network DNP
client
The timeout of the
6 t_AppLayer_TCP1_DNP 1~5 3 s 1 application layer of the
The heartbeat time interval
7 t_KeepAlive_TCP1_DNP 0~7200 120 s 1 of the No.1 network DNP
client
enable/disable the UR
Disabled
8 En_UR_TCP1_DNP Disabled - - (Unsolicited Response)
Enabled
message function of the
No.1 network DNP client.
When this setting is
enabled, the master
station must activate UR
reporting by enabling
unsolicited application
function (Function code:
20). After activation, the
Disabled No.1 network DNP client of
9 En_MsgCtrlUR_TCP1_DNP Enabled - -
Enabled this device begins to send
Class 1, 2, 3 events to the
master station
9 spontaneously.
disabled, this device sends
event data spontaneously
to the master station.
The online retransmission
number for sending the
10 Num_URRetry_TCP1_DNP 2~10 3 - 1
unsolicited message of the
The offline retransmission
11 t_UROfflRetry_TCP1_DNP 1~5000 60 s 1
interval for sending the

Date: 2021-08-01
9 Settings

The default class level of
12 Class_BI_TCP1_DNP 0~3 1 - 1 the “Binary Input” of the
13 Class_AI_TCP1_DNP 0~3 2 - 1 the “Analog Input” of the
The selection timeout of
the remote control and
14 t_Select_TCP1_DNP 0~240 30 s 1
remote adjustment of No.1
network DNP client
The time interval of the
time synchronization
15 t_TimeSynIntvl_TCP1_DNP 0~3600 180 s 1
function of the No.1
network DNP client
The “OBJ1” default
1-BISingleBit
16 Obj01DefltVar_TCP1_DNP 1-BISingleBit - - variation of the No.1
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
2-BIChWithA
17 Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime - - variation of the No.1
bsTime
3-BIChWithRelTime network DNP client
1-AI32Int
2-AI16Int The “OBJ30” default
3-AI32IntWo
18 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF - - variation of the No.1
utF
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
1-AI32IntEv
19 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT - - variation of the No.1
WoutT
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
20 Obj40DefltVar_TCP1_DNP 2-AO16Int 1-AO32Int - - variation of the No.1
3-AO32Flt network DNP client
9
Disabled
21 En_TCP2_DNP Disabled - 1 enable/disable the No.2
Enabled
network DNP client
0.0.0.0~
255.255.255.255
DNP client

Date: 2021-08-01
9 Settings

client
The timeout of the
client
Disabled
Enabled
enabled, the master
master station
spontaneously.
9 unsolicited message of the
33 Class_AI_TCP2_DNP 0~3 2 - 1
the “Analog Input” of the

Date: 2021-08-01
9 Settings

network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
2-BIChWithA
bsTime
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT
Disabled
Enabled
network DNP client
No.3 network DNP client 9
0.0.0.0~
255.255.255.255
DNP client
client
The timeout of the

Date: 2021-08-01
9 Settings

client
Disabled
Enabled
enabled, the master
master station
spontaneously.
9 52 Class_BI_TCP3_DNP 0~3 1 - 1
the “Binary Input” of the
network DNP client
55 t_TimeSynIntvl_TCP3_DNP 0~3600 180 s 1 The time interval of the

Date: 2021-08-01
9 Settings

network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
2-BIChWithA
bsTime
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT
Disabled
Enabled
network DNP client
0.0.0.0~
255.255.255.255
DNP client
client
The timeout of the
9
client
Disabled enable/disable the UR
68 En_UR_TCP4_DNP Disabled - -
Enabled (Unsolicited Response)

Date: 2021-08-01
9 Settings

enabled, the master
master station
spontaneously.
9 74 t_Select_TCP4_DNP 0~240 30 s 1
network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
77 Obj02DefltVar_TCP4_DNP 1-BIChWoutT 2-BIChWithA - - The “OBJ2” default

Date: 2021-08-01
9 Settings

2-BIChWithAbsTime bsTime variation of the No.4
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT
9.1.3.4 IEC103 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC103 Settings

Current
The language of group caption of IEC103
Language;
protocol
Fixed Current
1 Opt_Caption_103 - - It is recommended to be set as “Fixed
Chinese; Language
Chinese” if the device communicate with
Fixed
SCADA in Chinese.
English
This setting is only used for IEC 103
protocol. If NR network IEC103 protocol is
used, the setting must be set as
Disabled “Enabled”.
2 En_Broadcast_LAN1 Disabled - -
Enabled Disabled: the device does not send UDP
messages through Ethernet port A;
Enabled: the device sends UDP
messages through Ethernet port A.
protocol. If NR network IEC103 protocol is 9
messages through Ethernet port B;
messages through Ethernet port B.
Disabled
4 En_Broadcast_LAN3 Disabled - - protocol. If NR network IEC103 protocol is
Enabled

Date: 2021-08-01
9 Settings

“Enabled”.
Disabled: the device does not send UDP
messages through Ethernet port C;
messages through Ethernet port C.
protocol. If NR network IEC103 protocol is
messages through Ethernet port D;
messages through Ethernet port D.
This setting is used to set the data format
for sending waveform list using IEC
60870-5-103.
DisturbData;
6 Format_Wave_Sent File - - DisturbData: Send the waveform list in
File
ASDU23 mode;
File: Send the waveform list in ASDU222
mode.
It is used to set the change detection
threshold for suddenly sending
7 Pcnt_Deadband_Net 0~100.00 1.00 % 0.01 measurement value to the SCADA via the
device's Ethernet port using IEC
60870-5-103
It is used to set the time period for
sending the measurement value to
8 Period_Measmt_Net 0~65535 30 s 1
SCADA via the device's Ethernet port
using IEC 60870-5-103 or IEC 61850.
The logic setting to enable/disable the
Disabled
9 En_IEC103_TCP&UDP_Port Disabled - - TCP port and the UDP port in IEC
Enabled
60870-5-103 protocol
9 9.1.3.5 Modbus Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  Modbus Settings

Disabled
1 En_Modbus_TCP_Port Disabled - - enable/disable the TCP port
Enabled
in Modbus protocol
9.1.3.6 GOOSE Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  GOOSE Settings

Date: 2021-08-01
9 Settings

The GOOSE receiving mode.
DoubleFrameChk: double frame
DoubleFrameChk
1 Opt_RecvMode_GOOSE SingleFrameChk - - check mode;
SingleFrameChk
SingleFrameChk: single frame
check mode;
Disabled Logic setting to enable/disable
2 En_NetA_GOOSE Enabled - -
Enabled GOOSE net A
Disabled Logic setting to enable/disable
3 En_DualNet_GOOSE Disabled - -
Enabled GOOSE double-net mode
Logic setting to enable/disable
GOOSE complex-net mode.
GOOSE complex-net mode: for
Disabled
4 En_ComplexNet_GOOSE Disabled - - the GOOSE receiving, some
Enabled
control blocks adopt dual-net
receiving and other control blocks
adopt single-net receiving.
9.1.3.7 SV Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  SV Settings

1 SampleRate_SV 0~65535 4000 - 1 It is used to set sampling rate of SV.
It is backward time delay of SV
2 t_Dly_Interp_Net_SV 1500~15000 2000 μs 1
interpolation for networking mode.
It is backward time delay of SV
3 t_Dly_Interp_P2P_SV 600~1500 850 μs 1
interpolation for peer-to-peer (P2P) mode.
The option of SV receiving mode.
NetMode
NetMode: networking mode
4 Opt_RecvMode_SV P2P P2P - -
P2P: peer-to-peer (P2P) mode
Resv
Resv: reserved
9.1.4 Disturbance Fault Recording Settings

Access path: MainMenu  Settings  Global Settings  DFR Settings
9
Waveform recorded duration before the trigger
1 RecDur_PreTrigDFR 0~1 0.1 s 0.001
element operating
Waveform recorded duration after the fault
2 RecDur_PostFault 0~10 5 s 0.001
happens
The maximum waveform recorded duration
3 MaxRecDur_PostTrigDFR 0~10 10 s 0.001
after the trigger element operating

Date: 2021-08-01
9 Settings
9.1.5 Label Settings

Access path: MainMenu  Settings  Global Settings  Label Settings
No. Symbol Default Description
Label setting of GOOSE communication link ** (**=00~63) of

1 Bx.Name_**_GCommLink GOOSE_Link00
the module located in slot No.x.
Label setting of SV communication link ** (**=00~03) of the

2 Bx.Name_**_SVCommLink SV_Link00
module located in slot No.x.
These settings are used to definite the label of each GOOSE and SV communication link. The
label of each GOOSE and SV communication link will influence the displayed contents of all
reports, settings and metering that related with each GOOSE and SV communication link.
9.1.6 Clock Synchronization Settings

Access path: MainMenu  Settings  Global Settings  ClockSyn Settings
No
Settings Range Default Unit Step Remark
.
Conventional Select the time
1 Opt_TimeSyn SAS NoTimeSyn - - synchronization mode of the
NoTimeSyn device.
The local time zone also
2 OffsetHour_UTC -12~12 8 - 1 refered to as the hour offset
hour from UTC .
The offset minute of local time
3 OffsetMinute_UTC 0~60 0 - 1
from UTC.
The IP address of the server
0.0.0.0~ when SNTP time
4 IP_Server_SNTP 0.0.0.0 - -
255.255.255.255 synchronization mode is
selected
The IP address of the standby
IP_StandbyServer_S 0.0.0.0~ server when SNTP time
5 0.0.0.0 - -
NTP 255.255.255.255 synchronization mode is
selected
9 When the setting
[OptTimeSyn] is configured as
“Conventional”, if it is
required to receive the SNTP
Disabled message as the backup clock
6 En_ConvModeSNTP Disabled - -
Enabled synchronization source while
hardware-based clock is lost
(i.e.: IRIG-B, IEEE 1588 or
PPS), please configure the
setting [En_ConvModeSNTP]

Date: 2021-08-01
9 Settings
No
.
as “Enabled”. In this condition,
the alarm signal
“Alm_TimeSyn” will still be
issued, so as to indicate the
failure of the “Conventional”
clock synchronization.
If the SNTP backup clock
synchronization source is not
required for the
“Conventional” mode, please
configure the setting
[En_ConvModeSNTP] as
“Disabled”.
The logic setting is used to
Disabled
7 DST.En Disabled - - enable or disable Daylight
Enabled
Saving Time (DST)
It is used to set the minute
offset of DST, i.e. the
8 DST.OffsetMinute 0~255 60 - 1
difference between DST time
and local time
Jan, Feb, Mar,
DST.MonthInYear_St Apr, May, Jun, It is used to set the start month
9 Mar - -
art Jul, Aug, Sep, of DST.
Oct, Nov, Dec
DST.WeekInMonth_S 1st, 2nd, 3nd, It is used to set the start week
10 1st - -
tart 4th, Last of DST.
Sunday, Monday,
Tuesday,
DST.DayInWeek_Star It is used to set the start day of
11 Wednesday, Sunday - -
t DST.
Thursday, Friday,
Saturday
12 DST.HourInDay_Start 0~23 3 - 1
It is used to set the start hour
of DST.
9
Jan, Feb, Mar,
DST.MonthInYear_En Apr, May, Jun, It is used to set the end month
13 Oct - -
d Jul, Aug, Sep, of DST.
Oct, Nov, Dec
DST.WeekInMonth_E 1st, 2nd, 3nd, It is used to set the end week
14 1st - -
nd 4th, Last of DST.
Sunday, Monday,
It is used to set the end day of
15 DST.DayInWeek_End Tuesday, Sunday - -
DST.
Wednesday,

Date: 2021-08-01
9 Settings
No
.
Thursday, Friday,
Saturday
It is used to set the end hour of
16 DST.HourInDay_End 0~23 9 - 1
DST.
1. [Opt_TimeSyn]
There are three selections for clock synchronization of the device, each selection includes
different time clock synchronization signals shown in following table.
Item Description
IRIG-B (RS-485): IRIG-B via RS-485 differential level.
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B (Fiber): IRIG-B via optical-fibre interface.
Conventional
PPS (Fiber): Pulse per second (PPS) via optical-fibre interface.
IEEE1588 (Fiber): Clock message via IEEE1588.
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SNTP(BC): Broadcast SNTP mode via Ethernet network.
SAS
IEC103: Clock messages through IEC103 protocol.
MODBUS: Clock messages through MODBUS protocol.
If time synchronization function is not needed for the device, this option can be
NoTimeSyn
selected.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn].
2) When “Conventional” mode is selected, if there is no conventional clock synchronization

signal, “SAS” mode will be enabled automatically with the alarm signal “Alm_TimeSyn” being
issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send time synchronization alarm
signal.
9
The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.
9.1.7 OutMap Settings
Access path: MainMenu  Settings  Global Settings  OutMap Settings

OutMapxxx 00000000~ Tripping logic setting of programmable trip
1 - 0
(xxx=001, 002…032) FFFFFFFF output map xxx

Date: 2021-08-01
9 Settings

t_Dwell_xxx_OutMap The pulse width setting of programmable
2 0.000~0.500 s 0.060
(xxx=001, 002…032) trip output map xxx
9.1.8 Supervision Settings


The calculated residual current
1 CTS.3I0_Set 0~200 0.1 A 0.001 setting of CT circuit supervision
function.
The calculated residual voltage
2 CTS.3U0_Set 0~200 30 V 0.001 setting of CT circuit supervision
function.
Delay pick-up time setting for
3 CTS.t_DPU 0~100 10 s 0.001
CT circuit failure
Delay drop-out time setting for
4 CTS.t_DPO 0~100 10 s 0.001
CT circuit failure
Disabled Enabling/disabling CT circuit
5 CTS.En Disabled - -
Enabled supervision function.
Positive-sequence voltage
6 VTS.U1_Set 0~100 30.00 V 0.01 threshold for VT circuit
supervision
Zero-sequence voltage
7 VTS.3U0_Set 0~100 8.00 V 0.01 (calculated) threshold for VT
circuit supervision
Negative-sequence voltage
8 VTS.U2_Set 0~100 8.00 V 0.01 setting of VT circuit supervision
function.
Delay pickup setting for the
9 VTS.t_DPU 0.2~30 1.500 s 0.001
alarm of VT circuit supervision
Delay drop off setting for the
10 VTS.t_DDO 0.2~30 10.000 s 0.001
alarm of VT circuit supervision
Disabled Logic setting for alarm function
11 VTS.En
Enabled
Enabled - -
of VT circuit supervision 9
12 VTS.Opt_VT Bus or Bay Bus - - Selection of Bay VT or Bus VT
Positive-sequence voltage
13 Bus2.VTS.U1_Set 0~100 30.00 V 0.01 threshold for VT circuit
supervision of Bus2
Zero-sequence voltage
14 Bus2.VTS.3U0_Set 0~100 8.00 V 0.01 (calculated) threshold for VT
Negative-sequence voltage
15 Bus2.VTS.U2_Set 0~100 8.00 V 0.01
setting of VT circuit supervision

Date: 2021-08-01
9 Settings

function of Bus2.
Delay pickup setting for the
16 Bus2.VTS.t_DPU 0.2~30 1.500 s 0.001 alarm of VT circuit supervision
of Bus2
Delay drop off setting for the
17 Bus2.VTS.t_DDO 0.2~30 10.000 s 0.001 alarm of VT circuit supervision
of Bus2
Logic setting for alarm function
Disabled
18 Bus2.VTS.En Enabled - - of VT circuit supervision of
Enabled
Bus2
19 Bus2.VTS.Opt_VT Bus or Bay Bus - - Selection of Bay VT or Bus2 VT
enabling/disabling the CT
64REF.En_AutoRecov Disabled circuit failure alarm signal being
20 Disabled - -
_Alm_CTS Enabled automatically reset after the CT
circuit returns to normal
condition.
9.2 Protection Settings

9.2.1 Phase Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  OC Settings

The low voltage blocking setting
1 50/51P.VCE.Upp 10~100 70 V 0.001 of the voltage control element of
The negative-sequence voltage
blocking setting of the voltage
2 50/51P.VCE.U2 2~57 8 V 0.001
The residual voltage setting (set
9 3 50/51P.VCE.3U0 2~57 8 V 0.001

according to 3U0) of voltage
4 50/51P.DIR.RCA -180~179 45 deg 1 the direction control element of
The relay negative-sequence
50/51P.DIR.RCA_N characteristic angle of the
5 -180~179 45 deg 1
egOC direction control element of

Date: 2021-08-01
9 Settings

50/51P.DIR.phi_Min
_Fwd
50/51P.DIR.phi_Ma
x_Fwd
50/51P.DIR.phi_Min
_Rev
50/51P.DIR.phi_Ma
x_Rev
The voltage polarization mode
for direction control element of
Upp; Upp: phase-to-phase voltage
50/51P.DIR.Opt_Pol
10 Up; Upp - - polarized
arizedVolt
U1 Up: phase-to-ground voltage
polarized
U1: positive-sequence voltage
polarized
11 50/51P.DIR.I_Min (0.05~1)In 0.05 - 0.001
protection
12 50/51P.DIR.U_Min 1~10 4 V 0.001
protection
behaviour of phase overcurrent
9
Disabled; Disabled: phase overcurrent
13 50/51P.En_VTS_Blk Disabled - -
Enabled protection will not affected by VT
circuit failure
phase overcurrent protection will
be blocked by VT circuit failure
signal

Date: 2021-08-01
9 Settings

50/51P.HMB.K_Hm
14 0.1~1 0.2 - 0.001 harmonic control element of
2
The current setting for releasing
15 50/51P.HMB.I_Rls 2~150 20 A 0.001 the harmonic control element of
harmonic blocking mode of
PhaseBlk phase overcurrent protection
50/51P.HMB.Opt_Bl
16 CrossBlk PhaseBlk - - PhaseBlk: phase blocking
k
MaxPhaseBlk CrossBlk: cross blocking
MaxPhaseBlk: maximum phase
blocking
17 50/51P1.I_Set 0.05~200 15 A 0.001
protection
protection
20 Disabled - -
element
9 Non_Directional
element
Non_Directio
nal

Date: 2021-08-01
9 Settings

22 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
9
IECDefTime;
UserDefine
50/51P1.Opt_Curve
_DropOut

Date: 2021-08-01
9 Settings

protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
32 50/51P2.I_Set 0.05~200 15 A 0.001
protection
protection
9 phase overcurrent protection

35 Disabled - -
element
element

Date: 2021-08-01
9 Settings

Non_Directio
nal
37 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
9
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

50/51P2.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
47 50/51P3.I_Set 0.05~200 15 A 0.001
9 protection
protection

Date: 2021-08-01
9 Settings

50 Disabled - -
element
element
Non_Directio
nal
52 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P3.Opt_Curve
_DropOut
protection
0.000
1
9 protection
0.000
1
protection

Date: 2021-08-01
9 Settings

0.000
1
protection
62 50/51P4.I_Set 0.05~200 15 A 0.001
protection
protection
65 Disabled - -
element
element
Non_Directio
nal
50/51P4.En_Hm_Bl Disabled;
overcurrent protection is not
9
67 Disabled - -
control element
control element
Disabled;
Enabled

Date: 2021-08-01
9 Settings

m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P4.Opt_Curve
_DropOut
protection
0.000
1
protection

Date: 2021-08-01
9 Settings

0.000
1
protection
0.000
1
protection
77 50/51P5.I_Set 0.05~200 15 A 0.001
protection
protection
80 Disabled - -
element
element
Non_Directio
nal
9

Date: 2021-08-01
9 Settings

82 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
9 IECLT;
IECDefTime;
UserDefine
50/51P5.Opt_Curve
_DropOut

Date: 2021-08-01
9 Settings

protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
92 50/51P6.I_Set 0.05~200 15 A 0.001
protection
protection
9
95 Disabled - -
element
element

Date: 2021-08-01
9 Settings

Non_Directio
nal
97 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
9 IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

50/51P6.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
9.2.2 Earth Fault Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  ROC Settings
Uni
No. Settings Range Default
t
Step Description
9
1 50/51G.DIR.RCA -180~179 45 deg 1
50/51G.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
protection

Date: 2021-08-01
9 Settings
Uni
No. Settings Range Default Step Description
t
50/51G.DIR.phi_Max_ forward direction element of
3 10~90 90 deg 1
protection
50/51G.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
protection
50/51G.DIR.phi_Max_ reverse direction element of
5 10~90 90 deg 1
protection
6 50/51G.DIR.3I0_Min (0.05~1)In 0.05 - 0.001
7 50/51G.DIR.3U0_Min 1~10 4 V 0.001
behaviour of earth fault
failure happens.
Disabled;
8 50/51G.En_VTS_Blk Disabled - - Disabled: earth fault
Enabled
protection will be blocked by
9 VT circuit failure signal
9 50/51G.HMB.K_Hm2 0.1~1 0.2 - 0.001
protection
The current setting for
releasing the harmonic control
10 50/51G.HMB.I_Rls 2~150 20 A 0.001

Date: 2021-08-01
9 Settings
Uni
t
11 50/51G1.Opt_3I0 Ext - -
current
current
protection
15 50/51G1.Opt_Dir - -
Reverse protection.
Disabled;
Enabled
control element
9
control element
protection

Date: 2021-08-01
9 Settings
Uni
t
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G1.Opt_Curve_
DropOut
drop-out
23 50/51G1.K 0.001~120 0.14 - 0.0001 operation characteristic of

Date: 2021-08-01
9 Settings
Uni
t
24 50/51G1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
25 50/51G1.C 0 ~1.2 0 - 0.0001 operation characteristic of
26 50/51G2.Opt_3I0 Ext - -
current
current
protection
30 50/51G2.Opt_Dir - -
Reverse protection.

Date: 2021-08-01
9 Settings
Uni
t
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
9 IEC;
protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings
Uni
t
50/51G2.Opt_Curve_
DropOut
drop-out
9
41 50/51G3.Opt_3I0 Ext - -
current
current
protection

Date: 2021-08-01
9 Settings
Uni
t
45 50/51G3.Opt_Dir - -
Reverse protection.
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
9

Date: 2021-08-01
9 Settings
Uni
t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G3.Opt_Curve_
DropOut
drop-out
9

Date: 2021-08-01
9 Settings
Uni
t
56 50/51G4.Opt_3I0 Ext - -
current
current
protection
60 50/51G4.Opt_Dir - -
Reverse protection.
9 61 50/51G4.En_Hm_Blk
Disabled;
Disabled - -
overcurrent protection is not
Enabled
control element
control element

Date: 2021-08-01
9 Settings
Uni
t
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G4.Opt_Curve_
DropOut
drop-out
9

Date: 2021-08-01
9 Settings
Uni
t
71 50/51G5.Opt_3I0 Ext - -
current
current
protection
9 Non_Direction
75 50/51G5.Opt_Dir - -
Reverse protection.

Date: 2021-08-01
9 Settings
Uni
t
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
protection. 9
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings
Uni
t
50/51G5.Opt_Curve_
DropOut
drop-out
9 residual current that used for

86 50/51G6.Opt_3I0 Ext - -
current
current
protection

Date: 2021-08-01
9 Settings
Uni
t
90 50/51G6.Opt_Dir - -
Reverse protection.
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
9

Date: 2021-08-01
9 Settings
Uni
t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51G6.Opt_Curve_
DropOut
drop-out
9 customized inverse-time

Date: 2021-08-01
9 Settings
Uni
t
9.2.3 Another Group of Earth Fault Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  ROC2 Settings

1 A.50/51G1.3I0_Set 0.05~200 15 A 0.001
protection
of stage 1 of another group
2 A.50/51G1.t_Op 0 ~100 0.1 s 0.001
protection
3 A.50/51G1.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
4 A.50/51G1.En Enabled - - stage 1 of another group of
Enabled
protection
Enabling stage 1 of
another group of earth fault
Alm: for alarm purpose 9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE; The setting for selecting
ANSILTV; the inverse-time operation
ANSILT; characteristic curve of
6 A.50/51G1.Opt_Curve IECDefTime - -
IECN; stage 1 of another group of
IECV; earth fault overcurrent
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
A.50/51G1.Opt_Curve_D protection
7 DefTime; Inst - -
ropOut Inst: instantaneous
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
8 A.50/51G1.TMS 0.04~ 20 1 - 0.001
protection
9 time setting of stage 1 of
9 A.50/51G1.tmin 0 ~10 0.02 s 0.001
operation characteristic of
10 A.50/51G1.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

11 A.50/51G1.Alpha 0.01 ~3 0.02 - 0.0001
protection
12 A.50/51G1.C 0 ~1.2 0 - 0.0001
protection
13 A.50/51G2.3I0_Set 0.05~200 15 A 0.001
protection
14 A.50/51G2.t_Op 0 ~100 0.1 s 0.001
protection
15 A.50/51G2.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 2 of
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
20 A.50/51G2.TMS 0.04~ 20 1 - 0.001
protection
21 A.50/51G2.tmin 0 ~10 0.02 s 0.001
22 A.50/51G2.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

23 A.50/51G2.Alpha 0.01 ~3 0.02 - 0.0001
protection
24 A.50/51G2.C 0 ~1.2 0 - 0.0001
protection
25 A.50/51G3.3I0_Set 0.05~200 15 A 0.001
protection
26 A.50/51G3.t_Op 0 ~100 0.1 s 0.001
protection
27 A.50/51G3.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 3 of
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
32 A.50/51G3.TMS 0.04~ 20 1 - 0.001
protection
33 A.50/51G3.tmin 0 ~10 0.02 s 0.001
34 A.50/51G3.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

35 A.50/51G3.Alpha 0.01 ~3 0.02 - 0.0001
protection
36 A.50/51G3.C 0 ~1.2 0 - 0.0001
protection
37 A.50/51G4.3I0_Set 0.05~200 15 A 0.001
protection
38 A.50/51G4.t_Op 0 ~100 0.1 s 0.001
protection
39 A.50/51G4.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 4 of
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
44 A.50/51G4.TMS 0.04~ 20 1 - 0.001
protection
45 A.50/51G4.tmin 0 ~10 0.02 s 0.001
46 A.50/51G4.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

47 A.50/51G4.Alpha 0.01 ~3 0.02 - 0.0001
protection
48 A.50/51G4.C 0 ~1.2 0 - 0.0001
protection
49 A.50/51G5.3I0_Set 0.05~200 15 A 0.001
protection
50 A.50/51G5.t_Op 0 ~100 0.1 s 0.001
protection
51 A.50/51G5.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 5 of
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
56 A.50/51G5.TMS 0.04~ 20 1 - 0.001
protection
57 A.50/51G5.tmin 0 ~10 0.02 s 0.001
58 A.50/51G5.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

59 A.50/51G5.Alpha 0.01 ~3 0.02 - 0.0001
protection
60 A.50/51G5.C 0 ~1.2 0 - 0.0001
protection
61 A.50/51G6.3I0_Set 0.05~200 15 A 0.001
protection
62 A.50/51G6.t_Op 0 ~100 0.1 s 0.001
protection
63 A.50/51G6.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 6 of
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
drop-out
drop-out
IDMT: inverse-time
drop-out
68 A.50/51G6.TMS 0.04~ 20 1 - 0.001
protection
69 A.50/51G6.tmin 0 ~10 0.02 s 0.001
70 A.50/51G6.K 0.001~120 0.14 - 0.0001
protection

Date: 2021-08-01
9 Settings

71 A.50/51G6.Alpha 0.01 ~3 0.02 - 0.0001
protection
72 A.50/51G6.C 0 ~1.2 0 - 0.0001
protection
9.2.4 Negative-sequence Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  NegOC Settings

1 50/51Q.DIR.RCA -180~179 45 deg 1
50/51Q.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd negative-sequence
50/51Q.DIR.phi_Max forward direction element of
3 10~90 90 deg 1
_Fwd negative-sequence
50/51Q.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
Rev negative-sequence
The maximum boundary of the 9
50/51Q.DIR.phi_Max reverse direction element of
5 10~90 90 deg 1
_Rev negative-sequence
6 50/51Q.DIR.I2_Min (0.05~1)In 0.05 - 0.001 control element of
negative-sequence

Date: 2021-08-01
9 Settings

7 50/51Q.DIR.U2_Min 1.0~10.0 4 V 0.001 control element of
negative-sequence
behaviour of
negative-sequence
failure happens.
Disabled;
8 50/51Q.En_VTS_Blk Disabled - - Disabled: negative-sequence
Enabled
negative-sequence
overcurrent protection will be
blocked by VT circuit failure
signal
12 50/51Q1.Opt_Dir - -
9 The logic setting for
Enabling stage 1 of
negative-sequence

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51Q1.Opt_Curve_
DropOut
drop-out
18 50/51Q1.tmin 0 ~10 0.02 s 0.001
negative-sequence
9

Date: 2021-08-01
9 Settings

25 50/51Q2.Opt_Dir - -
Enabling stage 2 of
negative-sequence

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51Q2.Opt_Curve_
DropOut
drop-out
31 50/51Q2.tmin 0 ~10 0.02 s 0.001
negative-sequence
9

Date: 2021-08-01
9 Settings

9.2.5 Broken Conductor Protection (46BC)
Access path: MainMenuSettingsProtection SettingsBCP Settings

Minimum operating current setting of
1 46BC.I_Min (0.05~40) In 1.000 A 0.001
Ratio setting (negative-sequence
2 46BC.I2/I1_Set 0~5 0.500 - 0.001 current to positive-sequence current) of
Time delay of broken conductor
3 46BC.t_Op 0~10 1.000 s 0.001
protection
Disabled Enabling/disabling broken conductor
4 46BC.En Enabled - -
Enabled protection
Enabling/disabling broken conductor
Trp protection operate to trip or alarm
5 46BC.Opt_Trp/Alm Trp - -
9.2.6 Sensitive Earth Fault Protection Settings
Access path: MainMenu  Settings  Protection Settings  SEF Settings

1 50/51SEF.DIR.RCA -180~179 45 deg 1 the direction control element of
50/51SEF.DIR.phi_Mi
n_Fwd
9 sensitive earth fault protection
50/51SEF.DIR.phi_M
ax_Fwd
50/51SEF.DIR.phi_Mi
n_Rev
50/51SEF.DIR.phi_M
ax_Rev

Date: 2021-08-01
9 Settings

50/51SEF.DIR.3I0_Mi setting for the direction control
6 (0.005~1)In 0.05 - 0.001
n element of sensitive earth fault
protection
50/51SEF.DIR.3U0_ setting for the direction control
7 1.0~10.0 4 V 0.001
Min element of sensitive earth fault
protection
behaviour of sensitive earth fault
50/51SEF.En_VTS_Bl Disabled; Disabled: sensitive earth fault
8 Disabled - -
k Enabled protection will not affected by VT
circuit failure
will be blocked by VT circuit
failure signal
9 50/51SEF1.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF1.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
13 50/51SEF1.En
Enabled
Enabled - - enabling/disabling the stage 1 of
9
Alm Alm

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
15 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF1.Opt_Curv
e_DropOut
protection
9 protection
protection

Date: 2021-08-01
9 Settings

protection
22 50/51SEF2.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF2.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
28 - -
e IECN;
IECV;
me characteristic curve of stage 2 of
9
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

50/51SEF2.Opt_Curv
e_DropOut
protection
protection
protection
protection
35 50/51SEF3.3I0_Set 0.005~2 1 A 0.001
9 protection
50/51SEF3.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2021-08-01
9 Settings

Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
41 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF3.Opt_Curv
e_DropOut
protection
9
protection

Date: 2021-08-01
9 Settings

protection
protection
48 50/51SEF4.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF4.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
54 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF4.Opt_Curv
e_DropOut
protection
protection
9
protection

Date: 2021-08-01
9 Settings

protection
61 50/51SEF5.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF5.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
67 - -
9 e IECN;
IECV;
me characteristic curve of stage 5 of
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

50/51SEF5.Opt_Curv
e_DropOut
protection
protection
protection
protection
74 50/51SEF6.3I0_Set 0.005~2 1 A 0.001
protection
9
50/51SEF6.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2021-08-01
9 Settings

Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
80 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF6.Opt_Curv
e_DropOut
protection
9 earth fault protection
protection

Date: 2021-08-01
9 Settings

protection
protection
9.2.7 RMS Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  RMS OC Settings

The operating time
2 50/51R1.t_Op 0 ~100 0.1 s 0.001
RMS overcurrent
protection
The drop-out time
3 50/51R1.t_DropOut 0 ~100 0 s 0.001
RMS overcurrent
protection
Enabling stage 1 of
RMS overcurrent
5 50/51R1.Opt_Trp/Alm
Alm
Trp - -
trip or alarm. 9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
the inverse-time
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
stage 1 of RMS
IDMT dropout
dropout
IDMT: inverse-time
dropout
The time multiplier
8 50/51R1.TMS 0.04~ 20 1 - 0.001
RMS overcurrent
protection
9 9 50/51R1.tmin 0 ~10 0.02 s 0.001
of RMS overcurrent
protection
customized
10 50/51R1.K 0.001~120 0.14 - 0.0001
of RMS overcurrent
protection

Date: 2021-08-01
9 Settings

customized
11 50/51R1.Alpha 0.01 ~3 0.02 - 0.0001
of RMS overcurrent
protection
customized
12 50/51R1.C 0 ~1.2 0 - 0.0001
of RMS overcurrent
protection
The operating time
14 50/51R2.t_Op 0 ~100 0.1 s 0.001
RMS overcurrent
protection
The drop-out time
15 50/51R2.t_DropOut 0 ~100 0 s 0.001
RMS overcurrent
protection
Enabling stage 2 of
RMS overcurrent
Alm trip or alarm.
9

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
the inverse-time
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
stage 2 of RMS
IDMT dropout
dropout
IDMT: inverse-time
dropout
The time multiplier
20 50/51R2.TMS 0.04~ 20 1 - 0.001
RMS overcurrent
protection
9 21 50/51R2.tmin 0 ~10 0.02 s 0.001
of RMS overcurrent
protection
customized
22 50/51R2.K 0.001~120 0.14 - 0.0001
of RMS overcurrent
protection

Date: 2021-08-01
9 Settings

customized
23 50/51R2.Alpha 0.01 ~3 0.02 - 0.0001
of RMS overcurrent
protection
customized
24 50/51R2.C 0 ~1.2 0 - 0.0001
of RMS overcurrent
protection
9.2.8 Phase Overvoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  OV Settings

voltage or phase voltage for
Up; overvoltage protection.
1 59P.Opt_Up/Upp Upp - -
Upp Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode or
3-out-of-3 mode for
3P;
2 59P.Opt_1P/3P 3P - - overvoltage protection.
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
protection
overvoltage protection 9

Date: 2021-08-01
9 Settings

protection
Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
DefTime protection
drop-out
stage 1 of phase
9 overvoltage protection
stage 1 of phase
stage 1 of phase

Date: 2021-08-01
9 Settings

protection
protection
Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
DefTime protection
DefTime:
drop-out
definite-time
9

Date: 2021-08-01
9 Settings

stage 2 of phase
stage 2 of phase
stage 2 of phase
9.2.9 Residual Overvoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  ROV Settings

Option of measured residual voltage or
calculated residual voltage for residual
Ext;
1 59G.Opt_3U0 Cal - - overvoltage protection
Cal
Ext: the measured residual voltage
Cal: the calculated residual voltage
2 59G1.3U0_Set 1~200 50 V 0.001
3 59G1.K_DropOut 0.93 ~1 0.98 - 0.001
4 59G1.t_Op 0.1 ~100 1 s 0.001
5 59G1.t_DropOut 0 ~100 0 s 0.001
9 6 59G1.En
Disabled;
Enabled - -
The logic setting for enabling/disabling the
8 59G2.3U0_Set 1~200 50 V 0.001
9 59G2.K_DropOut 0.93 ~1 0.98 - 0.001

Date: 2021-08-01
9 Settings

10 59G2.t_Op 0.1 ~100 1 s 0.001
11 59G2.t_DropOut 0 ~100 0 s 0.001
9.2.10 Negative-sequence Overvoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  NegOV Settings

1 59Q1.U2_Set 2~100 15 V 0.001
protection
3 59Q1.t_Op 0.1~100 1 s 0.001
4 59Q1.t_DropOut 0~100 0 s 0.001
7 59Q2.U2_Set 2~100 15 V 0.001
9
protection
9 59Q2.t_Op 0.1~100 1 s 0.001
10 59Q2.t_DropOut 0~100 0 s 0.001

Date: 2021-08-01
9 Settings

9.2.11 Positive-sequence Overvoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  PosOV Settings

1 59Pos.U1_Set 2~100 60 V 0.001
The drop-out coefficient setting of the
2 59Pos.K_DropOut 0.93~1 0.98 - 0.001
The time setting of the positive-sequence
3 59Pos.t_Op 0.1~100 1 s 0.001
The drop-out time setting of the
4 59Pos.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of the positive-sequence
5 59Pos.En Enabled - -
Enabled overvoltage protection
Enabling the positive-sequence
6 59Pos.Opt_Trp/Alm Trp - -
9.2.12 Phase Undervoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  UV Settings

voltage or phase voltage
for stage x of
Up;
1 27P.Opt_Up/Upp Upp - - undervoltage protection
Upp
Up: phase voltage
Upp: phase-to-phase
9 voltage
Option of 1-out-of-3 mode
or 3-out-of-3 mode for
3P; stage x of undervoltage
2 27P.Opt_1P/3P 3P - -
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode

Date: 2021-08-01
9 Settings

Breaker closed position
check mode
None: no check
Curr: check the current
None; CBPos: check the
Curr; normally open auxiliary
3 27P.Opt_LogicMode CBPos; Curr - - contact
CurrOrCBPos; CurrOrCBPos: check the
CurrAndCBPos current and normally open
auxiliary contact
CurrAndCBPos: check the
current or normally open
auxiliary contact
phase undervoltage
Disabled;
Enabled
failure happens.
9

Date: 2021-08-01
9 Settings

Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
stage 1 of phase
InvTime_U
stage 1 of phase
Inst;
DefTime
Inst: instantaneous
drop-out
drop-out
13 27P1.TMS 0.04~ 20 1 - 0.001 of stage 1 of phase
14 27P1.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
stage 1 of phase
9 16 27P1.Alpha 0.01 ~3 0.02 - 0.0001

stage 1 of phase
stage 1 of phase

Date: 2021-08-01
9 Settings

phase undervoltage
Disabled;
Enabled
failure happens.
Trp;
24 27P2.Opt_Trp/Alm Trp - operate to trip or alarm.
Alm
ANSIDefTime;
9
IECDefTime;
UserDefine;
stage 2 of phase
InvTime_U

Date: 2021-08-01
9 Settings

stage 2 of phase
Inst;
DefTime
Inst: instantaneous
drop-out
drop-out
27 27P2.TMS 0.04~ 20 1 0.001 of stage 2 of phase
28 27P2.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
stage 2 of phase
stage 2 of phase
stage 2 of phase
9.2.13 Frequency Protection Settings

9 Access path: MainMenu  Settings  Protection Settings  FreqProt Settings

2 81O1.f_Set 50~65 52 Hz 0.001
3 81O1.t_Op 0~100 0.3 s 0.001
protection

Date: 2021-08-01
9 Settings

Enabled protection
5 Trp - -
6 81O2.f_Set 50~65 52 Hz 0.001
7 81O2.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
9 Trp - -
10 81O3.f_Set 50~65 52 Hz 0.001
11 81O3.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
13 Trp - -
14 81O4.f_Set 50~65 52 Hz 0.001
15 81O4.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
17
81O4.Opt_Trp/
Alm
Trp;
Alm
Trp - -
operate to trip or alarm.
9
18 81O5.f_Set 50~65 52 Hz 0.001
19 81O5.t_Op 0~100 0.3 s 0.001
protection
Enabled protection

Date: 2021-08-01
9 Settings

21 Trp - -
22 81O6.f_Set 50~65 52 Hz 0.001
23 81O6.t_Op 0~100 0.3 s 0.001
protection
Enabled protection
25 Trp - -
32 81U1.f_Set 45~60 48 Hz 0.001
33 81U1.t_Op 0~100 0.3 s 0.001
35 Trp - -
36 81U2.f_Set 45~60 48 Hz 0.001
37 81U2.t_Op 0~100 0.3 s 0.001
39 Trp - -

40 81U3.f_Set 45~60 48 Hz 0.001
41 81U3.t_Op 0~100 0.3 s 0.001
43 Trp - -

Date: 2021-08-01
9 Settings

44 81U4.f_Set 45~60 48 Hz 0.001
45 81U4.t_Op 0~100 0.3 s 0.001
47 Trp - -
48 81U5.f_Set 45~60 48 Hz 0.001
49 81U5.t_Op 0~100 0.3 s 0.001
51 Trp - -
52 81U6.f_Set 45~60 48 Hz 0.001
53 81U6.t_Op 0~100 0.3 s 0.001
55 Trp - -
56 81R1.df/dt_Set -5~5 0.5 Hz/s 0.001
57 81R1.t_Op 0.1~100 0.1 s 0.001
9
58 81R1.f_Pkp 45~65 50 Hz 0.001
81R1.Opt_Trp/ Trp;
60 Trp - - alarm.
Alm Alm

Date: 2021-08-01
9 Settings

61 81R2.df/dt_Set -5~5 0.5 Hz/s 0.001
62 81R2.t_Op 0.1~100 0.1 s 0.001
63 81R2.f_Pkp 45~65 50 Hz 0.001
81R2.Opt_Trp/ Trp;
65 Trp - - alarm.
Alm Alm
66 81R3.df/dt_Set -5~5 0.5 Hz/s 0.001
67 81R3.t_Op 0.1~100 0.1 s 0.001
68 81R3.f_Pkp 45~65 50 Hz 0.001
81R3.Opt_Trp/ Trp;
70 Trp - - alarm.
Alm Alm
71 81R4.df/dt_Set -5~5 0.5 Hz/s 0.001
72 81R4.t_Op 0.1~100 0.1 s 0.001
73 81R4.f_Pkp 45~65 50 Hz 0.001
9 Enabled rate-of-change protection
81R4.Opt_Trp/ Trp;
75 Trp - - alarm.
Alm Alm
76 81R5.df/dt_Set -5~5 0.5 Hz/s 0.001
77 81R5.t_Op 0.1~100 0.1 s 0.001

Date: 2021-08-01
9 Settings

78 81R5.f_Pkp 45~65 50 Hz 0.001
81R5.Opt_Trp/ Trp;
80 Trp - - alarm.
Alm Alm
81 81R6.df/dt_Set -5~5 0.5 Hz/s 0.001
82 81R6.t_Op 0.1~100 0.1 s 0.001
83 81R6.f_Pkp 45~65 50 Hz 0.001
81R6.Opt_Trp/ Trp;
85 Trp - - alarm.
Alm Alm
9.2.14 Reverse Power Protection Settings
Access path: MainMenu  Settings  Protection Settings  RevPower Settings

1 32R.U1_VCE 5~60 5 V 0.001 positive-sequence voltage control element
The positive-sequence current setting of
2 32R.I1_CCE 0.01~1 0.1 p.u. 0.001 the current control element of the reverse
power protection
3 32R.U2_VCE 8~60 8 V 0.001 negative-sequence voltage control element 9
4 32R1.P_Set 0.1~10 0.15 p.u. 0.001
power protection
5 32R1.t_Op 0.01~100 0.1 s 0.001
power protection

Date: 2021-08-01
9 Settings

8 32R2.P_Set 0.1~10 0.15 p.u. 0.001
power protection
9 32R2.t_Op 0.01~100 0.1 s 0.001
power protection
9.2.15 Cold Load Pickup Logic Settings
Access path: MainMenu  Settings  Protection Settings  CLP Settings

The setting for selecting the cold load
Curr;
1 CLP.Opt_LogicMode CBPos - - initiation condition.
CBPos
Curr: current; CBPos: CB position.
The time setting for ensuring the cold
2 CLP.t_Cold 0~4000 3 s 0.001
load condition is met
The time setting for resetting the cold
3 CLP.t_Rst 0~4000 3 s 0.001
load pickup logic
The time setting for fast resetting the cold
4 CLP.t_ShortRst 0~600 1 s 0.001
load pickup logic
Disabled; The logic setting of the cold load pickup
5 CLP.En Enabled - -
Enabled logic function
active
9 7 50/51P1.CLP.t_Op 0~100 0.1 s 0.001
active
9 50/51G1.CLP.IMult 1~10 1 - 0.001 zero-sequence overcurrent protection
when CLP is active
10 50/51G1.CLP.t_Op 0~100 0.1 s 0.001 zero-sequence overcurrent protection
when CLP is active

Date: 2021-08-01
9 Settings

11 50/51G1.CLP.TMS 0.05~100 1 s 0.001 zero-sequence IDMT overcurrent
active
13 50/51P2.CLP.t_Op 0~100 0.1 s 0.001
active
when CLP is active
when CLP is active
active
19 50/51P3.CLP.t_Op 0~100 0.1 s 0.001
active
when CLP is active
when CLP is active
9
active
25 50/51P4.CLP.t_Op 0~100 0.1 s 0.001

Date: 2021-08-01
9 Settings

active
when CLP is active
when CLP is active
active
31 50/51P5.CLP.t_Op 0~100 0.1 s 0.001
active
when CLP is active
when CLP is active
active
37 50/51P6.CLP.t_Op 0~100 0.1 s 0.001
9 protection when CLP is active
active
when CLP is active
when CLP is active

Date: 2021-08-01
9 Settings

9.2.16 Undercurrent Settings
Access path: MainMenu  Settings  Protection Settings  UC Settings

The current setting of the
1 37.I_Set 0.1~5 0.5 A 0.001
undercurrent protection
The time setting of the undercurrent
2 37.t_Op 0.1~100 0.1 s 0.001
protection
1P;
3 37.Opt_1P/3P 3P - - three-phase criterion (3P) or
3P
single-phase criterion (1P)
None;
Curr;
CurrAnd The setting of the CB position check
4 37.Opt_LogicMode CBPos; - -
CBPos mode.
CurrAndCBPos;
CurrOrCBPos
Disabled; The logic setting of the undercurrent
5 37.En Enabled - -
Enabled protection
Enabling undercurrent protection
Trp; operate to trip or alarm.
6 37.Opt_Trp/Alm Trp - -
9.2.17 Breaker Failure Protection Settings

Access path: MainMenu  Settings  Protection Settings  BFP Settings

The phase current setting of breaker
1 50BF.I_Set 0.05~200 1.000 A 0.001
failure protection
The zero-sequence current setting of
2 50BF.3I0_Set 0.05~200 1.000 A 0.001
breaker failure protection 9
The negative-sequence current setting of
3 50BF.I2_Set 0.05~200 1.000 A 0.001
The re-trip time delay of breaker failure
4 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
5 50BF.t1_Op 0~20 0.100 s 0.001
protection
The second time delay of breaker failure
6 50BF.t2_Op 0~20 0.200 s 0.001
protection

Date: 2021-08-01
9 Settings
Disabled Enabling/disabling breaker failure

7 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
8 50BF.En_ReTrp Enabled - -
Disabled Enabling/disabling first time delay of
Disabled Enabling/disabling second time delay of
Enabling/disabling phase overcurrent
Disabled
11 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
three-phases initiating signal
12 50BF.En_3I0_3P Disabled - -
signal
Enabling/disabling negative-sequence
13 50BF.En_I2_3P Disabled - -
signal
Enabling/disabling breaker failure
Disabled
14 50BF.En_CB_Ctrl Disabled - - protection be initiated by normally closed
Enabled
contact of circuit breaker
Disabled Enabling/disabling abnormality check of
15 50BF.En_Alm_Init Disabled - -
Enabled breaker failure initiating signal
Disabled Enabling/disabling current check criterion
16 50BF.En_Curr Enabled - -
Disabled Enabling/disabling contact check criterion
17 50BF.En_CBPos Disabled - -
9.2.18 Switch-on-to-Fault ProtectionSettings

The initiating time for the SOTF
9 1 SOTF.t_En 0.2~100 3 s 0.001
protection
Current setting of phase overcurrent
2 50PSOTF.I_Set 0.05~200 1 A 0.001
SOTF protection
Voltage setting for phase
3 50PSOTF.Up_Set 0~200 1 V 0.001
Voltage setting for phase-to-phase
4 50PSOTF.Upp_Set 0~200 1 V 0.001
Voltage setting for negative-sequence
5 50PSOTF.U2_Set 0~200 1 V 0.001

Date: 2021-08-01
9 Settings
Voltage setting for zero-sequence

6 50PSOTF.3U0_Set 0~200 1 V 0.001
Time delay for phase overcurrent
7 50PSOTF.t_Op 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling phase overcurrent
8 50PSOTF.En Enabled - -
Enabling/disabling second harmonic
Disabled
9 50PSOTF.En_Hm2_Blk Enabled - - blocking for phase overcurrent SOTF
Enabled
protection
Enabling/disabling phase
Disabled
10 50PSOTF.En_Up_UV Enabled - - undervoltage supervision logic for
Enabled
Enabling/disabling phase-to-phase
Disabled
11 50PSOTF.En_Upp_UV Enabled - - undervoltage supervision logic for
Enabled
Enabling/disabling
Disabled negative-sequence overvoltage
12 50PSOTF.En_U2_OV Enabled - -
Enabled supervision logic for phase
Disabled
13 50PSOTF.En_3U0_OV Enabled - - overvoltage supervision logic for
Enabled
The option of the residual current
used by earth fault overcurrent SOTF
Ext
14 50GSOTF.Opt_3I0 Cal - - protection
Cal
Ext: the measured residual current
Cal: the calculated residual current
Current setting of earth fault
15 50GSOTF.3I0_Set 0.05~200 1 A 0.001
Time delay for earth fault overcurrent
16 50GSOTF.t_Op_3P 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling earth fault
17 50GSOTF.En Enabled - -
Enabled overcurrent SOTF protection
18 50GSOTF.En_Hm2_Blk
Disabled
Disabled - -
Enabling/disabling earth
overcurrent SOTF protection blocked
fault
9
Enabled
by harmonic
Time delay of distance protection
0.000~100.
19 21SOTF.t_ManCls 0.025 s 0.001 accelerating to trip when manual
000
closing
Time delay of distance protection
0.000~100.
20 21SOTF.t_3PAR 0.025 s 0.001 accelerating to trip when 3-pole
000
reclosing
Disabled Enabling/disabling distance SOTF
21 21SOTF.En Enabled - -
Enabled protection

Date: 2021-08-01
9 Settings
Disabled Enabling/disabling zone 2 of distance

22 21SOTF.Z2.En_ManCls Enabled - -
Enabled SOTF protection for manual closing
23 21SOTF.Z3.En_ManCls Disabled - -
24 21SOTF.Z4.En_ManCls Disabled - -
25 21SOTF.Z2.En_3PAR Enabled - -
Enabled SOTF protection for 3-pole reclosing
26 21SOTF.Z3.En_3PAR Disabled - -
27 21SOTF.Z4.En_3PAR Disabled - -
Enabling/disabling zone 2 controlled
Disabled
28 21SOTF.Z2.En_PSBR Enabled - - by PSB of distance SOTF protection
Enabled
for 3-pole reclosing
Disabled
Enabled
Disabled
Enabled
0.000~100. Undervoltage setting of deadline
31 SOTF.U_Ddl 30.000 - -
000 detection
0.200~100.
32 SOTF.t_Ddl 15.000 - - Time delay of deadline detection
000
Option of manual SOTF mode
ManClsBI: initiated by input signal of
ManClsBI
manual closing
SOTF.Opt_Mode_Man CBPos
33 CBPos - - CBPos: initiated by CB position
Cls ManClsBI/
ManClsBI/CBPos: initiated by either
CBPos
input signal of manual closing or CB
position
9.2.19 Thermal Overload Protection Settings

9
Access path: MainMenu  Settings  Protection Settings  ThOvLd Settings

The reference current setting of thermal
1 49.Ib_Set 0.05~200 15 A 0.001
overload protection
2 49.K_Trp 1~3 1.2 - 0.001
tripping
3 49.K_Alm 1~3 1.1 - 0.001
alarm

Date: 2021-08-01
9 Settings
The heat accumulation time constant of

4 49.t_Tau 0.1~100 1 min 0.001
thermal overload protection
The temperature constant of thermal
5 49.K_T_Diff 0~200 30 - 0.001
overload protection
The cooling factor of thermal overload
6 49.Alpha_Cold 1~2 2 - 0.001
protection
Heat dissipation time constant setting.
0.100~10 When the current Ieq is lower than 0.04In,
7 49.C_Disspt 1.000 - 0.001
.000 the thermal time constant adopts the value
of [49.Tau]*[49.C_Disspt].
8 49.En_Trp Disabled - -
Enabled protection operate to trip
9 49.En_Alm Disabled - -
Enabled protection operate to alarm
9.2.20 Fault Location Settings
Access path: MainMenu  Settings  Protection Settings  Line Settings

Positive-sequence reactance of the whole
1 X1L 0~600 10 Ω 0.001
Positive-sequence resistance of the whole
2 R1L 0~600 1 Ω 0.001
Zero-sequence reactance of the whole
3 X0L 0~600 20 Ω 0.001
Zero-sequence resistance of the whole
4 R0L 0~600 3 Ω 0.001
5 LineLength 0~500 30 km 0.01 Length of the whole line
9.2.21 Restricted Earth Fault Protection Settings
Access path: MainMenu  Settings  Protection Settings  REF Settings

1 64REF.I_Biased 0.050~5.000 In 0.500 Pickup current setting of REF protection
2 64REF.I_Alm 0.050~1.500 In 0.200

Current setting of REF protection 9
abnormality alarm
Knee point setting of REF protection,
3 64REF.I_Knee 0.100~4.000 In 0.500
0.5In is recommended.
Percentage restraint coefficient of REF
4 64REF.Slope 0.200~0.750 - 0.500
protection, 0.5 is recommended.
Operation angle setting of REF
5 64REF.ROA 45.000~90.000 deg 60.000
protection
Time delay for REF protection, the
6 64REF.t_Op 0.000~20.000 s 0.000
recommended value is 0.

Date: 2021-08-01
9 Settings

7 64REF.En - Disabled
Disabled REF protection
8 64REF.En_NPCurr - Disabled
Disabled neutral current criterion
Logic setting for enabling/disabling
Enabled,
9 64REF.En_CTS_Blk - Enabled blocking REF protection during CT
Disabled
circuit failure
Logic setting for enabling/disabling the
Enabled,
10 64REF.En_Dir_Blk - Disabled function of direction criterion blocking
Disabled
REF protection
9.2.22 Arc Flash Protection Settings
Access path: MainMenu  Settings  Protection Settings  ArcFlash Settings

_Sensor01
protection
_Sensor02
protection
50L/NL.LgtIncr_Set
2
_Sensor03
protection
50L/NL.LgtIncr_Set
2
_Sensor04
protection
5 1~30000 3300 - 1
6 1~30000 3300 - 1
7 1~30000 3300 - 1
9 50L/NL.K_Calbr_Se The channel coefficient of the arc
8 1~30000 3300 - 1
This setting is used to
enable/disable each arc sensor, it is
50L/NL.Map.En_Se
nsor
the corresponding arc channel is
enabled.

Date: 2021-08-01
9 Settings
The current setting of arc flash

10 50L/NL.I_Set 0.05~200 6 A 0.001
protection
The time delay setting of arc flash
11 50L/NL.t_Op 0~1 0 s 0.001
protection
Disabled; The logic setting for
12 50L/NL.En Disabled - -
Enabled enabling/disabling arc flash protection
Disabled;
13 50L/NL.En_CCE Disabled - - enabling/disabling the current
Enabled
criterion of arc flash protection
the tripping of each arc sensor, it is
50L/NL.Map.En_Se
nsor_Trp
the tripping of corresponding arc
channel is enabled.
9.2.23 Current Unbalance Protection Settings
Access path: MainMenu  Settings  Protection Settings  UnbalCurr Settings

1 60/50-1.I_Set 0.02~200 1 A 0.001
2 60/50-1.t_Op 0.05~100 0.1 s 0.001
3 60/50-1.En Enabled - -
5 60/50-2.I_Set 0.02~200 1 A 0.001
6 60/50-2.t_Op 0.05~100 0.1 s 0.001
current unbalance protection 9
7 60/50-2.En Enabled - -
9.2.24 Voltage Unbalance Protection Settings

Access path: MainMenu  Settings  Protection Settings  UnbalVolt Settings

Date: 2021-08-01
9 Settings

1 60/59-1.U_Set 1~63.5 50 V 0.001
2 60/59-1.t_Op 0.1~100 1 s 0.001
3 60/59-1.En Enabled - -
5 60/59-2.U_Set 1~63.5 50 V 0.001
6 60/59-2.t_Op 0.1~100 1 s 0.001
7 60/59-2.En Enabled - -
9.2.25 Automatic Reclosure Settings
Access path: MainMenu  Settings  Protection Settings  AR Settings

Maximum number of reclosing
1 79.Num 1~4 1 - 1
attempts
Dead time of first shot 3-pole
2 79.t_Dd_3PS1 0~600 0.600 s 0.001
reclosing
Dead time of second shot 3-pole
3 79.t_Dd_3PS2 0~600 0.600 s 0.001
reclosing
Dead time of third shot 3-pole
4 79.t_Dd_3PS3 0~600 0.600 s 0.001
reclosing
9 Dead time of fourth shot 3-pole
5 79.t_Dd_3PS4 0~600 0.600 s 0.001
reclosing
Time delay of circuit breaker in
6 79.t_CBClsd 0~600 5.000 s 0.001
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
signal [79.CB_Healthy] is
7 79.t_CBReady 0~600 5.000 s 0.001
de-energized and if it is not
energized within this time delay, AR
will be blocked.

Date: 2021-08-01
9 Settings

Maximum wait time for synchronism
8 79.t_Wait_Chk 0~600 10.000 s 0.001
check
9 79.t_Reclaim 0~600 15.000 s 0.001 Reclaim time of AR
Drop-out time delay of blocking AR,

when blocking signal for AR
10 79.t_DDO_Blk 0~600 5.000 s 0.001
disappears, AR blocking condition
drops out after this time delay
Time delay of excessive trip signal
11 79.t_PersistTrp 0~600 0.200 s 0.001
to block AR
Time delay allow for CB status
12 79.t_Fail 0~600 0.200 s 0.001 change to conform reclosing
successful
13 79.t_PW 0~600 0.120 s 0.001 Pulse width of AR closing signal
Enabling/disabling confirm whether

Disabled
14 79.En_FailCheck Disabled - - AR is successful by checking CB
Enabled
state
Disabled Enabling/disabling adjust the length
15 79.En_CutPulse Disabled - -
Enabled of reclosing pulse
Disabled
16 79.En Enabled - - Enabling/disabling auto-reclosing
Enabled
Enabling/disabling AR by external
input signal besides logic setting
Setting [79.En]
17 79.Opt_Enable Setting - -
Setting&Config Setting: only the setting
Setting&Config: the setting and
Disabled Enabling/disabling AR be initiated
18 79.En_CBInit Disabled - -
Enabled by open state of circuit breaker
Selection of decision mode for AR
synchronism check
79.Opt_RSYN_Valid Setting;
19 Setting - - Setting: determined by the setting
Mode Config
Config: determined by the
configuration signal 9
Enabling/disabling synchro-check
Disabled of AR (valid only if the setting
20 79.En_SynChk Disabled - -
Setting)

Date: 2021-08-01
9 Settings

both the reference side and the
Disabled synchronization side (valid only if
21 79.En_SynDd_RefDd Disabled - -
Enabled the setting
Setting)
Enabling/disabling live check for
synchronization side and dead
Disabled check for reference side (valid only
22 79.En_SynLv_RefDd Disabled - -
Enabled if the setting
Setting)
synchronization side and live check
Disabled
23 79.En_SynDd_RefLv Disabled - - for reference side (valid only if the
Enabled
setting [79.Opt_RSYN_ValidMode]
= Setting)
Enabling/disabling AR without any
Disabled check (valid only if the setting
24 79.En_NoChk Enabled - -
Setting)
9.2.26 Another Group of Phase Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  OC2 Settings

9 3
S2.50/51P1.t_Drop
Out
0 ~100 0 s 0.001 stage 1 of another group of
4 S2.50/51P1.En Enabled - -

Date: 2021-08-01
9 Settings

5 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
7 DefTime; Inst - -
IDMT
9
9 S2.50/51P1.tmin 0 ~10 0.02 s 0.001
protection
0.000
1

Date: 2021-08-01
9 Settings

0.000
1
0.000
1
S2.50/51P2.t_Drop
Out
16 S2.50/51P2.En Enabled - -
17 Trp - -
p/Alm Alm alarm.

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
21 S2.50/51P2.tmin 0 ~10 0.02 s 0.001
protection
22 S2.50/51P2.K 0.001~120 0.14 -
0.000
operation characteristic of stage
9
1
0.000
1

Date: 2021-08-01
9 Settings

0.000
1
S2.50/51P3.t_Drop
Out
28 S2.50/51P3.En Enabled - -
29 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
9 rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

Inst;
IDMT
33 S2.50/51P3.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1
0.000
1
9
S2.50/51P4.t_Drop
Out
40 S2.50/51P4.En Enabled - -

Date: 2021-08-01
9 Settings

41 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
9 The minimum operating time
45 S2.50/51P4.tmin 0 ~10 0.02 s 0.001
protection
0.000
1

Date: 2021-08-01
9 Settings

0.000
1
0.000
1
S2.50/51P5.t_Drop
Out
52 S2.50/51P5.En Enabled - -
53 Trp - -
p/Alm Alm alarm.

Date: 2021-08-01
9 Settings

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
57 S2.50/51P5.tmin 0 ~10 0.02 s 0.001
protection
9 58 S2.50/51P5.K 0.001~120 0.14 -
0.000
operation characteristic of stage
1
0.000
1

Date: 2021-08-01
9 Settings

0.000
1
S2.50/51P6.t_Drop
Out
64 S2.50/51P6.En Enabled - -
65 Trp - -
p/Alm Alm alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
rve IECN;
IECV;
another group of phase 9
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-08-01
9 Settings

Inst;
IDMT
69 S2.50/51P6.tmin 0 ~10 0.02 s 0.001
protection
0.000
1
0.000
1
0.000
1
9.2.27 Distance Protection Settings
9 Access path: MainMenu  Settings  Protection Settings  DistProt Settings

Current setting of DPFC current
1 21L.FD.DPFC.I_Set (0.050~40.000)×In A 0.100
Current setting of residual current
2 21L.FD.ROC.3I0_Set (0.050~40.000)×In A 0.100
Current setting of
3 21L.FD.NOC.I2_Set (0.050~40.000)×In A 0.100 negative-sequence current fault
detector element
4 21L.Ang_Alpha 5~30 ° 15 The angle of directional line in the

Date: 2021-08-01
9 Settings

second quadrant for quadrilateral
5 21L.Ang_Beta 5~30 ° 15 fourth quadrant for quadrilateral
Angle setting of load trapezoid
6 21L.LoadEnch.phi 5~50 ° 12 according to the maximum load
area angle (φLoad_Max), φLoad_Max+5°
is recommended.
Resistance setting of load trapezoid
7 21L.LoadEnch.R_Set (0.000~4Unn)/In Ω 40.000 according to the minimum load
resistance, 70%~90% minimum
load resistance is recommended.
Current setting for power swing
8 21L.I_PSBR (0.050~30.000)×In A 1.000
blocking releasing
9 21L.ZG.Opt_Characteristic - Mho
Quad phase-to-ground distance element
10 21L.ZP.Opt_Characteristic - Mho
Quad phase-to-phase distance element
Forward
Direction option for zone x of
11 21Lx.DirMode Reverse - Forward
Non_Directional
Real component of zero-sequence
12 21Lx.Real_K0 -4.000~4.000 - 0.660 compensation coefficient for zone x
of distance protection (x=1~4)
Imaginary component of
zero-sequence compensation
13 21Lx.Imag_K0 -4.000~4.000 - 0.000
coefficient for zone x of distance
protection (x=1~4)
Phase angle of positive-sequence
14 21Lx.phi1_Reach 30~89 ° 78 impedance for zone x of distance
protection (x=1~4)
9
15 21Lx.ZG.RCA 0~45 ° 12
(x=1~4)
16 21Lx.ZG.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(x=1~4)
17 21Lx.ZG.Z_Offset (0.000~4Unn)/In Ω 10.000

Date: 2021-08-01
9 Settings

(x=1~4)
18 21Lx.ZG.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-ground
19 21Lx.ZG.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-ground distance element
(x=1~4)
20 21Lx.ZG.t_Op 0.000~10.000 s 0.200 phase-to-ground distance element
(x=1~4)
Disabled
21 21Lx.ZG.En - Enabled phase-to-ground distance element
Enabled
(x=1~4)
Disabled phase-to-ground distance element
22 21Lx.ZG.En_3I0 - Disabled
Enabled controlled by residual current fault
detector element (x=1~4)
Disabled
23 21Lx.ZG.En_NeuDir_Blk - Enabled blocked by direction control
Enabled
element of earth fault protection
(x=1~4)
Disabled
24 21Lx.ZG.En_NegDir_Blk - Enabled blocked by direction control
Enabled
25 21Lx.ZP.RCA 0~45 ° 12
(x=1~4)
9 26 21Lx.ZP.Z_Set (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element

(x=1~4)
27 21Lx.ZP.Z_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(x=1~4)
28 21Lx.ZP.R_Set (0.000~4Unn)/In Ω 10.000 quadrilateral phase-to-phase
29 21Lx.ZP.R_Offset (0.000~4Unn)/In Ω 10.000 phase-to-phase distance element
(x=1~4)

Date: 2021-08-01
9 Settings

30 21Lx.ZP.t_Op 0.000~10.000 s 0.200 phase-to-phase distance element
(x=1~4)
Disabled
31 21Lx.ZP.En - Enabled phase-to-phase distance element
Enabled
(x=1~4)
Disabled
32 21Lx.ZP.En_NegDir_Blk - Enabled blocked by direction control
Enabled
Enabling/disabling load trapezoid
Disabled
33 21Lx.LoadEnch.En - Enabled characteristics for zone x of
Enabled
Disabled
34 21Lx.En_PSBR - Enabled distance protection controlled by
Enabled
PSBR (x=1~4)
Disabled
35 21Lx.En_ReacLine - Disabled distance protection controlled by
Enabled
the reactance line (x=1~4)
9.3 Measurement and Control Settings
In this section, the "XXXX" stands for bay indication. By default, it could be
BayMMXU, BusMMXU, etc. and it is configurable through the configuration
tool PCS-Studio.
9.3.1 Function Settings

Access path: Main Menu  Settings  Meas Control Settings  Function Settings

Ia-Ib-Ic or
9
1 Opt_CT_Measmt Ia-Ib-Ic - - Source selection of current measurement
Ia-Ic
2 ZeroDrift_U 0.20 0.00~1.00 0.01 %

Threshold to limit the zero-drift influence of
voltage, current or power due to temperature or
3 ZeroDrift_I 0.20 0.00~1.00 0.01 % other environmental factors. A measured value
less than this setting will be regarded as a zero
drift and ignored.
4 ZeroDrift_PQ 0.50 0.00~1.00 0.01 %
5 Neu.ZeroDrift_I 0.20 0.00~1.00 0.01 % Threshold to limit the zero-drift influence of

Date: 2021-08-01
9 Settings

6 Neu2.ZeroDrift_I 0.20 0.00~1.00 0.01 % corresponding current due to temperature or
other environmental factors. A measured value
7 60/50.ZeroDrift_I 0.20 0.00~1.00 0.01 % less than this setting will be regarded as a zero
drift and ignored.
8 Delt.ZeroDrift_U 0.20 0.00~1.00 0.01 % Threshold to limit the zero-drift influence of
9 Syn.ZeroDrift_U 0.20 0.00~1.00 0.01 % corresponding voltage due to temperature or
other environmental factors. A measured value
10 60/59.ZeroDrift_U 0.20 0.00~1.00 0.01 % less than this setting will be regarded as a zero
drift and ignored.
9.3.2 Synchronism Check Settings
Access path: Main Menu  Settings  Meas Control Settings  Syn Settings

Selection of decision
mode for
synchronism check
Setting: the mode

depends on the
setting values of
Setting or [25.En_SynChk] and
1 25.Opt_ValidMode Setting - -
Config [25.En_DdChk];
Config: the mode

depends on the
input values of
"in_syn_chk" and
"in_vol_chk"
terminals.
Logic setting for
synchro-check (valid
Disabled or
2 25.En_SynChk Enabled - - only if the setting
Enabled
[25.Opt_ValidMode]
9 = Setting)
Logic setting for
dead charge check
Disabled or (valid only if the
3 25.En_DdChk Enabled - -
Enabled setting
[25.Opt_ValidMode]
= Setting)
Percentage
4 25.U_UV 80.00 0~100 0.01 % threshold of under
voltage for CB

Date: 2021-08-01
9 Settings

closing blocking
Percentage
threshold of over
5 25.U_OV 170.00 100~170 0.01 %
voltage for CB
closing blocking
Percentage
threshold of under
6 25.f_UF 45.000 45~65 0.001 Hz
frequency for CB
closing blocking
Percentage
threshold of over
7 25.f_OF 65.000 45~65 0.001 Hz
frequency for CB
closing blocking
Selection of voltage
Ua, Ub, Uc,
8 25.Opt_U_SynChk Ua - - for synchronism
Uab, Ubc, Uca
check
Threshold of voltage
9 25.U_Diff_Set 10.00 0~100 0.01 V difference for
synchronism check
Logic setting for
Disabled or
10 25.En_f_Diff_Chk Enabled - - frequency difference
Enabled
check
Threshold of
frequency difference
11 25.f_Diff_Set 0.50 0~2 0.01 Hz
for synchronism
check
Logic setting for
Disabled or
12 25.En_df/dt_Chk Enabled - - frequency variation
Enabled
difference check
Threshold of
frequency variation
13 25.df/dt_Set 1.00 0~2 0.01 Hz/s
for synchronism
check.
Threshold of phase
9
14 25.phi_Diff_Set 15.00 0~180 0.01 ° difference for
synchronism check
Compensation angle
of phase difference
15 25.phi_Comp 0.00 0~360 0.01 °
for synchronism
check
SynDdRefDd
Selection of dead
16 25.Opt_Mode_DdChk AnySideDd SynLvRefDd - -
charge check mode
SynDdRefLv

Date: 2021-08-01
9 Settings

RefDd
SynDd
SynLvRefDd/S
ynDdRefLv
AnySideDd
Threshold for
17 25.U_DdChk 17.32 0~100 0.01 V
voltage dead check
Threshold for
18 25.U_LvChk 34.64 0~100 0.01 V
voltage live check
Threshold of
19 25.t_Reset 5 0~60 1 s duration for
synchro-check
Circuit breaker
closing time. It is the
time from receiving
20 25.t_Close_CB 20 0~2000 1 ms
closing command
pulse till the CB is
completely closed.
9.3.3 Double Point Status Settings
Access path: Main Menu  Settings  Meas Control Settings  DPS Settings

Delay Pick Up (DPU) time, i.e. debounce
1 CB.DPS.t_DPU 500 0~60000 1 ms
time, for DPS of the circuit breaker
Disabled or Logic setting for DPS alarm of the circuit
2 CB.DPS.En_Alm Disabled - -
Enabled breaker
Operation time delay of DPS alarm of the
3 CB.DPS.t_Alm 500 0~60000 1 ms
circuit breaker
4 DS01.DPS.t_DPU 500 0~60000 1 ms
time, for DPS of disconnector switch 01
Disabled or Logic setting for DPS alarm of
5 DS01.DPS.En_Alm Disabled - -
Enabled disconnector switch 01
9 Operation time delay of DPS alarm of
6 DS01.DPS.t_Alm 500 0~60000 1 ms
disconnector switch 01
7 DS02.DPS.t_DPU 500 0~60000 1 ms
9 DS02.DPS.t_Alm 500 0~60000 1 ms
10 DS03.DPS.t_DPU 500 0~60000 1 ms

Date: 2021-08-01
9 Settings

12 DS03.DPS.t_Alm 500 0~60000 1 ms
13 DS04.DPS.t_DPU 500 0~60000 1 ms
15 DS04.DPS.t_Alm 500 0~60000 1 ms
16 DS05.DPS.t_DPU 500 0~60000 1 ms
18 DS05.DPS.t_Alm 500 0~60000 1 ms
19 DS06.DPS.t_DPU 500 0~60000 1 ms
21 DS06.DPS.t_Alm 500 0~60000 1 ms
22 DS07.DPS.t_DPU 500 0~60000 1 ms
24 DS07.DPS.t_Alm 500 0~60000 1 ms
25 DS08.DPS.t_DPU 500 0~60000 1 ms
27 DS08.DPS.t_Alm 500 0~60000 1 ms
9
28 DS09.DPS.t_DPU 500 0~60000 1 ms
30 DS09.DPS.t_Alm 500 0~60000 1 ms
9.3.4 Control Settings

Access path: Main Menu  Settings  Meas Control Settings  Control Settings

Date: 2021-08-01
9 Settings

Pulse Width (PW), i.e. holding time, for opening
1 CB.t_PW_Opn 500 0~60000 1 ms
output of the circuit breaker
Pulse Width (PW), i.e. holding time, for closing
2 CB.t_PW_Cls 500 0~60000 1 ms
output of the circuit breaker
Pulse Width (PW), i.e. holding time, for direct
3 DS01.t_PW_Opn 500 0~60000 1 ms
opening output of disconnector switch 01
4 DS01.t_PW_Cls 500 0~60000 1 ms
closing output of disconnector switch 01
5 DS02.t_PW_Opn 500 0~60000 1 ms
6 DS02.t_PW_Cls 500 0~60000 1 ms
7 DS03.t_PW_Opn 500 0~60000 1 ms
8 DS03.t_PW_Cls 500 0~60000 1 ms
9 DS04.t_PW_Opn 500 0~60000 1 ms
10 DS04.t_PW_Cls 500 0~60000 1 ms
11 DS05.t_PW_Opn 500 0~60000 1 ms
12 DS05.t_PW_Cls 500 0~60000 1 ms
13 DS06.t_PW_Opn 500 0~60000 1 ms
14 DS06.t_PW_Cls 500 0~60000 1 ms
15 DS07.t_PW_Opn 500 0~60000 1 ms
16 DS07.t_PW_Cls 500 0~60000 1 ms
9 17 DS08.t_PW_Opn 500 0~60000 1 ms

18 DS08.t_PW_Cls 500 0~60000 1 ms
19 DS09.t_PW_Opn 500 0~60000 1 ms
20 DS09.t_PW_Cls 500 0~60000 1 ms

Date: 2021-08-01
9 Settings
9.3.5 Interlocking Logic Settings

Access path: Main Menu  Settings  Meas Control Settings  Interlock Settings

Disabled or Logic setting for interlocking logic control
1 CB.En_CILO_Opn Disabled - -
Enabled of opening output of the circuit breaker.
Disabled or Logic setting for interlocking logic control
2 CB.En_CILO_Cls Disabled - -
Enabled of closing output of the circuit breaker.
Logic setting for interlocking logic control
Disabled or
3 DS01.En_CILO_Opn Disabled - - of direct opening output of disconnector
Enabled
switch 01.
Disabled or
4 DS01.En_CILO_Cls Disabled - - of direct closing output of disconnector
Enabled
switch 01.
Disabled or
Enabled
switch 02.
Disabled or
Enabled
switch 02.
Disabled or
Enabled
switch 03.
Disabled or
Enabled
switch 03.
Disabled or
Enabled
switch 04.
Disabled or
Enabled
switch 04.
Disabled or
11 DS05.En_CILO_Opn Disabled
Enabled
- - of direct opening output of disconnector
switch 05.
9
Disabled or
Enabled
switch 05.
Disabled or
Enabled
switch 06.
Disabled or
Enabled
switch 06.

Date: 2021-08-01
9 Settings

Disabled or
Enabled
switch 07.
Disabled or
Enabled
switch 07.
Disabled or
Enabled
switch 08.
Disabled or
Enabled
switch 08.
Disabled or
Enabled
switch 09.
Disabled or
Enabled
switch 09.
9.3.6 DC Analogue Output Settings
Access path: Main Menu  Settings  Meas Control Settings  DCAO Settings

4~20mA
0~10V Option of DC analogue
1 B**.DCAO**.Opt_Type_Regu 4~20mA - -
0~5V output range
0~20mA
The minimal converted
2 B**.DCAO**.Min_Regu 0 -60000~60000 0.01 -
physical quantity value
The maximal
3 B**.DCAO**.Max_Regu 10 -60000~60000 0.01 - converted physical
quantity value
9
9.4 PMU Settings
9.4.1 PMU Global Settings
Access path: Main Menu  Settings  PMU Settings  PMU Global Settings

Disabled or Enabling/Disabling PMU function for
1 En_PMU Enabled - -
Enabled synchrophasor measurement

Date: 2021-08-01
9 Settings

Performance class option of the
measured values for the use in
P_Class or calculation
2 Opt_Class_PMU M_Class - -
M_Class P class: faster response time
M class: higher measurement
precision
3 DataRate 50 10~120 1 fps Data transmission rate (to PDC)
Max. 16
4 Substation_PMU NR_Station1 - - Name of PMU substation
characters
Times of change of CFG
To inform the updated version number
5 N_Chgd_CFG 1 0~65535 1 - which should be increased if any
configuration or setting has been
modified
6 Port_TCP 4712 0~65535 1 - PMU port TCP address
7 Port_UDP 4713 1024~65535 1 - PMU port UDP address
9.4.2 PMU Comm Settings
Access path: Main Menu  Settings  PMU Settings  PMU Comm Settings  PDC**
Settings

1 PDC**.Name PDC** - - - Connected PDC name
000.000.000.000~ IP address of connected
2 PDC**.IP_TCP 198.120.0.20 - -
255.255.255.255 PDC
000.000.000.000~
3 PDC**.IP_UDP_Dest 198.120.0.20 - - Destination IP address
255.255.255.255
Multicast source IP
000.000.000.000~
4 PDC**.IP_MulticastSrc 198.120.0.1 - - address, valid for multicast
255.255.255.255
mode using UDP
Option of PDC
communication protocol
None: no communication 9
between PDC and PMU
TCP: TCP for the
None,
transmission of
TCP,
5 PDC**.Opt_Protocol None - - configuration frame,
UDP,
TCP-UDP
frame.
UDP: UDP for the
transmission of

Date: 2021-08-01
9 Settings

frame.
TCP-UDP: TCP for the
transmission of
configuration frame and
command frame; UDP for
the transmission of data
frame.
Unicast,
Option of UDP broadcast
6 PDC**.Opt_UDP Multicast Broadcast, - -
mode
Multicast
7 PDC**.IDCODE 1 1~65534 - - Connected PDC IDCODE
9.4.3 PMU Bay Settings
Access path: Main Menu  Settings  PMU Settings  PMU Bay Settings

Max. 12
1 Name_PMUBay STN-Bay** - - Configurable PMU bay name
characters
None,
Bay,
2 XXXX.Opt_UnitType Bay 1 - Bay application scenario
Bus(U_3P),
Bus(U_1P)
U1,
Ua, Option of base voltage for
3 XXXX.Opt_U_MeasFreq U1 1 -
Ub, frequency measurement
Uc
Enabling/Disabling disturbance
Disabled or
4 XXXX.En_TrigDFR Enabled - - fault recording function in case
Enabled
any following over limit situation
5 XXXX.Up_UpLmt 1.200 0.010~2.000 0.001 Un Upper limit of phase voltage
6 XXXX.U1_UpLmt 1.200 0.010~2.000 0.001 Un
voltage
9 7 XXXX.U2_UpLmt 0.200 0.010~2.000 0.001 Un

voltage
8 XXXX.U0_UpLmt 0.200 0.010~2.000 0.001 Un
voltage
9 XXXX.Up_LowLmt 0.900 0.010~2.000 0.001 Un Lower limit of phase voltage
Lower limit of positive sequence
10 XXXX.U1_LowLmt 0.900 0.010~2.000 0.001 Un
voltage
11 XXXX.Ip_UpLmt 1.200 0.010~2.000 0.001 In Upper limit of phase current
12 XXXX.I1_UpLmt 1.200 0.010~2.000 0.001 In
current

Date: 2021-08-01
9 Settings

13 XXXX.I2_UpLmt 0.200 0.010~2.000 0.001 In
current
14 XXXX.I0_UpLmt 0.200 0.010~2.000 0.001 In
current
15 XXXX.f_Diff_Lmt 0.50 0.01~10.00 0.01 Hz Limit of frequency deviation
Limit of rate-of-change of
16 XXXX.df/dt_Lmt 1.00 0.01~50.00 0.01 Hz/s
frequency
9.4.4 PMU BI Settings
Access path: Main Menu  Settings  PMU Settings  PMU BI Settings

Max. 16
1 Name_BI_** STN-Digital** - - Configurable PMU binary signal name
charactors
Disabled or
2 Link_BI_TrigDFR Enabled - - recording function in case state change
Enabled
of any PMU binary signal
Disabled or
3 BI_**.En_TrigDFR Enabled - - recording function in case state change
Enabled
of the PMU binary signal BI_**
9.4.5 PMU Label Settings
Access path: Main Menu  Settings  PMU Settings  PMU Label Settings

1 Name_Amp_Ua -UAV - - - Label for amplitude of phase A voltage phasor
2 Name_Amp_Ub -UBV - - - Label for amplitude of phase B voltage phasor
3 Name_Amp_Uc -UCV - - - Label for amplitude of phase C voltage phasor
4 Name_Amp_U0 -U0V - - - Label for amplitude of zero sequence voltage phasor
Label for amplitude of positive sequence voltage
phasor
Label for amplitude of negative sequence voltage
phasor 9
7 Name_Amp_Ia -IAV - - - Label for amplitude of phase A current phasor
8 Name_Amp_Ib -IBV - - - Label for amplitude of phase B current phasor
9 Name_Amp_Ic -ICV - - - Label for amplitude of phase C current phasor
10 Name_Amp_I0 -I0V - - - Label for amplitude of zero sequence current phasor
Label for amplitude of positive sequence current
phasor
Label for amplitude of negative sequence current
phasor

Date: 2021-08-01
9 Settings

13 Name_Ang_Ua -UAP - - - Label for angle of phase A voltage phasor
14 Name_Ang_Ub -UBP - - - Label for angle of phase B voltage phasor
15 Name_Ang_Uc -UCP - - - Label for angle of phase C voltage phasor
16 Name_Ang_U0 -U0P - - - Label for angle of zero sequence voltage phasor
17 Name_Ang_U1 -U1P - - - Label for angle of positive sequence voltage phasor
18 Name_Ang_U2 -U2P - - - Label for angle of negative sequence voltage phasor
19 Name_Ang_Ia -IAP - - - Label for angle of phase A current phasor
20 Name_Ang_Ib -IBP - - - Label for angle of phase B current phasor
21 Name_Ang_Ic -ICP - - - Label for angle of phase C current phasor
22 Name_Ang_I0 -I0P - - - Label for angle of zero sequence current phasor
23 Name_Ang_I1 -I1P - - - Label for angle of positive sequence current phasor
24 Name_Ang_I2 -I2P - - - Label for angle of negative sequence current phasor
25 Name_f -FRQ - - - Label for bay frequency
26 Name_df/dt -DFT - - - Label for bay rate-of-change of frequency
27 Name_P -00P - - - Label for bay active power
28 Name_Q -00Q - - - Label for bay reactive power
29 Name_phi_diff -FAI - - - Label for bay phase difference
9.5 Logic Links
Logic link is a special logic setting which can be configured through local HMI or remote PC.
These logic links provide a convenient way for the operator to put the function in service or out of
service remotely away from an unattended substation.
9.5.1 Function Links

Access path: MainMenu  Settings  Logic Links  Function Links
No. Settings Range Default Remark
1 Link_** Disabled; Enabled Enabled Function link setting ** (**=01~08)
9 9.5.2 GOOSE Sending Links

Access path: MainMenu  Settings  Logic Links  GOOSE Send Links
@Bx.Name_**_GCommLink.G Disabled GOOSE sending link ** is enabled or disabled

1 Enabled
Link_Send Enabled (**=00~63)
@Bx.Name_**_GCommLink is the set value of the label setting of [Bx.Name_**_GCommLink].
9.5.3 GOOSE Receiving Links

Access path: MainMenu  Settings  Logic Links  GOOSE Recv Links

Date: 2021-08-01
9 Settings
@Bx.Name_**_GCommLink.G Disabled GOOSE receiving link ** is enabled or disabled

1 Enabled
Link_Recv Enabled (**=00~63)
Enabling/disabling the allowance for the acceptance

of GOOSE messages
Disabled Disabled: not receiving the GOOSE message
2 GLink_RecvSim Disabled
Enabled (simulation=1)
Enabled: receiving the GOOSE message
(simulation=1)
@Bx.Name_**_GCommLink is the set value of the label setting of [Bx.Name_**_GCommLink].
9.5.4 SV Links
Access path: MainMenu  Settings  Logic Links  SV Links
@Bx.Name_**_SVCommLink Disabled SV receiving link ** is enabled or disabled

1 Enabled
.SVLink_Recv Enabled (**=00~03)
Enabling/disabling the allowance for the

acceptance of simulated messages
Disabled Disabled: not receiving the simulated message
2 SVLink_RecvSim Disabled
Enabled (simulation=1)
Enabled: receiving the simulated message
(simulation=1)
@Bx.Name_**_SVCommLink is the set value of the label setting of [Bx.Name_**_SVCommLink].

Date: 2021-08-01
9 Settings

Date: 2021-08-01
Appendix A Glossary
Appendix A Glossary
The abbreviations adopted in this manual are listed as below.
A BOM Binary Output Module
"a" Contact is breaker auxiliary contact (ANSI C

Standard Device Number 52A) that closes
when the breaker is closed and opens when C37.94 IEEE/ANSI protocol used when
the breaker is open. sending binary signals between IEDs
AC Alternating current CB Circuit breaker
A/D converter Analog-to-digital converter CID Configured IED Description
AI Analog input COMTRADE Standard Common Format for

Transient Data Exchange format for
ANSI American National Standards Institute
Disturbance recorder according to IEEE/ANSI
AR Autoreclosing C37.111, 1999 / IEC 60255-24
ASDU Application Service Data Unit – An CPU Central Processing Unit

ASDU can consist of one or more identical
CRC Cyclic Redundancy Check
information objects. A sequence of the same
information elements, for example measured CT Current Transformer
values, is identified by the address of the
CTS Current Circuit Supervision
information object. The address of the
information object defines the associated
D
address of the first information element of the
sequence. A consecutive number identifies the
DBDL Dead Bus Dead Line
subsequent information elements. The number
builds on this address in integral increments DBLL Dead Bus Live Line
(+1).
DC Direct Current
B DLLB Dead Line Live Bus
DNP Distributed Network Protocol as per IEEE

"b" Contact is breaker auxiliary contact (ANSI
Std 1815-2012
Standard Device Number 52B) that closes
when the breaker is open and opens when the DPFC Deviation of Power Frequency
breaker is closed. Component–In case of a fault occurred in the
power system, the fault component could be
BFP Breaker failure protection
analyzed into three parts: the power frequency
BI Binary Input components before the fault, the power
frequency variables during the fault and the
BO Binary Output
transient variables during the fault. DPFC is A
BIM Binary Input Module the power frequency variable during the fault.
PCS-9611S Feeder Relay 1

Date: 2021-08-01
Appendix A Glossary
DSP Digital Signal Processor L

DTT Direct Transfer Trip Scheme
LCD Liquid Crystal Display
E LED Light-emitting Diode
EHV Extra High Voltage M

EMC Electromagnetic Compatibility
MCB Miniature Circuit Breaker
F MMS Manufacturing Message Specification
MOV Metal-oxide Varistor

FL Fault Location
FR Fault Recorder P
G PD Pole Discrepancy
PL Programmable Logic
G.703 Electrical and functional description for
digital lines used by local telephone PPS Pulse Per Second
companies. Can be transported over balanced
PRP Parallel Redundancy Protocol
and unbalanced lines
GIS Gas-insulated Switchgear R

GOOSE Generic Object-Oriented Substation
RMS Root Mean Square
Event
RSTP Rapid Spanning Tree Protocol
GPS Global Positioning System
RTD Resistance Temperature Detector
H
RTU Remote Terminal Unit
HMI Human-machine Interface

S
HSR High-availability Seamless Redundancy
SA Substation Automation
HV High-voltage
SCADA Supervision, Control And Data
HVDC High-voltage Direct Current
Acquisition
I SCD Substation Configuration Description
SCL Substation Configuration Description

ICD IED Capability Description
Language
IEC International Electrotechnical Commission
SLD Single-line Diagram
IED Intelligent Electronic Device
SIR Source-to-line Impedance Ratio
A IRIG-B InterRange Instrumentation Group
SNMP Simple Network Management Protocol
Time code format B
–An Internet standard protocol and serves for
2 PCS-9611S Feeder Relay

Date: 2021-08-01
Appendix A Glossary
the administration of nodes in an IP network. T

SNTP Simple Network Time Protocol – A
TCS Trip Circuit Supervision
protocol for the synchronization of clocks via
the Internet. With SNTP, client computers can TCP/IP Transmission Control Protocol over
synchronize their clocks via the Internet with a Internet Protocol
time server.
U
SOE Sequence of Events – An ordered,
time-stamped log of status changes at binary
UTC Coordinated Universal Time
inputs (also referred to as state inputs). SOE is
used to restore or analyze the performance, or
V
an electrical power system itself, over a certain
period of time.
VT Voltage transformer
SOTF Switch-Onto-Fault
VTS Voltage Circuit Supervision
STP Rapid Spanning Tree Protocol
A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:
21 Distance element 50 Instantaneous overcurrent element
25 Synchronism-check element 51 Definite-time or inverse-time overcurrent

element
27 Undervoltage element
52 AC circuit breaker
32 Power element
59 Overvoltage element
37 Undercurrent element
67 Directional overcurrent element
46 Phase-balance current element
79 Reclosing element
49 Thermal overload element
81 Frequency element
These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:
P Phase element Q Negative-sequence element
G Residual/Ground element
PCS-9611S Feeder Relay 3

Date: 2021-08-01
Appendix A Glossary
4 PCS-9611S Feeder Relay

Date: 2021-08-01

PCS-9611S - X - Technical Manual - EN - Overseas General - X - R1.23

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About This Manual

Product Documentation Set

DS SLG TM AM CPM OCM IMM CM STG

PCS-9611S Feeder Relay I

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

II PCS-9611S Feeder Relay

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, may result

in minor or moderate injury or equipment damage.

Important information about the device, product handling or a certain

Instructions and Warnings

Disconnect or de-energize all external connections BEFORE opening this

This device is shipped with default passwords. Default passwords should

PCS-9611S Feeder Relay III

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical

DO NOT perform any procedures or adjustments that this instruction

During installation, maintenance, or testing of the optical ports, ONLY use

Incorporated components, such as LEDs, transceivers, and laser emitters,

Equipment components are SENSITIVE to electrostatic discharge (ESD).

Insufficiently rated insulation can deteriorate under abnormal operating

IV PCS-9611S Feeder Relay

SEVERE power and ground problems can occur on the communications

Use of controls or adjustments, or performance of procedures other than

The firmware may be upgraded to add new features or enhance/modify

⚫ Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection

⚫ Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

⚫ Cross-references are presented in italics.

For example: press the button "ENT".

PCS-9611S Feeder Relay V

& & &

>=1 >=1 >=1

⚫ Binary signal Input

Optional definite-time or inverse-time characteristics

Fixed delay pickup (10ms), fixed delay drop-out (2ms)

VI PCS-9611S Feeder Relay

Settable delay pickup, fixed delay drop-out

Fixed delay pickup, settable delay drop-out

Settable delay pickup, settable delay drop-out

PCS-9611S Feeder Relay VII

Three-phase Corresponding Relationship

VIII PCS-9611S Feeder Relay

PCS-9611S Feeder Relay IX

Describes the abbreviations adopted in this manual.

Document Revision History

Current version: R1.23

R1.00 R1.00 2019-01-31 ⚫ Form the original manual.

⚫ Positive-sequence overvoltage protection is added;

⚫ Thermal overload protection and arc flash protection are

⚫ Broken conductor protection is added;

R1.03 R1.12 2019-11-21 ⚫ The VT circuit supervision function is modified;

⚫ The control function is modified;

⚫ The NR6311A module is added.

⚫ The logic diagram of enabling/disabling phase overvoltage

protection, residual overvoltage protection, negative-sequence

overvoltage protection, positive-sequence overvoltage

protection and under voltage protection is modified;