PCS-9611S - X - Technical Manual - EN - Overseas General - X - R1.01

Copyright © 2019 NR. All rights reserved.
NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and
benefits afforded under P.R. China and international copyright and patent laws in its products,
including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is
licensed to use this document as well as all intellectual property rights owned or held by NR
Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how,
trade secrets, trademarks and trade names, service marks, design rights, database rights and
rights in data, utility models, domain names and all similar rights.
The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.
To the extent required the products described herein meet applicable IEC and IEEE standards,
but no such assurance is given with respect to local codes and ordinances because they vary
greatly.
Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered
sufficiently for your purposes, please do not hesitate to contact us.
Preface
Preface
About This Manual

The technical manual describes the protection, automation, control, and supervision functions of
PCS S series device, and contains operation principle descriptions, and lists function blocks, logic
diagrams, input and output signals, setting parameters and technical data, sorted per function, as
well as the hardware of the device. The manual can be used as a technical reference during the
engineering phase and during normal service. In addition, the manual also includes a glossary
that lists and defines technical terms used throughout the manual.
Safety Information
This manual is not a complete index of all safety measures required for operation of the
equipment (module or device). However, it comprises important information that must be followed
for personal safety, as well as to avoid material damage. Information is highlighted and illustrated
as follows according to the degree of danger:
Indicates an imminently hazardous situation that, if not avoided, will
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, could
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, may result
in minor or moderate injury or equipment damage.
Indicates that property damage can result if the measures specified are
not taken.
Important information about the device, product handling or a certain

section of the documentation which must be given particular attention.
Instructions and Warnings

The following hazard statements apply to this device.
Disconnect or de-energize all external connections BEFORE opening this

device. Contact with hazardous voltages and currents inside this device
PCS-9611S Feeder Relay I

Date: 2019-04-24
Preface
can cause electrical shock resulting in injury or death.
Contact with instrument terminals can cause electrical shock that can
result in injury or death.
Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.
Have only qualified personnel service this equipment. If you are not
qualified to service this equipment, you can injure yourself or others, or
cause equipment damage.
This device is shipped with default passwords. Default passwords should

be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access.
NR shall not be responsible for any damage resulting from unauthorized
access.
DO NOT look into the fiber (laser) ports/connectors.
DO NOT look into the end of an optical cable connected to an optical

output.
DO NOT perform any procedures or adjustments that this instruction

manual does not describe.
During installation, maintenance, or testing of the optical ports, ONLY use

the test equipment qualified for Class 1 laser products!
II PCS-9611S Feeder Relay

Date: 2019-04-24
Preface
Incorporated components, such as LEDs, transceivers, and laser emitters,

are NOT user serviceable. Return units to NR for repair or replacement.
Equipment components are SENSITIVE to electrostatic discharge (ESD).

Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.
Insufficiently rated insulation can deteriorate under abnormal operating

conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.
SEVERE power and ground problems can occur on the communications

ports of this equipment as a result of using non-standard cables. Please
use the wiring method recommended in the manual for communication
terminals.
DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage
can result otherwise.
Use of controls or adjustments, or performance of procedures other than

those specified herein, may RESULT IN hazardous radiation exposure.
The firmware may be upgraded to add new features or enhance/modify

existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.
PCS-9611S Feeder Relay III

Date: 2019-04-24
Preface
Document Conventions
 The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
Glossary also contains definitions of important terms.
 Menu path is connected with the arrow "→" and bold.
For example: the access path of protection settings is: MainMenu→Settings→Protection

Settings
 Settings not in the table should be placed in brackets.
For example: the system setting [Opt_SysFreq]
 Cross-references are presented in italics.
For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1
 Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.
For example: press the button "ENT".
Symbols
 AND Gate
& & &
 OR Gate
>=1 >=1 >=1
 Comparator
 Binary signal Input
BI xxx
 Signal input
SIG xxx
IV PCS-9611S Feeder Relay

Date: 2019-04-24
Preface
 Setting input
SET xxx
 Enable input
EN xxx
 Timer
Optional definite-time or inverse-time characteristics
Timer
t
t
 Timer
Fixed delay pickup (10ms), fixed delay dropout (2ms)
10ms 2ms
 Timer
Settable delay pickup, fixed delay dropout
[Tset1] 0ms
 Timer
Fixed delay pickup, settable delay dropout
0ms [Tset2]
 Timer
Settable delay pickup, settable delay dropout
[Tset1] [Tset2]
 Generator
 Transformer
PCS-9611S Feeder Relay V

Date: 2019-04-24
Preface
 Reactor
 Motor
 Capacitor
 Busbar
 Circuit breaker
52
 Current transformer
3CT
*
 Voltage transformer
3VT
 Disconnector
VI PCS-9611S Feeder Relay

Date: 2019-04-24
Preface
 Earth
Three-phase Corresponding Relationship

Basic
A, B, C L1, L2, L3 R, Y, B
AN, BN, CN L1N, L2N, L3N RN,YN, BN
ABC L123 RYB
U (voltage) V U
Example
Ia, Ib, Ic, I0 IL1, IL2, IL3, IN IR, IY, IB, IN
Ua, Ub, Uc VL1, VL2, VL3 UR, UY, UB
Uab, Ubc, Uca VL12, VL23, VL31 URY, UYB, UBR
U0, U1, U2 VN, V1, V2 UN, U1, U2
Warranty
This product is covered by the standard NR 10-year warranty. For warranty details, please consult
the manufacturer or agent for warranty information.
Document Structure
This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using this device. To concentrate on
the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.
1 Introduction
Introduces the features of this device, summarizes functions and applications of the device.
2 Technical Data
Lists device specifications, type tests, and ratings.
3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, and provides the relevant logic diagrams.
4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.
PCS-9611S Feeder Relay VII

Date: 2019-04-24
Preface
5 Measurement
Provides information on viewing fundamental and metering quantities for voltages and currents,
as well as power and energy metering data.
6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.
7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.
8 Hardware
Describes the hardware of the PCS S series device family and provides general information on
the product structure and the modules’ information.
9 Settings
Provides a list of all PCS-9611S settings and their ranges, unit, steps, defaults. The organization
of the settings is similar to the settings organization in the device and in the PCS-Studio
configuration tool.
Appendix A Glossary
Describes the abbreviations adopted in this manual.
Document Revision History

PN: ZL_PCS-9611S_X_Technical Manual_EN_Overseas General_X
Current version: R1.01
Corresponding Version
Date Description of change
Document Software
R1.00 R1.00 2019-01-31  Form the original manual.
 Positive-sequence overvoltage protection is added;

R1.01 R1.00 2019-04-24
 Outmap settings are added.
VIII PCS-9611S Feeder Relay

Date: 2019-04-24
Introduction
1 Introduction
1
Table of Contents
1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-1
1.3 Features ............................................................................................................ 1-6
List of Figures
Figure 1.1-1 Functional diagram of PCS-9611S ....................................................................... 1-1
PCS-9611S Feeder Relay 1-a

Date: 2019-04-24
1 Introduction
1-b PCS-9611S Feeder Relay

Date: 2019-04-24
Introduction
1.1 Application
The PCS-9611S relay is a protection, control and monitoring unit for various primary equipment
1
(such as overhead line, underground cable and transformer etc.) on solidly grounded, impedance
grounded, Peterson coil grounded and ungrounded system. This relay is suitable for wall surface
mounted indoors or outdoors or flush mounted into a control panel.
The function diagram of this relay is shown in Figure 1.1-1.
Busbar
3VTs
52
27P 59P 59Q VTS 59G 81U 81O 81R 25 79

1VT
67P 32R
3CTs
*
50P 51P CTS 50BF 51Q
1CT
*
50G 51G SOTF 67G 37
1CT
*
51SEF 60/59 60/50 67SEF FR

1VT
Load
Figure 1.1-1 Functional diagram of PCS-9611S
1.2 Functions
1 Protection functions
PCS-9611S Feeder Relay 1-1

Date: 2019-04-24
1 Introduction
ANSI Protection Functions Remark

 Up to 6 stages with independent logic
1 

Voltage control element for each stage
Optional direction element for each stage, including
67P forward direction, reverse direction and non-direction
Phase overcurrent protection
50/51P  Optional definite-time characteristic and inverse-time
characteristic for each stage
 Selectable trip purpose or alarm purpose for each stage
 Harmonic control element for each stage
 Optional direction element for each stage, including
forward direction, reverse direction and non-direction
 Optional measured zero-sequence current or calculated
67G
Earth fault protection zero-sequence current
50/51G
 Optional definite-time characteristic and inverse-time
 Harmonic control element for each stage
 Only measured zero-sequence current is supported
A.67G Another group of earth fault
A.50/51G overcurrent protection
Negative-sequence overcurrent forward direction, reverse direction and non-direction
50/51Q
protection  Optional definite-time characteristic and inverse-time
 The measured zero-sequence current from the
high-precision CT is adopted
50/51SEF Sensitive earth fault protection
forward direction, reverse direction and non-direction
nd th
 Full-current RMS value includes 2 ~11 harmonic
50/51R RMS overcurrent protection
component
 Optional blocking condition, including circuit breaker
37 Undercurrent protection position and current criterion
1-2 PCS-9611S Feeder Relay

Date: 2019-04-24
Introduction
 Breaker failure protection and re-trip function

 Optional current criterion (phase overcurrent element,
50BF Breaker failure protection

zero-sequence overcurrent element, negative-sequence
overcurrent element)
1
 It can be initiated by current, circuit breaker position or
external binary input
 Two time delays
 One stage of phase overcurrent SOTF protection
 One stage of earth fault overcurrent SOTF protection
50PSOTF
Switch-on-to-fault protection  Harmonic control element
50GSOTF
 Voltage control element for phase overcurrent SOTF
protection
59P Overvoltage protection
 Optional phase voltage or phase-to-phase voltage
 Optional “1-out-of-3” logic or “3-out-of-3” logic
 Optional phase voltage or phase-to-phase voltage
27P Undervoltage protection  Optional “1-out-of-3” logic or “3-out-of-3” logic
 Check mode using circuit breaker position and current
criterion
 Blocked by instantaneous VT circuit failure
Negative-sequence overvoltage  Up to 2 stages with independent logic
59Q
protection  Selectable trip purpose or alarm purpose for each stage
Positive-sequence overvoltage  One stage of positive-sequence overvoltage protection
59Pos
protection  Selectable trip purpose or alarm purpose
 Optional measured zero-sequence voltage or calculated
59G Residual overvoltage protection
zero-sequence voltage
81O Overfrequency protection
 Voltage control element
81U Underfrequency protection
 Voltage control element
Frequency rate-of-change  Up to 6 stages with independent logic
81R
protection  Voltage control element
32R Reverse power protection

Date: 2019-04-24
1 Introduction

60/50 Unbalance current protection
1 60/59 Unbalance voltage protection



Up to 2 stages with independent logic
Selectable trip purpose or alarm purpose for each stage
 It can be triggered by on-load signal or circuit breaker
CLP Cold load pickup position
 Short resetting is supported
25 Synchrocheck  Independent logic for auto-reclosing and manually closing
 One shot or multi-shot
 3-pole AR
79 Auto-reclosing  It can be triggered by protection operation signal or
external binary input signal
 Supports synchronism check or dead charge check
CTS Current transformer supervision
VTS Voltage transformer supervision
TCS Tripping circuit supervision
2 Control functions
 Circuit breaker & disconnector control (Remote/Local)
 Synchronism check for remote and manual closing
3 Measurement functions
 Energy metering (active and reactive energy are calculated in import and export direction
respectively)
 Power (Apparent/Active/Reactive)
 Power factor
 Frequency
 Event recorder including 1024 disturbance items, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
 Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
4 Supervision functions
 VT circuit supervision
 CT circuit supervision
 Trip/Close coil supervision
 Self diagnostic
 DC power supply supervision
 System frequency supervision

Date: 2019-04-24
Introduction
5 Communication functions
 Up to four 10Base-T/100Base-TX copper Ethernet ports using IEC 61850, DNP3.0 or

IEC 60870-5-103 over TCP/IP 1
 Up to four 100Base-FX optical Ethernet ports using IEC 61850, DNP3.0 or IEC
60870-5-103 over TCP/IP
 Two RS-485 serial ports using IEC 60870-5-103
 One RS-485 serial port for clock synchronization
 Support GOOSE communication module using IEC 61850-8-1 GOOSE
 Full compatibility between IEC 61850 Editions 1 and 2
 Redundancy protocols PRP and HSR
 One front RJ45 port for debugging
6 User Interfaces
 Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and
set-point adjustment
 Push buttons for open/close, switch for selection between local and remote control, and
user's login and logout authority management
 4 Programmable operator pushbuttons with user-configurable labels
 Up to 15/18 (1/3U or 1/2U chassis) programmable target LEDs with user-configurable

labels
 1 RS-232 or RS-485 rear ports for printer
 Language switchover—English+ selected language
 Configuration tool—PCS-Studio
7 Additional functions
 User programmable logic
 Fault location
 Fault phase selection
 System phase sequences rotation function (ABC or ACB)
 Clock synchronization
 IRIG-B: IRIG-B via RS-485 differential level or TTL level
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 PPM: Pulse per minute (PPM) via RS-485 differential level or binary input

Date: 2019-04-24
1 Introduction
 IEEE1588: Clock message based on IEEE1588 via optical fiber interface
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network

1  SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol,

Modbus protocol and DNP3.0 protocol
 Cyber security
 NERC CIP
 IEC 62351
 IEC 62443
 IEEE 1686
1.3 Features
 Unified software and hardware platform, comprehensive power grid solutions of protection,
control, measurement and monitoring, easy to use and maintain.
 High reliability and redundancy design for drive systems of the sampling circuit and the output
circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD
can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of
output relays.
 Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analog programming are supported.
 Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be mixed with different I/O modules, with online self-check and
monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.
 Support memory check and error correction function, ensure high reliability and safety.
 Support the internet communication protocol of native PRP/HSR and RSTP.
 Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV
communication with multi-sampling rate.
 Full comply with cyber security standards, including IEC62443, IEC62351, IEEE1686,
NERC-CIP, support role based access control (RBAC), security audit, security encryption
communication and security tool, improve the cyber security capability of devices.

Date: 2019-04-24
Introduction
 Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.
1
 Settable secondary rated current (1A/5A) and settable voltage threshold of binary input
 Support small size and large size LCD, control and multifunction button
 Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.
 Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm 2 lead
 Multiple variants with case size 1/3 or 1/2 × 19"
 Protection class of front side is up to IP54
 PCS-Studio engineering tool is the application software on the user's PC for the interface with
PCS S series devices providing all the related functionality. It ranges from device configuration
to full substation design of bay integration.
 Support IEEE1588, IRIG-B clock synchronization
 Support actual system phase sequence, either ABC or ACB, incorrect connection of actual
phase sequence can automatically be verified and relevant protection functions can be
blocked.
 Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
abnormality in advance.
 Support setup up to 40 users and allow each user to own different password and access
authority.
 Fully integrates multi functions into one device and can realize the protection and monitoring
function of feeder and capacitor etc.
 Comprehensive functionality includes phase overcurrent protection, earth fault overcurrent
protection, negative-sequence overcurrent protection, sensitive earth fault protection,
overvoltage protection, undervoltage protection, frequency protection, reverse power
protection, breaker failure protection, undercurrent protection etc. The breaker failure,
reclosing, measuring, monitoring and control function are supported.
 The overcurrent protection is combined with harmonic blocking and cold load pickup logic,
which can prevent mal-operation affected by inrush current while the transformer is no-load
energized.
 Selectable IEC, ANSI inverse-time characteristic curves, also the curve can be defined by

Date: 2019-04-24
1 Introduction
users and the inverse-time drop-out curve selection is supported.
 Overvoltage and undervoltage protection support single phase and three phase operation
1
criteria setting, phase voltage and phase-to-phase voltage measurement mode are selectable,
which can be for various applications.
 Complete event recording function is provided: 64 latest protection operation reports, 1024
latest supervision records, 1024 latest control operation records, 1024 latest user operation
records and 1024 latest records of time tagged sequence of event (SOE) can be recorded.

Date: 2019-04-24
2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1 2

2.1.1 AC Current Input ................................................................................................................... 2-1
2.1.2 AC Voltage Input ................................................................................................................... 2-2
2.1.3 Power Supply ....................................................................................................................... 2-2
2.1.4 Binary Input .......................................................................................................................... 2-2
2.1.5 Binary Output........................................................................................................................ 2-4
2.2 Mechanical Specifications .............................................................................. 2-5

2.3 Ambient Temperature and Humidity Range .................................................. 2-6
2.4 Communication Port ....................................................................................... 2-6
2.4.1 EIA-485 Port ......................................................................................................................... 2-6
2.4.2 Ethernet Port ........................................................................................................................ 2-6
2.4.3 Optical Fiber Port ................................................................................................................. 2-7
2.4.4 Print Port ............................................................................................................................... 2-7
2.4.5 Clock Synchronization Port .................................................................................................. 2-7
2.5 Type Tests ........................................................................................................ 2-7

2.5.1 Environmental Tests ............................................................................................................. 2-7
2.5.2 Mechanical Tests .................................................................................................................. 2-8
2.5.3 Electrical Tests ...................................................................................................................... 2-8
2.5.4 Electromagnetic Compatibility .............................................................................................. 2-8
2.6 Certifications .................................................................................................. 2-10

2.7 Liquid Crystal Display (LCD) ........................................................................ 2-10
2.8 Terminals ........................................................................................................ 2-10
2.8.1 Ring Ferrule ........................................................................................................................ 2-10
2.8.2 Pin Ferrule .......................................................................................................................... 2-11
2.9 Measurement Scope and Accuracy ..............................................................2-11

2.10 Management Function..................................................................................2-11

Date: 2019-04-24
2 Technical Data
2.10.1 Control Performance ........................................................................................................ 2-11
2.10.2 Clock Performance ........................................................................................................... 2-12
2.10.3 Fault and Disturbance Recording..................................................................................... 2-12
2.10.4 Binary Input Signal ........................................................................................................... 2-12
2 2.11 Protective Functions ................................................................................... 2-12

2.11.1 Phase Overcurrent Protection (50/51P) ........................................................................... 2-12
2.11.2 Earth Fault Protection (50/51G) ....................................................................................... 2-13
2.11.3 Another Group of Earth Fault Overcurrent Protection ...................................................... 2-14
2.11.4 Negative-sequence Overcurrent Protection (50/51Q)...................................................... 2-14
2.11.5 Sensitive Earth Fault Protection (50/51SEF) ................................................................... 2-15
2.11.6 RMS Overcurrent Protection (50/51R) ............................................................................. 2-16
2.11.7 Phase Overvoltage Protection (59P) ................................................................................ 2-16
2.11.8 Residual Overvoltage Protection (59G) ........................................................................... 2-17
2.11.9 Negative-sequence Overvoltage Protection (59Q) .......................................................... 2-17
2.11.10 Positive-sequence Overvoltage Protection (59Pos) ...................................................... 2-17
2.11.11 Phase Undervoltage Protection (27P) ............................................................................ 2-17
2.11.12 Overfrequency Protection (81O) .................................................................................... 2-18
2.11.13 Underfrequency Protection (81U)................................................................................... 2-18
2.11.14 Frequency Rate-of-change Protection (81R) ................................................................. 2-18
2.11.15 Reverse Power Protection (32R).................................................................................... 2-18
2.11.16 Undercurrent Protection (37) .......................................................................................... 2-19
2.11.17 Breaker Failure Protection (50BF).................................................................................. 2-19
2.11.18 Unbalance Current Protection (60/50) ........................................................................... 2-19
2.11.19 Unbalance Voltage Protection (60/59) ........................................................................... 2-20
2.11.20 Auto-reclosing (79) ......................................................................................................... 2-20
2.11.21 Transient Overreach ....................................................................................................... 2-20
2.11.22 Fault Locator ................................................................................................................... 2-20

Date: 2019-04-24
2 Technical Data
2.1 Electrical Specifications
“System phase sequence”, which can be set by PCS-Studio, this setting

informs the device of the actual system phase sequence, either ABC or 2
ACB. CT and VT inputs on the device, labeled as A, B and C, must be
connected to system phase A, B and C for correct operation.
2.1.1 AC Current Input
 Conventional AC current input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated current (In) 1A/5A (Settable)
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.05VA/phase @1A, <0.25VA/phase @5A
Number Up to 5 current inputs according to various applications
 AC current input for sensitive earth fault protection
Rated current (In) 1A
Linear to 0.01A~5A
Thermal withstand
-continuously 20A
-for 10s 100A
-for 1s 300A
-for half a cycle 750A
Burden <0.15VA/phase @1A

Date: 2019-04-24
2 Technical Data
2.1.2 AC Voltage Input
Phase rotation ABC or ACB
Nominal frequency (fn) 50Hz, 60Hz
Rated voltage (Un) 100V~130V
2 Linear to 1V~300V
Thermal withstand Phase-to-ground Phase-to-phase
-continuously 300V 519V
-10s 600V 1038V
-1s 660V 1141V
Burden at rated <0.10VA/phase @100V
Number Up to 5 voltage inputs according to various applications
2.1.3 Power Supply
Standard IEC 61000-4-29:2000
100Vac/110Vac/115Vac/120Vac
Rated voltage 110Vdc/125Vdc/220Vdc/250Vdc 127Vac/220Vac/230Vac/240Vac
250Vac
Permissible voltage range 88~300Vdc 88~275Vac
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Burden
Quiescent condition <15W
Operating condition <20W
2.1.4 Binary Input
Settable pickup voltage and dropout voltage
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA
On value (default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc
Off value (default set) <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc

Date: 2019-04-24
2 Technical Data
Withstand voltage 2000Vac, 2800Vdc (continuously)
Up to 34 (6U, 1/3, ring ferrule), 41 (6U, 1/3, pin ferrule), 84 (6U, 1/2,
Number ring ferrule) or 105 (6U, 1/2, pin ferrule) binary inputs according to
various hardware configurations
2
Rated voltage 110Vac 220Vac
Rated current drain 0.73mA 1.47mA
On value (default set) 69.3~132Vac 138.6~264Vac
Off value (default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 24V 48V
Rated current drain 0.16mA 0.32mA
On value (default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (default set) <12V <24V
Maximum permissible voltage 300Vdc

Date: 2019-04-24
2 Technical Data
2.1.5 Binary Output
Tripping/signaling contact
Output mode Potential free contact
Max. system voltage 250Vac, 300Vdc
2 Continuous carry 10A
Pickup time (Typical value) <5ms
Dropout time (Resistive load) <6ms
0.5A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
0.5A@48Vdc
0.35A@110Vdc
Cyclic Capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc
0.15A@250Vdc
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Number ring ferrule) or 56 (6U, 1/2, pin ferrule) binary outputs according to
Heavy-capacity tripping contact
Output mode Potential free contact
MOV Protection (maximum voltage ) 350Vdc, 275Vac
Continuous carry 10A
Pickup time (Typical value) <1ms

Date: 2019-04-24
2 Technical Data
Dropout time (Resistive load) <10ms
10A@48V
10A@110V
Breaking capacity (L/R=40ms)
10A@125V
10A@250V 2
10A@48V L/R=40ms
Cyclic Capacity (4cycles in 1 second,
10A@110V L/R=40ms
followed by 2 minutes idle for thermal
10A@125V L/R=40ms
dissipation)
10A@250V L/R=20ms
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Up to 4 (6U, 1/3, ring ferrule) or 12 (6U, 1/2, ring ferrule)

Number heavy-capacity binary outputs according to various hardware
configurations
2.2 Mechanical Specifications
Chassis color Silver grey
Approx. 8.66kg (6U, 1/2)

Weight per device
Approx. 6.93kg (6U, 1/3)
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection Class
Standard IEC 60529-2013
Front side IP52
Other sides IP50
Rear side, connection terminals IP20

Date: 2019-04-24
2 Technical Data
2.3 Ambient Temperature and Humidity Range
Standard IEC 60255-1:2009
-40°C to +80°C (Readability of display may be impaired below -20°C

Operating temperature
2 and above 70°C)
Transport and storage temperature

-40°C to +80°C
range
Permissible humidity 5%~95%, without condensation
Pollution degree Ⅱ
Altitude <3000m
2.4 Communication Port
2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997 or Modbus
Max. capacity 32
Max. transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port
Connector type RJ-45 LC
Transmission rate 100Mbits/s
Transmission standard 100Base-TX 100Base-FX
Max. transmission distance 100m 2km (1310nm)
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850

Date: 2019-04-24
2 Technical Data
2.4.3 Optical Fiber Port
For Station Level
Characteristic Glass optical fiber
Connector type LC
Fiber type Multi mode 2

Max. transmission distance 2km
Wave length 1310nm
Transmission power 50μm: -24dBm 62.5μm: -20dBm
Minimum receiving power Min -31dBm
Margin 50μm: -7dBm 62.5μm: -9dBm
2.4.4 Print Port
Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
2.4.5 Clock Synchronization Port
Type RS-485 serial port
Input Demodulated IRIG-B or PPS
Nominal Voltage 5Vdc+10%
Maximum Voltage 8Vdc
Input Impedance 2.5kΩ
Isolation 500Vdc
2.5 Type Tests
2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007

Date: 2019-04-24
2 Technical Data
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration IEC 60255-21-1:1988 Class Ⅰ
Shock and bump IEC 60255-21-2:1988 Class Ⅰ

2
2.5.3 Electrical Tests
Standard IEC 60255-27:2013
Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 61000-4-2:2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radiated amplitude-modulated
Radio frequency interference tests 10V/m (rms), f=80~1000MHz, 14000~2700MHz
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
IEC 60255-26:2013
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅳ, 4kV, 5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
Surge immunity test IEC 60255-26:2013

Date: 2019-04-24
2 Technical Data
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26:2013
Conducted RF Electromagnetic
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ, 10Vrms, 150 2
kHz~80MHz
Disturbance
Spot frequency
10V/m (rms), f=27MHz/68MHz
Power Frequency Magnetic Field IEC 61000-4-8: 2009
Immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2016
Pulse Magnetic Field Immunity
class Ⅴ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2016
immunity class Ⅴ, 100kHz & 1MHz–100A/m
IEC 60255-26:2013
Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average
0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average
IEC 60255-26:2013
30MHz~230MHz: 40dB (μV/m) quasi peak @10m,
50dB (μV/m) quasi peak @3m

Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,
Radiated emission 57dB (μV/m) quasi peak @3m
1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)
peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)
peak @3m
Auxiliary power supply performance IEC 60255-26:2013

Date: 2019-04-24
2 Technical Data
- Voltage dips
Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions
50ms for interruption without rebooting without energy storage board
(Typical configuration)
500ms for interruption without rebooting with energy storage board
2 (Typical configuration)
2.6 Certifications
 ISO9001:2008
 ISO14001:2004
 OHSAS18001:2007
 ISO10012:2003
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 Products safety (LVD): 2014/35/EU, EN60255-27:2014
2.7 Liquid Crystal Display (LCD)
Type Resolution
Large size 320x240 pixels
Small size 240x160 pixels
2.8 Terminals
2.8.1 Ring Ferrule
Connection Type Wire Size Screw Type Torque
AC current Screw terminals, 1.5~4mm2 lead M4 1.6~1.8 N⋅m
2
AC voltage Screw terminals, 0.8~4mm lead M4 1.6~1.8 N⋅m
Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N⋅m
2
Contact I/O Screw terminals, 0.8~4mm lead M4 0.8~1.4 N⋅m
2
Grounding (Earthing) Connection BVR type, 0.8~4mm lead M3 0.6~0.8 N⋅m

Date: 2019-04-24
2 Technical Data
2.8.2 Pin Ferrule
Connection Type Wire Size Screw Type Torque
Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N⋅m
2
Contact I/O Screw terminals, 0.3~3.3mm lead M2.5 0.4~0.6 N⋅m
2
2.9 Measurement Scope and Accuracy
Item Range Accuracy
Phase range 0°~ 360° ≤±1°
Frequency fn±3 Hz ≤ 0.01Hz
Currents from protection measurement current transformers
≤ 1.0% of rating (0.05~1.00In)

Current 0.05~4.00In
≤ 0.5% of applied quantities (1.00~4.00In)
≤ 1.0% of rating (0.05~1.00Un)

Voltage 0.05~1.50Un
≤ 0.5% of applied quantities (1.00~1.50Un)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Active power (W)
0.05~4.00In ≤ 1.0% of applied quantities (1.00~4.00In, 1.00~1.50Un)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Reactive power (VAr)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Apparent power (VA)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Energy (Wh)
0.05~1.50Un ≤ 2.0% of rating (0.05~1.00In, 0.05~1.00Un)

Energy (VAh)
2.10 Management Function
2.10.1 Control Performance
Control mode Local or remote

Date: 2019-04-24
2 Technical Data
Response time of local control ≤1s
Response time of remote control ≤3s
2.10.2 Clock Performance
Real time clock accuracy ≤1s/day

2 Accuracy of GPS synchronization ≤1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.10.3 Fault and Disturbance Recording

Settable pre-disturbance, post-disturbance and maximum recorded
Duration & Recording position
duration
Sampling rate Up to 9.6kHz
2.10.4 Binary Input Signal
Resolution of binary input signal ≤1ms
Binary input mode Potential-free contact
2.11 Protective Functions
2.11.1 Phase Overcurrent Protection (50/51P)
Without direction controlled element
Pickup current 1.0×Setting
Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater
Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater
Pickup time ≤25ms (at 2 times current setting)
Operating time delay accuracy

≤1%×Setting or 25ms (at 2 times current setting)
(Definite-time characteristics)
≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
(Inverse-time characteristics)
Dropout time accuracy (Definite-time
≤1%×Setting or 30ms
characteristics)
Dropout time accuracy (Inverse-time
≤5% of calculated value or 30ms
characteristics)
Dropout ratio 0.95

Date: 2019-04-24
2 Technical Data
With direction controlled element
Pickup time ≤40ms (at 2 times current setting) 2

characteristics)
characteristics)
Dropout ratio 0.95
Phase angel accuracy ≤3°
2.11.2 Earth Fault Protection (50/51G)

characteristics)
characteristics)
Dropout ratio 0.95

Date: 2019-04-24
2 Technical Data

2 characteristics)

characteristics)
Dropout ratio 0.95
2.11.3 Another Group of Earth Fault Overcurrent Protection

characteristics)
characteristics)
Dropout ratio 0.95
2.11.4 Negative-sequence Overcurrent Protection (50/51Q)

characteristics)
Dropout time accuracy (Inverse-time ≤5% of calculated value or 30ms

Date: 2019-04-24
2 Technical Data
characteristics)
Dropout ratio 0.95

2

characteristics)
characteristics)
Dropout ratio 0.95
2.11.5 Sensitive Earth Fault Protection (50/51SEF)
Current setting accuracy ≤0.5%×Setting or 1mA, whichever is greater

Operating time delay accuracy ≤5% of calculated value + 0.5% current tolerance or 35ms
(Inverse-time characteristics) (1.2≤I/Ip≤30)

characteristics)
characteristics)
Dropout ratio 0.95

Date: 2019-04-24
2 Technical Data
Current setting accuracy ≤0.5%×Setting or 1mA, whichever is greater
2 Pickup time ≤40ms (at 2 times current setting)

Operating time delay accuracy ≤5% of calculated value + 0.5% current tolerance or 35ms
(Inverse-time characteristics) (1.2≤I/Ip≤30)

characteristics)
characteristics)
Dropout ratio 0.95
2.11.6 RMS Overcurrent Protection (50/51R)
Operating time delay accuracy ≤1%×Setting or 25ms (at 2 times current setting)
Dropout time accuracy ≤1%×Setting or 30ms
Dropout ratio 0.95
2.11.7 Phase Overvoltage Protection (59P)
Pickup voltage 1.0×Setting
Pickup time ≤35ms (at 1.1 times voltage setting)

≤1%×Setting or 35ms (at 1.1 times voltage setting)
Operating time accuracy
≤5% of calculated value + 1% voltage tolerance or 40ms (1.1≤U/Up≤2)
Dropout ratio Settable 0.93~1.00, default value: 0.98

Date: 2019-04-24
2 Technical Data
2.11.8 Residual Overvoltage Protection (59G)
Operating time delay accuracy ≤1%×Setting or 40ms (at 1.1 times voltage setting) 2
Dropout time accuracy ≤30ms
2.11.9 Negative-sequence Overvoltage Protection (59Q)
Operating time delay accuracy ≤1%×Setting or 40ms (at 1.1 times voltage setting)
2.11.10 Positive-sequence Overvoltage Protection (59Pos)
Operating time delay accuracy ≤1%×Setting or 40ms (at 1.1 times voltage setting)
2.11.11 Phase Undervoltage Protection (27P)

≤1%×Setting or 35ms (at 0.9 times voltage setting)
≤5% of calculated value + 1% voltage tolerance or 50ms (U/Up≤0.9)
characteristics)

Date: 2019-04-24
2 Technical Data
2.11.12 Overfrequency Protection (81O)
Pickup frequency 1.0×Setting

2 Frequency setting accuracy ≤ 0.01Hz
Pickup time ≤70ms
Time delay accuracy ≤1%×Setting+70ms
Dropout frequency 1.0×Setting
2.11.13 Underfrequency Protection (81U)
Frequency setting accuracy ≤ 0.01Hz
Pickup time ≤70ms
2.11.14 Frequency Rate-of-change Protection (81R)
Frequency rate-of-change setting

≤ 0.02Hz
accuracy
Pickup time ≤70ms
2.11.15 Reverse Power Protection (32R)
Pickup power 1.0×Setting
Power setting accuracy ≤2%×Setting or 0.01pu, whichever is greater
Current setting accuracy ≤1%×Setting or 0.01pu, whichever is greater

Date: 2019-04-24
2 Technical Data
Pickup time ≤25ms (at 2 times power setting)
Operating time delay accuracy ≤1%×Setting or 25ms (at 2 times voltage setting)
Dropout ratio 0.95 2

2.11.16 Undercurrent Protection (37)
Current setting Accuracy ≤1%×Setting or 0.01In, whichever is greater
Pickup time ≤25ms (at 0.5 times current setting)
Operating time delay accuracy ≤1%×Setting or 25ms (at 0.5 times current setting)
Drop-out time accuracy ≤30ms
Dropout ratio 1.1
2.11.17 Breaker Failure Protection (50BF)
Current setting Accuracy ≤1%×Setting or 0.01In, whichever is greater
Pickup time ≤20ms
Dropout time <20ms
Dropout ratio 1
2.11.18 Unbalance Current Protection (60/50)
Dropout ratio 0.95

Date: 2019-04-24
2 Technical Data
2.11.19 Unbalance Voltage Protection (60/59)
2 Operating time delay accuracy ≤1%×Setting or 35ms (at 1.1 times voltage setting)
Dropout ratio 0.95
2.11.20 Auto-reclosing (79)

Phase angel accuracy (synchronism
≤2°
check)
Voltage setting accuracy
≤1%×Setting or 0.1V, whichever is greater
(synchronism check)
Frequency setting accuracy
0.01Hz
(synchronism check)
Time delay accuracy (synchronism
≤1%×Setting+20ms
check)
Time delay accuracy (Reclaim) ≤1%×Setting+20ms
Time delay accuracy (Reclosing) ≤1%×Setting+20ms
2.11.21 Transient Overreach
Accuracy for all high-speed protection ≤2%
2.11.22 Fault Locator

Accuracy for multi-phase faults with < ±2.5%
single end feed
Tolerance will be higher in case of single-phase fault with high ground resistance.

Date: 2019-04-24
Table of Contents
3.1 Three-phase Current Element (TCUR3P) ....................................................... 3-1

3.1.1 Function Description............................................................................................................. 3-1
3.1.2 Function Block Diagram ....................................................................................................... 3-2
3.1.3 I/O Signals ............................................................................................................................ 3-2 3

3.1.4 Settings ................................................................................................................................. 3-3
3.2 Three-phase Voltage Element (TVOL3P)........................................................ 3-3

3.2.3 I/O Signals ............................................................................................................................ 3-4
3.2.4 Settings ................................................................................................................................. 3-5
3.3 One-phase Current Element (TCUR1P).......................................................... 3-5

3.3.3 I/O Signals ............................................................................................................................ 3-6
3.3.4 Settings ................................................................................................................................. 3-6
3.4 One-phase Voltage Element (TVOL1P) .......................................................... 3-6

3.4.3 I/O Signals ............................................................................................................................ 3-7
3.4.4 Settings ................................................................................................................................. 3-7
3.5 Phase Overcurrent Protection (50/51P) ......................................................... 3-7

3.5.2 Function Block Diagram ..................................................................................................... 3-19
3.5.3 I/O Signal ............................................................................................................................ 3-20
3.5.4 Logic ................................................................................................................................... 3-21
3.5.5 Settings ............................................................................................................................... 3-21

Date: 2019-04-24
3.6 Earth Fault Overcurrent Protection (50/51G) ............................................... 3-37

3.6.1 Function Description........................................................................................................... 3-37
3.6.3 I/O Signal ............................................................................................................................ 3-46
3.6.4 Logic ................................................................................................................................... 3-47
3.6.5 Settings ............................................................................................................................... 3-47
3.7 Another Group of Earth Fault Overcurrent Protection ............................... 3-63

3 3.7.1 Function Description........................................................................................................... 3-63
3.7.3 I/O Signal ............................................................................................................................ 3-69
3.7.4 Logic ................................................................................................................................... 3-70
3.7.5 Settings ............................................................................................................................... 3-70
3.8 Negative-sequence Overcurrent Protection (50/51Q) ................................. 3-82

3.8.3 I/O Signal ............................................................................................................................ 3-91
3.8.4 Logic ................................................................................................................................... 3-92
3.8.5 Settings ............................................................................................................................... 3-92
3.9 Sensitive Earth Fault Protection (50/51SEF) ............................................... 3-97

3.9.2 Function Block Diagram ................................................................................................... 3-106
3.9.3 I/O Signal .......................................................................................................................... 3-106
3.9.4 Logic ................................................................................................................................. 3-107
3.9.5 Settings ............................................................................................................................. 3-107
3.10 RMS Overcurrent Protection (50/51R).......................................................3-118

3.10.1 Function Description....................................................................................................... 3-118
3.10.2 Function Block Diagram ................................................................................................. 3-121
3.10.3 I/O Signal ........................................................................................................................ 3-122
3.10.4 Logic ............................................................................................................................... 3-122
3.10.5 Settings ........................................................................................................................... 3-122

Date: 2019-04-24
3.11 Phase Overvoltage Protection (59P) ........................................................ 3-123

3.11.1 Function Description ....................................................................................................... 3-123
3.11.3 I/O Signal ........................................................................................................................ 3-129
3.11.4 Logic ............................................................................................................................... 3-130
3.11.5 Settings ........................................................................................................................... 3-130
3.12 Residual Overvoltage Protection (59G) ................................................... 3-134

3.12.1 Function Description....................................................................................................... 3-134 3
3.12.3 I/O Signal ........................................................................................................................ 3-137
3.12.4 Logic ............................................................................................................................... 3-137
3.12.5 Settings ........................................................................................................................... 3-137
3.13 Negative-sequence Overvoltage Protection (59Q) .................................. 3-138

3.13.3 I/O Signals ...................................................................................................................... 3-141
3.13.4 Logic ............................................................................................................................... 3-142
3.13.5 Settings ........................................................................................................................... 3-142
3.14 Positive-sequence Overvoltage Protection (59Pos) ............................... 3-143

3.14.3 I/O Signals ...................................................................................................................... 3-146
3.14.4 Logic ............................................................................................................................... 3-146
3.14.5 Settings ........................................................................................................................... 3-146
3.15 Phase Undervoltage Protection (27P) ...................................................... 3-147

3.15.3 I/O Signal ........................................................................................................................ 3-154
3.15.4 Logic ............................................................................................................................... 3-155
3.15.5 Settings ........................................................................................................................... 3-156
PCS-9611S Feeder Relay 3-c

Date: 2019-04-24
3.16 Overfrequency Protection (81O)............................................................... 3-160

3.16.3 I/O Signals ...................................................................................................................... 3-162
3.16.4 Logic ............................................................................................................................... 3-163
3.16.5 Settings ........................................................................................................................... 3-163
3.17 Underfrequency Protection (81U)............................................................. 3-164

3 3.17.1 Function Description....................................................................................................... 3-164
3.17.3 I/O Signals ...................................................................................................................... 3-166
3.17.4 Logic ............................................................................................................................... 3-167
3.17.5 Settings ........................................................................................................................... 3-167
3.18 Frequency Rate-of-change Protection (81R) ........................................... 3-168

3.18.3 I/O Signals ...................................................................................................................... 3-170
3.18.4 Logic ............................................................................................................................... 3-171
3.18.5 Settings ........................................................................................................................... 3-171
3.19 Reverse Power Protection (32R) .............................................................. 3-172

3.19.3 I/O Signals ...................................................................................................................... 3-175
3.19.4 Logic ............................................................................................................................... 3-176
3.19.5 Settings ........................................................................................................................... 3-176
3.20 Cold Load Pickup Logic (CLP) ................................................................. 3-177

3.20.3 I/O Signals ...................................................................................................................... 3-177
3.20.4 Logic ............................................................................................................................... 3-178
3.20.5 Settings ........................................................................................................................... 3-178
3-d PCS-9611S Feeder Relay

Date: 2019-04-24
3.21 Undercurrent Protection (37) .................................................................... 3-181

3.21.3 I/O Signals ...................................................................................................................... 3-185
3.21.4 Logic ............................................................................................................................... 3-186
3.21.5 Settings........................................................................................................................... 3-186
3.22 Breaker Failure Protection (50BF) ............................................................ 3-187

3.22.1 Function Description....................................................................................................... 3-187 3
3.22.3 I/O Signals ...................................................................................................................... 3-189
3.22.4 Logic ............................................................................................................................... 3-190
3.22.5 Settings ........................................................................................................................... 3-191
3.23 Switch-on-to-Fault Protection (SOTF) ...................................................... 3-192

3.23.3 I/O Signals ...................................................................................................................... 3-193
3.23.4 Logic ............................................................................................................................... 3-194
3.23.5 Settings ........................................................................................................................... 3-196
3.24 Unbalance Current Protection (60/50) ...................................................... 3-197

3.24.3 I/O Signals ...................................................................................................................... 3-200
3.24.4 Logic ............................................................................................................................... 3-200
3.24.5 Settings ........................................................................................................................... 3-200
3.25 Unbalance Voltage Protection (60/59) ...................................................... 3-201

3.25.3 I/O Signals ...................................................................................................................... 3-204
3.25.4 Logic ............................................................................................................................... 3-204
3.25.5 Settings ........................................................................................................................... 3-204
PCS-9611S Feeder Relay 3-e

Date: 2019-04-24
3.26 Automatic Reclosure (79).......................................................................... 3-205

3.26.3 I/O Signals ...................................................................................................................... 3-214
3.26.4 Settings ........................................................................................................................... 3-215
3.27 VT Circuit Supervision (VTS) .................................................................... 3-216

3.27.1 General Application ........................................................................................................ 3-216
3 3.27.2 Function Description....................................................................................................... 3-217
3.27.3 Function Block ................................................................................................................ 3-217
3.27.4 I/O Signals ...................................................................................................................... 3-217
3.27.5 Logic ............................................................................................................................... 3-218
3.27.6 Settings ........................................................................................................................... 3-218
3.28 CT Circuit Supervision (CTS).................................................................... 3-219

3.28.3 I/O Signals ...................................................................................................................... 3-219
3.28.4 Logics ............................................................................................................................. 3-220
3.28.5 Settings ........................................................................................................................... 3-220
List of Figures
Figure 3.5-1 The enabling and blocking logic of phase overcurrent protection .................. 3-8
Figure 3.5-2 Logic diagram of the fault detector element of phase overcurrent protection3-8
Figure 3.5-3 Logic diagram of the voltage control element of phase overcurrent protection3-9
Figure 3.5-4 The direction element operation characteristics when phase A voltage is
polarized ..................................................................................................................................... 3-10
Figure 3.5-5 Logic diagram of forward and reverse direction element of phase overcurrent
protection ................................................................................................................................... 3-12
Figure 3.5-6 Logic diagram of harmonic control element of phase overcurrent protection3-13
Figure 3.5-7 Definite-time operation characteristic curve of phase overcurrent protection3-15
Figure 3.5-8 Inverse-time operation characteristic curve of phase overcurrent protection3-16
3-f PCS-9611S Feeder Relay

Date: 2019-04-24
Figure 3.5-9 Definite-time dropout characteristic of phase overcurrent protection .......... 3-17
Figure 3.5-10 Inverse-time dropout characteristic curve of phase overcurrent protection3-18
Figure 3.5-11 Inverse-time dropout characteristic of phase overcurrent protection......... 3-19
Figure 3.5-12 Logic diagram of phase overcurrent protection ............................................ 3-21
Figure 3.6-1 The enabling and blocking logic of earth fault overcurrent protection ......... 3-38
Figure 3.6-2 Logic diagram of the fault detector element of earth fault overcurrent
protection ................................................................................................................................... 3-38
Figure 3.6-3 The direction element operation characteristics when zero-sequence voltage
is polarized ................................................................................................................................. 3-39
3
Figure 3.6-4 Logic diagram of forward and reverse direction element of earth fault
overcurrent protection .............................................................................................................. 3-40
Figure 3.6-5 Logic diagram of harmonic control element of earth fault overcurrent
protection ................................................................................................................................... 3-41
Figure 3.6-6 Definite-time operation characteristic curve of earth fault overcurrent

protection ................................................................................................................................... 3-42
Figure 3.6-7 Inverse-time operation characteristic curve of earth fault overcurrent

protection ................................................................................................................................... 3-43
Figure 3.6-8 Definite-time dropout characteristic of earth fault overcurrent protection ... 3-44
Figure 3.6-9 Inverse-time dropout characteristic curve of earth fault overcurrent protection3-45
Figure 3.6-10 Inverse-time dropout characteristic of earth fault overcurrent protection . 3-46
Figure 3.6-11 Logic diagram of earth fault overcurrent protection...................................... 3-47
Figure 3.7-1 The enabling and blocking logic of another group of earth fault overcurrent
protection ................................................................................................................................... 3-63
Figure 3.7-2 Logic diagram of the fault detector element of another group of earth fault
Figure 3.7-3 Definite-time operation characteristic curve of another group of earth fault
Figure 3.7-4 Inverse-time operation characteristic curve of another group of earth fault
Figure 3.7-5 Definite-time dropout characteristic of another group of earth fault overcurrent
protection ................................................................................................................................... 3-67
Figure 3.7-6 Inverse-time dropout characteristic curve of another group of earth fault
Figure 3.7-7 Inverse-time dropout characteristic of another group of earth fault overcurrent
PCS-9611S Feeder Relay 3-g

Date: 2019-04-24
protection ................................................................................................................................... 3-69
Figure 3.7-8 Logic diagram of another group of earth fault overcurrent protection ......... 3-70
Figure 3.8-1 The enabling and blocking logic of negative-sequence overcurrent protection3-83
Figure 3.8-2 Logic diagram of the fault detector element of negative-sequence overcurrent
protection ................................................................................................................................... 3-83
Figure 3.8-3 The direction element operation characteristics of negative-sequence

Figure 3.8-4 Logic diagram of forward and reverse direction element of negative-sequence
3 overcurrent protection .............................................................................................................. 3-85
Figure 3.8-5 Definite-time operation characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-86
Figure 3.8-6 Inverse-time operation characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-87
Figure 3.8-7 Definite-time dropout characteristic of negative-sequence overcurrent

protection ................................................................................................................................... 3-89
Figure 3.8-8 Inverse-time dropout characteristic curve of negative-sequence overcurrent

protection ................................................................................................................................... 3-90
Figure 3.8-9 Inverse-time dropout characteristic of negative-sequence overcurrent

protection ................................................................................................................................... 3-91
Figure 3.8-10 Logic diagram of negative-sequence overcurrent protection ...................... 3-92
Figure 3.9-1 The enabling and blocking logic of sensitive earth fault protection ............. 3-98
Figure 3.9-2 Logic diagram of the fault detector element of sensitive earth fault protection3-98
Figure 3.9-3 The direction element operation characteristics of sensitive earth fault
protection ................................................................................................................................... 3-99
Figure 3.9-4 Logic diagram of forward and reverse direction element of sensitive earth fault
protection ................................................................................................................................. 3-100
Figure 3.9-5 Definite-time operation characteristic curve of sensitive earth fault protection3-102
Figure 3.9-6 Inverse-time operation characteristic curve of sensitive earth fault protection3-103
Figure 3.9-7 Definite-time dropout characteristic of sensitive earth fault protection ..... 3-104
Figure 3.9-8 Inverse-time dropout characteristic curve of sensitive earth fault protection3-105
Figure 3.9-9 Inverse-time dropout characteristic of sensitive earth fault protection ...... 3-106
Figure 3.9-10 Logic diagram of sensitive earth fault protection ........................................ 3-107
Figure 3.10-1 The enabling and blocking logic of RMS overcurrent protection .............. 3-119
3-h PCS-9611S Feeder Relay

Date: 2019-04-24
Figure 3.10-2 Logic diagram of the fault detector element of RMS overcurrent protection3-119
Figure 3.10-3 Definite-time operation characteristic curve of RMS overcurrent protection3-120
Figure 3.10-4 Definite-time dropout characteristic of RMS overcurrent protection ........ 3-121
Figure 3.10-5 Logic diagram of RMS overcurrent protection ............................................. 3-122
Figure 3.11-1 The enabling and blocking logic of phase overvoltage protection ............ 3-124
Figure 3.11-2 Logic diagram of the fault detector element of phase overvoltage protection3-125
Figure 3.11-3 Definite-time operation characteristic curve of phase overvoltage protection3-126
Figure 3.11-4 Inverse-time operation characteristic curve of phase overvoltage protection3-127 3

Figure 3.11-5 Definite-time dropout characteristic of phase overvoltage protection ...... 3-128
Figure 3.11-6 Logic diagram of phase overvoltage protection .......................................... 3-130
Figure 3.12-1 The enabling and blocking logic of residual overvoltage protection ........ 3-134
Figure 3.12-2 Logic diagram of the fault detector element of residual overvoltage
protection ................................................................................................................................. 3-135
Figure 3.12-3 Definite-time operation characteristic curve of residual overvoltage

protection ................................................................................................................................. 3-135
Figure 3.12-4 Definite-time dropout characteristic of residual overvoltage protection .. 3-136
Figure 3.12-5 Logic diagram of residual overvoltage protection ....................................... 3-137
Figure 3.13-1 Logic diagram of enabling/disabling negative-sequence overvoltage

protection ................................................................................................................................. 3-139
Figure 3.13-2 Logic diagram of the fault detector of negative-sequence overvoltage

protection ................................................................................................................................. 3-139
Figure 3.13-3 Operation characteristic curve of negative-sequence overvoltage protection3-140
Figure 3.13-4 Definite-time dropout characteristic of negative-sequence overvoltage

protection ................................................................................................................................. 3-141
Figure 3.13-5 Logic diagram of negative-sequence overvoltage protection .................... 3-142
Figure 3.14-1 Logic diagram of enabling/disabling positive-sequence overvoltage

protection ................................................................................................................................. 3-143
Figure 3.14-2 Logic diagram of the fault detector of positive-sequence overvoltage

protection ................................................................................................................................. 3-144
Figure 3.14-3 Operation characteristic curve of positive-sequence overvoltage protection3-144
Figure 3.14-4 Definite-time dropout characteristic of positive-sequence overvoltage

protection ................................................................................................................................. 3-145
PCS-9611S Feeder Relay 3-i

Date: 2019-04-24
Figure 3.14-5 Logic diagram of positive-sequence overvoltage protection ..................... 3-146
Figure 3.15-1 The enabling and blocking logic of phase undervoltage protection ......... 3-148
Figure 3.15-2 Logic diagram of the fault detector element of phase undervoltage protection
................................................................................................................................................... 3-150
Figure 3.15-3 Definite-time operation characteristic curve of phase undervoltage protection

................................................................................................................................................... 3-151
Figure 3.15-4 Inverse-time operation characteristic curve of phase undervoltage protection

................................................................................................................................................... 3-152
3 Figure 3.15-5 Definite-time dropout characteristic of undervoltage protection ............... 3-153
Figure 3.15-6 Logic diagram of phase undervoltage protection ........................................ 3-155
Figure 3.16-1 Logic diagram of enabling/disabling overfrequency protection ................ 3-161
Figure 3.16-2 Logic diagram of the fault detector of overfrequency protection .............. 3-161
Figure 3.16-3 Operation characteristic curve of overfrequency protection ..................... 3-162
Figure 3.16-4 Function block diagram of overfrequency protection ................................. 3-162
Figure 3.16-5 Logic diagram of overfrequency protection ................................................. 3-163
Figure 3.17-1 Logic diagram of enabling/disabling underfrequency protection .............. 3-165
Figure 3.17-2 Logic diagram of the fault detector of underfrequency protection ............ 3-165
Figure 3.17-3 Operation characteristic curve of underfrequency protection ................... 3-166
Figure 3.17-4 Function block diagram of underfrequency protection............................... 3-166
Figure 3.17-5 Logic diagram of underfrequency protection ............................................... 3-167
Figure 3.18-1 Logic diagram of enabling/disabling frequency rate-of-change protection3-169
Figure 3.18-2 Logic diagram of the fault detector of frequency rate-of-change protection3-169
Figure 3.18-3 Operation characteristic curve of frequency rate-of-change protection ... 3-170
Figure 3.18-4 Function block diagram of frequency rate-of-change protection .............. 3-170
Figure 3.18-5 Logic diagram of frequency rate-of-change protection............................... 3-171
Figure 3.19-1 Logic diagram of enabling/disabling reverse power protection ................ 3-173
Figure 3.19-2 Logic diagram of the fault detector of reverse power protection .............. 3-173
Figure 3.19-3 Operation characteristic curve of reverse power protection ...................... 3-174
Figure 3.19-4 Function block diagram of reverse power protection ................................. 3-175
Figure 3.19-5 Logic diagram of reverse power protection.................................................. 3-176
Figure 3.20-1 Function block diagram of cold load pickup logic....................................... 3-177
3-j PCS-9611S Feeder Relay

Date: 2019-04-24
Figure 3.20-2 Logic diagram of cold load pickup logic ....................................................... 3-178
Figure 3.21-1 Logic diagram of enabling/disabling undercurrent protection................... 3-182
Figure 3.21-2 Logic diagram of the fault detector of undercurrent protection ................ 3-183
Figure 3.21-3 Operation characteristic curve of undercurrent protection ........................ 3-184
Figure 3.21-4 Function block diagram of undercurrent protection ................................... 3-184
Figure 3.21-5 Logic diagram of undercurrent protection.................................................... 3-186
Figure 3.22-1 Logic of enabling breaker failure protection ................................................ 3-190
Figure 3.22-2 Logic of breaker failure initiating signal abnormality .................................. 3-190 3
Figure 3.22-3 Logic of breaker failure protection ................................................................ 3-190
Figure 3.23-1 The enabling and blocking logic of SOTF protection .................................. 3-192
Figure 3.10-3 Logic of auto-reclosing signal........................................................................ 3-194
Figure 3.10-2 Logic of manual closing signal ...................................................................... 3-194
Figure 3.23-2 Logic of phase overcurrent SOTF protection ............................................... 3-195
Figure 3.23-3 Logic of earth fault overcurrent SOTF protection ........................................ 3-196
Figure 3.24-1 Application of the unbalance current protection ......................................... 3-198
Figure 3.24-2 Logic diagram of enabling/disabling unbalance current protection.......... 3-198
Figure 3.24-3 Logic diagram of the fault detector of unbalance current protection........ 3-199
Figure 3.24-4 Operation characteristic curve of unbalance current protection ............... 3-199
Figure 3.24-5 Function block diagram of unbalance current protection .......................... 3-200
Figure 3.24-6 Logic diagram of unbalance current protection........................................... 3-200
Figure 3.25-1 Application of the unbalance voltage protection ......................................... 3-202
Figure 3.25-2 Logic diagram of enabling/disabling unbalance voltage protection ......... 3-202
Figure 3.25-3 Logic diagram of the fault detector of unbalance voltage protection ....... 3-203
Figure 3.25-4 Operation characteristic curve of unbalance voltage protection ............... 3-203
Figure 3.25-5 Function block diagram of unbalance voltage protection .......................... 3-204
Figure 3.25-6 Logic diagram of unbalance voltage protection .......................................... 3-204
Figure 3.26-1 Logic of enabling AR ....................................................................................... 3-206
Figure 3.26-2 Logic of AR block ............................................................................................. 3-207
Figure 3.26-3 Logic of AR ready ............................................................................................ 3-208
Figure 3.26-4 Tripping initiating AR ....................................................................................... 3-208
PCS-9611S Feeder Relay 3-k

Date: 2019-04-24
Figure 3.26-5 CB state initiating AR ...................................................................................... 3-209
Figure 3.26-6 One-shot AR ..................................................................................................... 3-209
Figure 3.26-7 Reclosing output logic .................................................................................... 3-210
Figure 3.26-8 Reclosing failure and success ....................................................................... 3-211
Figure 3.26-9 Transient fault................................................................................................... 3-212
Figure 3.26-10 Permanent fault ([79.Num]=2) ....................................................................... 3-213
Figure 3.27-1 VT circuit supervision logic diagram ............................................................. 3-218
3 Figure 3.28-1 Logic of CT circuit failure................................................................................ 3-220
List of Tables
Table 3.1-1 Input/Output signals of three-phase current element ......................................... 3-2
Table 3.1-2 Settings of three-phase current element............................................................... 3-3
Table 3.2-1 Input/Output signals of three-phase voltage element ......................................... 3-4
Table 3.2-2 Settings of three-phase voltage element .............................................................. 3-5
Table 3.3-1 Input/Output signals of one-phase current element ............................................ 3-6
Table 3.3-2 Settings of one-phase current element ................................................................. 3-6
Table 3.4-1 Input/Output signals of one-phase voltage element ............................................ 3-7
Table 3.4-2 Settings of one-phase voltage element ................................................................. 3-7
Table 3.5-1 Input/output signals of phase overcurrent protection ...................................... 3-20
Table 3.5-2 Settings of phase overcurrent protection ........................................................... 3-21
Table 3.6-1 Input/output signals of earth fault overcurrent protection ............................... 3-46
Table 3.6-2 Settings of earth fault overcurrent protection .................................................... 3-47
Table 3.7-1 Input/output signals of another group of earth fault overcurrent protection . 3-69
Table 3.7-2 Settings of another group of earth fault overcurrent protection ...................... 3-70
Table 3.8-1 Input/output signals of negative-sequence overcurrent protection ................ 3-91
Table 3.8-2 Settings of negative-sequence overcurrent protection..................................... 3-92
Table 3.9-1 Input/output signals of sensitive earth fault protection .................................. 3-106
Table 3.9-2 Settings of sensitive earth fault protection ...................................................... 3-107
Table 3.10-1 Input/output signals of RMS overcurrent protection ..................................... 3-122
Table 3.10-2 Settings of RMS overcurrent protection ......................................................... 3-122
3-l PCS-9611S Feeder Relay

Date: 2019-04-24
Table 3.11-1 Input/output signals of phase overvoltage protection .................................. 3-129
Table 3.11-2 Settings of phase overvoltage protection ....................................................... 3-131
Table 3.12-1 Input/output signals of residual overvoltage protection ............................... 3-137
Table 3.12-2 Settings of residual overvoltage protection ................................................... 3-137
Table 3.13-1 Input/output signals of negative-sequence overvoltage protection ............ 3-141
Table 3.13-2 Settings of negative-sequence overvoltage protection ................................ 3-142
Table 3.14-1 Input/output signals of positive-sequence overvoltage protection ............. 3-146
Table 3.14-2 Settings of positive-sequence overvoltage protection ................................. 3-147 3

Table 3.15-1 Input/output signals of phase undervoltage protection ................................ 3-154
Table 3.15-2 Settings of phase undervoltage protection .................................................... 3-156
Table 3.16-1 Input/output signals of overfrequency protection ......................................... 3-162
Table 3.16-2 Settings of overfrequency protection.............................................................. 3-163
Table 3.17-1 Input/output signals of underfrequency protection ....................................... 3-166
Table 3.17-2 Settings of underfrequency protection ........................................................... 3-167
Table 3.18-1 Input/output signals of frequency rate-of-change protection ...................... 3-170
Table 3.18-2 Settings of frequency rate-of-change protection ........................................... 3-171
Table 3.19-1 Input/output signals of reverse power protection.......................................... 3-175
Table 3.19-2 Settings of reverse power protection .............................................................. 3-176
Table 3.20-1 Input/output signals of cold load pickup logic ............................................... 3-177
Table 3.20-2 Settings of cold load pickup logic ................................................................... 3-179
Table 3.21-1 Input/output signals of undercurrent protection............................................ 3-185
Table 3.21-2 Settings of undercurrent protection ................................................................ 3-186
Table 3.22-1 Input/output signals of breaker failure protection ......................................... 3-189
Table 3.22-2 Settings of breaker failure protection.............................................................. 3-191
Table 3.23-1 Input/output signals of SOTF protection ........................................................ 3-193
Table 3.23-2 Settings of SOTF protection ............................................................................. 3-196
Table 3.24-1 Input/output signals of unbalance current protection................................... 3-200
Table 3.24-2 Settings of unbalance current protection ....................................................... 3-201
Table 3.25-1 Input/output signals of unbalance voltage protection .................................. 3-204
Table 3.25-2 Settings of unbalance voltage protection ....................................................... 3-205
PCS-9611S Feeder Relay 3-m

Date: 2019-04-24
Table 3.26-1 Input/Output signals of AR ............................................................................... 3-214
Table 3.26-2 Settings of AR .................................................................................................... 3-215
Table 3.27-1 Input/output signals of VT circuit supervision ............................................... 3-217
Table 3.27-2 Settings of VT circuit supervision ................................................................... 3-218
Table 3.28-1 Input/output signals of CT circuit supervision ............................................... 3-219
Table 3.28-2 Settings of CT circuit supervision ................................................................... 3-220
3-n PCS-9611S Feeder Relay

Date: 2019-04-24
3.1 Three-phase Current Element (TCUR3P)
Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phase angles of three phase currents, etc. All
calculated information of three-phase current element is used for protection logic calculation.
Three-phase current element is a basic element, for a specific application,

the displayed signals and settings may have different prefixes in front of
them.
3
3.1.1 Function Description
Three-phase current element has following functions:
1. Pre-process three phase currents
2. Calculate information related to three-phase current
When any phase current is greater than 0.04In, the input current signals are valid and the valid
signal will be outputted for programmable logic application.
CT circuit supervision of three-phase current is carried out by the CTS element, which can refer to
Section 3.28 for details.

Date: 2019-04-24
3.1.2 Function Block Diagram
TCUR3P
in_ia I3P
in_ib Ia_Sec
in_ic Ib_Sec
Ic_Sec
I1_Sec
3 I2_Sec
3I0_Cal_Sec
Ang(Ia-Ib)
Ang(Ib-Ic)
Ang(Ic-Ia)
Ang(Ia)
Ang(Ib)
Ang(Ic)
Ang(3I0_Cal)
Alm_CTS
Flg_OnLoad
3.1.3 I/O Signals

Table 3.1-1 Input/Output signals of three-phase current element
No. Input Signal Description

1 in_ia Sampled value of phase-A current
2 in_ib Sampled value of phase-B current
3 in_ic Sampled value of phase-C current
No. Output Signal Description
1 I3P A current data set
2 Ia_Sec Amplitude of secondary phase-A current
3 Ib_Sec Amplitude of secondary phase-B current
4 Ic_Sec Amplitude of secondary phase-C current
5 I1_Sec Amplitude of secondary positive-sequence current
6 I2_Sec Amplitude of secondary negative-sequence current
7 3I0_Cal_Sec Amplitude of calculated secondary residual current
8 Ang(Ia-Ib) Phase angle between phase A and phase B currents
9 Ang(Ib-Ic) Phase angle between phase B and phase C currents

Date: 2019-04-24
10 Ang(Ic-Ia) Phase angle between phase C and phase A currents

11 Ang(Ia) Phase angle of phase-A current
12 Ang(Ib) Phase angle of phase-B current
13 Ang(Ic) Phase angle of phase-C current
14 Ang(3I0_Cal) Phase angle of calculated residual current
15 Alm_CTS CT secondary circuit failure
16 Flg_OnLoad A flag indicating that the load current is detected
3.1.4 Settings
 Access path:
MainMenu  Settings  Global Settings  System Settings

3
Table 3.1-2 Settings of three-phase current element
No. Item Range Step Unit Default Description

1 Prot.I1n 0~9999 1 A 1000 Primary current value of the three-phase CT
2 Prot.I2n 1 or 5 - A 1 Secondary current value of the three-phase CT
Enabled, Logic setting of enabling/disabling the current
3 Prot.En_RevCT - - Disabled
Disabled polarity of the three-phase CT reversed
3.2 Three-phase Voltage Element (TVOL3P)
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase voltages, etc. All
calculated information of three-phase voltage element is used for the protection logic calculation.

Three-phase voltage element has following functions:
1. Pre-process three phase voltages
2. Calculate information related to three phase voltages
VT circuit failure supervision of three-phase voltage is carried out by the VTS element, which can
refer to Section 3.27 for details.

Date: 2019-04-24
TVOL3P
in_ua U3P
in_ub Ua_Sec
in_uc Ub_Sec
BI_En_VT Uc_Sec
U1_Sec
3 U2_Sec
3U0_Cal_Sec
Ang(Ua-Ub)
Ang(Ub-Uc)
Ang(Uc-Ua)
Ang(Ua)
Ang(Ub)
Ang(Uc)
Ang(3U0_Cal)
Alm_VTS
3.2.3 I/O Signals

Table 3.2-1 Input/Output signals of three-phase voltage element
No. Input signal Description

1 in_ua Sampled value of phase-A voltage
2 in_ub Sampled value of phase-B voltage
3 in_uc Sampled value of phase-C voltage
4 BI_En_VT Input signal of indicating VT in service
No. Output signal Description
1 U3P A voltage data set
2 Ua_Sec Amplitude of phase-A secondary voltage
3 Ub_Sec Amplitude of phase-B secondary voltage
4 Uc_Sec Amplitude of phase-C secondary voltage
5 U1_Sec Amplitude of positive-sequence secondary voltage
6 U2_Sec Amplitude of negative-sequence secondary voltage
7 3U0_Cal_Sec Amplitude of calculated residual secondary voltage
8 Ang(Ua-Ub) Phase angle between phase A and phase B voltages
9 Ang(Ub-Uc) Phase angle between phase B and phase C voltages

Date: 2019-04-24

10 Ang(Uc-Ua) Phase angle between phase C and phase A voltages
11 Ang(Ua) Phase angle of phase-A voltage
12 Ang(Ub) Phase angle of phase-B voltage
13 Ang(Uc) Phase angle of phase-C voltage
14 Ang(3U0_Cal) Phase angle of calculated residual voltage
15 Alm_VTS VT secondary circuit abnormality
3.2.4 Settings
 Access path:

3
Table 3.2-2 Settings of three-phase voltage element

1 Prot.U1n 1~1100 0.001 kV Rated value of primary voltage of the three-phase VT
2 Prot.U2n 1~120 0.001 V Rated value of secondary voltage of the three-phase VT
Enabled,
3 En_VT Enabled Logic setting to put the three-phase VT into service
Disabled
3.3 One-phase Current Element (TCUR1P)
One-phase current element is responsible for pre-processing measured one-phase current and
calculating the magnitude and the phase angle of the one-phase current, etc. All calculated
information of one-phase current element is used for the protection logic calculation.

One-phase current element has following functions:
1. Pre-process measured one-phase current
2. Calculate information related to the one-phase current
TCUR1P
x.in_ip x.I1P
x.3I0_Ext_Sec
x.Ang(3I0_Ext)
x.Flg_OnLoad

Date: 2019-04-24
3.3.3 I/O Signals

Table 3.3-1 Input/Output signals of one-phase current element

1 x.in_ip Measured one-phase current
1 x.I1P A current data set
2 x.3I0_Ext_Sec Amplitude of external residual secondary current
3 x.Ang(3I0_Ext) Phase angle of external residual current
4 x.Flg_OnLoad A flag indicating there is load current
3 3.3.4 Settings
One-phase current element is a basic element, for a specific application,

the displayed settings may have different prefixes in front of them.
 Access path:
Table 3.3-2 Settings of one-phase current element

1 x.I1n 0~9999 1 A 1000 Primary rated current of the one-phase CT
Secondary rated current of the one-phase
2 x.I2n 1 or 5 - A 1
CT
Enabled, Logic setting of enabling/disabling the
3 x.En_RevCT - - Disabled
Disabled current polarity of the one-phase CT
3.4 One-phase Voltage Element (TVOL1P)
One-phase voltage element is responsible for pre-processing one-phase voltage and calculating
the magnitude and the phase angle of the one-phase voltage, etc. All calculated information of
one-phase voltage element is used for the protection logic calculation.
One-phase voltage element has following functions:
1. Pre-process measured one-phase voltage
2. Calculate information related to one-phase voltage

Date: 2019-04-24
TVOL1P
in_up U1P
BI_En_VT U_Sec
Ang(U)
3.4.3 I/O Signals

Table 3.4-1 Input/Output signals of one-phase voltage element
3
1 x.iIn_up Measured one-phase voltage
2 BI_En_VT Input signal of indicating VT in service
1 U1P A voltage data set
2 U_Sec Amplitude of the one-phase voltage (secondary value)
3 Ang(U) Phase angle of the one-phase voltage
3.4.4 Settings
One-phase voltage element is a basic element, for a specific application,

the displayed settings may have different prefixes in front of them.
 Access path:
Table 3.4-2 Settings of one-phase voltage element

1 x.U1n 0~1100 0.001 kV - Primary rated voltage of the one-phase VT
2 x.U2n 1~200 0.001 V - Secondary rated voltage of the one-phase VT
3.5 Phase Overcurrent Protection (50/51P)

Phase overcurrent protection is the most widely used type of protection element in power systems.
It can be used as the main protection of the feeder, and can also be used as the backup protection
for power equipment such as transformers, reactors, and motors. When a fault occurs in the
system, a fault current will be generated and the phase overcurrent protection can reflect the
increase of the fault current.

Date: 2019-04-24

The device can provide six stages of phase overcurrent protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics.
The dropout characteristics can be set as instantaneous dropout, definite-time dropout or
inverse-time dropout. Users can choose whether it is blocked by the voltage control element,
direction control element, or harmonic control element, users can also choose whether it is
controlled by cold load pickup. The direction control element can be set as no direction, forward
direction and reverse direction. The phase overcurrent protection picks up when the current
exceeds the current threshold value, and operates after a certain time delay, once the fault
disappears, the phase overcurrent protection will dropout.
3 Phase overcurrent protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, overcurrent protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overcurrent protection.
The enabling and blocking logic of phase overcurrent protection is shown in the figure below:
EN 50/51Px.En &
50/51Px.On
SIG 50/51Px.Enable
&
SIG 50/51Px.Block ≥1 50/51Px.Blocked
SIG Fail_Device
&
50/51Px.Valid
Figure 3.5-1 The enabling and blocking logic of phase overcurrent protection
The logic diagram of the fault detector element of phase overcurrent protection is as follows:
SET Ia>0.95×[50/51Px.I_Set]
>=1
SET Ib>0.95×[50/51Px.I_Set] &
0 500ms &
SET Ic>0.95×[50/51Px.I_Set]
50/51Px.Pkp
SIG 50/51Px.On
SIG 50/51Px.Valid
&
FD.Pkp
SET [50/51Px.Opt_Trp/Alm]=Alm
Figure 3.5-2 Logic diagram of the fault detector element of phase overcurrent protection
3.5.1.1 Voltage Control Element
When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the
voltage control element can be adopted to increase the sensitivity for this kind of fault. Users can

Date: 2019-04-24
enable or disable the voltage control element via the setting [50/51Px.En_Volt_Blk] (x=1~6). If the
VT circuit supervision function is enabled for the device, and the setting [50/51P.En_VTS_Blk] is
set as “1”, when VT circuit failure happens, the device will issue a VT circuit failure alarm signal
[VTS.Alm], and the voltage controlled phase overcurrent protection will be blocked. If the voltage
control element of phase overcurrent protection is not enabled, phase overcurrent protection will
not effected by VT circuit failure. The corresponding relationship between the phase-segregated
overcurrent element and the voltage control element is as follows.
Voltage control
Phase A Phase B Phase C
criterion
Phase-to-phase Uab<[50/51P.VCE.Upp] Uab<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp]
criterion Uca<[50/51P.VCE.Upp] Ubc<[50/51P.VCE.Upp] Uca<[50/51P.VCE.Upp] 3
Negative-sequence
U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2] U2>[50/51P.VCE.U2]
criterion
Zero-sequence
U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0] U0_Cal>[50/51P.VCE.3U0]
criterion
The relationship between the phase-to-phase criterion, the negative-sequence criterion and the
zero-sequence criterion is "or". The logic diagram of the voltage control element action is shown
below:
EN [50/51P.En_VTS_Blk] &
>=1
SIG VTS.Alm
>=1
SIG Uab, Ubc, Uca & 50/51P.VCE.Op
criterion
Voltage
SIG U2, U0_Cal
SIG Prot.BI_En_VT &
EN [En_VT]
Figure 3.5-3 Logic diagram of the voltage control element of phase overcurrent protection
3.5.1.2 Direction Control Element
In order to ensure the selectivity of phase overcurrent protection, direction control element is
introduced. The setting [50/51Px.Opt_Dir] (x=1~6) is used for users to select the directional mode
of each stage of phase overcurrent protection: no direction, forward direction and reverse
direction are selectable.
Takes the phase A fault as an example, the polarization mode is set as “Up”, its operation
characteristics are shown in the figure below. The principle of phase B and phase C is the same. If
the positive-sequence voltage or the phase-to-phase voltage is polarized, the operation

Date: 2019-04-24
characteristics are the same.
The operation boundary of the forward direction element can be set by [50/51P.DIR.phi_Min_Fwd]
and [50/51P.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51P.DIR.phi_Min_Rev] and [50/51P.DIR.phi_Max_Rev].
Ua
[50/51P.DIR.phi_Min_Fwd]
3 Non-operating
area
Ia
[50/51P.DIR.phi_Max_Rev] Operating area in

forward direction
[50/51P.DIR.RCA]
Operating area in
reverse direction
[50/51P.DIR.phi_Max_Fwd]
[50/51P.DIR.phi_Min_Rev] Non-operating
area
Figure 3.5-4 The direction element operation characteristics when phase A voltage is polarized
Where:
The sensitivity angle of the direction control element (RCA) can be set by the setting
[50/51P.DIR.RCA].
The selection of the polarization voltage can be set by the setting [50/51P.DIR.Opt_PolarizedVolt].
The following table shows the relationship between the operating current, the polarized voltage
and the polarization mode.
Direction criterion
Polarization Faulty Operating
Polarized voltage Angle difference
mode phase current
Phase-A Positive-sequence
Phase A Angle_A=Angle(U1)-Angle(Ia)-RCA
current Ia voltage
Positive-sequence Phase-B Positive-sequence
Phase B Angle_B=Angle(U1)-Angle(Ib)-RCA-120º
voltage polarized current Ib voltage
Phase-C Positive-sequence
Phase C Angle_C=Angle(U1)-Angle(Ic)-RCA+120º
current Ic voltage
Phase-to-phase Phase-A Phase-to-phase
Phase A Angle_A=Angle(Ubc)-Angle(Ia)-RCA+90º
voltage polarized current Ia voltage Ubc

Date: 2019-04-24
Phase-B Phase-to-phase
Phase B Angle_B=Angle(Uca)-Angle(Ib)-RCA+90º
current Ib voltage Uca
Phase-C Phase-to-phase
Phase C Angle_C=Angle(Uab)-Angle(Ic)-RCA+90º
current Ic voltage Uab
Phase-A Phase-to-ground
Phase A Angle_A=Angle(Ua)-Angle(Ia)-RCA
current Ia voltage Ua
Phase-to-ground Phase-B Phase-to-ground
Phase B Angle_B=Angle(Ub)-Angle(Ib)-RCA
voltage polarized current Ib voltage Ub
Phase-C Phase-to-ground
Phase C Angle_C=Angle(Uc)-Angle(Ic)-RCA
current Ic voltage Uc
In order to improve the reliability of the direction control element, the direction control element with 3
the above three polarization modes must be used in conjunction with the negative-sequence
direction criterion. The negative-sequence direction criterion is shown in the table below.
Negative-sequence direction criterion

Operating current Polarized voltage Angle difference
Negative-sequence current Negative-sequence voltage Angle_I2=Angle(U2)-Angle(I2)-RCA+180º
Therefore, the criterion for the three-phase direction control element is as follows:
Three-phase direction control element

Direction element Operating condition
Angle_A forward direction operates and Angle_I2 reverse direction does not
Phase A forward direction
operate.
Angle_A reverse direction operates and Angle_I2 forward direction does not
Phase A reverse direction
operate.
Angle_B forward direction operates and Angle_I2 reverse direction does not
Phase B forward direction
operate.
Angle_B forward direction operates and Angle_I2 forward direction does not
Phase B reverse direction
operate.
Angle_C forward direction operates and Angle_I2 reverse direction does not
Phase C forward direction
operate.
Angle_C forward direction operates and Angle_I2 forward direction does not
Phase C reverse direction
operate.
The direction element calculation needs to judge the voltage threshold and current threshold. The
direction can be judged only when both of the voltage and current are greater than the threshold,
choose a different polarization mode, the selection of voltage and current, and the threshold are
not the same, the specific principles are:
Polarized voltage Minimum operating current Minimum operating voltage

Phase-to-phase voltage Phase current Phase-to-phase voltage
Phase-to-ground voltage Phase current Phase-to-ground voltage
Positive-sequence voltage Phase current Positive-sequence voltage
Negative-sequence voltage Negative-sequence current Negative-sequence voltage

Date: 2019-04-24
The direction element has memory function that can eliminate the dead zone of the direction
element when the close up three-phase short circuit fault occurs. When the polarized voltage is
less than the minimum operating voltage setting [50/51P.DIR.U_Min], the positive-sequence
voltage before two cycles is used to judge the direction. The polarized voltage will not be used to
judge the direction until it is greater than [50/51P.DIR.U_Min]. The logic diagram of the forward
direction element and reverse direction element is shown as below.
3 >=1
SIG VTS.Alm
SIG Three-phase currents Forward direction & >=1

50/51P.FwdDir.Op
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [50/51P.DIR.Opt_PolarizedVolt]
SIG Prot.BI_En_VT &
EN [En_VT]
>=1
SIG VTS.Alm
SIG Three-phase currents & >=1

Reverse direction
50/51P.RevDir.Op
SIG Three-phase voltages
criterion
SIG Memorized U1
SET [50/51P.DIR.Opt_PolarizedVolt]
SIG Prot.BI_En_VT &
EN [En_VT]
Figure 3.5-5 Logic diagram of forward and reverse direction element of phase overcurrent protection
Where:
Memorized U1: the positive-sequence memory voltage, it refers to the positive-sequence voltage
of two cycles before the polarized voltage is less than the minimum operating voltage setting
[50/51P.DIR.U_Min], and it is calculated from the three-phase voltage.

Date: 2019-04-24
3.5.1.3 Harmonic Control Element
When transformer and other equipment are energized without any load, the inrush current may be
generated, which may cause the mal-operation of the phase overcurrent protection. According to
the characteristics of high secondary harmonic component in the inrush current and low
secondary harmonic component in common fault current, the secondary harmonic control element
is added to prevent the phase overcurrent protection from mal-operation due to inrush current. For
the harmonic control element, the harmonic blocking mode can be selected through the setting
[50/51P.HMB.Opt_Blk], it can support phase locking, cross locking, and maximum phase locking.
The correspondences are shown in the following table:
Setting Value
Phase A
Harmonic blocking criterion
Phase B Phase C
3
1 PhaseBlk Ia2/Ia1>[50/51P.HMB.K_Hm2] Ib2/Ib1>[50/51P.HMB.K_Hm2] Ic2/Ic1>[50/51P.HMB.K_Hm2]
2 CrossBlk (Ia2/Ia1) or (Ib2/Ib1) or (Ic2/Ic1)> [50/51P.HMB.K_Hm2]
Max(Ia2, Ib2, Ic2)/Ia1> Max(Ia2, Ib2, Ic2)/Ib1> Max(Ia2, Ib2, Ic2)/Ic1>
3 MaxPhaseBlk
[50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2] [50/51P.HMB.K_Hm2]
Where:
Ia1, Ib1, Ic1: the fundamental current;
Ia2, Ib2, Ic2: the secondary harmonic component of the current.
When the fundamental current is greater than the setting [50/51P.HMB.I_Rls], the harmonic
blocking element of the corresponding phase is released.
The following figure shows the logic diagram of the harmonic control element of phase
overcurrent protection.
SET Imax>[50/51P.HMB.I_Rls]
SIG Ia1, Ib1, Ic1

&
50/51P.HMB.Op
Harmonic
criterion
SIG Ia2, Ib2, Ic2
SET [50/51P.HMB.Opt_Blk]
Figure 3.5-6 Logic diagram of harmonic control element of phase overcurrent protection
Where:
Ia1, Ib1, Ic1: the fundamental current
Ia2, Ib2, Ic2: the 2nd harmonic current
Imax: the maximum phase current
3.5.1.4 Operation Characteristic
Phase overcurrent protection can operate without time delay or operate with a definite-time limit, it
can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and

Date: 2019-04-24
ANSI C37.112 standards. Phase overcurrent protection can support definite-time limit, IEC &
ANSI standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51Px.Opt_Curve] (x=1~6), the relationship between the value of
the setting and the curve is shown in the table below.
50/51Px.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely Inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal Inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately Inverse 0.0515 0.02 0.114 4.85
3
ANSIDefTime ANSI Definite Time - - - -
ANSILTE ANSI Long Time Extremely Inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long Time Very Inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long Time Inverse 0.086 0.02 0.185 4.6
IECN IEC Normal Inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IEC IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short-time inverse 0.05 0.04 0 -
IECLT IEC Long-time inverse 120.0 1.0 0 -
IECDefTime IEC Definite Time - - - -
UserDefine Programmable
Only when the setting [50/51Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Px.K], [50/51Px.C] and [50/51Px.Alpha]
are useful, the inverse-time operating curve is determined by the three settings.
 Without time delay
When I > Ip , phase overcurrent protection operates immediately.
 Definite-time characteristic
When I > Ip , the protection operates with a time delay of top (i.e. the value of the setting
[50/51Px.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2019-04-24
t op
3
IP I
Figure 3.5-7 Definite-time operation characteristic curve of phase overcurrent protection
 Inverse-time characteristic
When I > Ip , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Px.tmin] (x=1~6). The
inverse-time operation characteristic equation is:
 k 
t 
 c   TMS
 (I / I P ) 1 
Where:
Ip is the current setting [50/51Px.I_Set];

TMS is the inverse-time time multiplier, i.e. the setting [50/51Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Px.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Px.Alpha];
I is the measured current.

The inverse-time operation characteristic curve is shown as below:

Date: 2019-04-24
3 t min
IP ID I
Figure 3.5-8 Inverse-time operation characteristic curve of phase overcurrent protection
When the applied current is not a fixed value, but changes with time, the operating behavior of the
protection is shown in the following equation:
T0
1
 t ( I )dt
0
1
Where:
T0 is the operating time of the protection element;
t(I) is the theoretical operating time when the current is I.
3.5.1.5 Dropout Characteristic
The supported dropout characteristics of the phase overcurrent protection include instantaneous
dropout, definite-time dropout and ANSI inverse-time dropout.
When the operating curve is selected as definite-time, IEC inverse-time or user-defined

inverse-time characteristic, the dropout characteristic can only be selected as instantaneous
dropout or definite-time dropout, if inverse-time dropout is selected, the alarm signal
"Fail_Settings" will be issued and the device will be blocked.
When the operating curve is selected as ANSI inverse-time characteristic, the dropout
characteristic can be selected as instantaneous dropout, definite-time dropout and ANSI
inverse-time dropout.
 Instantaneous dropout
When I <0.95* Ip , the protection drops out immediately.
 Definite-time dropout

Date: 2019-04-24
When I <0.95* Ip , the protection drops out with a time delay of tdr (i.e. the value of the setting
[50/51Px.t_DropOut]), and the dropout characteristic curve is shown in the following figure:
Start time
I>Ip
Start
signal
3
Operating
signal
Protection
Operating threshold operate
Operating
counter
t dr t dr t dr
Dropout time setting
Dropout time
Dropout time
Figure 3.5-9 Definite-time dropout characteristic of phase overcurrent protection
 Inverse-time dropout
When I > Ip , the inverse-time operating accumulator begins to accumulate, the accumulated
value after tp (Assuming tp is less than the theoretical operating time) is calculated according
to the following equation:
tp
1
I tp   dt
0
t ( I )
At this time, if I <0.95* Ip , the protection element starts dropout, and the dropout characteristic
meets the following equation:
TR
1
I tp   dt  0
t (I )
0 R
Where:
TR is the dropout time;

tR ( I ) is the dropout characteristic equation

Date: 2019-04-24
When I <0.95* Ip , the inverse-time dropout characteristic equation is as follows:
 tr 
tR   2
 TMS
1  ( I / I P ) 
Where:
Ip is the current setting [50/51Px.I_Set];

TMS is the inverse-time factor, i.e. the setting [50/51Px.TMS];
tr is the dropout time coefficient, it is the dropout time required for the current to drop to 0 after
3 the protection operates.
I is the measured current.

When 0.95* Ip < I < Ip , the accumulator will neither accumulate nor drop out
The inverse time dropout characteristic curve is shown in the figure below.
tr
IP I
Figure 3.5-10 Inverse-time dropout characteristic curve of phase overcurrent protection
The correspondence between the start signal, operating signal, and operating accumulator in the
inverse-time dropout characteristic is shown in the figure below:

Date: 2019-04-24
Start time
I>Ip
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter
tr Dropout time coefficient

Dropout time
Dropout time
Figure 3.5-11 Inverse-time dropout characteristic of phase overcurrent protection
50/51P
50/51Px.Enable 50/51Px.On
50/51Px.Block 50/51Px.Blocked
50/51Px.Valid
50/51Px.St
50/51Px.StA
50/51Px.StB
50/51Px.StC
50/51Px.Op
50/51Px.Op.PhA
50/51Px.Op.PhB
50/51Px.Op.PhC
50/51P.FwdDir.Op
50/51P.RevDir.Op
50/51Px.Alm

Date: 2019-04-24
3.5.3 I/O Signal

Table 3.5-1 Input/output signals of phase overcurrent protection

Stage x of phase overcurrent protection enabling input, it is triggered from
1 50/51Px.Enable
binary input or programmable logic etc. (x=1~6)
Stage x of phase overcurrent protection blocking input, it is triggered from
2 50/51Px.Block
1 50/51Px.On Stage x of phase overcurrent protection is enabled
3 2 50/51Px.Blocked Stage x of phase overcurrent protection is blocked

3 50/51Px.Valid Stage x of phase overcurrent protection is valid
4 50/51Px.St Stage x of phase overcurrent protection starts
5 50/51Px.StA Stage x of phase overcurrent protection starts (Phase A)
6 50/51Px.StB Stage x of phase overcurrent protection starts (Phase B)
7 50/51Px.StC Stage x of phase overcurrent protection starts (Phase C)
8 50/51Px.Op Stage x of phase overcurrent protection operates
9 50/51Px.Op.PhA Stage x of phase overcurrent protection operates (Phase A)
10 50/51Px.Op.PhB Stage x of phase overcurrent protection operates (Phase B)
11 50/51Px.Op.PhC Stage x of phase overcurrent protection operates (Phase C)
12 50/51Px.Alm Stage x of phase overcurrent protection alarms
13 50/51P.FwdDir.Op The forward direction element of phase overcurrent protection operates
14 50/51P.RevDir.Op The reverse direction element of phase overcurrent protection operates

Date: 2019-04-24
3.5.4 Logic
SET Ia>[50/51Px.I_Set]
SIG 50/51P.VCE.Op_A >=1 &
EN [50/51Px.En_Volt_Blk]
SIG 50/51P.FwdDir.Op_A
selection
Direction
SIG 50/51P.RevDir.Op_A
SIG [50/51Px.Opt_Dir] 50/51Px.StA

&
3
SIG 50/51P.HMB.Op_A & & Timer
t
&
t
EN [50/51Px.En_Hm_Blk] 50/51Px.Op.PhA
SIG 50/51Px.Pkp
SET [50/51Px.Opt_Trp/Alm]=Trp
&
50/51Px.Alm.PhA
SET [50/51Px.Opt_Trp/Alm]=Alm
SIG 50/51Px.StA
>=1
SIG 50/51Px.StB 50/51Px.St
SIG 50/51Px.StC
SIG 50/51Px.Op.PhA
>=1
SIG 50/51Px.Op.PhB 50/51Px.Op
SIG 50/51Px.Op.PhC
SIG 50/51Px.Alm.PhA
>=1
SIG 50/51Px.Alm.PhB 50/51Px.Alm
SIG 50/51Px.Alm.PhC
Figure 3.5-12 Logic diagram of phase overcurrent protection
3.5.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  OC Settings
Table 3.5-2 Settings of phase overcurrent protection
Default
No. Settings Range Unit Step Description
value
The low voltage blocking setting
1 50/51P.VCE.Upp 10~100 70 V 0.001 of the voltage control element of
phase overcurrent protection

Date: 2019-04-24
Default
value
The negative-sequence voltage
blocking setting of the voltage
2 50/51P.VCE.U2 2~57 8 V 0.001
control element of phase
overcurrent protection
The residual voltage setting (set
according to 3U0) of voltage
3 50/51P.VCE.3U0 2~57 8 V 0.001
3 4 50/51P.DIR.RCA -180~179 45 deg 1

The relay characteristic angle of
the direction control element of
The relay negative-sequence
50/51P.DIR.RCA_N characteristic angle of the
5 -180~179 45 deg 1
egOC direction control element of
The minimum boundary of the
50/51P.DIR.phi_Min
6 10~90 90 deg 1 forward direction element of
_Fwd
The maximum boundary of the
50/51P.DIR.phi_Ma
x_Fwd
50/51P.DIR.phi_Min
8 10~90 90 deg 1 reverse direction element of
_Rev
50/51P.DIR.phi_Ma
x_Rev
The voltage polarization mode
for direction control element of
Upp; Upp: phase-to-phase voltage
50/51P.DIR.Opt_Pol
10 Up; Upp - - polarized
arizedVolt
U1 Up: phase-to-ground voltage
polarized
U1: positive-sequence voltage
polarized
The minimum operating current
setting for the direction control
11 50/51P.DIR.I_Min (0.05~1)In 0.05 - 0.001
element of phase overcurrent
protection

Date: 2019-04-24
Default
value
The minimum operating voltage
12 50/51P.DIR.U_Min 1~10 4 V 0.001
protection
Logic setting to determine the
behavior of phase overcurrent
protection when VT circuit
supervision function is enabled
Disabled;
and VT circuit failure happens.
Disabled: phase overcurrent
3
13 50/51P.En_VTS_Blk Disabled - -
Enabled protection will not effected by VT
circuit failure
Enabled: voltage controlled
phase overcurrent protection will
be blocked by VT circuit failure
signal
The percent setting of the
50/51P.HMB.K_Hm
14 0.1~1 0.2 - 0.001 harmonic control element of
2
The current setting for releasing
15 50/51P.HMB.I_Rls 2~150 20 A 0.001 the harmonic control element of
The setting used to select the
harmonic blocking mode of
PhaseBlk phase overcurrent protection
50/51P.HMB.Opt_Bl
16 CrossBlk PhaseBlk - - PhaseBlk: phase blocking
k
MaxPhaseBlk CrossBlk: cross blocking
MaxPhaseBlk: maximum phase
blocking
The current setting of stage 1 of
17 50/51P1.I_Set 0.05~200 15 A 0.001
The operating time setting of
18 50/51P1.t_Op 0 ~100 0.1 s 0.001 stage 1 of phase overcurrent
protection
The dropout time setting of
19 50/51P1.t_DropOut 0 ~100 0 s 0.001 stage 1 of phase overcurrent
protection

Date: 2019-04-24
Default
value
The logic setting for
enabling/disabling the voltage
control element of stage 1 of
Disabled: stage 1 of phase
50/51P1.En_Volt_Bl Disabled; overcurrent protection is not
20 Disabled - -
k Enabled controlled by the voltage control
element
3 Enabled: stage 1 of phase

overcurrent protection is
controlled by the voltage control
element
Non_Directional The setting used to select the
Non_Directio
21 50/51P1.Opt_Dir Forward - - directional mode of stage 1 of
nal
Reverse phase overcurrent protection.
enabling/disabling the harmonic
50/51P1.En_Hm_Bl Disabled; overcurrent protection is not
22 Disabled - -
k Enabled controlled by the harmonic
control element
Enabled: stage 1 of phase
controlled by the harmonic
control element
Disabled;
23 50/51P1.En Enabled - - enabling/disabling the stage 1 of
Enabled
Enabling stage 1 of phase
overcurrent protection operate
50/51P1.Opt_Trp/Al Trp;
24 Trp - - to trip or alarm.
m Alm
Trp: for tripping purpose
Alm: for alarm purpose

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV; The setting for selecting the
ANSILT; inverse-time operation
25 50/51P1.Opt_Curve IECDefTime - -
IECN;
IECV;
characteristic curve of stage 1 of
phase overcurrent protection.
3
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
The setting for selecting the
inverse-time dropout
Inst; characteristic curve of stage 1 of
50/51P1.Opt_Curve
26 DefTime; Inst - - phase overcurrent protection
_DropOut
IDMT Inst: instantaneous dropout
DefTime: definite-time dropout
IDMT: inverse-time dropout
The time multiplier setting of
27 50/51P1.TMS 0.04~ 20 1 - 0.001 stage 1 of phase overcurrent
protection
The minimum operating time
28 50/51P1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of phase
The constant “k” of the
customized inverse-time
0.000
29 50/51P1.K 0.001~120 0.14 - operation characteristic of stage
1
1 of phase overcurrent
protection
The constant “α” of the
0.000
30 50/51P1.Alpha 0.01 ~3 0.02 - operation characteristic of stage
1
protection

Date: 2019-04-24
Default
value
The constant “C” of the
0.000
31 50/51P1.C 0 ~1 0 - operation characteristic of stage
1
protection
32 50/51P1.I_Set 0.05~200 15 A 0.001
3 33 50/51P2.t_Op 0 ~100 0.1 s 0.001 stage 2 of phase overcurrent

protection
protection
35 Disabled - -
element
element
Non_Directio
nal
37 Disabled - -
control element
control element

Date: 2019-04-24
Default
value
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
3
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IECN; characteristic curve of stage 2 of
IECV; phase overcurrent protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P2.Opt_Curve
_DropOut
protection
0.000
1
protection

Date: 2019-04-24
Default
value
0.000
1
protection
0.000
1
3 2 of
protection
phase overcurrent

47 50/51P3.I_Set 0.05~200 15 A 0.001
protection
protection
50 Disabled - -
element
element
Non_Directio
nal

Date: 2019-04-24
Default
value
52 Disabled - -
control element
3
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default
value
50/51P3.Opt_Curve
_DropOut
3 57 50/51P3.TMS 0.04~ 20 1 - 0.001 stage 3 of phase overcurrent

protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
62 50/51P4.I_Set 0.05~200 15 A 0.001
protection
protection

Date: 2019-04-24
Default
value
65 Disabled - -
element
3
element
Non_Directio
nal
67 Disabled - -
control element
control element
Disabled;
Enabled
m Alm

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
3 IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P4.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection

Date: 2019-04-24
Default
value
0.000
1
protection
77 50/51P5.I_Set 0.05~200 15 A 0.001
protection
3
protection
80 Disabled - -
element
element
Non_Directio
nal
82 Disabled - -
control element
control element

Date: 2019-04-24
Default
value
Disabled;
Enabled
m Alm
3 ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P5.Opt_Curve
_DropOut
protection
0.000
1
protection

Date: 2019-04-24
Default
value
0.000
1
protection
0.000
1
5 of
protection
phase overcurrent
3
92 50/51P6.I_Set 0.05~200 15 A 0.001
protection
protection
95 Disabled - -
element
element
Non_Directio
nal

Date: 2019-04-24
Default
value
97 Disabled - -
control element

control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default
value
50/51P6.Opt_Curve
_DropOut
protection
3
0.000
1
protection
0.000
1
protection
0.000
1
protection
3.6 Earth Fault Overcurrent Protection (50/51G)

The normal operating power system is three-phase symmetrical, its zero-sequence current and
voltage are theoretically zero. Most of the faults are three-phase asymmetrical, according to the
asymmetry of the fault, various protections reflect sequence component principle can be
constituted. Earth fault overcurrent protection has been widely used in power systems, it can be
used for the fault conditions that zero-sequence fault current flows into the earth, including
single-phase earth fault and phase-to-phase short-circuit earth fault etc..
The device can provide six stages of earth fault overcurrent protection with independent logic.
Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout, definite-time

Date: 2019-04-24
dropout or inverse-time dropout. Users can choose whether it is blocked by the direction control
element or the harmonic control element, users can also choose whether it is controlled by cold
load pickup. The direction control element can be set as no direction, forward direction and
reverse direction. The zero-sequence current used by earth fault overcurrent protection can be
calculated zero-sequence current or the measured zero-sequence current, it can operate to trip or
alarm, it can be enabled or blocked by the external binary input.
Earth fault overcurrent protection can be enabled or disabled via the settings or binary input
signals, for some specific applications, the protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block earth fault overcurrent
protection. The enabling and blocking logic of earth fault overcurrent protection is shown in the
3 figure below:
EN 50/51Gx.En &
50/51Gx.On
SIG 50/51Gx.Enable
&
SIG 50/51Gx.Block ≥1 50/51Gx.Blocked
SIG Fail_Device
&
50/51Gx.Valid
Figure 3.6-1 The enabling and blocking logic of earth fault overcurrent protection
The logic diagram of the fault detector element of earth fault overcurrent protection is as follows:
SET 3I0>0.95*[50/51Gx.3I0_Set] & 50/51Gx.Pkp

0 500ms
&
SIG 50/51Gx.On &
FD.Pkp
SIG 50/51Gx.Valid
EN [50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.6-2 Logic diagram of the fault detector element of earth fault overcurrent protection
In order to ensure the selectivity of earth fault overcurrent protection, direction control element is
introduced. The setting [50/51Gx.Opt_Dir] (x=1~6) is used for users to select the directional mode
of each stage of earth fault overcurrent protection: no direction, forward direction and reverse
The operation boundary of the forward direction element can be set by [50/51G.DIR.phi_Min_Fwd]
and [50/51G.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51G.DIR.phi_Min_Rev] and [50/51G.DIR.phi_Max_Rev].

Date: 2019-04-24
-U0
[50/51G.DIR.phi_Min_Fwd]
Non-operating I0
area
Operating area in
[50/51G.DIR.phi_Max_Rev] forward direction
[50/51G.DIR.RCA]
Operating area in
reverse direction
3
[50/51G.DIR.phi_Max_Fwd]
Non-operating
area
[50/51G.DIR.phi_Min_Rev]
Figure 3.6-3 The direction element operation characteristics when zero-sequence voltage is polarized
Where:
[50/51G.DIR.RCA].
The forward direction characteristic is:
-[50/51G.DIR.phi_Min_Fwd]<angle<[50/51G.DIR.phi_Max_Fwd]
The reverse direction characteristic is:
180-[50/51G.DIR.phi_Min_Rev]<angle<180+[50/51G.DIR.phi_Max_Rev]
Polarized
Polarization mode Operating current Angle difference
voltage
Zero-sequence Calculated residual current 3I0_Cal -3U0 angle=angle(-3U0)-angle(3I0_Cal)-RCA
voltage polarized Measured residual current 3I0_Ext -3U0 angle=angle(-3U0)-angle(3I0_Ext)-RCA
The logic diagram of the forward direction element and reverse direction element is as follows.

Date: 2019-04-24
EN [50/51G.En_VTS_Blk] &
>=1
SIG VTS.Alm
SIG 3I0_Ext, 3I0_Cal

& >=1
direction
Forward
criterion
50/51G.FwdDir.Op
SIG 3U0_Cal
3 EN [En_VT] &
SIG Prot.BI_En_VT
EN [50/51G.En_VTS_Blk] &
>=1
SIG VTS.Alm
& >=1
SIG 3I0_Ext, 3I0_Cal 50/51G.RevDir.Op
direction
Reverse
criterion
SIG 3U0_Cal
EN [En_VT] &
SIG Prot.BI_En_VT
Figure 3.6-4 Logic diagram of forward and reverse direction element of earth fault overcurrent protection
Where:
3I0_Ext is the measured residual current.
3I0_Cal is the calculated residual current.
3U0_Cal: the calculated residual voltage
3.6.1.2 Harmonic Control Element
Zero-sequence harmonic control element can be used together with earth fault overcurrent
protection when harmonic blocking is required, the zero-sequence current can be the calculated
zero-sequence current or the measured zero-sequence current.
When the percentage of second harmonic component to fundamental component of residual

current is greater than the setting [50/51G.HMB.K_Hm2], harmonic blocking element operates to
block stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm_Blk] is
enabled.

Date: 2019-04-24
When the fundamental zero-sequence current is greater than the setting [50/51G.HMB.I_Rls], the
harmonic blocking element is released.
The following figure shows the logic diagram of the harmonic control element of earth fault
SET 3I0>[50/51G.HMB.I_Rls]
&
SIG 3I0_Ext or 3I0_Cal
50/51G.Hm_Op
Harmonic
blocking
logi c
3
SET 3I02/3I0>[50/51G.HMB.K_Hm2]
Figure 3.6-5 Logic diagram of harmonic control element of earth fault overcurrent protection
Where:
3I0_Ext, 3I0_Cal: the measured residual current and the calculated residual current
3I02: the 2nd harmonic residual current
Earth fault overcurrent protection can operate without time delay or operate with a definite-time
limit, it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3
and ANSI C37.112 standards. Earth fault overcurrent protection can support definite-time limit,
IEC & ANSI standard inverse time limit and user-defined inverse-time limit, users can select the
wanted operating curve by the setting [50/51Gx.Opt_Curve], the relationship between the value of
the setting and the curve is shown in the table below.
50/51Gx.Opt_Curve Time Characteristic k α c tr


Date: 2019-04-24
Only when the setting [50/51Gx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Gx.K], [50/51Gx.C] and [50/51Gx.Alpha]
When I 0 > I 0 p , the protection operates immediately.
When I 0 > I 0 p , the protection operates with a time delay of top (i.e. the value of the setting
[50/51Gx.t_Op]), and the operation characteristic curve is shown in the following figure:
3 t
t op
I0p I0
Figure 3.6-6 Definite-time operation characteristic curve of earth fault overcurrent protection
When I 0 > I 0 p , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I 0 . The larger current is, the smaller the operating time is, but not
unlimited. When the current is large enough to a certain threshold ( I 0 p ), the inverse-time
operating time will not continue to decrease, then the operation characteristic becomes the
definite-time characteristic, and the operating time is tmin , i.e. the setting [50/51Gx.tmin]. The
 k 
t   
 c   TMS
(I 0 / I 0P )  1 
Where:
I 0 p is the current setting [50/51Gx.3I0_Set];

TMS is the inverse-time time multiplier, i.e. the setting [50/51Gx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Gx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Gx.C];

Date: 2019-04-24
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Gx.Alpha];
I is the measured zero-sequence current.
t min
I0P ID I0
Figure 3.6-7 Inverse-time operation characteristic curve of earth fault overcurrent protection
When the applied zero-sequence current I 0 is not a fixed value, but changes with time, the
operating behavior of the protection is shown in the following equation:
T0
1
 t ( I )dt
0 0
1
Where:
t(I0) is the theoretical operating time when the current is I 0 .
The supported dropout characteristics of the earth fault overcurrent protection include
instantaneous dropout, definite-time dropout and ANSI inverse-time dropout.


Date: 2019-04-24
When I 0 <0.95* I 0 p , the protection drops out immediately.
When I 0 <0.95* I 0 p , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51Gx.t_DropOut]), the dropout characteristic curve is shown in the following figure:
Start time
I0>I0p
3
Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.6-8 Definite-time dropout characteristic of earth fault overcurrent protection
When I 0 > I 0 p , the inverse-time operating accumulator begins to accumulate, the accumulated
tp
1
Itp   t(I
0
0
dt
)
At this time, if I 0 <0.95* I 0 p , the protection element starts dropout, and the dropout characteristic
TR
1
I tp   dt  0
0
t R ( I )
Where:

Date: 2019-04-24
tR( I ) is the dropout characteristic equation
When I 0 <0.95* I 0 p , the inverse-time dropout characteristic equation is as follows:
 tr 
tR   2
 TMS
1  ( I / I P ) 
Where:
IP is the current setting [50/51Gx.3I0_Set]; 3

TMS is the inverse-time factor, i.e. the setting [50/51Gx.TMS];
the protection operates.
I 0 is the measured current.

When 0.95* I 0 p < I 0 < I 0 p , the accumulator will neither accumulate nor drop out
tr
I0 P I0
Figure 3.6-9 Inverse-time dropout characteristic curve of earth fault overcurrent protection

Date: 2019-04-24
Start time
I0>I0p
Start
signal
Operating
signal
3 Operating threshold
Protection
operate
Operating
counter

Dropout time
Dropout time
Figure 3.6-10 Inverse-time dropout characteristic of earth fault overcurrent protection
50/51G
50/51Gx.Enable 50/51Gx.On
50/51Gx.Block 50/51Gx.Blocked
50/51Gx.Valid
50/51Gx.St
50/51Gx.Op
50/51Gx.Alm
50/51Gx.FwdDir.Op
50/51Gx.RevDir.Op
3.6.3 I/O Signal

Table 3.6-1 Input/output signals of earth fault overcurrent protection

Stage x of earth fault overcurrent protection enabling input, it is triggered from
1 50/51Gx.Enable
Stage x of earth fault overcurrent protection blocking input, it is triggered from
2 50/51Gx.Block

Date: 2019-04-24

1 50/51Gx.On Stage x of earth fault overcurrent protection is enabled
2 50/51Gx.Blocked Stage x of earth fault overcurrent protection is blocked
3 50/51Gx.Valid Stage x of earth fault overcurrent protection is valid
4 50/51Gx.St Stage x of earth fault overcurrent protection starts
5 50/51Gx.Op Stage x of earth fault overcurrent protection operates
6 50/51Gx.Alm Stage x of earth fault overcurrent protection alarms
7 50/51G.FwdDir.Op The forward direction element of earth fault overcurrent protection operates
8 50/51G.RevDir.Op The reverse direction element of earth fault overcurrent protection operates
3.6.4 Logic
3
SET 3I0>[50/51Gx.3I0_Set]
SIG 50/51G.FwdDir.Op 50/51Gx.St

&
selection
Direction
SIG 50/51G.RevDir.Op & Timer

t
SET [50/51Gx.Opt_Dir] t
SIG 50/51G.HMB.Op &
EN [50/51Gx.En_Hm_Blk]
SIG 50/51Gx.Pkp
&
50/51Gx.Op
SET [50/51Gx.Opt_Trp/Alm]=Trp
&
50/51Gx.Alm
SET [50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.6-11 Logic diagram of earth fault overcurrent protection
3.6.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  ROC Settings
Table 3.6-2 Settings of earth fault overcurrent protection
Default Uni
No. Settings Range Step Description
value t
The relay characteristic angle
of the direction control
1 50/51G.DIR.RCA -180~179 45 deg 1
element of earth fault

Date: 2019-04-24
Default Uni
value t
50/51G.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd earth fault overcurrent
protection
50/51G.DIR.phi_Max_ forward direction element of
3 10~90 90 deg 1
protection
3 50/51G.DIR.phi_Min_
reverse direction element of
4 10~90 90 deg 1
Rev earth fault overcurrent
protection
50/51G.DIR.phi_Max_ reverse direction element of
5 10~90 90 deg 1
protection
The minimum operating
current setting for the direction
6 50/51G.DIR.I_Min (0.05~1)In 0.05 - 0.001
control element of earth fault
voltage setting for the direction
7 50/51G.DIR.U_Min 1~10 4 V 0.001
behavior of earth fault
overcurrent protection when
VT circuit supervision function
is enabled and VT circuit
failure happens.
Disabled;
8 50/51G.En_VTS_Blk Disabled - - Disabled: earth fault
Enabled
overcurrent protection will not
effected by VT circuit failure
earth fault overcurrent
protection will be blocked by
VT circuit failure signal
harmonic control element of
9 50/51G.HMB.K_Hm2 0.1~1 0.2 - 0.001
protection

Date: 2019-04-24
Default Uni
value t
The current setting for
releasing the harmonic control
10 50/51G.HMB.I_Rls 2~150 20 A 0.001
residual current that used for
stage 1 of earth fault
Ext; overcurrent protection
11 50/51G1.Opt_3I0 Ext - -
Cal Ext: the measured residual
current
3
Cal: the calculated residual
current
The current setting of stage 1
12 50/51G1.3I0_Set 0.05~200 15 A 0.001 of earth fault overcurrent
protection
13 50/51G1.t_Op 0 ~100 0.1 s 0.001 stage 1 of earth fault
14 50/51G1.t_DropOut 0 ~100 0 s 0.001 stage 1 of earth fault
directional mode of stage 1 of
Non_Direction
al; Non_Directio
15 50/51G1.Opt_Dir - - protection.
Forward; nal
1: no direction;
Reverse
2: forward direction;
3: reverse direction.
enabling/disabling the
the stage 1 of earth fault
Disabled: stage 1 of earth fault
Disabled;
16 50/51G1.En_Hm_Blk Disabled - - overcurrent protection is not
Enabled
control element
Enabled: stage 1 of earth fault
control element

Date: 2019-04-24
Default Uni
value t
Disabled; enabling/disabling the stage 1
17 50/51G1.En Enabled - -
Enabled of earth fault overcurrent
protection
Enabling stage 1 earth fault
Trp;
18 50/51G1.Opt_Trp/Alm Trp - - to trip or alarm.
Alm
3 ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
inverse-time operation
ANSILT;
19 50/51G1.Opt_Curve IECDefTime - - characteristic curve of stage 1
IECN;
of earth fault overcurrent
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
characteristic curve of stage 1
Inst;
50/51G1.Opt_Curve_ of earth fault overcurrent
20 DefTime; Inst - -
DropOut protection
IDMT
Inst: instantaneous dropout
21 50/51G1.TMS 0.04~ 20 1 - 0.001 stage 1 of earth fault
22 50/51G1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of earth fault

Date: 2019-04-24
Default Uni
value t
23 50/51G1.K 0.001~120 0.14 - 0.0001 operation characteristic of
24 50/51G1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
stage 1 of
earth fault
3
25 50/51G1.C 0 ~1 0 - 0.0001 operation characteristic of
26 50/51G2.Opt_3I0 Ext - -
current
current
protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse

Date: 2019-04-24
Default Uni
value t
Disabled;
Enabled
3 control element
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default Uni
value t
Inst;
DropOut protection
IDMT
36 50/51G2.TMS 0.04~ 20 1 - 0.001

3
41 50/51G3.Opt_3I0 Ext - -
current
current
protection

Date: 2019-04-24
Default Uni
value t
Non_Direction
3 45 50/51G3.Opt_Dir
al; Non_Directio
- -
earth
protection.
fault overcurrent
Forward; nal
1: no direction;
Reverse
Disabled;
Enabled
control element
control element
protection
Trp;
Alm

Date: 2019-04-24
Default Uni
value t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
of earth fault overcurrent 3
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT

Date: 2019-04-24
Default Uni
value t
3 56 50/51G4.Opt_3I0
Ext;
Cal
Ext - -
Ext: the measured residual
current
current
protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse
Disabled;
Enabled
control element
control element

Date: 2019-04-24
Default Uni
value t
protection
Trp;
Alm
ANSIE;
3
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT

Date: 2019-04-24
Default Uni
value t
3 stage 4 of
earth fault

71 50/51G5.Opt_3I0 Ext - -
current
current
protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse

Date: 2019-04-24
Default Uni
value t
Disabled;
Enabled
control element
3
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default Uni
value t
Inst;
DropOut protection
IDMT
3 81 50/51G5.TMS 0.04~ 20 1 - 0.001

86 50/51G6.Opt_3I0 Ext - -
current
current
protection

Date: 2019-04-24
Default Uni
value t
Non_Direction
90 50/51G6.Opt_Dir
al; Non_Directio
- -
earth
protection.
fault overcurrent
3
Forward; nal
1: no direction;
Reverse
Disabled;
Enabled
control element
control element
protection
Trp;
Alm

Date: 2019-04-24
Default Uni
value t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
3 IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT

Date: 2019-04-24
Default Uni
value t
3.7 Another Group of Earth Fault Overcurrent Protection

For the applications of some grounding transformers and station transformers that two sets of
residual currents are required, the device provides another group of earth fault overcurrent 3
protection.

The device can provide six stages of another group of earth fault overcurrent protection with
independent logic. Each stage can be independently set as definite-time characteristics or
inverse-time characteristics. The dropout characteristics can be set as instantaneous dropout,
definite-time dropout or inverse-time dropout. The protection fixedly adopts the measured residual
current, the calculated residual current is not supported. It can operate to trip or alarm, it can be
enabled or blocked by the external binary input.
Another group of earth fault overcurrent protection can be enabled or disabled via the settings or
binary input signals, for some specific applications, the protection needs to be blocked by the
external signal, so the device provides a function block input signal to be used to block another
group of earth fault overcurrent protection. The enabling and blocking logic of another group of
earth fault overcurrent protection is shown in the figure below:
EN A.50/51Gx.En &
A.50/51Gx.On
SIG A.50/51Gx.Enable
&
SIG A.50/51Gx.Block ≥1 A.50/51Gx.Blocked
SIG Fail_Device
&
A.50/51Gx.Valid
Figure 3.7-1 The enabling and blocking logic of another group of earth fault overcurrent protection
The logic diagram of the fault detector element of another group of earth fault overcurrent
protection is as follows:

Date: 2019-04-24
SET 3I0>0.95*[A.50/51Gx.3I0_Set] & A.50/51Gx.Pkp

0 500ms
&
SIG A.50/51Gx.On &
FD.Pkp
SIG A.50/51Gx.Valid
EN [A.50/51Gx.Opt_Trp/Alm]=Alm
Figure 3.7-2 Logic diagram of the fault detector element of another group of earth fault overcurrent
protection

3 Another group of earth fault overcurrent protection can operate without time delay or operate with
a definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets
the IEC60255-3 and ANSI C37.112 standards. Another group of earth fault overcurrent protection
can support definite-time limit, IEC & ANSI standard inverse time limit and user-defined
inverse-time limit, users can select the wanted operating curve by the setting
[A.50/51Gx.Opt_Curve], the relationship between the value of the setting and the curve is shown
in the table below.
A.50/51Gx.Opt_Curve Time Characteristic k α c tr

Only when the setting [A.50/51Gx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [A.50/51Gx.K], [A.50/51Gx.C] and
[A.50/51Gx.Alpha] are useful, the inverse-time operating curve is determined by the three
settings.

Date: 2019-04-24
[A.50/51Gx.t_Op]), and the operation characteristic curve is shown in the following figure:
3
t op
I0p I0
Figure 3.7-3 Definite-time operation characteristic curve of another group of earth fault overcurrent
protection
affected by the applied current I 0 . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [A.50/51Gx.tmin]. The inverse-time
operation characteristic equation is:
 k 
t   
 c   TMS
(I 0 / I 0P )  1 
Where:
I 0 p is the current setting [A.50/51Gx.3I0_Set];

TMS is the inverse-time time multiplier, i.e. the setting [A.50/51Gx.TMS];
k is the inverse-time coefficient K, i.e. the setting [A.50/51Gx.K];

c is the inverse-time coefficient C, i.e. the setting [A.50/51Gx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [A.50/51Gx.Alpha];
I 0 is the measured zero-sequence current.


Date: 2019-04-24
3 t min
I0P ID I0
Figure 3.7-4 Inverse-time operation characteristic curve of another group of earth fault overcurrent
protection
When the applied zero-sequence current I 0 is not a fixed value, but changes with time, the
T0
1
 t ( I )dt
0 0
1
Where:
t(I0) is the theoretical operating time when the current is I 0 .
The supported dropout characteristics of another group of earth fault overcurrent protection
include instantaneous dropout, definite-time dropout and ANSI inverse-time dropout.


Date: 2019-04-24
setting [A.50/51Gx.t_DropOut]), and the dropout characteristic curve is shown in the following
figure:
Start time
I0>I0p
Start
signal
3
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.7-5 Definite-time dropout characteristic of another group of earth fault overcurrent protection
tp
1
Itp   t(I
0
0
dt
)
TR
1
I tp   dt  0
0
t R ( I )
Where:

Date: 2019-04-24
tR( I ) is the dropout characteristic equation
 tr 
tR   2
 TMS
1  ( I / I P ) 
Where:
3 IP is the current setting [A.50/51Gx.3I0_Set];
TMS is the inverse-time factor, i.e. the setting [A.50/51Gx.TMS];

tr
I0 P I0
Figure 3.7-6 Inverse-time dropout characteristic curve of another group of earth fault overcurrent
protection

Date: 2019-04-24
Start time
I0>I0p
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter

Dropout time
Dropout time
Figure 3.7-7 Inverse-time dropout characteristic of another group of earth fault overcurrent protection
A.50/51G
A.50/51Gx.On
A.50/51Gx.Enable A.50/51Gx.Blocked
A.50/51Gx.Block A.50/51Gx.Valid
A.50/51Gx.St
A.50/51Gx.Op
A.50/51Gx.Alm
3.7.3 I/O Signal

Table 3.7-1 Input/output signals of another group of earth fault overcurrent protection

Stage x of another group of earth fault overcurrent protection enabling input, it
1 A.50/51Gx.Enable
is triggered from binary input or programmable logic etc. (x=1~6)
Stage x of another group of earth fault overcurrent protection blocking input, it
2 A.50/51Gx.Block
is triggered from binary input or programmable logic etc. (x=1~6)
1 A.50/51Gx.On Stage x of another group of earth fault overcurrent protection is enabled
2 A.50/51Gx.Blocked Stage x of another group of earth fault overcurrent protection is blocked
3 A.50/51Gx.Valid Stage x of another group of earth fault overcurrent protection is valid

Date: 2019-04-24

4 A.50/51Gx.St Stage x of another group of earth fault overcurrent protection starts
5 A.50/51Gx.Op Stage x of another group of earth fault overcurrent protection operates
6 A.50/51Gx.Alm Stage x of another group of earth fault overcurrent protection alarms
3.7.4 Logic
A.50/51Gx.St
Timer &
SET 3I0>[A.50/51Gx.3I0_Set] & A.50/51Gx.Op
t
3 SIG A.50/51Gx.Pkp
t
SET [A.50/51Gx.Opt_Trp/Alm] = Trp &

A.50/51Gx.Alm
SET [A.50/51Gx.Opt_Trp/Alm] = Alm
Figure 3.7-8 Logic diagram of another group of earth fault overcurrent protection
3.7.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  ROC2 Settings
Table 3.7-2 Settings of another group of earth fault overcurrent protection
Default
value
The current setting of
stage 1 of another group of
1 A.50/51G1.3I0_Set 0.05~200 15 A 0.001
protection
The operating time setting
of stage 1 of another group
2 A.50/51G1.t_Op 0 ~100 0.1 s 0.001
protection
3 A.50/51G1.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
4 A.50/51G1.En Enabled - - stage 1 of another group of
Enabled
protection

Date: 2019-04-24
Default
value
Enabling stage 1 of
another group of earth fault
Trp; overcurrent protection
5 A.50/51G1.Opt_Trp/Alm Trp - -
Alm operate to trip or alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
3
ANSIDefTime;
ANSILTE; The setting for selecting
ANSILTV; the inverse-time operation
ANSILT; characteristic curve of
6 A.50/51G1.Opt_Curve IECDefTime - -
IECN; stage 1 of another group of
IECV; earth fault overcurrent
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
The setting for selecting
the inverse-time dropout
characteristic curve of
Inst; earth fault overcurrent
A.50/51G1.Opt_Curve_D
7 DefTime; Inst - - protection
ropOut
IDMT Inst: instantaneous
dropout
DefTime: definite-time
dropout
The time multiplier setting
8 A.50/51G1.TMS 0.04~ 20 1 - 0.001
protection
time setting of stage 1 of
9 A.50/51G1.tmin 0 ~10 0.02 s 0.001

Date: 2019-04-24
Default
value
operation characteristic of
10 A.50/51G1.K 0.001~120 0.14 - 0.0001
protection
3 11 A.50/51G1.Alpha 0.01 ~3 0.02 - 0.0001

protection
12 A.50/51G1.C 0 ~1 0 - 0.0001
protection
13 A.50/51G2.3I0_Set 0.05~200 15 A 0.001
protection
14 A.50/51G2.t_Op 0 ~100 0.1 s 0.001
protection
15 A.50/51G2.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 2 of

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IECN;
IECV;
3
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
dropout
dropout
20 A.50/51G2.TMS 0.04~ 20 1 - 0.001
protection
21 A.50/51G2.tmin 0 ~10 0.02 s 0.001
22 A.50/51G2.K 0.001~120 0.14 - 0.0001
protection

Date: 2019-04-24
Default
value
23 A.50/51G2.Alpha 0.01 ~3 0.02 - 0.0001
protection
3 24 A.50/51G2.C 0 ~1 0 - 0.0001
protection
25 A.50/51G3.3I0_Set 0.05~200 15 A 0.001
protection
26 A.50/51G3.t_Op 0 ~100 0.1 s 0.001
protection
27 A.50/51G3.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 3 of

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IECN;
IECV;
3
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
dropout
dropout
32 A.50/51G3.TMS 0.04~ 20 1 - 0.001
protection
33 A.50/51G3.tmin 0 ~10 0.02 s 0.001
34 A.50/51G3.K 0.001~120 0.14 - 0.0001
protection

Date: 2019-04-24
Default
value
35 A.50/51G3.Alpha 0.01 ~3 0.02 - 0.0001
protection
3 36 A.50/51G3.C 0 ~1 0 - 0.0001
protection
37 A.50/51G4.3I0_Set 0.05~200 15 A 0.001
protection
38 A.50/51G4.t_Op 0 ~100 0.1 s 0.001
protection
39 A.50/51G4.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 4 of

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IECN;
IECV;
3
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
dropout
dropout
44 A.50/51G4.TMS 0.04~ 20 1 - 0.001
protection
45 A.50/51G4.tmin 0 ~10 0.02 s 0.001
46 A.50/51G4.K 0.001~120 0.14 - 0.0001
protection

Date: 2019-04-24
Default
value
47 A.50/51G4.Alpha 0.01 ~3 0.02 - 0.0001
protection
3 48 A.50/51G4.C 0 ~1 0 - 0.0001
protection
49 A.50/51G5.3I0_Set 0.05~200 15 A 0.001
protection
50 A.50/51G5.t_Op 0 ~100 0.1 s 0.001
protection
51 A.50/51G5.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 5 of

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IECN;
IECV;
3
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
dropout
dropout
56 A.50/51G5.TMS 0.04~ 20 1 - 0.001
protection
57 A.50/51G5.tmin 0 ~10 0.02 s 0.001
58 A.50/51G5.K 0.001~120 0.14 - 0.0001
protection

Date: 2019-04-24
Default
value
59 A.50/51G5.Alpha 0.01 ~3 0.02 - 0.0001
protection
3 60 A.50/51G5.C 0 ~1 0 - 0.0001
protection
61 A.50/51G6.3I0_Set 0.05~200 15 A 0.001
protection
62 A.50/51G6.t_Op 0 ~100 0.1 s 0.001
protection
63 A.50/51G6.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 6 of

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IECN;
IECV;
3
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
ropOut
dropout
dropout
68 A.50/51G6.TMS 0.04~ 20 1 - 0.001
protection
69 A.50/51G6.tmin 0 ~10 0.02 s 0.001
70 A.50/51G6.K 0.001~120 0.14 - 0.0001
protection

Date: 2019-04-24
Default
value
71 A.50/51G6.Alpha 0.01 ~3 0.02 - 0.0001
protection
3 72 A.50/51G6.C 0 ~1 0 - 0.0001
protection
3.8 Negative-sequence Overcurrent Protection (50/51Q)

When a phase-to-phase phase fault occurs in the system, the fault current is small, and the phase
current criterion may not be able to detect the fault. At this time, the negative-sequence
overcurrent protection with higher sensitivity can be used. Negative-sequence overcurrent
protection can also be used to detect the broken phase operation or load unbalance.

The device can provide two stages of negative-sequence overcurrent protection with independent
logic. Each stage can be independently set as definite-time characteristics or inverse-time
characteristics. The dropout characteristics can be set as instantaneous dropout, definite-time
dropout or inverse-time dropout. For a double-circuit or a ring network line, the negative-sequence
fault current may have different flow direction. Considering the protection selectivity, the
negative-sequence overcurrent protection can be blocked by the direction control element.
Negative-sequence overcurrent protection can operate to trip or alarm, it can be enabled or
blocked by the external binary input.
Negative-sequence overcurrent protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, the protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block negative-sequence
overcurrent protection. The enabling and blocking logic of negative-sequence overcurrent
protection is shown in the figure below:

Date: 2019-04-24
EN [50/51Qx.En] &
50/51Qx.On
SIG 50/51Qx.Enable
&
SIG 50/51Qx.Block ≥1 50/51Qx.Blocked
SIG Fail_Device
&
50/51Qx.Valid
Figure 3.8-1 The enabling and blocking logic of negative-sequence overcurrent protection
3
The logic diagram of the fault detector element of negative-sequence overcurrent protection is as
follows:
SET I2>0.95×[50/51Qx.I2_Set] & 50/51Qx.Pkp

0 500ms &
SIG 50/51Qx.On &
FD.Pkp
SIG 50/51Qx.Valid
SET [50/51Qx.Opt_Trp/Alm]=Alm
Figure 3.8-2 Logic diagram of the fault detector element of negative-sequence overcurrent protection
In order to ensure the selectivity of negative-sequence overcurrent protection, direction control

element is introduced. The setting [50/51Qx.Opt_Dir] (x=1 and 2) is used for users to select the
directional mode of each stage of negative-sequence overcurrent protection: no direction, forward
direction and reverse direction are selectable.
The operation boundary of the forward direction element can be set by [50/51Q.DIR.phi_Min_Fwd]
and [50/51Q.DIR.phi_Max_Fwd]. The operation boundary of the reverse direction element can be
set by [50/51Q.DIR.phi_Min_Rev] and [50/51Q.DIR.phi_Max_Rev].
For the direction control element of negative-sequence overcurrent protection, the

negative-sequence voltage is polarized, the operation characteristic is shown as below.

Date: 2019-04-24
-U2
[50/51Q.DIR.phi_Min_Fwd]
Non-operating I2
area
[50/51Q.DIR.phi_Max_Rev]
Operating area in
forward direction
[50/51Q.DIR.RCA]
3 Operating area in
reverse direction
[50/51Q.DIR.phi_Max_Fwd]
Non-operating
area
[50/51Q.DIR.phi_Min_Rev]
Figure 3.8-3 The direction element operation characteristics of negative-sequence overcurrent protection
Where:
[50/51Q.DIR.RCA].

-[50/51Q.DIR.phi_Min_Fwd]<angle<[50/51Q.DIR.phi_Max_Fwd]

180-[50/51Q.DIR.phi_Min_Rev]<angle<180+[50/51Q.DIR.phi_Max_Rev]
Polarized
voltage
Negative-sequence
Negative-sequence current I2 -U2 Angle=Angle(-U2)-Angle(I2)-RCA
voltage polarized

Date: 2019-04-24
EN [50/51Q.En_VTS_Blk] &
>=1
SIG VTS.Alm
& >=1
SIG I2 50/51Q.FwdDir.Op
direction
Forward
criterion
SIG U2
EN [En_VT] & 3
SIG Prot.BI_En_VT
EN [50/51Q.En_VTS_Blk] &
>=1
SIG VTS.Alm
& >=1
SIG I2 50/51Q.RevDir.Op
direction
Reverse
criterion
SIG U2
EN [En_VT] &
SIG Prot.BI_En_VT
Figure 3.8-4 Logic diagram of forward and reverse direction element of negative-sequence overcurrent
protection
Negative-sequence overcurrent protection can operate instantaneously or operate with a

definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets the
IEC60255-3 and ANSI C37.112 standards. Negative-sequence overcurrent protection can support
definite-time limit, IEC & ANSI standard inverse time limit and user-defined inverse-time limit,
users can select the wanted operating curve by the setting [50/51Qx.Opt_Curve] (x=1 or 2), the
relationship between the value of the setting and the curve is shown in the table below.
50/51Qx.Opt_Curve Time Characteristic k α c tr


Date: 2019-04-24
50/51Qx.Opt_Curve Time Characteristic k α c tr

3 IECDefTime IEC Definite Time - - - -
Only when the setting [50/51Qx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51Qx.K], [50/51Qx.C] and [50/51Qx.Alpha]
 Without time delay (Instantaneously)
[50/51Qx.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
I2p I2
Figure 3.8-5 Definite-time operation characteristic curve of negative-sequence overcurrent protection

Date: 2019-04-24
affected by the applied current I 2 . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Qx.tmin]. The inverse-time
Where:
I 2 p is the current setting [50/51Qx.I2_Set]; 3

TMS is the inverse-time time multiplier, i.e. the setting [50/51Qx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Qx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Qx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Qx.Alpha];
I 2 is the measured negative-sequence overcurrent current.

t min
I2P ID I2
Figure 3.8-6 Inverse-time operation characteristic curve of negative-sequence overcurrent protection
When the applied negative-sequence overcurrent current I 2 is not a fixed value, but changes
with time, the operating behavior of the protection is shown in the following equation:

Date: 2019-04-24
Where:
t(I2) is the theoretical operating time when the current is I2 .

The supported dropout characteristics of the negative-sequence overcurrent protection include

instantaneous dropout, definite-time dropout and ANSI inverse-time dropout.

3 dropout or definite-time dropout, if inverse-time dropout is selected, the alarm signal
setting [50/51Qx.t_DropOut]), and the dropout characteristic curve is shown in the following
figure:

Date: 2019-04-24
Start time
I2>I2p
Start
signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.8-7 Definite-time dropout characteristic of negative-sequence overcurrent protection
tp
1
I tp   dt
0
t ( I 2 )
TR
1
I tp   dt  0
0
tR ( I 2 )
Where:
tR( I 2 ) is the dropout characteristic equation

Date: 2019-04-24
Where:
I 2 p is the current setting [50/51Qx.I2_Set];
3 TMS is the inverse-time factor, i.e. the setting [50/51Qx.TMS];
tr
Figure 3.8-8 Inverse-time dropout characteristic curve of negative-sequence overcurrent protection

Date: 2019-04-24
Start time
I2>I2p
Start
signal
Operating
signal
Operating threshold
Protection
operate
3
Operating
counter

Dropout time
Dropout time
Figure 3.8-9 Inverse-time dropout characteristic of negative-sequence overcurrent protection
50/51Q
50/51Qx.On
50/51Qx.Enable
50/51Qx.Blocked
50/51Qx.Block
50/51Qx.Valid
50/51Qx.St
50/51Qx.Op
50/51Qx.Alm
50/51Q.FwdDir.Op
50/51Q.RevDir.Op
3.8.3 I/O Signal

Table 3.8-1 Input/output signals of negative-sequence overcurrent protection

Stage x of negative-sequence overcurrent protection enabling input, it is
1 50/51Qx.Enable
triggered from binary input or programmable logic etc. (x=1~2)
Stage x of negative-sequence overcurrent protection blocking input, it is
2 50/51Qx.Block
1 50/51Qx.On Stage x of negative-sequence overcurrent protection is enabled

Date: 2019-04-24

2 50/51Qx.Blocked Stage x of negative-sequence overcurrent protection is blocked
3 50/51Qx.Valid Stage x of negative-sequence overcurrent protection is valid
4 50/51Qx.St Stage x of negative-sequence overcurrent protection starts
5 50/51Qx.Op Stage x of negative-sequence overcurrent protection operates
6 50/51Qx.Alm Stage x of negative-sequence overcurrent protection alarms
The forward direction element of negative-sequence overcurrent protection
7 50/51Q.FwdDir.Op
operates
The reverse direction element of negative-sequence overcurrent protection
8 50/51Q.RevDir.Op
operates
3 3.8.4 Logic
SET I2>[50/51Qx.I2_Set]
50/51Qx.St
SIG 50/51Q.FwdDir.Op
&
& Timer
selection
Direction
t
SIG 50/51Q.RevDir.Op
t
SET [50/51Qx.Opt_Dir]
SIG 50/51Qx.Pkp
&
50/51Qx.Op
SET [50/51Qx.Opt_Trp/Alm]=Trp
&
50/51Qx.Alm
SET [50/51Qx.Opt_Trp/Alm]=Alm
Figure 3.8-10 Logic diagram of negative-sequence overcurrent protection
3.8.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  NegOC Settings
Table 3.8-2 Settings of negative-sequence overcurrent protection
Default
value
1 50/51Q.DIR.RCA -180~179 45 deg 1
element of negative-sequence
50/51Q.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd negative-sequence

Date: 2019-04-24
Default
value
50/51Q.DIR.phi_Max forward direction element of
3 10~90 90 deg 1
_Fwd negative-sequence
50/51Q.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
Rev negative-sequence
50/51Q.DIR.phi_Max
reverse direction element of
3
5 10~90 90 deg 1
_Rev negative-sequence
6 50/51Q.DIR.I_Min (0.05~1)In 0.05 - 0.001 control element of
negative-sequence
7 50/51Q.DIR.U_Min 1.0~10.0 4 V 0.001 control element of
negative-sequence
behavior of
negative-sequence
failure happens.
Disabled;
8 50/51Q.En_VTS_Blk Disabled - - Disabled: negative-sequence
Enabled
negative-sequence
overcurrent protection will be
blocked by VT circuit failure
signal
9 50/51Q1.I2_Set 0.05~200 15 A 0.001 of negative-sequence

Date: 2019-04-24
Default
value
10 50/51Q1.t_Op 0.03 ~100 0.1 s 0.001 stage 1 of negative-sequence
11 50/51Q1.t_DropOut 0 ~100 0 s 0.001 stage 1 of negative-sequence
Non_Direction
3 12 50/51Q1.Opt_Dir
al Non_Directio
- -
negative-sequence
Forward nal
1: no direction;
Reverse
13 50/51Q1.En Enabled - -
Enabled of negative-sequence
Enabling stage 1 of
negative-sequence
Trp; overcurrent protection operate
14 50/51Q1.Opt_Trp/Alm Trp - -
Alm to trip or alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
15 50/51Q1.Opt_Curve IECDefTime - - characteristic curve of stage 1
IECN;
of negative-sequence
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default
value
Inst;
50/51Q1.Opt_Curve_ of negative-sequence
DropOut overcurrent protection
IDMT
17 50/51Q1.TMS 0.04~ 20 1 - 0.001

stage 1 of negative-sequence
3
setting of stage 1 of
18 50/51Q1.tmin 0 ~10 0.02 s 0.001
negative-sequence
19 50/51Q1.K 0.001~120 0.14 - 0.0001 operation characteristic of
20 50/51Q1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
21 50/51Q1.C 0 ~1 0 - 0.0001 operation characteristic of

Date: 2019-04-24
Default
value
Non_Direction
negative-sequence
al Non_Directio
25 50/51Q2.Opt_Dir - - overcurrent protection.
Forward nal
1: no direction;
Reverse
3 26 50/51Q2.En
Disabled;
Enabled
Enabled - -
enabling/disabling the stage 2
Enabling stage 2 of
negative-sequence
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT

Date: 2019-04-24
Default
value
30 50/51Q2.TMS 0.04~ 20 1 - 0.001 stage 2 of negative-sequence
31 50/51Q2.tmin 0 ~10 0.02 s 0.001
negative-sequence
32 50/51Q2.K 0.001~120 0.14 - 0.0001

customized
operation
inverse-time
characteristic of
3
3.9 Sensitive Earth Fault Protection (50/51SEF)

If a single-phase earth fault occurs in some non-effectively grounded systems, the amplitude of
the earth current is small due to the large ground resistance, so it is difficult to detect by the
ordinary CTs. Sensitive earth fault protection using high-precision CT can effectively detect the
earth current.
The device can provide six stages of sensitive earth fault protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics.
The dropout characteristics can be set as instantaneous dropout, definite-time dropout or
inverse-time dropout. Users can choose whether it is blocked by the direction control element.
The direction control element can be set as no direction, forward direction and reverse direction.
The zero-sequence current used by sensitive earth fault protection is the measured
zero-sequence current from the high-precision CT. Sensitive earth fault protection can operate to
trip or alarm, it can be enabled or blocked by the external binary input.
Sensitive earth fault protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, the protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block sensitive earth fault protection.

Date: 2019-04-24
The enabling and blocking logic of sensitive earth fault protection is shown in the figure below:
EN 50/51SEFx.En &
50/51SEFx.On
SIG 50/51SEFx.Enable
&
SIG 50/51SEFx.Block ≥1 50/51SEFx.Blocked
SIG Fail_Device
&
50/51SEFx.Valid
3
Figure 3.9-1 The enabling and blocking logic of sensitive earth fault protection
The logic diagram of the fault detector element of sensitive earth fault protection is as follows:
SET Isef>0.95*[50/51SEFx.3I0_Set] & 50/51SEFx.Pkp

0 500ms
&
SIG 50/51SEFx.On &
FD.Pkp
SIG 50/51SEFx.Valid
EN [50/51SEFx.Opt_Trp/Alm]=Alm
Figure 3.9-2 Logic diagram of the fault detector element of sensitive earth fault protection
In order to ensure the selectivity of sensitive earth fault protection, direction control element is
introduced. The setting [50/51SEFx.Opt_Dir] (x: 1~6) is used for users to select the directional
mode of each stage of sensitive earth fault protection: no direction, forward direction and reverse

Date: 2019-04-24
-U0
[50/51SEF.DIR.phi_Min_Fwd]
Non-operating Isef
area
Operating area in
[50/51SEF.DIR.phi_Max_Rev] forward direction
[50/51SEF.DIR.RCA] 3
Operating area in
reverse direction
[50/51SEF.DIR.phi_Max_Fwd]
Non-operating
area
[50/51SEF.DIR.phi_Min_Rev]
Figure 3.9-3 The direction element operation characteristics of sensitive earth fault protection
Where:
[50/51SEF.DIR.RCA].
The operation boundary of the forward direction element can be set by

[50/51SEF.DIR.phi_Min_Fwd] and [50/51SEF.DIR.phi_Max_Fwd].
The operation boundary of the reverse direction element can be set as

[50/51SEF.DIR.phi_Min_Rev] and [50/51SEF.DIR.phi_Max_Rev].
-[50/51SEF.DIR.phi_Min_Fwd]<angle<[50/51SEF.DIR.phi_Max_Fwd]
180-[50/51SEF.DIR.phi_Min_Rev]<angle<180+[50/51SEF.DIR.phi_Max_Rev]
Polarized
voltage
Zero-sequence The sensitive earth fault current
-3U0 Angle=Angle(-3U0)-Angle(Isef)-RCA
voltage polarized Isef

Date: 2019-04-24
EN [50/51SEF.En_VTS_Blk] &
>=1
SIG VTS.Alm
SIG Isef
& >=1
Forward direction
50/51SEF.Fwd Dir.Op
3
criterion
SIG 3U0_Cal
SIG Prot.BI_En_VT &
EN [En_VT]
EN [50/51SEF.En_VTS_Blk] &
>=1
SIG VTS.Alm
SIG Isef
& >=1
Reverse direction
50/51SEF.RevDir.Op
criterion
SIG 3U0_Cal
SIG Prot.BI_En_VT &
EN [En_VT]
Figure 3.9-4 Logic diagram of forward and reverse direction element of sensitive earth fault protection
Sensitive earth fault protection can operate without time delay or operate with a definite-time limit,
it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and
ANSI C37.112 standards. Sensitive earth fault protection can support definite-time limit, IEC &
ANSI standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51SEFx.Opt_Curve] (x=1~6), the relationship between the
value of the setting and the curve is shown in the table below.

Date: 2019-04-24
50/51SEFx.Opt_Curve Time Characteristic k α c tr

IECV IEC Very inverse 13.5 1.0 0 - 3
Only when the setting [50/51SEFx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined
inverse-time characteristic is selected, the settings [50/51SEFx.K], [50/51SEFx.C] and
[50/51SEFx.Alpha] are useful, the inverse-time operating curve is determined by the three
settings.
When Isef > Isef _ set , the protection operates immediately.
When Isef > Isef _ set , the protection operates with a time delay of top (i.e. the value of the setting
[50/51SEFx.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2019-04-24
t op
I sef_set Isef
Figure 3.9-5 Definite-time operation characteristic curve of sensitive earth fault protection
When Isef > Isef _ set , the inverse-time accumulator begins to accumulate, and the operating time
is affected by the applied current Isef . The operating time will decrease with the current
increasing, but the operating time shall not less than tmin , i.e. the setting [50/51SEFx.tmin]. The
Where:
Isef _ set is the current setting [50/51SEFx.3I0_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51SEFx.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51SEFx.K];

c is the inverse-time coefficient C, i.e. the setting [50/51SEFx.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51SEFx.Alpha];
Isef is the measured zero-sequence current.


Date: 2019-04-24
t min 3
I Sef_set ID Isef
Figure 3.9-6 Inverse-time operation characteristic curve of sensitive earth fault protection
When the applied zero-sequence current Isef is not a fixed value, but changes with time, the
T0
1
 t(I
0 sef )
dt  1
Where:
t ( I sef ) is the theoretical operating time when the current is Isef .
The supported dropout characteristics of the sensitive earth fault protection include instantaneous
dropout, definite-time dropout and ANSI inverse-time dropout.

When Isef <0.95* Isef _ set , the protection drops out immediately.

Date: 2019-04-24
When Isef <0.95* Isef _ set , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51SEFx.t_DropOut]), and the dropout characteristic curve is shown in the following
figure:
Start time
Isef>Isef_set
3 Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.9-7 Definite-time dropout characteristic of sensitive earth fault protection
When Isef > Isef _ set , the inverse-time operating accumulator begins to accumulate, the
accumulated value after tp (Assuming tp is less than the theoretical operating time) is
calculated according to the following equation:
tp
1
I tp   dt
0
t ( I sef )
At this time, if Isef <0.95* Isef _ set , the protection element starts dropout, and the dropout
characteristic meets the following equation:
TR
1
I tp   dt  0
0
t R ( I sef )
Where:

Date: 2019-04-24
tR( I sef ) is the dropout characteristic equation
When Isef <0.95* Isef _ set , the inverse-time dropout characteristic equation is as follows:
Where:
Isef _ set is the current setting [50/51SEFx.3I0_Set];

3
TMS is the inverse-time factor, i.e. the setting [50/51SEFx.TMS];
Isef is the measured current.

When 0.95* Isef I
_ set < sef < Isef _ set , the accumulator will neither accumulate nor drop out
tr
Isef_set Isef
Figure 3.9-8 Inverse-time dropout characteristic curve of sensitive earth fault protection

Date: 2019-04-24
Start time
Isef>Isef_set
Start
signal
Operating
signal
3 Operating threshold
Protection
operate
Operating
counter

Dropout time
Dropout time
Figure 3.9-9 Inverse-time dropout characteristic of sensitive earth fault protection
50/51SEF
50/51SEFx.Enable 50/51SEFx.On
50/51SEFx.Block 50/51SEFx.Blocked
50/51SEFx.Valid
50/51SEFx.St
50/51SEFx.Op
50/51SEFx.Alm
50/51SEF.FwdDir.Op
50/51SEF.RevDir.Op
3.9.3 I/O Signal

Table 3.9-1 Input/output signals of sensitive earth fault protection

Stage x of sensitive earth fault protection enabling input, it is triggered from
1 50/51SEFx.Enable
Stage x of sensitive earth fault protection blocking input, it is triggered from
2 50/51SEFx.Block

Date: 2019-04-24

1 50/51SEFx.On Stage x of sensitive earth fault protection is enabled
2 50/51SEFx.Blocked Stage x of sensitive earth fault protection is blocked
3 50/51SEFx.Valid Stage x of sensitive earth fault protection is valid
4 50/51SEFx.St Stage x of sensitive earth fault protection starts
5 50/51SEFx.Op Stage x of sensitive earth fault protection operates
6 50/51SEFx.Alm Stage x of sensitive earth fault protection alarms
7 50/51SEF.FwdDir.Op The forward direction element of sensitive earth fault protection operates
8 50/51SEF.RevDir.Op The reverse direction element of sensitive earth fault protection operates
3.9.4 Logic
3
SET Isef>[50/51SEFX.3I0_Set]
50/51SEFx.St
SIG 50/51SEF.FwdDir.Op
&
& Timer
selection
Direction
t
SIG 50/51SEF.RevDir.Op
t
SET [50/51SEFx.Opt_Dir]
SIG 50/51SEFx.Pkp
&
50/51SEFx.Op
SET [50/51SEFx.Opt_Trp/Alm]=Trp
&
50/51SEFx.Alm
SET [50/51SEFx.Opt_Trp/Alm]=Alm
Figure 3.9-10 Logic diagram of sensitive earth fault protection
3.9.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  SEF Settings
Table 3.9-2 Settings of sensitive earth fault protection
Default
value
1 50/51SEF.DIR.RCA -180~179 45 deg 1 the direction control element of
sensitive earth fault protection
50/51SEF.DIR.phi_Mi
n_Fwd
50/51SEF.DIR.phi_M
ax_Fwd

Date: 2019-04-24
Default
value
50/51SEF.DIR.phi_Mi
n_Rev
50/51SEF.DIR.phi_M
ax_Rev
6 50/51SEF.DIR.I_Min (0.05~1)In 0.05 - 0.001
3 element of sensitive earth fault
protection
7 50/51SEF.DIR.U_Min 1.0~10.0 4 V 0.001
element of sensitive earth fault
protection
behavior of sensitive earth fault
50/51SEF.En_VTS_Bl Disabled; Disabled: sensitive earth fault
8 Disabled - -
k Enabled protection will not effected by VT
circuit failure
will be blocked by VT circuit
failure signal
9 50/51SEF1.3I0_Set 0.005~2 1 A 0.001
10 50/51SEF1.t_Op 0 ~100 0.1 s 0.001 stage 1 of sensitive earth fault
protection
50/51SEF1.t_DropOu
11 0 ~100 0 s 0.001 stage 1 of sensitive earth fault
t
protection
Non_Dire
12 50/51SEF1.Opt_Dir Forward - - directional mode of stage 1 of
ctional
Reverse sensitive earth fault protection.
Disabled;
13 50/51SEF1.En Enabled - - enabling/disabling the stage 1 of
Enabled

Date: 2019-04-24
Default
value
Enabling stage 1 of sensitive
earth fault protection operate to
50/51SEF1.Opt_Trp/ Trp;
14 Trp - - trip or alarm.
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
3
ANSILTE;
50/51SEF1.Opt_Curv ANSILT; IECDefTi inverse-time operation
15 - -
e IECN; me characteristic curve of stage 1 of
IECV; sensitive earth fault protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF1.Opt_Curv
16 DefTime; Inst - - sensitive earth fault protection
e_DropOut
17 50/51SEF1.TMS 0.04~ 20 1 - 0.001 stage 1 of sensitive earth fault
protection
18 50/51SEF1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of sensitive
earth fault protection
19 50/51SEF1.K 0.001~120 0.14 - 0.0001 operation characteristic of stage
1 of sensitive earth fault
protection

Date: 2019-04-24
Default
value
20 50/51SEF1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of stage
protection
21 50/51SEF1.C 0 ~1 0 - 0.0001 operation characteristic of stage
3 1 of
protection
sensitive earth fault

22 50/51SEF2.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF2.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
28 - -
e IECN;
IECV;
me characteristic curve of stage 2 of
sensitive earth fault protection.
3
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF2.Opt_Curv
e_DropOut
protection
protection
protection

Date: 2019-04-24
Default
value
protection
35 50/51SEF3.3I0_Set 0.005~2 1 A 0.001
3 36 50/51SEF3.t_Op 0 ~100 0.1 s 0.001 stage 3 of sensitive earth fault

protection
50/51SEF3.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
41 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default
value
50/51SEF3.Opt_Curv
e_DropOut
protection
3
protection
protection
protection
48 50/51SEF4.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF4.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2019-04-24
Default
value
Alm Alm
ANSIE;
ANSIV;
ANSIN;
3 ANSIM;
ANSIDefTime;
ANSILTE;
54 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF4.Opt_Curv
e_DropOut
protection
protection

Date: 2019-04-24
Default
value
protection
4 of
protection
sensitive earth fault
3
61 50/51SEF5.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF5.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2019-04-24
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
67 - -
3 e IECN;
IECV;
me characteristic curve of stage 5 of
sensitive earth fault protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF5.Opt_Curv
e_DropOut
protection
protection
protection

Date: 2019-04-24
Default
value
protection
74 50/51SEF6.3I0_Set 0.005~2 1 A 0.001
protection
3
50/51SEF6.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
80 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
Default
value
50/51SEF6.Opt_Curv
e_DropOut
3 82 50/51SEF6.TMS 0.04~ 20 1 - 0.001 stage 6 of sensitive earth fault

protection
protection
protection
protection
3.10 RMS Overcurrent Protection (50/51R)

When the capacitive equipment such as a capacitor bank or the inductive equipment such as a
rotating electrical machine in the system has a serious fault, the fundamental component in the
fault current will be relatively low, and the higher harmonic component will be higher. The
conventional phase overcurrent protection uses filtering algorithms to filter out higher harmonics
and perform calculation based on the fundamental component, resulting in failure to truly reflect
the fault condition and the protection sensitivity is affected. The RMS overcurrent protection
calculates the full-current RMS value includes 2nd~11th harmonic component, which can
sensitively reflect the actual fault current, so the fault can be removed quickly and accurately.

The device can provide two stages of RMS overcurrent protection with independent logic. When

Date: 2019-04-24
the fault current with more harmonic component is generated in the system, the amplitude is
larger than the current threshold of RMS overcurrent protection, the RMS overcurrent protection
will operate.
The operation characteristics of RMS overcurrent protection is definite-time characteristics. The

dropout characteristics can be set as instantaneous dropout or definite-time dropout. RMS
overcurrent protection can operate to trip or alarm, it can be enabled or blocked by the external
binary input.
RMS overcurrent protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, the protection needs to be blocked by the external signal, so the
device provides a function block input signal to be used to block RMS overcurrent protection. The
enabling and blocking logic of RMS overcurrent protection is shown in the figure below:
3
EN 50/51Rx.En &
50/51Rx.On
SIG 50/51Rx.Enable
&
SIG 50/51Rx.Block ≥1 50/51Rx.Blocked
SIG Fail_Device
&
50/51Rx.Valid
Figure 3.10-1 The enabling and blocking logic of RMS overcurrent protection
The logic diagram of the fault detector element of RMS overcurrent protection is as follows:
SET IRMS >0.95*[50/51Rx.I_Set] & 50/51Rx.Pkp

0 500ms
&
SIG 50/51Rx.On &
FD.Pkp
SIG 50/51Rx.Valid
EN [50/51Rx.Opt_Trp/Alm]=Alm
Figure 3.10-2 Logic diagram of the fault detector element of RMS overcurrent protection
RMS overcurrent protection can operate without time delay or operate with a definite-time limit,
the characteristic curve meets the IEC60255-3 and ANSI C37.112 standards.
When IRMS is larger than the current setting, the protection operates with a time delay of top (i.e.
the value of the setting [50/51Rx.t_Op]), and the operation characteristic curve is shown in the
following figure:

Date: 2019-04-24
t 0p
3
IRMSp IRMS
Figure 3.10-3 Definite-time operation characteristic curve of RMS overcurrent protection
The supported dropout characteristics of the phase overvoltage protection include instantaneous
dropout and definite-time dropout.
When I RMS <0.95* I RMSP , the protection drops out immediately.
When I RMS <0.95* I RMSP , the protection drops out with a time delay of tdr (i.e. the value of the
setting [50/51Rx.t_DropOut]), and the dropout characteristic curve is shown in the following figure:

Date: 2019-04-24
Start time
IRMS >Iset
Start
signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.10-4 Definite-time dropout characteristic of RMS overcurrent protection
50/51R
50/51Rx.Enable 50/51Rx.On
50/51Rx.Blocked
50/51Rx.Block
50/51Rx.Valid
50/51Rx.St
50/51Rx.StA
50/51Rx.StB
50/51Rx.StC
50/51Rx.Op
50/51Rx.Op.PhA
50/51Rx.Op.PhB
50/51Rx.Op.PhC
50/51Rx.Alm

Date: 2019-04-24
3.10.3 I/O Signal

Table 3.10-1 Input/output signals of RMS overcurrent protection

Stage x of RMS overcurrent protection enabling input, it is triggered from binary
1 50/51Rx.Enable
input or programmable logic etc. (x=1~2)
Stage x of RMS overcurrent protection blocking input, it is triggered from binary
2 50/51Rx.Block
1 50/51Rx.On Stage x of RMS overcurrent protection is enabled
3 2 50/51Rx.Blocked Stage x of RMS overcurrent protection is blocked

3 50/51Rx.Valid Stage x of RMS overcurrent protection is valid
4 50/51Rx.St Stage x of RMS overcurrent protection starts
5 50/51Rx.StA Stage x of RMS overcurrent protection starts (Phase A)
6 50/51Rx.StB Stage x of RMS overcurrent protection starts (Phase B)
7 50/51Rx.StC Stage x of RMS overcurrent protection starts (Phase C)
8 50/51Rx.Op Stage x of RMS overcurrent protection operates
9 50/51Rx.Op.PhA Stage x of RMS overcurrent protection operates (Phase A)
10 50/51Rx.Op.PhB Stage x of RMS overcurrent protection operates (Phase B)
11 50/51Rx.Op.PhC Stage x of RMS overcurrent protection operates (Phase C)
12 50/51Rx.Alm Stage x of RMS overcurrent protection alarms
3.10.4 Logic
50/51Rx.St
Timer &
SET IRMS>[50/51Rx.I_Set] & 50/51Rx.Op
t
t
SIG 50/51Rx.Pkp
SET [50/51Rx.Opt_Trp/Alm] = Trp &

50/51Rx.Alm
SET [50/51Rx.Opt_Trp/Alm] = Alm
Figure 3.10-5 Logic diagram of RMS overcurrent protection
3.10.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  RMS OC Settings
Table 3.10-2 Settings of RMS overcurrent protection
Default
value
The current setting of stage 1 of RMS
1 50/51R1.I_Set 0.05~200 15 A 0.001

Date: 2019-04-24
Default
value
The operating time setting of stage 1 of
2 50/51R1.t_Op 0 ~100 0.1 s 0.001
RMS overcurrent protection
The dropout time setting of stage 1 of
3 50/51R1.t_DropOut 0 ~100 0 s 0.001
Disabled; The logic setting for enabling/disabling the
4 50/51R1.En Enabled - -
Enabled stage 1 of RMS overcurrent protection
Enabling stage 1 of RMS overcurrent
Trp; protection operate to trip or alarm.
5 50/51R1.Opt_Trp/Alm Trp - -
Alm Trp: for tripping purpose 3
6 50/51R2.I_Set 0.05~200 15 A 0.001
7 50/51R2.t_Op 0 ~100 0.1 s 0.001
8 50/51R2.t_DropOut 0 ~100 0 s 0.001
Alm Trp: for tripping purpose
3.11 Phase Overvoltage Protection (59P)

Some abnormal conditions in the power system will generate high voltage, which may damage
the insulation performance of transformers, capacitors, motors and transmission lines, resulting in
equipment damage. Phase overvoltage protection can effectively detect the overvoltage that may
be generated in the system.

The device can provide two stages of phase overvoltage protection with independent logic. When
a high voltage occurs in the system, it is greater than the voltage threshold, phase overvoltage
protection will operate to remove the device from the system after a time delay. In addition, the
overvoltage protection also provides the alarm function, prompting the overvoltage of the system,
it allows users to find the cause timely, and preventing further deterioration of the fault. Each stage
of phase overvoltage protection can be independently set as definite-time characteristics or
inverse-time characteristics. The dropout characteristics can be set as instantaneous dropout and
definite-time dropout.
Users can select phase voltage or phase-to-phase voltage for the protection calculation via the
setting [59P.Opt_Up/Upp]. If it is set as “Up”, phase voltage criterion is selected, and if it is set to
“Upp”, phase-to-phase voltage criterion is selected.

Date: 2019-04-24
Users can select “1-out-of-3” or “3-out-of-3” logic for the protection criterion via the setting
[59P.Opt_1P/3P]. If it is set as “1P”, phase overvoltage protection can operate if any
phase/phase-to-phase voltage is greater than the voltage setting. If it is set as “3P”, phase
overvoltage protection cannot operate unless three phase/phase-to-phase voltages are greater
than the voltage setting.
Phase overvoltage protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, overvoltage protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overvoltage protection.
The enabling and blocking logic of phase overvoltage protection is shown in the figure below:
3 EN 59Px.En &
59Px.On
SIG 59Px.Enable
&
SIG 59Px.Block ≥1 59Px.Blocked
SIG Fail_Device
&
59Px.Valid
Figure 3.11-1 The enabling and blocking logic of phase overvoltage protection
The logic diagram of the fault detector element of phase overvoltage protection is as follows:

Date: 2019-04-24
SET [59P.Opt_Up/Upp]=Upp
SET Uab>[U_DropOut]
>=1
SET Ubc>[U_DropOut] &
SET Uca>[U_DropOut]
SET [59P.Opt_1P/3P]=1P
&
SET [59P.Opt_1P/3P]=3P >=1
SET Uab>[U_DropOut]
&
&
SET Ubc>[U_DropOut]
SET Uca>[U_DropOut]
3
SET Ua>[U_DropOut]
>=1
SET Ub>[U_DropOut] &
SET Uc>[U_DropOut]
SET [59P.Opt_1P/3P]=3P >=1

SET Ua>[U_DropOut]
&
&
SET Ub>[U_DropOut]
SET Uc>[U_DropOut]
& &
0 500ms &
SET [59P.Opt_Up/Upp]=Up x.59Px.Pkp
SIG 59Px.On
SIG 59Px.Valid
&
FD.Pkp
SET [59Px.Opt_Trp/Alm]=Alm
Figure 3.11-2 Logic diagram of the fault detector element of phase overvoltage protection
Where:
U_DropOut: the dropout voltage value, i.e. [59Px.K_DropOut]*[59Px.U_Set]
Phase overvoltage protection can operate with a definite-time limit, it can also operate with an
inverse-time limit, the characteristic curve meets the IEC60255-3 and ANSI C37.112 standards.
Phase overvoltage protection can support definite-time limit, IEC & ANSI standard inverse time
limit and user-defined inverse-time limit, users can select the wanted operating curve by the
setting [59Px.Opt_Curve] (x=1, 2), the relationship between the value of the setting and the curve
is shown in the table below.
59Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite Time - - -
IECDefTime IEC Definite Time - - -
UserDefine UserDefine
InvTime_U InvCrv_U 1 1 0

Date: 2019-04-24
When the setting [59Px.Opt_Curve] is set as “InvTime_U”, the operation characteristic is the
corresponding selected operating curve type, and the settings [59Px.K], [59Px.C] and
[59Px.Alpha] are useless.
When the setting [59Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time
characteristic is selected, the inverse-time operating curve is determined by the settings [59Px.K],
[59Px.C] and [59Px.Alpha].
When the setting [59Px.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, it is definite-time

overvoltage protection.
3 When U > Up , the protection operates with a time delay of top (i.e. the value of the setting
[59Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
Up U
Figure 3.11-3 Definite-time operation characteristic curve of phase overvoltage protection
When U > Up , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied voltage U . The larger voltage is, the smaller the operating time is, but not
unlimited. When the voltage is large enough to a certain threshold ( Up ), the inverse-time
operating time will not continue to decrease, then the operation characteristic becomes the
definite-time characteristic, and the operating time is tmin , i.e. the setting [59Px.tmin]. The
 k 
t 
 c   TMS
 (U / U P )  1 
Where:
Up is the voltage setting [59Px.U_Set];
TMS is the inverse-time time multiplier, i.e. the setting [59Px.TMS];

Date: 2019-04-24
k is the inverse-time coefficient K, i.e. the setting [59Px.K];

c is the inverse-time coefficient C, i.e. the setting [59Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [59Px.Alpha];
U is the measured voltage.

t min
UP UD U
Figure 3.11-4 Inverse-time operation characteristic curve of phase overvoltage protection
When the applied voltage is not a fixed value, but changes with time, the operating behavior of the
T0
1
 t (U )dt
0
1
Where:
t (U ) is the theoretical operating time when the voltage is U .
The supported dropout characteristics of the phase overvoltage protection include instantaneous
When U <[ 59Px.K_DropOut]* Up , the protection drops out immediately.
When U <[59Px.K_DropOut]* Up , the protection drops out with a time delay of tdr (i.e. the value

Date: 2019-04-24
of the setting [59Px.t_DropOut]), and the dropout characteristic curve is shown in the following
figure:
Start time
U>Up
Start
signal
3
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.11-5 Definite-time dropout characteristic of phase overvoltage protection

Date: 2019-04-24
59P
59Px.Enable 59Px.On
59Px.Block 59Px.Blocked
59Px.Valid
59Px.St
59Px.StA
59Px.StB 3
59Px.StC
59Px.Op
59Px.Op.PhA
59Px.Op.PhB
59Px.Op.PhC
59Px.Alm
3.11.3 I/O Signal

Table 3.11-1 Input/output signals of phase overvoltage protection

Stage x of phase overvoltage protection enabling input, it is triggered from
1 59Px.Enable
Stage x of phase overvoltage protection blocking input, it is triggered from
2 59Px.Block
1 59Px.On Stage x of phase overvoltage protection is enabled
2 59Px.Blocked Stage x of phase overvoltage protection is blocked
3 59Px.Valid Stage x of phase overvoltage protection is valid
4 59Px.St Stage x of phase overvoltage protection starts
5 59Px.StA Stage x of phase overvoltage protection starts (Phase A)
6 59Px.StB Stage x of phase overvoltage protection starts (Phase B)
7 59Px.StC Stage x of phase overvoltage protection starts (Phase C)
8 59Px.Op Stage x of phase overvoltage protection operates
9 59Px.Op.PhA Stage x of phase overvoltage protection operates (Phase A)
10 59Px.Op.PhB Stage x of phase overvoltage protection operates (Phase B)
11 59Px.Op.PhC Stage x of phase overvoltage protection operates (Phase C)
12 59Px.Alm Stage x of phase overvoltage protection alarms

Date: 2019-04-24
3.11.4 Logic
SET Uab>[59Px.U_Set]
>=1
SET Ubc>[59Px.U_Set] &
SET Uca>[59Px.U_Set]
&
SET [59P.Opt_1P/3P]=3P >=1 >=1
SET Uab>[59Px.U_Set]
&
3 SET Ubc>[59Px.U_Set]
&
SET Uca>[59Px.U_Set]
SET [59P.Opt_Up/Upp]=Up
SET Ua>[59Px.U_Set]
>=1
SET Ub>[59Px.U_Set] &
SET Uc>[59Px.U_Set]
&
SET [59P.Opt_1P/3P]=3P >=1
SET Ua>[59Px.U_Set]
&
& 59Px.St
SET Ub>[59Px.U_Set]
& Timer
SET Uc>[59Px.U_Set] t
&
t
SIG 59Px.Pkp 59Px.Op
SET [59Px.Opt_Trp/Alm]=Trp
&
59Px.Alm
Figure 3.11-6 Logic diagram of phase overvoltage protection
3.11.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  OV Settings

Date: 2019-04-24
Table 3.11-2 Settings of phase overvoltage protection
Default
value
Option of phase-to-phase
voltage or phase voltage for
Up; overvoltage protection
1 59P.Opt_Up/Upp Upp - -
Upp Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode or
3P;
3-out-of-3 mode for 3
2 59P.Opt_1P/3P 3P - - overvoltage protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
The voltage setting of stage
3 59P1.U_Set 57.7~200 115 V 0.001 1 of phase overvoltage
protection
The dropout coefficient of
4 59P1.K_DropOut 0.93 ~1.00 0.98 - 0.001 stage 1 of phase
overvoltage protection
5 59P1.t_Op 0.1 ~100 1 s 0.001 stage 1 of phase
6 59P1.t_DropOut 0 ~100 0 s 0.001 stage 1 of phase
Disabled; enabling/disabling the stage
7 59P1.En Enabled - -
Enabled 1 of phase overvoltage
protection
Trp;
8 59P1.Opt_Trp/Alm Trp - - operate to trip or alarm.
Alm
ANSIDefTime;
IECDefTime;
9 59P1.Opt_Curve IECDefTime - - characteristic curve of stage
UserDefine;
1 of phase overvoltage
InvTime_U
protection.

Date: 2019-04-24
Default
value
characteristic curve of stage
Inst; 1 of phase overvoltage
10 59P1.Opt_Curve_DropOut Inst - -
DefTime protection
dropout
3 11 59P1.TMS 0.04~ 20 1 - 0.001

stage 1 of phase
12 59P1.tmin 0 ~10 0.02 s 0.001 setting of stage 1 of phase
13 59P1.K 0.001~120 1 - 0.0001 operation characteristic of
stage 1 of phase
14 59P1.Alpha 0.01 ~3 1 - 0.0001 operation characteristic of
stage 1 of phase
15 59P1.C 0 ~1 0 - 0.0001 operation characteristic of
stage 1 of phase
protection

Date: 2019-04-24
Default
value
protection
Trp;
Alm
3
ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
DefTime protection
dropout
24 59P2.TMS 0.04~ 20 1 - 0.001 stage 2 of phase
stage 2 of phase
stage 2 of phase

Date: 2019-04-24
Default
value
stage 2 of phase
3.12 Residual Overvoltage Protection (59G)

If an earth fault occurs in the feeder of a high-resistance grounding system, the residual current
3 changes little and is difficult to detect. However, the amplitude of the residual voltage changes
significantly and can be used as a criterion for earth fault. In addition, the neutral point gap of the
transformer is grounded, once a fault occurs, the residual voltage increases, and the residual
overvoltage protection can also be used as the backup protection of the transformer. The residual
voltage can be measured from the open-triangle side of the voltage transformer, and it can also be
calculated internally by the protection device using three-phase voltage.

The device can provide two stages of residual overvoltage protection with independent logic.
When the residual voltage is greater than the voltage threshold, the residual overvoltage
protection will operate to remove the device from the system after a time delay. In addition, the
residual overvoltage protection also provides the alarm function, it prompt that there is an earth
fault leading to residual voltage generation, it allows users to find the cause timely, and preventing
further deterioration of the fault. The dropout characteristics of residual overvoltage protection can
be set as instantaneous dropout and definite-time dropout.
Residual overvoltage protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, residual overvoltage protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block residual
overvoltage protection. The enabling and blocking logic of residual overvoltage protection is
shown in the figure below:
EN 59Gx.En &
59Gx.On
SIG 59Gx.Enable
&
SIG 59Gx.Block ≥1 59Gx.Blocked
SIG Fail_Device
&
59Gx.Valid
Figure 3.12-1 The enabling and blocking logic of residual overvoltage protection

Date: 2019-04-24
The logic diagram of the fault detector element of residual overvoltage protection is as follows:
SET 3U0_Cal> U_DropOut &
SET [59G.Opt_3U0]=Cal
≥1
SET 3U0_Ext> U_DropOut &
& 59Gx.Pkp
SET [59Gx.Opt_3U0]=Ext 0 500ms
&
SIG 59Gx.On &
FD.Pkp
SIG
EN
59Gx.Valid
[59Gx.Opt_Trp/Alm]=Alm
3
Figure 3.12-2 Logic diagram of the fault detector element of residual overvoltage protection
Where:
U_DropOut: the dropout voltage value, i.e. [59Gx.K_DropOut]*[59Gx.3U0_Set]
Residual overvoltage protection can operate with a settable time delay. When U 0 > U 0 p , the
protection operates with a time delay of top (i.e. the value of the setting [59Gx.t_Op]), and the
operation characteristic curve is shown in the following figure:
t op
U0p U0
Figure 3.12-3 Definite-time operation characteristic curve of residual overvoltage protection
The supported dropout characteristics of the residual overvoltage protection include

Date: 2019-04-24
instantaneous dropout and definite-time dropout.
When U 0 <[59Gx.K_DropOut]* U 0 p , the protection drops out immediately.
When U 0 <[59Gx.K_DropOut]* U 0 p , the protection drops out with a time delay of tdr (i.e. the
value of the setting [59Gx.t_DropOut]), and the dropout characteristic curve is shown in the
following figure:
3 Start time
U0>U0p
Start
signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.12-4 Definite-time dropout characteristic of residual overvoltage protection
59G
59Gx.Enable 59Gx.On
59Gx.Block 59Gx.Blocked
59Gx.Valid
59Gx.St
59Gx.Op
59Gx.Alm

Date: 2019-04-24
3.12.3 I/O Signal

Table 3.12-1 Input/output signals of residual overvoltage protection

Stage x of residual overvoltage protection enabling input, it is triggered from
1 59Gx.Enable
Stage x of residual overvoltage protection blocking input, it is triggered from
2 59Gx.Block
1 59Gx.On Stage x of residual overvoltage protection is enabled
2 59Gx.Blocked Stage x of residual overvoltage protection is blocked 3
3 59Gx.Valid Stage x of residual overvoltage protection is valid
4 59Gx.St Stage x of residual overvoltage protection starts
5 59Gx.Op Stage x of residual overvoltage protection operates
6 59Gx.Alm Stage x of residual overvoltage protection alarms
3.12.4 Logic
SET 3U0_Cal> [59Gx.3U0_Set] & 59Gx.St
SET [59G.Opt_3U0]=Cal
≥1 &
[59Gx.t_Op] [59Gx.t_DropOut]
SET 3U0_Ext> [59Gx.3U0_Set] & &
59Gx.Op
SET [59Gx.Opt_3U0]=Ext
SIG 59Gx.Pkp
SET [59Gx.Opt_Trp/Alm] = Trp

&
59Gx.Alm
SET [59Gx.Opt_Trp/Alm] = Alm
Figure 3.12-5 Logic diagram of residual overvoltage protection
3.12.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  ROV Settings
Table 3.12-2 Settings of residual overvoltage protection
Default
value
Option of measured residual voltage or
calculated residual voltage for residual
Ext;
1 59G.Opt_3U0 Cal - - overvoltage protection
Cal
Ext: the measured residual voltage
Cal: the calculated residual voltage

Date: 2019-04-24
Default
value
The voltage setting of stage 1 of residual
2 59G1.3U0_Set 1~200 50 V 0.001
The dropout coefficient of stage 1 of residual
3 59G1.K_DropOut 0.93 ~1 0.98 - 0.001
4 59G1.t_Op 0.1 ~100 1 s 0.001
residual overvoltage protection
5 59G1.t_DropOut 0 ~100 0 s 0.001
3 The logic setting for enabling/disabling the

Disabled; stage 1 of residual overvoltage protection
6 59G1.En Enabled - -
Enabled 0: disabling
1: enabling
Enabling stage 1 of residual overvoltage
7 59G1.Opt_Trp/Alm Trp - -
8 59G2.3U0_Set 1~200 50 V 0.001
9 59G2.K_DropOut 0.93 ~1 0.98 - 0.001
10 59G2.t_Op 0.1 ~100 1 s 0.001
11 59G2.t_DropOut 0 ~100 0 s 0.001
The logic setting for enabling/disabling the
1: enabling
3.13 Negative-sequence Overvoltage Protection (59Q)
When the system has a broken-conductor, reverse phase sequence or inter-phase voltage
imbalance, the negative-sequence voltage increases, and the negative-sequence overvoltage
protection can reflect the system imbalance fault. It is used to protect the equipment from
insulation breakdown or premature aging due to overvoltage. The negative-sequence overvoltage
protection can also be used to alarm for prompting users the system voltage state is abnormal at
this moment.

Date: 2019-04-24

This device provides two stages of negative-sequence overvoltage protection. If the
negative-sequence voltage is larger than the predefined setting, this protection will operate. The
negative-sequence overvoltage protection can operate with a definite-time limit, and the
supported dropout characteristics include instantaneous dropout and definite-time dropout.
Negative-sequence overvoltage protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, overvoltage protection needs to be blocked by the
external signal, so the device provides a function block input signal to be used to block
overvoltage protection. The enabling and blocking logic of negative-sequence overvoltage
protection is shown in the figure below: 3
The logic diagram of enabling/disabling negative-sequence overvoltage protection is shown as
below.
EN 59Qx.En & 59Qx.On
SIG 59Qx.Enable
& 59Qx.Blocked
SIG 59Qx.Block ≥1
SIG Fail_Device
& 59Qx.Valid
Figure 3.13-1 Logic diagram of enabling/disabling negative-sequence overvoltage protection
When the negative-sequence overvoltage protection is enabled and no external blocking signal is
input, if the negative-sequence voltage is larger than the voltage setting multiplied by the dropout
coefficient setting of the negative-sequence overvoltage protection, the negative-sequence
overvoltage protection will pick up.
The logic diagram of the fault detector of the negative-sequence overvoltage protection is shown
as below.
SET U2 >U2_DropOut & 59Qx.Pkp

0ms 500ms
&
SIG 59Qx.On & FD.Pkp
SIG 59Qx.Valid
EN [59Qx.Opt_Trp/Alm]=Alm
Figure 3.13-2 Logic diagram of the fault detector of negative-sequence overvoltage protection
Where:

Date: 2019-04-24
U2_DropOut: the dropout voltage value, i.e. [59Qx.K_DropOut]*[59Qx.U2_Set]
Negative-sequence overvoltage protection can operate with a definite-time limit, the characteristic
curve meets the IEC60255-3 and ANSI C37.112 standards.
When the negative-sequence voltage is larger than the voltage setting, the protection operates
with a time delay of top (i.e. the value of the setting [59Qx.t_Op]), and the operation
characteristic curve is shown in the following figure:
t
3
t op
U2p U2
Figure 3.13-3 Operation characteristic curve of negative-sequence overvoltage protection
The supported dropout characteristics of the negative-sequence overvoltage protection include

When U2 <[ 59Qx.K_DropOut]*[59Qx.U2_Set] (x: 1~2), the protection drops out immediately.
When U2 <[59Qx.K_DropOut]*[59Qx.U2_Set] (x: 1~2), the protection drops out with a time delay
of tdr (i.e. the value of the setting [59Qx.t_DropOut]), and the dropout characteristic curve is
shown in the following figure:

Date: 2019-04-24
Start time
U 2> U2p
Start signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.13-4 Definite-time dropout characteristic of negative-sequence overvoltage protection
59Q
59Qx.Enable 59Qx.On
59Qx.Block 59Qx.Blocked
59Qx.Valid
59Qx.St
59Qx.Op
59Qx.Alm
3.13.3 I/O Signals

Table 3.13-1 Input/output signals of negative-sequence overvoltage protection

Stage x of negative-sequence overvoltage protection enabling input, it is
1 59Qx.Enable
Stage x of negative-sequence overvoltage protection blocking input, it is
2 59Qx.Block
1 59Qx.On Stage x of negative-sequence overvoltage protection is enabled

Date: 2019-04-24
2 59Qx.Blocked Stage x of negative-sequence overvoltage protection is blocked

3 59Qx.Valid Stage x of negative-sequence overvoltage protection is valid
4 59Qx.St Stage x of negative-sequence overvoltage protection starts
5 59Qx.Op Stage x of negative-sequence overvoltage protection operates
6 59Qx.Alm Stage x of negative-sequence overvoltage protection alarms
3.13.4 Logic
59Qx.St
SET U2 > [59Qx.U2_Set] &

3 SIG 59Qx.Pkp
[59Qx.t_Op] [59Qx.t_DropOut]
& 59Qx.Op
SET [59Qx.Opt_Trp/Alm] = Trp

& 59Qx.Alm
SET [59Qx.Opt_Trp/Alm] = Alm
Figure 3.13-5 Logic diagram of negative-sequence overvoltage protection
3.13.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  NegOV Settings
Table 3.13-2 Settings of negative-sequence overvoltage protection
No. Setting Range Default Unit Step Description

The voltage setting of the stage 1 of
1 59Q1.U2_Set 2~100 15 V 0.001
negative-sequence overvoltage protection
The dropout coefficient setting of the stage
2 59Q1.K_DropOut 0.93~1 0.98 - 0.001 1 of negative-sequence overvoltage
protection
The time setting of the stage 1 of
3 59Q1.t_Op 0.1~100 1 s 0.001
The dropout time setting of the stage 1 of
4 59Q1.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of the stage 1 of
5 59Q1.En Enabled - -
Enabled negative-sequence overvoltage protection
Enabling stage 1 of negative-sequence
Trp; overvoltage operate to trip or alarm.
6 59Q1.Opt_Trp/Alm Trp - -
7 59Q2.U2_Set 2~100 15 V 0.001

Date: 2019-04-24

protection
9 59Q2.t_Op 0.1~100 1 s 0.001
10 59Q2.t_DropOut 0~100 0 s 0.001
12 59Q2.Opt_Trp/Alm
Trp;
Trp - -
overvoltage operate to trip or alarm. 3
3.14 Positive-sequence Overvoltage Protection (59Pos)
This device provides one stage of positive-sequence overvoltage protection. If the

positive-sequence voltage is larger than the pre-defined setting, this protection will operate. The
positive-sequence overvoltage protection can operate with a definite-time limit, and the supported
dropout characteristics include instantaneous dropout and definite-time dropout.
Positive-sequence overvoltage protection can be enabled or disabled via the settings or binary
input signals, for some specific applications, overvoltage protection needs to be blocked by the
overvoltage protection. The enabling and blocking logic of positive-sequence overvoltage
protection is shown in the figure below:
The logic diagram of enabling/disabling positive-sequence overvoltage protection is shown as

below
EN 59Pos.En & 59Pos.On
SIG 59Pos.Enable
& 59Pos.Blocked
SIG 59Pos.Block ≥1
SIG Fail_Device
& 59Pos.Valid
Figure 3.14-1 Logic diagram of enabling/disabling positive-sequence overvoltage protection
When the positive-sequence overvoltage protection is enabled and no external blocking signal is

Date: 2019-04-24
input, if the positive-sequence voltage is larger than the voltage setting multiplied by the dropout
coefficient setting of the positive-sequence overvoltage protection, the positive-sequence
overvoltage protection will pick up.
The logic diagram of the fault detector of the positive-sequence overvoltage protection is shown
as below.
SET U1 >U1_DropOut & 59Pos.Pkp

0ms 500ms
&
SIG 59Pos.On & FD.Pkp
3 SIG 59Pos.Valid
EN [59Pos.Opt_Trp/Alm]=Alm
Figure 3.14-2 Logic diagram of the fault detector of positive-sequence overvoltage protection
Where:
U1: the positive-sequence voltage;
U1_DropOut: the dropout voltage value, i.e. [59Pos.K_DropOut]*[59Pos.U1_Set].
Positive-sequence overvoltage protection can operate with a definite-time limit, the characteristic
curve meets the IEC60255-3 and ANSI C37.112 standards.
When the positive-sequence voltage is larger than the voltage setting, the protection operates
with a time delay of top (i.e. the value of the setting [59Pos.t_Op]), and the operation
t op
U 1p U1
Figure 3.14-3 Operation characteristic curve of positive-sequence overvoltage protection

Date: 2019-04-24
The supported dropout characteristics of the positive-sequence overvoltage protection include

When U <[ 59Pos.K_DropOut]*[59Pos.U1_Set] (x: 1~2), the protection drops out immediately.
1
When U <[59Pos.K_DropOut]*[59Pos.U1_Set] (x: 1~2), the protection drops out with a time delay
1
of tdr (i.e. the value of the setting [59Pos.t_DropOut]), and the dropout characteristic curve is
shown in the following figure: 3
Start time
U 1> U1p
Start signal
Operating
signal
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.14-4 Definite-time dropout characteristic of positive-sequence overvoltage protection

Date: 2019-04-24
59Pos
59Pos.Enable 59Pos.On
59Pos.Block 59Pos.Blocked
59Pos.Valid
59Pos.St
59Pos.Op
59Pos.Alm
3 3.14.3 I/O Signals

Table 3.14-1 Input/output signals of positive-sequence overvoltage protection

Positive-sequence overvoltage protection enabling input, it is triggered from
1 59Pos.Enable
binary input or programmable logic etc.
Positive-sequence overvoltage protection blocking input, it is triggered from
2 59Pos.Block
1 59Pos.On Positive-sequence overvoltage protection is enabled
2 59Pos.Blocked Positive-sequence overvoltage protection is blocked
3 59Pos.Valid Positive-sequence overvoltage protection is valid
4 59Pos.St Positive-sequence overvoltage protection starts
5 59Pos.Op Positive-sequence overvoltage protection operates
6 59Pos.Alm Positive-sequence overvoltage protection alarms
3.14.4 Logic
59Pos.St
SET U1 > [59Pos.U1_Set] &

[59Pos.t_Op] [59Pos.t_DropOut]
& 59Pos.Op
SIG 59Pos.Pkp
SET [59Pos.Opt_Trp/Alm] = Trp

& 59Pos.Alm
SET [59Pos.Opt_Trp/Alm] = Alm
Figure 3.14-5 Logic diagram of positive-sequence overvoltage protection
3.14.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  PosOV Settings

Date: 2019-04-24
Table 3.14-2 Settings of positive-sequence overvoltage protection

The voltage setting of the
1 59Pos.U1_Set 2~100 60 V 0.001
positive-sequence overvoltage protection
The dropout coefficient setting of the
2 59Pos.K_DropOut 0.93~1 0.98 - 0.001
The time setting of the positive-sequence
3 59Pos.t_Op 0.1~100 1 s 0.001
The dropout time setting of the
4 59Pos.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of the positive-sequence 3
5 59Pos.En Enabled - -
Enabled overvoltage protection
Enabling the positive-sequence
6 59Pos.Opt_Trp/Alm Trp - -
3.15 Phase Undervoltage Protection (27P)

Some abnormal conditions in the power system will lead to low voltage. Electric equipment such
as motors cannot operate for a long time under the rated voltage and need to be removed from
the system in time. In addition, the voltage reduction may also be related to the shortage of
system reactive power. Reducing part of the reactive power load through the undervoltage
protection can help increase the voltage level of the system.

The device can provide two stages of phase undervoltage protection with independent logic.
When the voltage drops in the system and it is lower than the voltage threshold, phase
undervoltage protection will operate.
Taking into account that the role of undervoltage protection is to remove the running device from
the system, but in order to prevent that undervoltage protection is always operating when it is not
charged, the breaker closed position check criterion is added, users can choose to detect the
breaker position, current or no-check as the releasing condition for the protection.
In addition, the undervoltage protection also provides the alarm function, prompting the voltage
drop of the system, it allows users to find the cause timely, and preventing further deterioration of
the fault. Each stage of phase undervoltage protection can be independently set as definite-time
characteristics or inverse-time characteristics. The dropout characteristics can be set as
Users can select phase voltage or phase-to-phase voltage for the protection calculation via the
setting [27P.Opt_Up/Upp]. If it is set as “0”, phase voltage criterion is selected, and if it is set to “1”,
phase-to-phase voltage criterion is selected.

Date: 2019-04-24
[27P.Opt_1P/3P]. If it is set as “1P”, phase undervoltage protection can operate if any

phase/phase-to-phase voltage is smaller than the voltage setting. If it is set as “3P”, phase
undervoltage protection cannot operate unless three phase/phase-to-phase voltages are smaller
than the voltage setting.
The breaker closed position check mode is configured via the setting [27P.Opt_LogicMode], it
includes:
[27P.Opt_LogicMode]=None: no-check;
[27P.Opt_LogicMode]=Curr: check the current;
3 [27P.Opt_LogicMode]=CBPos: check the breaker position;
[27P.Opt_LogicMode]=CurrAndCBPos: check the current and the breaker position;
[27P.Opt_LogicMode]=CurrOrCBPos: check the current or the breaker position.
Undervoltage protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, undervoltage protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block undervoltage protection. The
enabling and blocking logic of undervoltage protection is shown in the figure below:
EN 27Px.En &
27Px.On
SIG 27Px.Enable
&
SIG 27Px.Block ≥1 27Px.Blocked
SIG Fail_Device
&
27Px.Valid
Figure 3.15-1 The enabling and blocking logic of phase undervoltage protection
The logic diagram of the fault detector element of phase undervoltage protection is as follows:

Date: 2019-04-24
&
SET Uab<[U_DropOut]
&
SET Ubc<[U_DropOut]
SET Uca<[U_DropOut]
>=1
&
SET Uab<[U_DropOut]
>=1
SET Ubc<[U_DropOut] 3
SET Uca<[U_DropOut]
&
SET Ua<[U_DropOut]
&
SET Ub<[U_DropOut] >=1
SET Uc<[U_DropOut]
>=1 Pickup voltage criterion
&
SET Ua<[U_DropOut]
>=1
SET Ub<[U_DropOut]
SET Uc<[U_DropOut]
SET [27P.Opt_LogicMode]=None
SET [27P.Opt_LogicMode]=Curr & >=1

>=1
SIG Ia, Ib and Ic > 0.04In Auxiliary criterion
SET [27P.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1
SET [27P.Opt_LogicMode]=CurrOrCBPos
&
&
SET [27P.Opt_LogicMode]=CurrAndCBPos

Date: 2019-04-24
SIG Pickup voltage criterion

& 27Px.Pkp
SIG Auxiliary criterion 0 500ms &
&
SIG VTS.Alm & FD.Pkp
&
EN [27Px.En_VTS_Blk]
SIG 27Px.On
SIG 27Px.Valid
3
Figure 3.15-2 Logic diagram of the fault detector element of phase undervoltage protection
Where:
U_DropOut: the dropout voltage value, i.e. [27Px.K_DropOut]*[27Px.U_Set]
Undervoltage protection can operate with a definite-time limit, it can also operate with an
inverse-time limit, the characteristic curve meets the IEC60255-3 and ANSI C37.112 standards.
Undervoltage protection can support definite-time limit, IEC & ANSI standard inverse time limit
and user-defined inverse-time limit, users can select the wanted operating curve by the setting
[27Px.Opt_Curve] (x=1 or 2), the relationship between the value of the setting and the curve is
shown in the table below.
27Px.Opt_Curve Time Characteristic k α c

ANSIDefTime ANSI Definite Time - - -
IECDefTime IEC Definite Time - - -
UserDefine UserDefine
InvTime_U InvCrv_U 1 1 0
When the setting [27Px.Opt_Curve] is set as “InvTime_U”, the operation characteristic is the
corresponding selected operating curve type, and the settings [27Px.K], [27Px.C] and
[27Px.Alpha] are useless.
When the setting [27Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time
characteristic is selected, the inverse-time operating curve is determined by the settings [27Px.K],
[27Px.C] and [27Px.Alpha].
When the setting [27Px.Opt_Curve] is set as “ANSIDefTime” or “IECDefTime”, it is definite-time

undervoltage protection.
When U < Up , the protection operates with a time delay of top (i.e. the value of the setting
[27Px.t_Op]), and the operation characteristic curve is shown in the following figure:

Date: 2019-04-24
t op
3
Up U
Figure 3.15-3 Definite-time operation characteristic curve of phase undervoltage protection
When U < Up , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied voltage U . The lower voltage is, the smaller the operating time is, but not
unlimited. When the voltage is low enough to a certain threshold ( Up ), the inverse-time operating
time will not continue to decrease, then the operation characteristic becomes the definite-time
characteristic, and the operating time is tmin , i.e. the setting [27Px.tmin]. The inverse-time
 k 
t 
 c   TMS
1  (U / U P ) 
Where:
Up is the voltage setting [27Px.U_Set];
TMS is the inverse-time time multiplier, i.e. the setting [27Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [27Px.K];

c is the inverse-time coefficient C, i.e. the setting [27Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [27Px.Alpha];
U is the measured voltage.


Date: 2019-04-24
3 t min
UD UP U
Figure 3.15-4 Inverse-time operation characteristic curve of phase undervoltage protection
When the applied voltage is not a fixed value, but changes with time, the operating behavior of the
T0
1
 t (U )dt
0
1
Where:
t (U ) is the theoretical operating time when the voltage is U .
The supported dropout characteristics of the undervoltage protection include instantaneous

When U >[27Px.K_DropOut]* Up , the protection drops out immediately.
When U >[27Px.K_DropOut]* Up , the protection drops out with a time delay of tdr (i.e. the value
of the setting [27Px.t_DropOut]), and the dropout characteristic curve is shown in the following
figure:

Date: 2019-04-24
Start time
U<Up
Start
signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time
Dropout time
Figure 3.15-5 Definite-time dropout characteristic of undervoltage protection
27P
27Px.Enable 27Px.On
27Px.Block 27Px.Blocked
27Px.Valid
27Px.St
27Px.StA
27Px.StB
27Px.StC
27Px.Op
27Px.Op.PhA
27Px.Op.PhB
27Px.Op.PhC
27Px.Alm

Date: 2019-04-24
3.15.3 I/O Signal

Table 3.15-1 Input/output signals of phase undervoltage protection

Stage x of phase undervoltage protection enabling input, it is triggered from binary
1 27Px.Enable
Stage x of phase undervoltage protection blocking input, it is triggered from binary
2 27Px.Block
1 27Px.On Stage x of phase undervoltage protection is enabled
3 2 27Px.Blocked Stage x of phase undervoltage protection is blocked

3 27Px.Valid Stage x of phase undervoltage protection is valid
4 27Px.St Stage x of phase undervoltage protection starts
5 27Px.StA Stage x of phase undervoltage protection starts (Phase A)
6 27Px.StB Stage x of phase undervoltage protection starts (Phase B)
7 27Px.StC Stage x of phase undervoltage protection starts (Phase C)
8 27Px.Op Stage x of phase undervoltage protection operates
9 27Px.Op.PhA Stage x of phase undervoltage protection operates (Phase A)
10 27Px.Op.PhB Stage x of phase undervoltage protection operates (Phase B)
11 27Px.Op.PhC Stage x of phase undervoltage protection operates (Phase C)
12 27Px.Alm Stage x of undervoltage protection alarms

Date: 2019-04-24
3.15.4 Logic
&
SET Uab<[27Px.U_Set]
&
SET Ubc<[27Px.U_Set]
SET Uca<[27Px.U_Set]
>=1
&
SET Uab<[27Px.U_Set]
>=1
3
SET Ubc<[27Px.U_Set]
SET Uca<[27Px.U_Set]
&
SET Ua<[27Px.U_Set]
&
SET Ub<[27Px.U_Set] >=1
SET Uc<[27Px.U_Set]
>=1 Voltage criterion
&
SET Ua<[27Px.U_Set]
>=1
SET Ub<[27Px.U_Set]
SET Uc<[27Px.U_Set]
SIG Voltage criterion 27Px.St

&
SIG Auxiliary criterion & Timer
t
t
SIG VTS.Alm &
&
EN [27Px.En_VTS_Blk]
SIG 27Px.On
SIG 27Px.Pkp
&
27Px.Op
SET [27Px.Opt_Trp/Alm]=Trp
&
27Px.Alm
Figure 3.15-6 Logic diagram of phase undervoltage protection

Date: 2019-04-24
Where:
Auxiliary criterion: please refer to Figure 3.15-2.
3.15.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  UV Settings
Table 3.15-2 Settings of phase undervoltage protection
Default
3
value
voltage or phase voltage
for stage x of
Up;
1 27P.Opt_Up/Upp Upp - - undervoltage protection
Upp
Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode
or 3-out-of-3 mode for
3P; stage x of undervoltage
2 27P.Opt_1P/3P 3P - -
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
Breaker closed position
check mode
None: no check
Curr: check the current
None; CBPos: check the
Curr; normally open auxiliary
3 27P.Opt_LogicMode CBPos; Curr - - contact
CurrOrCBPos; CurrOrCBPos: check the
CurrAndCBPos current and normally open
auxiliary contact
CurrAndCBPos: check the
current or normally open
auxiliary contact
The voltage setting of
4 27P1.U_Set 5~120 80 V 0.001 stage 1 of phase
undervoltage protection
5 27P1.K_DropOut 1~1.2 1.03 - 0.001 stage 1 of phase

Date: 2019-04-24
Default
value
6 27P1.t_Op 0.1 ~100 1 s 0.001 of stage 1 of phase
The dropout time setting
7 27P1.t_DropOut 0 ~100 0 s 0.001 of stage 1 of phase
Logic setting to determine
the behavior of stage 1 of
phase undervoltage
3
supervision function is
Disabled;
8 27P1.En_VTS_Blk Disabled - - enabled and VT circuit
Enabled
failure happens.
0: it is not effected by VT
circuit failure
1: it will be blocked by VT
circuit failure signal
Disabled; stage 1 of phase
Enabled undervoltage protection
0: disabling
1: enabling
Trp;
Alm
ANSIDefTime;
the inverse-time operation
IECDefTime;
11 27P1.Opt_Curve IECDefTime - - characteristic curve of
UserDefine;
stage 1 of phase
InvTime_U
stage 1 of phase
Inst;
12 27P1.Opt_Curve_DropOut Inst - - undervoltage protection
DefTime
Inst: instantaneous
dropout
dropout

Date: 2019-04-24
Default
value
13 27P1.TMS 0.04~ 20 1 - 0.001 of stage 1 of phase
14 27P1.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
3 15 27P1.K 0.001~120 0.14 - 0.0001

stage 1 of phase
16 27P1.Alpha 0.01 ~3 0.02 - 0.0001 operation characteristic of
stage 1 of phase
stage 1 of phase

Date: 2019-04-24
Default
value
phase undervoltage
Disabled;
Enabled
failure happens.
circuit failure
3
0: disabling
1: enabling
Trp;
24 27P2.Opt_Trp/Alm Trp - operate to trip or alarm.
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
stage 2 of phase
InvTime_U
stage 2 of phase
Inst;
DefTime
Inst: instantaneous
dropout
dropout
27 27P2.TMS 0.04~ 20 1 0.001 of stage 2 of phase

Date: 2019-04-24
Default
value
28 27P2.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
29 27P2.K 0.001~120 0.14 - 0.0001 operation characteristic of
stage 2 of phase
3 undervoltage protection
stage 2 of phase
stage 2 of phase
3.16 Overfrequency Protection (81O)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The increase of frequency indicates that
the output power of the system is much larger than that of the load. When the system frequency is
greater than the predefined setting, the overfrequency protection will operate for removing some
part of active power supplies from the system.

The device can provide six stages of overfrequency protection. If the system frequency is greater
than the setting, overfrequency protection will operate to remove some part of active power
supplies from the system. Overfrequency protection is with independent definite-time
characteristics and with instantaneous dropout characteristics.
Overfrequency protection protection can be enabled or disabled via the settings or binary input
signals, for some specific applications, overfrequency protection needs to be blocked by the
overfrequency protection. The enabling and blocking logic of overfrequency protection is shown in
the figure below:

Date: 2019-04-24
EN 81Ox.En & 81Ox.On
SIG 81Ox.Enable
& 81Ox.Blocked
SIG 81Ox.Block ≥1
SIG Fail_Device
& 81Ox.Valid
Figure 3.16-1 Logic diagram of enabling/disabling overfrequency protection

3
When the overfrequency protection is enabled and no external blocking signal is input, if the
system frequency is greater than the frequency setting of the overfrequency protection and all the
phase-to-phase voltages are greater than the setting of the voltage blocking element of the
overfrequency protection, the overfrequency protection will pick up.
The logic diagram of the fault detector of the overfrequency protection is shown in Figure 3.16-2.
SET f > [81Ox.f_Set] &
SET Upp_min > [81.Upp_Blk]
& 81Ox.Pkp
0ms 500ms
&
SIG 81Ox.On
FD.Pkp
SIG 81Ox.Valid
Figure 3.16-2 Logic diagram of the fault detector of overfrequency protection
The overfrequency protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the system frequency is greater than the frequency setting [81Ox.f_Set] (x:
1~6), the overfrequency protection will operate after the time setting [81Ox.t_Op] (x: 1~6).
The operation characteristic curve of overfrequency protection is shown in Figure 3.16-3.

Date: 2019-04-24
t op
fp f
Figure 3.16-3 Operation characteristic curve of overfrequency protection
The overfrequency protection is with instantaneous dropout characteristic. If the system frequency
is less than the setting [81Ox.f_Set] (x: 1~6), the overfrequency protection will drop out at once.
81O
81Ox.Enable 81Ox.On
81Ox.Blocked
81Ox.Block
81Ox.Valid
81Ox.St
81Ox.Op
Figure 3.16-4 Function block diagram of overfrequency protection
3.16.3 I/O Signals

Table 3.16-1 Input/output signals of overfrequency protection

Stage x of overfrequency protection enabling input, it is triggered from binary
1 81Ox.Enable
Stage x of overfrequency protection blocking input, it is triggered from binary
2 81Ox.Block
1 81Ox.On Stage x of overfrequency protection is enabled.
2 81Ox.Blocked Stage x of overfrequency protection is blocked.

Date: 2019-04-24
3 81Ox.Valid Stage x of overfrequency protection is valid.

4 81Ox.St Stage x of overfrequency protection starts.
5 81Ox.Op Stage x of overfrequency protection operates.
3.16.4 Logic
SET f>[81Ox.f_Set] & 81Ox.St
&
SET Upp_min>[81.Upp_Blk] [81Ox.t_Op] 0 81Ox.Op
SIG 81Ox.Pkp
3
Figure 3.16-5 Logic diagram of overfrequency protection
3.16.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  FreqProt Settings
Table 3.16-2 Settings of overfrequency protection

The setting of the low voltage blocking
1 81.Upp_Blk 10~150 70 V 0.001 element of the frequency protection
(phase-to-phase voltage)
The frequency setting of the stage 1 of
2 81O1.f_Set 50~65 52 Hz 0.001
overfrequency protection
3 81O1.t_Op 0.1~100 0.3 s 0.001
4 81O1.En Enabled - -
Enabled overfrequency protection
5 81O2.f_Set 50~65 52 Hz 0.001
6 81O2.t_Op 0.1~100 0.3 s 0.001
8 81O3.f_Set 50~65 52 Hz 0.001
9 81O3.t_Op 0.1~100 0.3 s 0.001
11 81O4.f_Set 50~65 52 Hz 0.001

Date: 2019-04-24

12 81O4.t_Op 0.1~100 0.3 s 0.001
14 81O5.f_Set 50~65 52 Hz 0.001
15 81O5.t_Op 0.1~100 0.3 s 0.001
3 17 81O6.f_Set 50~65 52 Hz 0.001

18 81O6.t_Op 0.1~100 0.3 s 0.001
3.17 Underfrequency Protection (81U)
Frequency is an important index of the power quality, which can reflect the balance of the output
power of the generator and the active power of the load. The decrease of frequency indicates that
the output power of the system is much less than that of the load. When the system frequency is
less than the predefined setting, the underfrequency protection will operate for shedding some
part of loads from the system.
This device provides six stages of underfrequency protection. If the system frequency is less than
the predefined setting, this protection will operate for shedding some part of loads from the system.
The underfrequency protection is with independent definite-time delay characteristic and with
instantaneous dropout characteristic.
3.17.1.1 Underfrequency Protection
The underfrequency protection can be enabled or disabled by the settings. If the setting [81Ux.En]
(x: 1~6) is set as “1”, and the signal [81Ux.Enable] (x: 1~6) is “1” and the signal [81Ux.Block] (x:
1~6) is “0”. For some special application, the underfrequency protection needs to be blocked by
external signal, the input signal [81Ux.Block] (x: 1~6) is provided for this purpose.
The logic diagram of enabling/disabling underfrequency protection is shown in Figure 3.17-1.

Date: 2019-04-24
EN 81Ux.En & 81Ux.On
SIG 81Ux.Enable
& 81Ux.Blocked
SIG 81Ux.Block ≥1
SIG Fail_Device
& 81Ux.Valid
Figure 3.17-1 Logic diagram of enabling/disabling underfrequency protection

3
When the underfrequency protection is enabled and no external blocking signal is input, if the
system frequency is less than the setting of the underfrequency protection and all the
phase-to-phase voltages are greater than the setting of the voltage blocking element of the
underfrequency protection, the underfrequency protection will pick up.
The logic diagram of the fault detector of the underfrequency protection is shown in Figure 3.17-2.
SET f < [81Ux.f_Set] &
SET Upp_min > [81.Upp_Blk]
& 81Ux.Pkp
0ms 500ms
&
SIG 81Ux.On
FD.Pkp
SIG 81Ux.Valid
Figure 3.17-2 Logic diagram of the fault detector of underfrequency protection
The underfrequency protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the system frequency is less than the frequency setting [81Ux.f_Set] (x:
1~6), the underfrequency protection will operate after the time setting [81Ux.t_Op] (x: 1~6).
The operation characteristic curve of underfrequency protection is shown in Figure 3.17-3.

Date: 2019-04-24
t op
3
fp f
Figure 3.17-3 Operation characteristic curve of underfrequency protection
The underfrequency protection is with instantaneous dropout characteristic. If the system

frequency is greater than the setting [81Ux.f_Set] (x: 1~6), the underfrequency protection will drop
out at once.
81U
81Ux.Enable 81Ux.On
81Ux.Block 81Ux.Blocked
81Ux.Valid
81Ux.St
81Ux.Op
Figure 3.17-4 Function block diagram of underfrequency protection
3.17.3 I/O Signals

Table 3.17-1 Input/output signals of underfrequency protection

Stage x of underfrequency protection enabling input, it is triggered from binary
1 81Ux.Enable
Stage x of underfrequency protection blocking input, it is triggered from binary
2 81Ux.Block
1 81Ux.On Stage x of underfrequency protection is enabled.
2 81Ux.Blocked Stage x of underfrequency protection is blocked.

Date: 2019-04-24
3 81Ux.Valid Stage x of underfrequency protection is valid.

4 81Ux.St Stage x of underfrequency protection starts.
5 81Ux.Op Stage x of underfrequency protection operates.
3.17.4 Logic
SET f<[81Ux.f_Set] & 81Ux.St
&
SET Upp_min>[81.Upp_Blk] [81Ux.t_Op] 0 81Ux.Op
SIG 81Ux.Pkp
3
Figure 3.17-5 Logic diagram of underfrequency protection
3.17.5 Settings
 Access path:
Table 3.17-2 Settings of underfrequency protection

2 81U1.f_Set 45~60 48 Hz 0.001
underfrequency protection
3 81U1.t_Op 0.1~100 0.3 s 0.001
4 81U1.En Enabled - -
Enabled underfrequency protection
5 81U2.f_Set 45~60 48 Hz 0.001
6 81U2.t_Op 0.1~100 0.3 s 0.001
8 81U3.f_Set 45~60 48 Hz 0.001
9 81U3.t_Op 0.1~100 0.3 s 0.001
11 81U4.f_Set 45~60 48 Hz 0.001

Date: 2019-04-24

12 81U4.t_Op 0.1~100 0.3 s 0.001
14 81U5.f_Set 45~60 48 Hz 0.001
15 81U5.t_Op 0.1~100 0.3 s 0.001
3 17 81U6.f_Set 45~60 48 Hz 0.001

18 81U6.t_Op 0.1~100 0.3 s 0.001
3.18 Frequency Rate-of-change Protection (81R)
Frequency rate-of-change reflects the balance of the output power of the generator and the active
power of the load. It can reflect the increase of active load power and the decrease of frequency.
When the frequency changes too fast, it is generally considered that the system has a fault, and
the frequency rate-of-change protection can operate in such a situation.
This device provides six stages of frequency rate-of-change protection. If the system frequency
rate-of-change is greater than the predefined setting, this protection will operate. The frequency
rate-of-change protection is with independent definite-time delay characteristic and with
instantaneous dropout characteristic.
3.18.1.1 Frequency Rate-of-change Protection
The frequency rate-of-change protection can be enabled or disabled by the settings. If the setting
[81Rx.En] (x: 1~6) is set as “1”, and the signal [81Rx.Enable] (x: 1~6) is “1” and the signal
[81Rx.Block] (x: 1~6) is “0”. For some special application, the frequency rate-of-change protection
needs to be blocked by external signal, the input signal [81Rx.Block] (x: 1~6) is provided for this
purpose.
The logic diagram of enabling/disabling the frequency rate-of-change protection is shown in

Figure 3.18-1.

Date: 2019-04-24
EN 81Rx.En & 81Rx.On
SIG 81Rx.Enable
& 81Rx.Blocked
SIG 81Rx.Block ≥1
SIG Fail_Device
& 81Rx.Valid
Figure 3.18-1 Logic diagram of enabling/disabling frequency rate-of-change protection

3
When the frequency rate-of-change protection is enabled and no external blocking signal is input,
if the absolute value of the system frequency rate-of-change is greater than the absolute value of
setting of the frequency rate-of-change protection, the frequency rate-of-change protection will
pick up.
The logic diagram of the fault detector of the frequency rate-of-change protection is shown in
Figure 3.18-2.
df/dt > 0 &

SET
df/dt > [81Rx.df/dt_Set] &
SET Upp_min > [81.Upp_Blk] ≥1
df/dt < 0 &

SET
df/dt < [81Rx.df/dt_Set] &
SET Upp_min > [81.Upp_Blk] & 81Rx.Pkp

0ms 500ms
& FD.Pkp
SIG 81Rx.On
SIG 81Rx.Valid
Figure 3.18-2 Logic diagram of the fault detector of frequency rate-of-change protection
The frequency rate-of-change protection has definite-time delay characteristic complied with IEC
60255-3 and ANSI C37.112. If the absolute value of the system frequency rate-of-change is
greater than the absolute value of setting [81Rx.df/dt_Set] (x: 1~6), the frequency rate-of-change
protection will operate after the time setting [81Rx.t_Op] (x: 1~6).
The operation characteristic curve of the frequency rate-of-change protection is shown in Figure
3.18-3.

Date: 2019-04-24
top
3
-df/dtset df/dtset
-df/dt df/dt
Figure 3.18-3 Operation characteristic curve of frequency rate-of-change protection
The frequency rate-of-change protection is with instantaneous dropout characteristic. If the

absolute value of the system frequency rate-of-change is less than the absolute value of setting
[81Rx.df/dt_Set] (x: 1~6), the frequency rate-of-change protection will drop out at once.
81R
81Rx.Enable 81Rx.On
81Rx.Blocked
81Rx.Block
81Rx.Valid
81Rx.St
81Rx.Op
Figure 3.18-4 Function block diagram of frequency rate-of-change protection
3.18.3 I/O Signals

Table 3.18-1 Input/output signals of frequency rate-of-change protection

Stage x of frequency rate-of-change protection enabling input, it is triggered from
1 81Rx.Enable
Stage x of frequency rate-of-change protection blocking input, it is triggered from
2 81Rx.Block
1 81Rx.On Stage x of frequency rate-of-change protection is enabled.
2 81Rx.Blocked Stage x of frequency rate-of-change protection is blocked.
3 81Rx.Valid Stage x of frequency rate-of-change protection is valid.

Date: 2019-04-24
4 81Rx.St Stage x of frequency rate-of-change protection starts.

5 81Rx.Op Stage x of frequency rate-of-change protection operates.
3.18.4 Logic
df/dt > 0 &

SET
df/dt > [81Rx.df/dt_Set]
&
SET f > [81Rx.f_Pkp]
81Rx.St
SET Upp_min > [81.Upp_VCE]
≥1
df/dt < 0 & &
3
SET
df/dt < [81Rx.df/dt_Set] [81Rx.t_Op] 0 81Rx.Op
&
SET f < [81Rx.f_Pkp]
SET Upp_min > [81.Upp_VCE]
SIG 81Rx.Pkp
Figure 3.18-5 Logic diagram of frequency rate-of-change protection
3.18.5 Settings
 Access path:
Table 3.18-2 Settings of frequency rate-of-change protection

The rate-of-change setting of the stage x of
2 81R1.df/dt_Set -5~5 0.5 Hz/s 0.001
frequency rate-of-change protection
The time setting of the stage x of frequency
3 81R1.t_Op 0.1~100 0.1 s 0.001
rate-of-change protection
The pickup frequency setting of the stage x
4 81R1.f_Pkp 45~65 50 Hz 0.001
of frequency rate-of-change protection
Disabled; The logic setting of the stage x of frequency
5 81R1.En Enabled - -
Enabled rate-of-change protection
The rate-of-change setting of the stage 1 of
6 81R2.df/dt_Set -5~5 0.5 Hz/s 0.001
The time setting of the stage 1 of frequency
7 81R2.t_Op 0.1~100 0.1 s 0.001
The pickup frequency setting of the stage 1
8 81R2.f_Pkp 45~65 50 Hz 0.001
Disabled; The logic setting of the stage 1 of frequency

Date: 2019-04-24

10 81R3.df/dt_Set -5~5 0.5 Hz/s 0.001
11 81R3.t_Op 0.1~100 0.1 s 0.001
12 81R3.f_Pkp 45~65 50 Hz 0.001
14 81R4.df/dt_Set -5~5 0.5 Hz/s 0.001
3 15 81R4.t_Op 0.1~100 0.1 s 0.001

16 81R4.f_Pkp 45~65 50 Hz 0.001
18 81R5.df/dt_Set -5~5 0.5 Hz/s 0.001
19 81R5.t_Op 0.1~100 0.1 s 0.001
20 81R5.f_Pkp 45~65 50 Hz 0.001
22 81R6.df/dt_Set -5~5 0.5 Hz/s 0.001
23 81R6.t_Op 0.1~100 0.1 s 0.001
24 81R6.f_Pkp 45~65 50 Hz 0.001
3.19 Reverse Power Protection (32R)
If a power supply failure occurs on the feeder, the synchronous motors become generators due to
the inertia of their load and the induction motors become generators. The aim of the reverse
power protection is to detect the inverse flow of energy and to ensure that the motor does not feed
the fault which has appeared on the network.

This device provides two stages of reverse power protection. If the reverse power is detected and
it is greater than the predefined setting, the reverse power protection will operate. The reverse

Date: 2019-04-24
power protection is with independent definite-time delay characteristic and with instantaneous
dropout characteristic.
3.19.1.1 Reverse Power Protection
The reverse power protection can be enabled or disabled by the settings. If the setting [32Rx.En]
(x: 1~2) is set as “1”, and the signal [32Rx.Enable] (x: 1~2) is “1” and the signal [32Rx.Block] (x:
1~2) is “0”. For some special application, the reverse power protection needs to be blocked by
external signal, the input signal [32Rx.Block] (x: 1~2) is provided for this purpose.
The logic diagram of enabling/disabling reverse power protection is shown in Figure 3.19-1.
EN 32Rx.En & 32Rx.On

3
SIG 32Rx.Enable
& 32Rx.Blocked
SIG 32Rx.Block ≥1
SIG Fail_Device
& 32Rx.Valid
Figure 3.19-1 Logic diagram of enabling/disabling reverse power protection
When the reverse power protection is enabled and no external blocking signal is input, if the
reverse power is greater than the power setting of the reverse power protection, the reverse
power protection will pick up.
The logic diagram of the fault detector of the reverse power protection is shown in Figure 3.19-2.
SET |P| > 0.95*[32Rx.P_Set] &
SIG P<0
32Rx.Pkp
SET U1 < [32R.U1_VCE] & & 0ms 500ms

&
≥1 & FD.Pkp
SET I1 < [32R.I1_CCE]
SET U2 > [32R.U2_VCE]
SIG 32Rx.On
SIG 32Rx.Valid
EN [32Rx.Opt_Trp/Alm]=Alm
Figure 3.19-2 Logic diagram of the fault detector of reverse power protection
Where:

Date: 2019-04-24
The power value is positive-sequence power, P1 = 3×U1×I1×cosθ (θ is the phase angle

between positive-sequence voltage and positive-sequence current).
[32Rx.P_Set] (x: 1~2) is the power setting of the stage x reverse power protection.
[32R.U1_VCE] is the setting of the positive-sequence voltage control element of the reverse
power protection.
[32R.I1_CCE] is the positive-sequence current setting of the current control element of the
reverse power protection.
[32R.U2_VCE] is the setting of the negative-sequence voltage control element of the reverse
3 power protection.
“I1” is the positive-sequence current.
“U1” is the positive-sequence voltage.
“U2” is the negative-sequence voltage.
The reverse power protection has definite-time delay characteristic complied with IEC 60255-3
and ANSI C37.112. If the power value is less than “0”, and the absolute power value is greater
than the power setting of the reverse power protection [32Rx.P_Set] (x: 1~2), the reverse power
protection will operate after the time setting [32Rx.t_Op] (x: 1~2).
The operation characteristic curve of reverse power protection is shown in Figure 3.19-3.
top
P1 P1set
Figure 3.19-3 Operation characteristic curve of reverse power protection
The reverse power protection is with instantaneous dropout characteristic. If the power is greater
than “0” or the power is less than the power setting [32Rx.P_Set] (x: 1~2) multiplied by 0.95, the
reverse power protection will drop out at once.

Date: 2019-04-24
32R
32Rx.Enable 32Rx.On
32Rx.Block 32Rx.Blocked
32Rx.Valid
32Rx.St
32Rx.Op
32Rx.Alm
3
Figure 3.19-4 Function block diagram of reverse power protection
3.19.3 I/O Signals

Table 3.19-1 Input/output signals of reverse power protection

Stage x of reverse power protection enabling input, it is triggered from binary
1 32Rx.Enable
Stage x of reverse power protection blocking input, it is triggered from binary
2 32Rx.Block
1 32Rx.On Stage x of reverse power protection is enabled.
2 32Rx.Blocked Stage x of reverse power protection is blocked.
3 32Rx.Valid Stage x of reverse power protection is valid.
4 32Rx.St Stage x of reverse power protection picks up.
5 32Rx.Op Stage x of reverse power protection operates.
6 32Rx.Alm Stage x of reverse power protection alarms.

Date: 2019-04-24
3.19.4 Logic
SET |P| > [32Rx.P_Set] &
SIG P<0
SET U1 < [32R.U1_VCE] & 32Rx.St
≥1
SET I1 < [32R.I1_CCE]
SET U2 > [32R.U2_VCE] &

[32Rx.t_Op] 0
& 32Rx.Op
3 SIG 32Rx.Pkp
SET [32Rx.Opt_Trp/Alm] = Trp

& 32Rx.Alm
SET [32Rx.Opt_Trp/Alm] = Alm
Figure 3.19-5 Logic diagram of reverse power protection
3.19.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  RevPower Settings
Table 3.19-2 Settings of reverse power protection

1 32R.U1_VCE 5~60 5 V 0.001 positive-sequence voltage control element
of the reverse power protection
The positive-sequence current setting of
2 32R.I1_CCE 0.01~1 0.1 p.u. 0.001 the current control element of the reverse
power protection
3 32R.U2_VCE 8~60 8 V 0.001 negative-sequence voltage control element
The power setting of the stage 1 of reverse
4 32R1.P_Set 0.1~10 0.15 p.u. 0.001
power protection
The time setting of the stage 1 of reverse
5 32R1.t_Op 0.01~100 0.1 s 0.001
power protection
Disabled; The logic setting of the stage 1 of reverse
Enabled power protection
Enabling stage 1 of reverse power
7 32R1.Opt_Trp/Alm Trp - -

Date: 2019-04-24

8 32R2.P_Set 0.1~10 0.15 p.u. 0.001
power protection
9 32R2.t_Op 0.01~100 0.1 s 0.001
power protection
3
3.20 Cold Load Pickup Logic (CLP)
The cold load pickup (CLP) logic which is included within this relay serves to either inhibit the
selected protective elements for an appointed duration, or to raise the settings of the selected
protective elements. Therefore, it allows the protection settings to be set closer to the load profile
by automatically increasing them following circuit energization. The CLP logic thus provides
stability, whilst maintaining protection during starting.
If the CLP logic is operated, the CLP settings are enabled for the overcurrent protection and the
zero-sequence overcurrent protection respectively. After the dropout time delay of the CLP logic
has elapsed, the normal protection settings are applied. And if a fast resetting signal is received,
the normal protection settings are applied after the pre-define short resetting time delay.
CLP
CLP.in_init CLP.On
CLP.in_shortRst CLP.Blocked
CLP.Valid
Figure 3.20-1 Function block diagram of cold load pickup logic
3.20.3 I/O Signals

Table 3.20-1 Input/output signals of cold load pickup logic

1 CLP.in_init The input of the CLP initiation signal
2 CLP.in_ShortRst The input of the short resetting signal
1 CLP.On The cold load pickup logic is enabled.

Date: 2019-04-24
2 CLP.Blocked The cold load pickup logic is blocked.

3 CLP.Valid The cold load pickup logic is valid.
3.20.4 Logic
SIG CLP.Onload &
SET [CLP.Opt_LogicMode] = 0
≥1
SE T
EN CLP.On tCold 0ms
S Q
&
SIG CLP.BI_52b R
CLR
Q
SET [CLP.Opt_LogicMode] = 1 tRst 0ms
3
≥1
& &
tS hort Rst 0ms
SIG CLP.In_ShortRst
SIG CLP.St_50/51
≥1
SIG CLP.in_Init
&
CLP.Op
EN CLP.On
Figure 3.20-2 Logic diagram of cold load pickup logic
Where:
CLP.Onload is the signal denotes anyone of the phase currents is greater than 0.04In.
CLP.BI_52b is the binary input for inputting the normally closed contact of the circuit breaker.
CLP.St_50/51 is the binary signal which denotes anyone of the selected protective elements
picked up.
“CLP.On” is the signal for denoting the cold load pickup logic function is enabled.
“tCold” is the setting [CLP.t_Cold], the time setting for ensuring the cold load condition is met.
“tRst” is the setting [CLP.t_Rst], the time setting for resetting the cold load pickup logic function.
“tShortRst” is the setting [CLP.t_ShortRst], the time setting for fast resetting the cold load pickup logic
function.
3.20.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  CLP Settings

Date: 2019-04-24
Table 3.20-2 Settings of cold load pickup logic

The setting for selecting the cold load
Curr;
1 CLP.Opt_LogicMode CBPos - - initiation condition.
CBPos
Curr: current; CBPos: CB position.
The time setting for ensuring the cold
2 CLP.t_Cold 0~4000 3 s 0.001
load condition is met
The time setting for resetting the cold
3 CLP.t_Rst 0~4000 3 s 0.001
load pickup logic
The time setting for fast resetting the cold
4 CLP.t_ShortRst 0~600 1 s 0.001
load pickup logic 3
Disabled; The logic setting of the cold load pickup
5 CLP.En Enabled - -
Enabled logic function
The multiple setting of the stage 1 of
6 50/51P1.CLP.IMult 1~10 1 - 0.001 overcurrent protection when CLP is
active
7 50/51P1.CLP.t_Op 0~100 0.1 s 0.001 overcurrent protection when CLP is
active
The time multiplier setting of the stage 1
8 50/51P1.CLP.TMS 0.05~100 1 s 0.001 of IDMT overcurrent protection when CLP
is active
9 50/51G1.CLP.IMult 1~10 1 - 0.001 zero-sequence overcurrent protection
when CLP is active
10 50/51G1.CLP.t_Op 0~100 0.1 s 0.001 zero-sequence overcurrent protection
when CLP is active
11 50/51G1.CLP.TMS 0.05~100 1 s 0.001 of zero-sequence IDMT overcurrent
protection when CLP is active
active
active
is active
when CLP is active

Date: 2019-04-24

when CLP is active
active
3 19 50/51P3.CLP.t_Op 0~100 0.1 s 0.001 overcurrent protection when CLP is

active
is active
when CLP is active
when CLP is active
active
active
is active
when CLP is active
when CLP is active

Date: 2019-04-24

active
active
is active
33 50/51G5.CLP.IMult 1~10 1 - 0.001 zero-sequence overcurrent
when CLP is active
protection
3
when CLP is active
active
active
is active
when CLP is active
when CLP is active
3.21 Undercurrent Protection (37)
The undercurrent protection can remove the device from the system by detecting the smaller load
current when the load is lost, the capacitor is lost of voltage and the motor is running without any
load.

Date: 2019-04-24

The device can provide one stage of undercurrent protection. For different protected equipment,
the single-phase criterion or three-phase criterion can be selected. The position of circuit breaker,
the load current also can be taken as the enabling conditions for the undercurrent protection. The
undercurrent protection is with definite-time operation characteristic and instantaneous dropout
characteristic. Undercurrent protection can operate to trip or alarm, it can be enabled or blocked
by the external binary input.
Undercurrent protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, undercurrent protection needs to be blocked by the external signal, so
3 the device provides a function block input signal to be used to block undercurrent protection. The
enabling and blocking logic of undercurrent protection is shown in the figure below:
EN 37.En & 37.On
SIG 37.Enable
& 37.Blocked
SIG 37.Block ≥1
SIG Fail_Device
& 37.Valid
Figure 3.21-1 Logic diagram of enabling/disabling undercurrent protection
When the undercurrent protection is enabled and no external blocking signal is input, if the
detected current is less than the current setting multiplied by 1.10 of the undercurrent protection,
the undercurrent protection will pick up.
[37.Opt_1P/3P]. If it is set as “1P”, undercurrent protection can operate if any phase current is
smaller than the current setting. If it is set as “3P”, undercurrent protection cannot operate unless
three phase currents are smaller than the current setting.
The circuit breaker position with/without the current condition can be used as an auxiliary criterion
for undercurrent protection, which can be configured via the setting [37.Opt_LogicMode].
The logic diagram of the fault detector of the undercurrent protection is shown as below.

Date: 2019-04-24
SIG Ia<1.10×[37.I_Set]
>=1
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]
>=1
Pickup current criterion
SET [37.Opt_1P/3P]=1P
SIG Ia<1.10×[37.I_Set]
&
SIG Ib<1.10×[37.I_Set] &
SIG Ic<1.10×[37.I_Set]
3
SET [37.Opt_LogicMode]=None
SET [37.Opt_LogicMode]=Curr & >=1

>=1
SIG Ip>0.04In Auxiliary criterion
SET [37.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1
SET [37.Opt_LogicMode]=CurrOrCBPos
&
&
SET [37.Opt_LogicMode]=CurrAndCBPos
SIG Pickup current criterion

& 37.Pkp
SIG Auxiliary criterion 0 500ms &
SIG 37.On
&
FD.Pkp
SIG 37.Valid
SET [37.Opt_Trp/Alm]=Alm
Figure 3.21-2 Logic diagram of the fault detector of undercurrent protection
The undercurrent protection has definite-time operation characteristic complied with IEC 60255-3
and ANSI C37.112. If the load current is less than the current setting of the undercurrent
protection [37.I_Set], the undercurrent protection will operate after the time setting [37.t_Op].
The operation characteristic curve of undercurrent protection is shown as below.

Date: 2019-04-24
t op
Ip I
Figure 3.21-3 Operation characteristic curve of undercurrent protection
The undercurrent protection is with instantaneous dropout characteristic. If the load current is
larger than the current setting [37.I_Set] multiplied by 1.10, the undercurrent protection will drop
out immediately.
37
37.Enable 37.On
37.Block 37.Blocked
37.Valid
37.St
37.StA
37.StB
37.StC
37.Op
37.Op.PhA
37.Op.PhB
37.Op.PhC
37.Alm
Figure 3.21-4 Function block diagram of undercurrent protection

Date: 2019-04-24
3.21.3 I/O Signals

Table 3.21-1 Input/output signals of undercurrent protection

Undercurrent protection enabling input, it is triggered from binary input or
1 37.Enable
programmable logic etc.
Undercurrent protection blocking input, it is triggered from binary input or
2 37.Block
1 37.On Undercurrent protection is enabled.
2 37.Blocked Undercurrent protection is blocked. 3
3 37.Valid Undercurrent protection is valid.
4 37.St Undercurrent protection starts.
5 37.StA Undercurrent protection starts (Phase A)
6 37.StB Undercurrent protection starts (Phase B)
7 37.StC Undercurrent protection starts (Phase C)
8 37.Op Undercurrent protection operates.
9 37.Op.PhA Undercurrent protection operates (Phase A)
10 37.Op.PhB Undercurrent protection operates (Phase B)
11 37.Op.PhC Undercurrent protection operates (Phase C)
12 37.Alm Undercurrent protection alarms.

Date: 2019-04-24
3.21.4 Logic
SIG Ia<[37.I_Set]
>=1
SIG Ib<[37.I_Set] &
SIG Ic<[37.I_Set]
>=1
Current criterion
SIG Ia<[37.I_Set]
&
SIG Ib<[37.I_Set] &
3 SIG Ic<[37.I_Set]
SIG Current criterion

& 37.St
SIG Auxiliary criterion &
[37.t_Op] 0
SIG 37.On
SIG 37.Pkp
&
37.Op
SET [37.Opt_Trp/Alm]=Trp
&
37.Alm
SET [37.Opt_Trp/Alm]=Alm
Figure 3.21-5 Logic diagram of undercurrent protection
Where:
Auxiliary criterion: please refer to Figure 3.21-2.
3.21.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  UC Settings
Table 3.21-2 Settings of undercurrent protection

The current setting of the
1 37.I_Set 0.1~5 0.5 A 0.001
undercurrent protection
The time setting of the undercurrent
2 37.t_Op 0.1~100 0.1 s 0.001
protection
1P;
3 37.Opt_1P/3P 3P - - three-phase criterion (3P) or
3P
single-phase criterion (1P)

Date: 2019-04-24
None;
Curr;
CurrAnd The setting of the CB position check
4 37.Opt_LogicMode CBPos; - -
CBPos mode.
CurrAndCBPos;
CurrOrCBPos
Disabled; The logic setting of the undercurrent
5 37.En Enabled - -
Enabled protection
Enabling undercurrent protection
Trp; operate to trip or alarm.
6 37.Opt_Trp/Alm Trp - -
3
3.22 Breaker Failure Protection (50BF)
When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure
protection is adopted to issue a backup tripping command to trip adjacent circuit breakers, and
isolate the fault as requested by the device.
According to the tripping information from the device and the auxiliary information (the current and
the position) of target circuit breaker, breaker failure protection constitutes the criterion to
discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker failure
protection will operate to trip the target circuit breaker with the time delay [50BF.t_ReTrp], trip it
again with the time delay [50BF.t1_Op] and trip the adjacent circuit breakers with the time delay
[50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly isolate the
fault, reduce the affected range by the fault, keep system stability and prevent generators,
transformers and other primary equipments from seriously damaged.
For breaker failure protection, re-trip and two time delays are available.
3.22.1.1 Re-trip
When breaker failure protection receives initiating signal of tripping and phase overcurrent
element of any phase operates, the device will issue tripping command to re-trip the target circuit
breaker with the time delay [50BF.t_ReTrp]. In order to improve the sensitivity, both
zero-sequence overcurrent element and negative-sequence overcurrent element are added,
which can be enabled or disabled by the settings [50BF.En_3I0_3P] and [50BF.En_I2_3P].
3.22.1.2 First Time Delay
As similar as re-trip, the device will operate to re-trip the target circuit breaker again with the time
delay [50BF.t1_Op] when the relevant operating criterion is satisfied.

Date: 2019-04-24
3.22.1.3 Second Time delay
As similar as re-trip, the device will operate to trip the adjacent circuit breakers with the time delay
[50BF.t2_Op] when the relevant operating criterion is satisfied.
3.22.1.4 Current Criterion
1. Phase overcurrent element
Where:
3 = A, B or C
2. Zero-sequence overcurrent element
Where:
is calculated residual current
3. Negative-sequence overcurrent element
Where:
is negative-sequence current
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal "50BF.ExTrp_WOI" is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker
failure current check to trigger breaker failure timer. The device takes current as priority with CB
auxiliary contact "50BF.52b" as an option criterion for breaker failure check.
When the initiating signal of breaker failure protection is energized for longer than 10s, an alarm
signal "50BF.Alm_Init" will be issued, and will drop out with a time delay of 10s.

Date: 2019-04-24
50BF
50BF.Enable 50BF.On
50BF.Block 50BF.Blocked
50BF.ExTrp3P 50BF.Valid
50BF.ExTrp_WOI 50BF.St
50BF.Op_ReTrp3P
50BF.Op_t1 3
50BF.Op_t2
50BF.Alm_Init
3.22.3 I/O Signals

Table 3.22-1 Input/output signals of breaker failure protection

Breaker failure protection enabling input, it is triggered from binary input or
1 50BF.Enable
Breaker failure protection blocking input, it is triggered from binary input or
2 50BF.Block
3 50BF.ExtTrp3P Input signal of initiating breaker failure protection (three-phases)
Input signal of initiating breaker failure protection with the position check of
4 50BF.ExtTrp_WOI
the circuit breaker
1 50BF.On Breaker failure protection is enabled.
2 50BF.Blocked Breaker failure protection is blocked.
3 50BF.Valid Breaker failure protection is valid.
4 50BF.St Breaker failure protection starts
5 50BF.Op_ReTrp3P Breaker failure protection operates to re-trip three-phases circuit breaker.
6 50BF.Op_t1 Breaker failure protection operates with the time delay [50BF.t1_Op].
7 50BF.Op_t2 Breaker failure protection operates with the time delay [50BF.t2_Op].
8 50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently.

Date: 2019-04-24
3.22.4 Logic
EN [50BF.En] &
50BF.On
SIG 50BF.Enable
&
SIG 50BF.Block >=1 50BF.Blocked
SIG Fail_Device
&
50BF.Valid
3
Figure 3.22-1 Logic of enabling breaker failure protection
SIG 50BF.ExtTrp3P 10s 10s >=1
SIG 50BF.ExtTrp_WOI 10s 10s
&
EN [50BF.En_Alm_Init] 50BF.Alm_Init
SIG 50BF.Valid
Figure 3.22-2 Logic of breaker failure initiating signal abnormality
SIG 50BF.Valid &
SIG 50BF.Alm_Init
EN [50BF.En_ReTrp]
EN [50BF.En_Ip]
SET IA>[50BF.I_Set] &

>=1 [50BF.t_ReTrp] 0 50BF.Op_ReTrp3P
SET IB>[50BF.I_Set]
SET IC>[50BF.I_Set]
&
SIG 50BF.ExtTrp3P
&
EN [50BF.En_3I0_3P] &
SET 3I0>[50BF.3I0_Set]
>=1 &
& >=1 [50BF.t1_Op] 0 50BF.Op_t1
EN [50BF.En_I2_3P] &
SET I2>[50BF.I2_Set]
SIG 50BF.ExtTrp_WOI
>=1
& 50BF.St
EN [50BF.En_CB_Ctrl]
SIG 50BF.52b
EN [50BF.En_t1]
&
[50BF.t2_Op] 0 50BF.Op_t2
EN [50BF.En_t2]
Figure 3.22-3 Logic of breaker failure protection

Date: 2019-04-24
Where:
50BF.52b: Input signal of three-phase open position of circuit breaker.
3.22.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  BFP Settings
Table 3.22-2 Settings of breaker failure protection
1 50BF.I_Set 0.05~200 1.000 A 0.001

The phase current setting of breaker 3
failure protection
The zero-sequence current setting of
2 50BF.3I0_Set 0.05~200 1.000 A 0.001
breaker failure protection
The negative-sequence current setting of
3 50BF.I2_Set 0.05~200 1.000 A 0.001
The re-trip time delay of breaker failure
4 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
5 50BF.t1_Op 0~20 0.100 s 0.001
protection
The second time delay of breaker failure
6 50BF.t2_Op 0~20 0.200 s 0.001
protection
Disabled Enabling/disabling breaker failure
7 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
8 50BF.En_ReTrp Enabled - -
Enabled breaker failure protection
Disabled Enabling/disabling first time delay of
9 50BF.En_t1 Disabled - -
Disabled Enabling/disabling second time delay of
Enabling/disabling phase overcurrent
Disabled
11 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
three-phases initiating signal
Enabling/disabling zero-sequence
Disabled overcurrent element of breaker failure
12 50BF.En_3I0_3P Disabled - -
Enabled protection via three-phases initiating
signal
Enabling/disabling negative-sequence
13 50BF.En_I2_3P Disabled - -
signal
Enabling/disabling breaker failure
Disabled
14 50BF.En_CB_Ctrl Disabled - - protection be initiated by normally closed
Enabled
contact of circuit breaker

Date: 2019-04-24
Disabled Enabling/disabling abnormality check of

15 50BF.En_Alm_Init Disabled - -
Enabled breaker failure initiating signal
3.23 Switch-on-to-Fault Protection (SOTF)

When the line is put into operation or the power is restored, the circuit breaker is necessary to be
closed automatically, it is possible to switch on to a permanent fault. The conventional phase
overcurrent protection or earth fault overcurrent protection requires a time delay to operate and
isolate the fault, which will affect the power system seriously. Switch-on-to-fault (SOTF) protection
can quickly operate to remove the fault and reduce the impact of the fault on the system.
3 3.23.1 Function Description

The device can provide one stage of phase overcurrent SOTF protection and one stage of earth
fault overcurrent SOTF protection. The SOTF protection is with definite-time delay characteristic
and instantaneous dropout characteristic, it can be enabled or blocked by the external binary
input.
The SOTF protection can be enabled or disabled via the settings or binary input signals, for some
specific applications, the protection needs to be blocked by the external signal, so the device
provides a function block input signal to be used to block RMS overcurrent protection. The
enabling and blocking logic of the SOTF protection is shown in the figure below:
EN 50PSOTF.En &
50PSOTF.On
SIG 50PSOTF.Enable
&
SIG 50PSOTF.Block ≥1 50PSOTF.Blocked
SIG Fail_Device
&
50PSOTF.Valid
EN 50GSOTF.En &
50GSOTF.On
SIG 50GSOTF.Enable
&
SIG 50GSOTF.Block ≥1 50GSOTF.Blocked
SIG Fail_Device
&
50GSOTF.Valid
Figure 3.23-1 The enabling and blocking logic of SOTF protection
The SOTF protection must be initiated by auto-reclosing signal or manual closing signal, the

Date: 2019-04-24
initiating time can be set by the setting [STOF.t_En]. After the acceleration condition is satisfied,
the SOTF protection will operate with a time delay of [50PSOTF.t_Op]/ [50GSOTF.t_Op].
The device provides a variety of accelerated tripping modes by manual closing signal, which can
choose circuit breaker position, external binary signal of manual closing.
1. Circuit breaker position (The setting [SOTF.Opt_Mode_ManCls] shall be set as "CBPos" or

"ManClsBI/CBPos")
When the circuit breaker is in open position while the device does not pick up, then manual
closing signal will be kept for a certain time which is determined by the setting [SOTF.t_En], and
SOTF protection will be enabled.
2. External binary signal of manual closing (The setting [SOTF.Opt_Mode_ManCls] shall be set
3
as "ManClsBI"or "ManClsBI/CBPos")
When external binary input of manual closing is energized, then manual closing signal will be kept
for a certain time which is determined by the setting [SOTF.t_En], and SOTF protection will be
enabled.
When the SOTF protection is used for the transformer bay, large inrush current generated during
manual closing and auto-reclosing maybe lead to an undesired operation of SOTF protection.
Second harmonic blocking can be selected by the setting
[50PSOTF.En_Hm2_Blk]/[50GSOTF.En_Hm2_Blk] to prevent the mal-operation due to inrush
current. The harmonic blocking characteristic of the phase overcurrent SOTF protection is
consistent with that of phase overcurrent protection. The harmonic blocking characteristic of the
earth fault overcurrent SOTF protection is consistent with that of earth fault overcurrent protection.
In order to improve the reliability, phase overcurrent SOTF protection can select phase voltage
element, phase-to-phase voltage element, zero-sequence voltage element and
negative-sequence voltage element as auxiliary criterion.
50PSOTF 50GSOTF
50PSOTF.Enable 50PSOTF.On 50GSOTF.Enable 50GSOTF.On
50PSOTF.Block 50PSOTF.Blocked 50GSOTF.Block 50GSOTF.Blocked
50PSOTF.Valid 50GSOTF.Valid
50PSOTF.Op
50GSOTF.Op
50PSOTF.St
50GSOTF.St
3.23.3 I/O Signals

Table 3.23-1 Input/output signals of SOTF protection

1 50PSOTF.Enable Phase overcurrent SOTF protection enabling input, it is triggered from binary

Date: 2019-04-24
input or programmable logic etc.

Phase overcurrent SOTF protection blocking input, it is triggered from binary
2 50PSOTF.Block
input or programmable logic etc.
Earth fault overcurrent SOTF protection enabling input, it is triggered from
3 50GSOTF.Enable
Earth fault overcurrent SOTF protection blocking input, it is triggered from
4 50GSOTF.Block
1 50PSOTF.On Phase overcurrent SOTF protection is enabled.
2 50PSOTF.Blocked Phase overcurrent SOTF protection is blocked
3 3 50PSOTF.Valid Phase overcurrent SOTF protection is valid

4 50PSOTF.Op Phase overcurrent SOTF protection operates.
5 50PSOTF.St Phase overcurrent SOTF protection starts.
6 50GSOTF.On Earth fault overcurrent SOTF protection is enabled.
7 50GSOTF.Op Earth fault overcurrent SOTF protection operates.
8 50GSOTF.Blocked Earth fault overcurrent SOTF protection is blocked
9 50GSOTF.Valid Earth fault overcurrent SOTF protection is valid
10 50GSOTF.St Earth fault overcurrent SOTF protection starts.
3.23.4 Logic
SIG 79.Close 0 [SOTF.t_En] AR signal
Figure 3.23-2 Logic of auto-reclosing signal
SIG 52b_PhA
>=1
SIG 52b_PhB
SIG 52b_PhC
&
SIG FD.Pkp
SET [SOTF.Opt_Mode_ManCls]=CBPos >=1
SET [SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos >=1

0 [SOTF.t_En] Manual closing signal
SET [SOTF.Opt_Mode_ManCls]=ManClsBI >=1
SET [SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos
&
SIG FD.Pkp
SIG ManCls
Figure 3.23-3 Logic of manual closing signal

Date: 2019-04-24
SIG AR signal >=1
SIG Manual closing signal
SET Ia>[50PSOTF.I_Set]
>=1
SET Ib>[50PSOTF.I_Set]
SET Ic>[50PSOTF.I_Set]
SIG I3P 2nd Hm Detect & &
EN [50PSOTF.En_Hm2_Blk]
SET Ua<[50PSOTF.Up_Set]
>=1
SET Ub<[50PSOTF.Up_Set]
SET Uc<[50PSOTF.Up_Set]
&
3
EN [50PSOTF.En_Up_UV]
SET Uab<[50PSOTF.Upp_Set]
>=1 >=1
SET Ubc<[50PSOTF.Upp_Set] &
SET Uca<[50PSOTF.Upp_Set]
EN [50PSOTF.En_Upp_UV]
SET U2>[50PSOTF.U2_Set] & >=1

>=1
EN [50PSOTF.En_U2_OV]
SET U2>[50PSOTF.3U0_Set] &
EN [50PSOTF.En_3U0_OV]
EN [50PSOTF.En_Up_UV]
>=1
EN [50PSOTF.En_Upp_UV]
EN [50PSOTF.En_U2_OV]
EN [50PSOTF.En_3U0_OV]
&
SIG FD.Pkp & [50PSOTF.t_Op] 0 50PSOTF.Op
SIG 50PSOTF.Enable & 50PSOTF.St
&
SIG 50PSOTF.Block 50PSOTF.On
EN [50PSOTF.En]
Figure 3.23-4 Logic of phase overcurrent SOTF protection

Date: 2019-04-24
SIG I3P 2nd Hm Detect &
SET [50/51G1.En_Hm2_Blk]
SIG AR signal >=1
SIG Manual closing signal

50GSOTF.St
SET 3I0>[50GSOTF.3I0_Set] & &
[50GSOTF.t_Op] 0 50GSOTF.Op
SIG FD.Pkp
SIG 50GSOTF.Enable &

3 SIG 50GSOTF.Block
&
50GSOTF.On
EN [50GSOTF.En]
Figure 3.23-5 Logic of earth fault overcurrent SOTF protection
3.23.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  SOTF Settings
Table 3.23-2 Settings of SOTF protection

The initiating time for the SOTF
1 SOTF.t_En 0.2~100 3 s 0.001
protection
Option of manual SOTF mode
ManClsBI:initiated by input signal of
ManClsBI
manual config
SOTF.Opt_Mode_Man CBPos
2 CBPos - - CBPos:initiaed by CB position
Cls ManClsBI/
ManClsBI/CBPos:initiated by either
CBPos
input signal of manual closing or CB
postition
Current setting of phase overcurrent
3 50PSOTF.I_Set 0.05~200 1 A 0.001
SOTF protection
Voltage setting for phase
4 50PSOTF.Up_Set 0~200 1 V 0.001
undervoltage supervision logic
Voltage setting for phase-to-phase
5 50PSOTF.Upp_Set 0~200 1 V 0.001
Voltage setting for negative-sequence
6 50PSOTF.U2_Set 0~200 1 V 0.001
overvoltage supervision logic
Voltage setting for zero-sequence
7 50PSOTF.3U0_Set 0~200 1 V 0.001
Time delay for phase overcurrent
8 50PSOTF.t_Op 0~100 0.1 s 0.001
SOTF protection

Date: 2019-04-24
Disabled Enabling/disabling phase overcurrent

9 50PSOTF.En Enabled - -
Enabled SOTF protection
Enabling/disabling second harmonic
Disabled
10 50PSOTF.En_Hm2_Blk Enabled - - blocking for phase overcurrent SOTF
Enabled
protection
Enabling/disabling phase
Disabled
11 50PSOTF.En_Up_UV Enabled - - undervoltage supervision logic for
Enabled
phase overcurrent SOTF protection
Enabling/disabling phase-to-phase
Disabled
12 50PSOTF.En_Upp_UV Enabled - - undervoltage supervision logic for
Enabled
3
Enabling/disabling
Disabled negative-sequence overvoltage
13 50PSOTF.En_U2_OV Enabled - -
Enabled supervision logic for phase
overcurrent SOTF protection
Disabled
14 50PSOTF.En_3U0_OV Enabled - - overvoltage supervision logic for
Enabled
The option of the residual current
used by earth fault overcurrent SOTF
Ext
15 50GSOTF.Opt_3I0 Cal - - protection
Cal
Ext: the measured residual current
Cal: the calculated residual current
Current setting of earth fault
16 50GSOTF.3I0_Set 0.05~200 1 A 0.001
Time delay for earth fault overcurrent
17 50GSOTF.t_Op_3P 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling earth fault
18 50GSOTF.En Enabled - -
Enabled overcurrent SOTF protection
Enabling/disabling earth fault
Disabled
19 50GSOTF.En_Hm2_Blk Disabled - - overcurrent SOTF protection blocked
Enabled
by harmonic
3.24 Unbalance Current Protection (60/50)
The unbalance current protection is adopted for the internal fault of capacitor bank with
double-star connection. The fault causes the capacitance reactance of a phase branch to be
changed, makes three phase reactance unequal and the unbalance current will be generated at
neutral point.
The application of the unbalance current protection in the capacitor bank with double-star
connection is shown in following figure.

Date: 2019-04-24
60/50N
Figure 3.24-1 Application of the unbalance current protection
This device provides two stages of unbalance current protection. If the unbalance current is
greater than the predefined setting, this protection will operate. The unbalance current protection
is with independent definite-time delay characteristic and with instantaneous dropout
characteristic.
3.24.1.1 Unbalance Current Protection
The unbalance current protection can be enabled or disabled by the settings. If the setting
[60/50-x.En] (x: 1~2) is set as “1”, and the signal [60/50-x.Enable] (x: 1~2) is “1” and the signal
[60/50-x.Block] (x: 1~2) is “0”. For some special application, the unbalance current protection
needs to be blocked by external signal, the input signal [60/50-x.Block] (x: 1~2) is provided for this
purpose.
The logic diagram of enabling/disabling unbalance current protection is shown in Figure 3.24-2.
EN 60/50-x.En & 60/50-x.On
SIG 60/50-x.Enable
& 60/50-x.Blocked
SIG 60/50-x.Block ≥1
SIG Fail_Device
& 60/50-x.Valid
Figure 3.24-2 Logic diagram of enabling/disabling unbalance current protection
When the unbalance current protection is enabled and no external blocking signal is input, if the

Date: 2019-04-24
unbalance current is greater than the current setting multiplied by 0.95 of the unbalance current
protection, the unbalance current protection will pick up.
The logic diagram of the fault detector of unbalance current protection is shown in Figure 3.24-3.
SET Iu > [60/50-x.I_Set] × 0.95 & 60/50-x.Pkp

0ms 500ms
&
SIG 60/50-x.On & FD.Pkp
SIG 60/50-x.Valid
EN [60/50-x.Opt_Trp/Alm]=Alm
3
Figure 3.24-3 Logic diagram of the fault detector of unbalance current protection
The unbalance current protection has definite-time delay characteristic complied with IEC
60255-3 and ANSI C37.112. If the unbalance current is greater than the voltage setting of the
unbalance current protection [60/50-x.I_Set] (x: 1~2), the unbalance current protection will
operate after the time setting [60/50-x.t_Op] (x: 1~2).
The operation characteristic curve of unbalance current protection is shown in Figure 3.24-4.
t op
I u_set Iu
Figure 3.24-4 Operation characteristic curve of unbalance current protection
The unbalance current protection is with instantaneous dropout characteristic. If the unbalance
current is less than the current setting [60/50-x.I_Set] (x: 1~2) multiplied by 0.95, the unbalance
current protection will drop out at once.

Date: 2019-04-24
60/50
60/50-x.Enable 60/50-x.On
60/50-x.Block 60/50-x.Blocked
60/50-x.Valid
60/50-x.St
60/50-x.Op
60/50-x.Alm
3 Figure 3.24-5 Function block diagram of unbalance current protection
3.24.3 I/O Signals

Table 3.24-1 Input/output signals of unbalance current protection

Stage x of unbalance current protection enabling input, it is triggered from binary
1 60/50-x.Enable
Stage x of unbalance current protection blocking input, it is triggered from binary
2 60/50-x.Block
1 60/50-x.On Stage x of unbalance current protection is enabled.
2 60/50-x.Blocked Stage x of unbalance current protection is blocked.
3 60/50-x.Valid Stage x of unbalance current protection is valid.
4 60/50-x.St Stage x of unbalance current protection picks up.
5 60/50-x.Op Stage x of unbalance current protection operates.
6 60/50-x.Alm Stage x of unbalance current protection alarms.
3.24.4 Logic
60/50-x.St
SET Iu > [60/50-x.I_Set] &

[60/50-x.t_Op] 0 & 60/50-x.Op
SIG 60/50-x.Pkp
SET [60/50-x.Opt_Trp/Alm] = Trp

& 60/50-x.Alm
SET [60/50-x.Opt_Trp/Alm] = Alm
Figure 3.24-6 Logic diagram of unbalance current protection
3.24.5 Settings
 Access path:
MainMenu  Settings  Protection Settings  UnbalCurr Settings

Date: 2019-04-24
Table 3.24-2 Settings of unbalance current protection

1 60/50-1.I_Set 0.02~200 1 A 0.001
unbalance current protection
2 60/50-1.t_Op 0.05~100 0.1 s 0.001
Disabled; The logic setting for enabling/disabling
3 60/50-1.En Enabled - -
Enabled stage 1 of unbalance current protection
Enabling stage 1 of unbalance current
4 60/50-1.Opt_Trp/Alm
Alm
Trp - -
Trp: for tripping purpose 3
5 60/50-2.I_Set 0.02~200 1 A 0.001
6 60/50-2.t_Op 0.05~100 0.1 s 0.001
7 60/50-2.En Enabled - -
8 60/50-2.Opt_Trp/Alm Trp - -
3.25 Unbalance Voltage Protection (60/59)
The unbalance voltage protection is adopted for the internal fault of capacitor bank with
double-star connection. The fault causes the capacitance reactance of a phase branch to be
changed, makes three phase reactance unequal and the unbalance voltage will be generated at
neutral point.
The application of the unbalance voltage protection for a capacitor bank with double-star
connection is shown in following figure.

Date: 2019-04-24
60/59N
Figure 3.25-1 Application of the unbalance voltage protection
This device supports two stages of unbalance voltage protection. If the unbalance voltage is
greater than the predefined setting, this protection will operate. The unbalance voltage protection
is with independent definite-time delay characteristic and with instantaneous dropout
characteristic. In order to adapt to different applications, unbalance voltage protection can operate
to trip or alarm, it can be enabled or blocked by the external binary input.
3.25.1.1 Unbalance voltage Protection
Unbalance voltage protection can be enabled or disabled via the settings or binary input signals,
for some specific applications, unbalance voltage protection needs to be blocked by the external
signal, so the device provides a function block input signal to be used to block unbalance voltage
protection. The enabling and blocking logic of unbalance voltage protection is shown in the figure
below:
EN 60/59-x.En & 60/59-x.On
SIG 60/59-x.Enable
& 60/59-x.Blocked
SIG 60/59-x.Block ≥1
SIG Fail_Device
& 60/59-x.Valid
Figure 3.25-2 Logic diagram of enabling/disabling unbalance voltage protection
When the unbalance voltage protection is enabled and no external blocking signal is input, if the

Date: 2019-04-24
unbalance voltage is greater than the voltage setting multiplied by 0.95, the unbalance voltage
protection will pick up.
The logic diagram of the fault detector of unbalance voltage protection is shown as below.
SET Uu > [60/59-x.U_Set]×0.95 & 60/59-x.Pkp

0ms 500ms
&
SIG 60/59-x.On & FD.Pkp
SIG 60/59-x.Valid
EN [60/59-x.Opt_Trp/Alm]=Alm
3
Figure 3.25-3 Logic diagram of the fault detector of unbalance voltage protection
The unbalance voltage protection can operate with a definite-time limit, the characteristic curve
meets the IEC60255-3 and ANSI C37.112 standards.
When the unbalance voltage (Uub) is larger than the voltage setting, the protection operates with a
time delay of top (i.e. the value of the setting [60/59-x.U_Set] (x=1~2)), and the operation
t op
Uu_set Uu
Figure 3.25-4 Operation characteristic curve of unbalance voltage protection
The unbalance voltage protection is with instantaneous dropout characteristic. If the unbalance
voltage is less than the voltage setting multiplied by 0.95, the unbalance voltage protection will
drop out immediately.

Date: 2019-04-24
60/59
60/59-x.Enable 60/59-x.On
60/59-x.Block 60/59-x.Blocked
60/59-x.Valid
60/59-x.St
60/59-x.Op
60/59-x.Alm
3 Figure 3.25-5 Function block diagram of unbalance voltage protection
3.25.3 I/O Signals

Table 3.25-1 Input/output signals of unbalance voltage protection

Stage x of unbalance voltage protection enabling input, it is triggered from
1 60/59-x.Enable
Stage x of unbalance voltage protection blocking input, it is triggered from binary
2 60/59-x.Block
1 60/59-x.On Stage x of unbalance voltage protection is enabled.
2 60/59-x.Blocked Stage x of unbalance voltage protection is blocked.
3 60/59-x.Valid Stage x of unbalance voltage protection is valid.
4 60/59-x.St Stage x of unbalance voltage protection starts
5 60/59-x.Op Stage x of unbalance voltage protection operates.
6 60/59-x.Alm Stage x of unbalance voltage protection alarms.
3.25.4 Logic
60/59-x.St
SET Uu > [60/59-x.U_Set] &

[60/59-x.t_Op] 0 & 60/59-x.Op
SIG 60/59-x.Pkp
SET [60/59-x.Opt_Trp/Alm] = Trp

& 60/59-x.Alm
SET [60/59-x.Opt_Trp/Alm] = Alm
Figure 3.25-6 Logic diagram of unbalance voltage protection
3.25.5 Settings
 Access path:

Date: 2019-04-24
MainMenu  Settings  Protection Settings  UnbalVolt Settings
Table 3.25-2 Settings of unbalance voltage protection

1 60/59-1.U_Set 1~63.5 50 V 0.001
unbalance voltage protection
2 60/59-1.t_Op 0.1~100 1 s 0.001
3 60/59-1.En Enabled - -
Enabled stage 1 of unbalance voltage protection
Enabling stage 1 of unbalance voltage 3
5 60/59-2.U_Set 1~63.5 50 V 0.001
6 60/59-2.t_Op 0.1~100 1 s 0.001
7 60/59-2.En Enabled - -
Enabling stage 2 of unbalance voltage
3.26 Automatic Reclosure (79)

To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. AR are installed to restore the faulted section of the
transmission system once the fault is extinguished (providing it is a transient fault). For certain
transmission systems, AR is used to improve system stability by restoring critical transmission
paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and AR is not initiated after faulty feeder is tripped. For some
mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines, etc., it is
required to ensure that AR is only initiated for faults overhead line section, or make a choice
according to the situation.

AR can be used with either integrated device or external device. When AR is used with integrated
device, the internal protection logic can initiate AR, moreover, a tripping contact from external

Date: 2019-04-24
device can be connected to the device via input signal to initiate integrated AR.
When AR is used as an independent device, it can be initiated by operating signal of protections.

The device can output some configurable output signals (such as, contact signals or digital signal,
for example, GOOSE signal) to initiate external AR or block external AR. The contact signals
includes tripping signal, blocking AR signal and protection operating signal, etc,. According to
requirement, these contacts can be selectively connected to external AR and the device can be
set as one-shot or multi-shot AR.
3.26.1.1 Enable AR
When the setting [79.Opt_Enable] is set as "Setting&Config", AR is determined whether it is

3 enabled or disabled by the external input signal and the internal setting. Otherwise, it is only
determined by the internal setting. When AR is enabled, the device outputs the signal "79.On",
otherwise the device outputs the signal "79.Off".
The logic of enabling AR is:
EN [79.En] &
>=1
SET [79.Opt_Enable]=Setting &
79.On
SET [79.Opt_Enable]=Setting&Config &
79.Off
SIG 79.Enable
SIG 79.Block
Figure 3.26-1 Logic of enabling AR
3.26.1.2 AR Ready
AR must be ready to operate before performing reclosing. The output signal [79.Ready] means
that the auto-reclosure can perform at least one time of reclosing function, i.e., breaker
open-close-open.
When the device is energized or after the settings are modified, AR cannot be ready unless the
following conditions are met:
1. AR is enabled.
2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3. The duration of the circuit breaker in closed position pre-fault is greater than the setting
[79.t_CBClsd].
4. There is no the signal of blocking AR.
After AR operates, it must reset, i.e. [79.Active]=0, in addition to the above conditions for reclosing
again.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After the fault is cleared, the tripping signal will drop out immediately. In case the circuit breaker is

Date: 2019-04-24
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [79.t_PersistTrp], AR will be blocked, as shown in following figure
The input signal [79.CB_Healthy] must be energized before AR gets ready. Because most circuit
breakers can finish one complete process: open-closed-open, it is necessary that circuit breaker
has enough energy before reclosing. When the time delay of AR is exhausted, AR will be blocked
if the input signal [79.CB_Healthy] is still not energized within time delay [79.t_CBReady]. If this
function is not required, the input signal [79.CB_Healthy] can be not to configure, and its state will
be thought as “1” by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input signal of blocking AR, when the circuit breaker is open by manually and there is CB
position input under normal conditions, AR will be blocked with the time delay of 100ms if AR is
3
not initiated and no any trip signal.
SIG Any tripping signal [79.t_PersistTrp] 0 >=1

0 [79.t_DDO_BlkAR] 79.AR_Blocked
SIG 79.LockOut
Figure 3.26-2 Logic of AR block
When AR is disabled, AR fails, synchronism check fails or last shot is reached, or when the
internal blocking condition of AR is met. AR will be discharged immediately and next AR will be
disabled. When the input signal [79.LockOut] is energized, AR will be blocked immediately. The
blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, AR will be blocked immediately. The logic of AR ready is shown as
below
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop out with a time delay [79.t_DDO_BlkAR] after blocking signal disappears.

Date: 2019-04-24
>=1
SIG CB closed position [79.t_CBClsd] 100ms &
SIG 79.Active >=1
SIG Any tripping signal

& &
2s 0 79.Ready
SIG 79.Inprog
BI [79.CB_Healthy] 0 [79.t_CBReady] &
3 SIG 79.AR_Blkd >=1

>=1
SIG 79.Lockout &
SIG 79.Failed
>=1
SIG 79.Fail_Chk
SIG Last shot is made
SIG 79.On
Figure 3.26-3 Logic of AR ready
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop out (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
3.26.1.3 AR Initiation
AR can be initiated by the tripping signal of line protection or CB state.
1. AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from
internal trip signal or external trip signal.
When AR is ready to reclosing (“79.Ready”=1) and the tripping signal is received, this tripping
signal will be kept in the device, and AR will be initiated after the tripping signal drops out. The
tripping signal kept in the device will be cleared after the completion of AR sequence (Reset
Command). Its logic is shown as below.
SIG Reset Command &

>=1
SIG Trip Signal
& AR Initiation
SIG 79.Ready
Figure 3.26-4 Tripping initiating AR

Date: 2019-04-24
2. AR initiated by CB state
AR can be initiated by CB state by setting the setting [79.En_CBInit]. Under normal conditions,
when AR is ready to reclose (“79.Ready”=1), AR will be initiated if circuit breaker is open and
corresponding phase current is nil. AR initiated by CB state logic is shown as below. Usually
normally closed contact of circuit breaker is used to reflect CB state.
SIG CB open
&
EN [79.En_CBInit] & AR Initiation
SIG 79.Ready
3
Figure 3.26-5 CB state initiating AR
3.26.1.4 AR Reclosing
When the dead time delay of AR expires after AR is initiated, if the synchronism check is enabled,
the release of reclosing signal shall be subject to the result of synchronism check.
After the dead time delay of AR expires, if the synchronism check is still unsuccessful within the
time delay [79.t_wait_Chk], the signal of synchronism check failure ("79.Fail_Chk") will be output
and the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of synchronism
check success ("25.RSYN_OK") will always be established. And the signal of synchronism check
success ("25.RSYN_OK") from the synchronism check logic can be applied by AR inside the
device or outside the device.
[79.t_Dd_3PS1] 0 & AR Pulse

If 79.Inhibit_AR operates,
SIG 79.Inhibit_AR then circuit of time delay
will be interrupted. >=1
& [79.t_Wait_Chk] 0 79.Fail_Chk
SIG 3-pole AR Initiation
SIG 79.Ok_Chk
Figure 3.26-6 One-shot AR
Reclosing pulse length may be set through the setting [79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, the setting [79.En_CutPulse] is available to control the reclosing
pulse. When this function is enabled, if the device operates to trip during reclosing, the reclosing
pulse will drop out immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing
signal is issued, AR will drop out with time delay [79.t_Reclaim], and can carry out next reclosing.
The reclaim timer is started when the CB closing signal is given. The reclaim timer defines a time
from the issue of the reclosing command, after which the reclosing function resets. Should a new
trip occur during this time, it is treated as a continuation of the first fault.

Date: 2019-04-24
SIG AR Pulse 0ms [79.t_PW_AR]
&
SIG Three- phase Trip 79.AR_Out
&
EN [ 79.En _ CutPulse]
>=1
&
79.AR_Out [79.t_ Reclaim] 0ms Reset Command
3
SIG
Figure 3.26-7 Reclosing output logic
3.26.1.5 Reclosing Failure and Success
For line fault, the fault will be cleared after the device operates to trip. When the following cases
appear, the reclosing is unsuccessful.
1. If any protection element operates to trip when AR is enabled ("79.On"=1) and AR is not
ready ("79.Ready"=0), the device will output the signal "79.Failed".
2. For one-shot AR, if the tripping signal is received again within reclaim time after the reclosing
pulse is issued, the reclosing shall be considered as unsuccessful.
3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping signal is received again after the last reclosing pulse is issued, the reclosing shall be
considered as unsuccessful.
4. The setting [79.En_FailCheck] is available to judge whether the reclosing is successful by CB

state, when it is set as “Enabled”. If CB is still in open position with a time delay [79.t_Fail]
after the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this
case, the device will issue a signal "79.Failed" to indicate that the reclosing is unsuccessful,
and this signal will drop out after (Reset Command). AR will be blocked if the reclosing shall
be considered as unsuccessful.
After unsuccessful AR is confirmed, AR will be blocked.

Date: 2019-04-24
SIG 79.On
&
SIG 79.Ready
SIG Any tripping command

& >=1
0 100ms
>=1
SIG Last shot is made 79.Failed
79.Inprog
SIG
&
SIG 79.AR_Blkd
>=1 3
SIG AR Pulse &
[79.t_Fail ] 0
&
SIG CB closed
EN [79.En_ FailCheck ]
&
79.Succeeded
&
0 [79.t_Fail ]
0s 2s 79.Completed
Figure 3.26-8 Reclosing failure and success
3.26.1.6 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.Num], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
 [79.Num]=1
It means one-shot reclosing. Line protection device will operate to trip when a transient fault
occurs on the line and AR will be initiated. After the dead time delay for AR is expired, the device
will send reclosing pulse, and then AR will drop out after the time delay [79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and the device will output the signal of reclosing failure "79.Failed".
 [79.Num]>1
It means multi-shot reclosing. For multi-shot reclosing, line protection device will operate to trip
when a transient fault occurs on the line and AR will be initiated. After the dead time delay of the
first reclosing is expired, the device will send reclosing pulse, and then AR will drop out after the
time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will
operate to trip again after the reclosing is performed, and then AR is initiated after the tripping
contact drops off. After the time delay for AR is expired, the device will send reclosing pulse. The
sequence is repeated until the reclosing is successful or the maximum permit reclosing number
[79.Num] is reached.
3.26.1.7 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and

Date: 2019-04-24
permanent fault respectively.
Signal
Fault
Trip
CB 52b
3 79.t_Reclaim
Open [79.t_Reclaim]
79.Active
79.Inprog [79.t_Dd_3PS1]
79.Inprog_3P [79.t_Dd_3PS1]
79.Ok_Chk
AR Out [79.t_PW_AR]
79.Perm_Trp3P
79.Failed
Time
Figure 3.26-9 Transient fault

Date: 2019-04-24
Signal
Fault
Trip
Open Open
52b
[79.t_Reclaim]
79.t_Reclaim
79.Active
79.Inprog 3
79.Inprog_3P1 [79.t_Dd_3PS1]
79.Inprog_3PS2 [79.t_Dd_3PS2]
79.Ok_Chk
AR Out [79.t_PW_AR] [79.t_PW_AR]
79.Perm_Trp3P
79.Failed 200ms
Time
Figure 3.26-10 Permanent fault ([79.Num]=2)

Date: 2019-04-24
79
79. Enable 79.On
79.Block 79.Off
79.Trp3P 79. Close
79. Lockout 79. Ready
79.CB_ Healthy 79.AR_Blkd
3 79.Clr_ Counter 79. Active
79. Inprog
79. Inprog_3P
79.Inprog _ 3PS1
79.Inprog _ 3PS2
79.Inprog _ 3PS3
79.Inprog _ 3PS4
79. Rcls_ Status
79.Failed
79.Succeeded
79.Completed
79.Fail_Chk
3.26.3 I/O Signals

Table 3.26-1 Input/Output signals of AR

Input signal of enabling AR, it is triggered from binary input or programmable logic
1 79.Enable
etc.
Input signal of blocking AR, it is triggered from binary input or programmable logic
2 79.Block
etc.
3 79.Trp3P Input signal of three-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the operating
4 79.Lockout signals of definite-time protection, transformer protection and busbar differential
protection, etc.
The input for indicating whether circuit breaker has enough energy to perform the
5 79.CB_Healthy
close function
6 79.Clr_Counter Clear the reclosing counter

Date: 2019-04-24
1 79.On AR is enabled.
2 79.Off AR is disabled.
3 79.Close AR operates.
4 79.Ready AR have been ready for reclosing cycle.
5 79.AR_Blkd AR is blocked.
6 79.Active AR logic is active.
7 79.Inprog AR cycle is in progress
8 79.Inprog_3P 3-pole AR cycle is in progress
9 79.Inprog_3PS1 First 3-pole AR cycle is in progress
10 79.Inprog_3PS2 Second 3-pole AR cycle is in progress
11 79.Inprog_3PS3 Third 3-pole AR cycle is in progress 3
12 79.Inprog_3PS4 Fourth 3-pole AR cycle is in progress
AR status
0: AR is preprocessed
13 79.Status 1: AR is ready.
2: AR is in progress.
3: AR is successful.
14 79.Failed Auto-reclosing fails
15 79.Succeeded Auto-reclosing is successful
16 79.Fail_Chk Synchrocheck for AR fails
17 79.Completed AR is completed.
3.26.4 Settings
 Access path:
MainMenu  Settings  Protection Settings  AR Settings
Table 3.26-2 Settings of AR
Default
value
Maximum number of reclosing
1 79.Num 1~4 1 - 1
attempts
Dead time of first shot 3-pole
2 79.t_Dd_3PS1 0~600 0.600 s 0.001
reclosing
Dead time of second shot 3-pole
3 79.t_Dd_3PS2 0~600 0.600 s 0.001
reclosing
Dead time of third shot 3-pole
4 79.t_Dd_3PS3 0~600 0.600 s 0.001
reclosing
Dead time of fourth shot 3-pole
5 79.t_Dd_3PS4 0~600 0.600 s 0.001
reclosing
Time delay of circuit breaker in
6 79.t_CBClsd 0~600 5.000 s 0.001
closed position before reclosing

Date: 2019-04-24
Default
value
Time delay to wait for CB healthy,
and begin to timing when the input
signal [79.CB_Healthy] is
7 79.t_CBReady 0~600 5.000 s 0.001
de-energized and if it is not
energized within this time delay, AR
will be blocked.
Maximum wait time for synchronism
8 79.t_Wait_Chk 0~600 10.000 s 0.001
check
3 9 79.t_Reclaim 0~600 15.000 s 0.001 Reclaim time of AR
Dropout time delay of blocking AR,

when blocking signal for AR
10 79.t_DDO_BlkAR 0~600 5.000 s 0.001
disappears, AR blocking condition
drops out after this time delay
Time delay of excessive trip signal
11 79.t_PersistTrp 0~600 0.200 s 0.001
to block AR
Time delay allow for CB status
12 79.t_Fail 0~600 0.200 s 0.001 change to conform reclosing
successful
13 79.t_PW_AR 0~600 0.120 s 0.001 Pulse width of AR closing signal
Enabling/disabling confirm whether

Disabled
14 79.En_FailCheck Disabled - - AR is successful by checking CB
Enabled
state
Disabled Enabling/disabling adjust the length
15 79.En_CutPulse Disabled - -
Enabled of reclosing pulse
Disabled
16 79.En Enabled - - Enabling/disabling auto-reclosing
Enabled
Enabling/disabling AR by external
input signal besides logic setting
Setting [79.En]
17 79.Opt_Enable Setting - -
Setting&Config Setting: only the setting
Setting&Config: the setting and
configuration signal
Disabled Enabling/disabling AR be initiated
18 79.En_CBInit Disabled - -
Enabled by open state of circuit breaker
3.27 VT Circuit Supervision (VTS)

3.27.1 General Application
The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,

Date: 2019-04-24
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
1. Line VT is used as protection VT and the protected line is out of service.
2. Only current protection functions are enabled and VT is not connected to the device.
VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence 3
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detects residual voltage greater than the setting
[VTS.3U0_Set] to determine single-phase or two-phase VT circuit failure, and detect three times
positive-sequence voltage less than the setting [VTS.U1_Set] to determine three-phase VT circuit
failure. Upon detecting abnormality on VT circuit, an alarm will comes up after a time delay of
[VTS.t_DPU] and drop off with a time delay of [VTS.t_DDO] after VT circuit restored to normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay. If the
auxiliary contact is not connected to the device, VT circuit supervision will be issued with time
delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm will be not issued if the system setting
[En_VT] is set as "Disabled". However, the alarm is still issued if the binary input [VTS.MCB_VT]
is energized, no matter that the logic setting [En_VT] is set as “Enabled” or “Disabled”.
3.27.3 Function Block
VTS
VTS.Enable VTS.Alm
VTS.Block VTS.InstAlm
VTS.MCB_VT
3.27.4 I/O Signals

Table 3.27-1 Input/output signals of VT circuit supervision

VT circuit supervision enabling input, it is triggered from binary input or programmable
1 VTS.Enable
logic etc.

Date: 2019-04-24
VT circuit supervision blocking input, it is triggered from binary input or programmable

2 VTS.Block
logic etc.
3 VTS.MCB_VT Binary input for VT MCB auxiliary contact
1 VTS.Alm Alarm signal to indicate VT circuit fails
2 VTS.InstAlm VT circuit failure instantaneous alarm signal
3.27.5 Logic
&
3 SIG FD.Pkp
SET 3U0>[VTS.3U0_Set]
>=1
SET U1<[VTS.U1_Set] &
>=1 If "FD.Pkp" operates, the circuit of time
SET [VTS.Opt_VT]=Bay & delay will be interrupted.
[VTS.t_DPU] [VTS.t_DDO]
SIG 52b (Three phases) >=1
&
SIG Ip > 0.04In
>=1
BI Prot.BI_En_VT >=1
VTS.Alm
EN [En_VT]
SIG VTS.MCB_VT &
EN [VTS.En]
&
SIG VTS.Enable
SIG VTS.Block
Figure 3.27-1 VT circuit supervision logic diagram
If fault detector element operates or automatic reclosing cycle is in progress, and VT circuit failure
signal have been detected, then the VT circuit failure signal will be maintained, only when the fault
detector element and automatic reclosing element are all drop-off, VT circuit supervision will
return to normal operation.
3.27.6 Settings
 Access path:
MainMenu  Settings  Global Settings  Superv Settings
Table 3.27-2 Settings of VT circuit supervision
No. Setting Default Range Step Unit Description

Disabled or Logic setting for alarm function of
1 VTS.En Enabled
Enabled VT circuit supervision
Delay pickup setting for the alarm of
2 VTS.t_DPU 1.500 0.000~30.000 0.001 s
VT circuit supervision
Delay drop off setting for the alarm
3 VTS.t_DDO 10.000 0.000~30.000 0.001 s
of VT circuit supervision
Positive-sequence voltage
4 VTS.U1_Set 30.00 0~100 0.01 V
threshold for VT circuit supervision
5 VTS.3U0_Set 8.00 0~100 0.01 V Zero-sequence voltage (calculated)

Date: 2019-04-24

threshold for VT circuit supervision
Negative-sequence voltage setting
6 VTS.U2_Set 8.00 0~100 0.01 V
of VT circuit supervision function.
3.28 CT Circuit Supervision (CTS)

The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.
When CT secondary circuit is abnormal, the current acquired by the device is not accurate, which
will affect protection functions related to the current. Therefore, it is necessary to monitor the CT
abnormal condition. When CT abnormality is detected, the device shall issue an alarm signal and
block the relevant protection functions. 3
Under normal conditions, CT secondary signal is continuously supervised by detecting the
residual current and voltage. If residual current is larger than [CTS.3I0_Set] whereas residual
voltage is less than [CTS.3U0_Set], and any phase current is less than 0.06In, CT circuit failure is
considered. The concerned protection functions are blocked and an alarm is issued with a time
delay of [CTS.t_DPU] and drop off with a time delay of [CTS.t_DDO] after CT circuit is restored to
normal condition.
CTS
CTS.Enable CTS.On
CTS.Block CTS.Blocked
CTS.Valid
CTS.Alm
3.28.3 I/O Signals

Table 3.28-1 Input/output signals of CT circuit supervision

CT circuit supervision enabling input, it is triggered from binary input or
1 CTS.Enable
CT circuit supervision blocking input, it is triggered from binary input or
2 CTS.Block
1 CTS.Alm Alarm signal to indicate CT circuit fails
2 CTS.On CT circuit supervision is enabled.
3 CTS.Blocked CT circuit supervision is blocked.
4 CTS.Valid CT circuit supervision is valid.

Date: 2019-04-24
3.28.4 Logics
EN [CTS.En] &
CTS.On
SIG CTS.Enable
&
SIG CTS.Block >=1 CTS.Blocked
SIG Fail_Device
&
CTS.Valid
3 SIG CTS.Valid &

[CTS.t_DPU] [CTS.t_DDO] CTS.Alm
SET 3I0>[CTS.3I0_Set]
&
SET 3U0<[CTS.3U0_Set]
SIG IA<0.06In
>=1
SIG IB<0.06In
SIG IC<0.06In
Figure 3.28-1 Logic of CT circuit failure
3.28.5 Settings
 Access path:
Table 3.28-2 Settings of CT circuit supervision
Default
No. Settings Range Unit Step Remark
value
The calculated residual
1 CTS.3I0_Set 0.00~200.00 0.1 A 0.001 current setting of CT circuit
supervision function.
The calculated residual
2 CTS.3U0_Set 0.00~200.00 30 V 0.001 voltage setting of CT circuit
supervision function.
Delay pick-up time setting
3 CTS.t_DPU 0.000~100.000 1.25 s 0.001
for CT circuit failure
Delay drop-off time setting
4 CTS.t_DPO 0.000~100.000 10 s 0.001
for CT circuit failure
Disabled Enabling/disabling CT circuit
5 CTS.En Disabled - -
Enabled supervision function.

Date: 2019-04-24
4 Control Functions
4 Control Functions
Table of Contents
4.1 Switchgear Control .......................................................................................... 4-1

4.1.1 Functional Description .......................................................................................................... 4-1
4.1.2 Operation Theory.................................................................................................................. 4-2
4.1.4 I/O Signals ............................................................................................................................ 4-5
4.1.5 Logics ................................................................................................................................... 4-6

4
4.1.6 Settings ................................................................................................................................. 4-7
4.2 Manual Closing Synchronism Check ............................................................. 4-8

4.2.1 Operation Theory.................................................................................................................. 4-8
4.2.3 I/O Signals .......................................................................................................................... 4-10
4.2.4 Logics ................................................................................................................................. 4-12
4.2.5 Settings ............................................................................................................................... 4-13
4.3 Voltage Selection ........................................................................................... 4-14

4.3.1 Functional Description ........................................................................................................ 4-15
4.3.3 I/O Signals .......................................................................................................................... 4-18
4.3.4 Logics ................................................................................................................................. 4-19
4.3.5 Settings ............................................................................................................................... 4-21
List of Figures
Figure 4.1-1 Logic diagram of switchgear control ................................................................... 4-2
Figure 4.1-2 DPS synthesis logic ............................................................................................... 4-6
Figure 4.1-3 DPS alarm logic ...................................................................................................... 4-6
Figure 4.1-4 Interlocking logic ................................................................................................... 4-6
Figure 4.1-5 Manual control logic .............................................................................................. 4-7
Figure 4.2-1 Relationship between reference and synchronous voltages ........................... 4-9

Date: 2019-04-24
4 Control Functions
Figure 4.2-2 Synchro-check logic ............................................................................................ 4-12
Figure 4.2-3 Dead charge check logic ..................................................................................... 4-12
Figure 4.3-1 Voltage connection for double busbars 1 ......................................................... 4-15
Figure 4.3-2 Voltage connection for double busbars 2 ......................................................... 4-16
Figure 4.3-2 Voltage connection for one-and-half breakers arrangement .......................... 4-17
Figure 4.3-3 Voltage selection for double busbar arrangement ........................................... 4-19
Figure 4.3-4 Voltage selection for 3/2 breakers arrangement (closing a bus CB) ............. 4-20
Figure 4.3-5 Voltage selection for 3/2 breakers arrangement (closing the tie CB) ............ 4-21
List of Tables
4
Table 4.1-1 Remote/Local control mode switch logic.............................................................. 4-3
Table 4.1-2 Input/Output signals of control function ............................................................... 4-5
Table 4.1-3 Settings of control function .................................................................................... 4-7
Table 4.2-1 Input signals of manual closing synchronism check ........................................ 4-10
Table 4.2-2 Output signals of manual closing synchronism check ..................................... 4-11
Table 4.2-3 Settings of synchronism check ........................................................................... 4-13
Table 4.3-1 Input signals of voltage selection ........................................................................ 4-18
Table 4.3-2 Output signals of voltage selection ..................................................................... 4-19
Table 4.3-3 Settings of voltage selection ................................................................................ 4-21

Date: 2019-04-24
4 Control Functions
4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be
divided into remote control and local control according to the control source location. A remote
control mainly refers to remote control commands from substation automation system (SAS) or
network control center (NCC). However, a control triggered manually from the device LCD, by a
terminal contact or by a panel handle is a local control. The switchgear control function is closely
related to interlocking, double point status (DPS), remote/local control mode switching and
tripping statistics.
4.1.1 Functional Description
A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure 4
that the control operation can be safely and reliably implemented. In addition, the device has a
hardware self-checking and blocking function to prevent hardware damage from mal-operation
output.
When the device is in the remote-control mode, the control command may be sent via the IEC
60870-5-103 or IEC 61850 protocol; when it is in the local control mode, the local operation may
be performed on the device LCD or panel handle.
A complete control process is:
1. Protocol module sends a selection command;
2. Control module responds the success or failure result of selection;
3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;
4. Control module responds the success or failure result of execution;
5. The control operation may be open/close or up/down/stop.
When the device is in the maintenance status, it can still respond to local control commands.
The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.
This device supports the following functional control module:
Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated

Date: 2019-04-24
4 Control Functions
Module Description
XSWI Synthesis of DS/ES position
SXCBR/SCSWI Trip statistics of CB/DS/ES
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
4.1.2 Operation Theory
The initiation of a control command may be sent to the device by the SCADA or the NCC through
protocol IEC 60870-5-103 or IEC 61850. It may also be the operation of the device LCD or the
manual triggering through configured signal. The command is sent by the CPU to the control
module for processing, and a control record is made on the CPU module according to the control
result.
4
SCADA/NCC IEC 60870-5-103
CPU
CSWI BO
IEC 61850
Control
Record
Local LCD
BI contact
Figure 4.1-1 Logic diagram of switchgear control
4.1.2.1 Remote/Local Control Mode Switch
Since the source of a control command may be SAS or NCC, or may be triggered by the device
LCD or terminal contact, it is necessary to provide a remote/local control mode switch function.
The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module
determines the current control authority to be remote or local according to the input value. By
default, if the input is not configured, any control operation is blocked.

Date: 2019-04-24
4 Control Functions
Table 4.1-1 Remote/Local control mode switch logic
in_Remote in_Local Remote Control Local Control

NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable
4.1.2.2 Double Point Status
A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
4
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".
DPS Bit0 = 0 Bit0 = 1

Bit1 = 0 DPS_INT DPS_OFF
Bit1 = 1 DPS_ON DPS_BAD
The unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated
positions, while the XSWI is used DS or ES position synthesis.
4.1.2.3 Trip Statistics
The trip statistics function takes the opening position as input count the trip times. For CB, this
device supports general trip statistics. The tripping statistics function is triggered by DPS change.
The statistics result is stored in non-volatile memory for power-off holding.
Use the clear command from the menu in local LCD or customized binary signal to reset the trip
statistics.
4.1.2.4 Interlocking
The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.
The interlocking function is very important for the control operation of switchgears. During the

Date: 2019-04-24
4 Control Functions
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could
judge the interlocking logic depending on the message within the command; for local control
through device LCD or terminal contact, please use the corresponding logic setting to
enable/disable the interlocking function.
4.1.2.5 Manual Control
The switchgear control function supports manual control function that can be configured with a
terminal contact or binary signal to trigger the control operation.
The manual control function supports the control input configuration of selection and open/close.
When the control object selection input is configured, the signal "1" indicates that the current
control object has to be selected before a control operation; if the control object selection input is
not configured, the control command can be directly issued without judgment of selection.
4 4.1.2.6 Direct Control
For applications such as signal reset and function enable/disable, the control mode is generally
direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.
The direct control function provides remote/local switch and interlocking configurations. The
control command is usually issued directly by the SAS. It also supports the command triggered by
binary signal.
CSWI：XCBR CSWI：XSWI
in_Remote in_Remote
in_Local in_Local
in_Pos_NO
in_Pos_NO
in_Pos_NC
in_Pos_NC
in_N_Trp
in_N_Trp
in_Rsyn
in_EnaOpn in_EnaOpn
in_EnaCls in_EnaCls
in_CILO_Bypass in_CILO_Bypass
in_Manual_Sel in_Manual_Sel
in_Manual_Opn
in_Manual_Opn
in_Manual_Cls
in_Manual_Cls

Date: 2019-04-24
4 Control Functions
4.1.4 I/O Signals

Table 4.1-2 Input/Output signals of control function

1 CSWI**.in_Remote Remote control mode
2 CSWI**.in_Local Local control mode
3 CSWI**.in_Pos_NO Normally opened contact input for DPS opening position
4 CSWI**.in_Pos_NC Normally closed contact input for DPS closing position
5 CSWI**.in_N_Trp Opening command for trip counter
6 CSWI**.in_Rsyn Pointer of synchronism check element (only valid in CB control)
7 CSWI**.in_EnaOpn Opening permission for interlocking
8 CSWI**.in_EnaCls Closing permission for interlocking
9 CSWI**.in_CILO_Bypass Bypass for interlocking
10 CSWI**.in_Manual_Sel Selection for manual control
11 CSWI**.in_Manual_Opn Opening for manual control 4
12 CSWI**.in_Manual_Cls Closing for manual control
1 CSWI**.Opn_Sel Opening selection
2 CSWI**.Cls_Sel Closing selection
3 CSWI**.Opn_Exec Opening operation
4 CSWI**.Cls_Exec Closing operation
5 CSWI**.Opn_Enabled Permission of opening operation
6 CSWI**.Cls_Enabled Permission of closing operation
7 CSWI**.Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
8 CSWI**.DPS Synthetic DPS for switchgear position
9 CSWI**.N_Trp Tripping statistics
10 CSWI**.DPS.Alm Alarm signal when DPS status is BAD or INT
11 CSWI**.Cmd_ManSel Selection command for manual control
12 CSWI**.Cmd_ManOpn Opening command for manual control
13 CSWI**.Cmd_ManCls Closing command for manual control
In above table, CSWI** can be “Breaker” or “Switch 01”~“Switch 09”.

Date: 2019-04-24
4 Control Functions
4.1.5 Logics
SIG DPS_A = OFF

≥1
DPS = OFF
SIG DPS_B = OFF
SIG DPS_C = OFF
SIG DPS_A = ON
&
DPS = ON
SIG DPS_B = ON
SIG DPS_C = ON
SIG DPS_A = INT

≥1
DPS = INT
SIG DPS_B = INT
SIG DPS_C = INT
SIG DPS_A = BAD

≥1
4 SIG DPS_B = BAD

DPS = BAD
SIG DPS_C = BAD
Figure 4.1-2 DPS synthesis logic
SIG CSWI**.DPS = BAD >=1
SIG CSWI**.DPS = INT & CSWI**.Alm_DPS

[CSWI**.DPS.t_Alm] 0ms
SET [CSWI**.DPS.En_Alm]
Figure 4.1-3 DPS alarm logic
Remote command from

SIG
SAS/NCC with "Interlocking" flag
≥1 CSWI** interlocking
Local command from device function activated
SIG
LCD with "InterlockChk"
≥1
&
Contact triggered manual
SIG
opening/closing operation
EN [CSWI**.En_Opn_Blk] ≥1
EN [CSWI**.En_Cls_Blk]
Figure 4.1-4 Interlocking logic

Date: 2019-04-24
4 Control Functions
SIG in_Manual_Sel not configurated &
SIG in_Manual_Opn=1
≥1
SIG in_Manual_Sel =1 &
SIG in_Manual_Opn=1
& Opn_Exec_Man
SIG Opn_Enabled =1
SIG Control mode is Local
SIG in_Manual_Sel not configurated &
SIG in_Manual_Cls=1
≥1
&
4
SIG in_Manual_Sel =1
SIG in_Manual_Cls=1
& Cls_Exec_Man
SIG Cls_Enabled =1
SIG Control mode is Local
Figure 4.1-5 Manual control logic
In above figures, CSWI** can be “Breaker” or “Switch 01”~“Switch 09”.
4.1.6 Settings
Table 4.1-3 Settings of control function

Delay Pick Up (DPU) time, i.e.
1 Breaker.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of the circuit
breaker
Disabled or Logic setting for DPS alarm of the
2 Breaker.DPS.En_Alm Disabled
Enabled circuit breaker
Operation time delay of DPS alarm of
3 Breaker.DPS.t_Alm 500 0~60000 1 ms
the circuit breaker
4 Switch**.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of switch**
(**=01~09)
5 Switch**.DPS.En_Alm Disabled
Enabled circuit breaker of switch** (**=01~09)
6 Switch**.DPS.t_Alm 500 0~60000 1 ms the circuit breaker of switch**
(**=01~09)

Date: 2019-04-24
4 Control Functions

Pulse Width (PW), i.e. holding time,
7 Breaker.t_PW_Opn 500 0~60000 1 ms for opening output of the circuit
breaker
8 Breaker.t_PW_Cls 500 0~60000 1 ms for closing output of the circuit
breaker
9 Switch**.t_PW_Opn 500 0~60000 1 ms for direct opening output of switch**
(**=01~09)
10 Switch**.t_PW_Cls 500 0~60000 1 ms for direct closing output of switch**
(**=01~09)
Logic setting for interlocking logic
4 11 Breaker.En_CILO_Opn Disabled
Disabled
Enabled
or
control of closing output of the circuit
breaker
Disabled or
12 Breaker.En_CILO_Cls Disabled control of opening output of the circuit
Enabled
breaker
Disabled or
13 Switch**.En_CILO_Opn Disabled control of direct closing output of
Enabled
switch** (**=01~09)
Disabled or
14 Switch**.En_CILO_Cls Disabled control of direct opening output of
Enabled
switch** (**=01~09)
4.2 Manual Closing Synchronism Check

The purpose of synchronism check is to ensure two systems are synchronous before they are
going to be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus, closing operation is
applied with the synchronism check to avoid this situation and maintain the system stability. The
synchronism check includes synchro-check and dead charge check.
4.2.1 Operation Theory

4.2.1.1 Synchro-check
The comparative relationship between the reference voltage and the synchronization voltage for
synchro-check is as follow. Furthermore, the measured three-phase voltages for synchro-check
should not exceed the overvoltage threshold [25.U_OV] or lag the undervoltage threshold
[25.U_UV].

Date: 2019-04-24
4 Control Functions
U_Ref
U_Syn
Figure 4.2-1 Relationship between reference and synchronous voltages
This figure shows the characteristics of synchro-check element used for CB closing if both
reference and synchronous sides are live. The element operates if the voltage difference,
frequency difference, slip frequency difference and phase angle difference are all within their 4
setting ranges.
 The difference between the reference voltage and the synchronization voltage is checked by
the following equation
|U_Ref- U_Syn| ≥ [25.U_Diff]
 The frequency difference between the reference side and the synchronization side is
checked by the following equation
|f(U_Ref)-f(U_Syn)| ≤ [25.f_Diff]
 The slip frequency difference is checked by the following equation
df/dt ≤ [25.df/dt]
 The phase difference between the reference voltage and the synchronization voltage is
checked by the following equation
∆δ ≤ [25.phi_Diff]
4.2.1.2 Dead Charge Check
The dead charge check mode checks only the synchro-check voltage. Several dead charge check
modes are supported in using the setting [25.Opt_Mode_DdChk]. The device compares the
reference side and the synchronous side voltages at both sides of circuit breaker with the settings
[25.U_LvChk] and [25.U_DdChk]. When the voltage is higher than [25.U_LvChk], the
corresponding side is regarded as live. When the voltage is lower than [25.U_DdChk], the
corresponding side is regarded as dead.
4.2.1.3 Voltage Input Channel
The synchronism check function is suitable for several applications. According to different
applications, user needs to configure different voltage input channel. For both the reference side
and the synchronous side, the voltage input channel may be single phase or three-phase.

Date: 2019-04-24
4 Control Functions
While configuring through the PCS-Studio software, user can configure three phase or single
phase voltage channel for reference and synchronization inputs.
In the meantime, the voltage selection logic can be adopted for the synchronism check input
channel, please refer to the following section.
For synchronism check voltage input channel configuration, please MAKE

SURE that the voltage source to connect to the inputs "in_ref" and
"in_syn" should be the same with that used in measurement function,
such as BayMMXU and UMMXN. Otherwise, the alarm "25.Alm_Cfg_Ch"
will be issued.

4
RSYN
in_ref_A
in_ref_B
in_ref_C
in_syn_A
in_syn_B
in_syn_C
in_25_Blk
in_Dd_Blk
in_Lv_Blk
in_SYN_Blk
in_25_Bypass
in_vol_chk
in_syn_chk
4.2.3 I/O Signals

Table 4.2-1 Input signals of manual closing synchronism check

1 in_ref_A Reference voltage channel (phase A or single phase)
2 in_ref_B Reference voltage channel (phase B)
3 in_ref_C Reference voltage channel (phase C)
4 in_syn_A Synchronization voltage channel (phase A or single phase)
5 in_syn_B Synchronization voltage channel (phase B)
6 in_syn_C Synchronization voltage channel (phase C)
7 in_25_Blk Signal to block synchronism check logic
8 in_Dd_Blk Signal to block dead charge logic
9 in_Lv_Blk Signal to block live check logic
10 in_SYN_Blk Signal to block synchro-check logic

Date: 2019-04-24
4 Control Functions

11 in_25_Bypass Signal to temporarily bypass synchronism check logic
12 in_syn_chk Activate synchro-check (valid only if the setting [25.Opt_ValidMode] = Config)
13 in_Vol_chk Activate dead charge check (valid only if the setting [25.Opt_ValidMode] = Config)
Table 4.2-2 Output signals of manual closing synchronism check

1 U_Diff Voltage difference
2 phi_DIff Phase angle difference
3 f_diff Frequency difference
4 df/dt Frequency rate-of-change
5 25.SynChk_OK Satisfaction of synchro-check logic
6 25.DdChk_OK Satisfaction of dead charge check logic
7 25.RSYN_OK Satisfaction of synchronism check logic, i.e. SynChk_OK or DdChk_OK
8 25.U_Diff_OK Voltage difference within setting range 4
9 25.f_Diff_OK Frequency difference within setting range
10 25.df/dt_OK Frequency variation difference within setting range
11 25.phi_Diff_OK Phase difference within setting range
12 25.RefDd The reference side is dead.
13 25.RefLv The reference side is live.
14 25.SynDd The synchronous side is dead.
15 25.SynLv The synchronous side is live.

Date: 2019-04-24
4 Control Functions
4.2.4 Logics
SIG in_2 5_Blk

SIG in_S YN_Blk
SET df/d t ≤ [25.df/d t]
≥1
SET [25.En_df/dtChk] = Disabled
SET ΔU ≤ [25.U_ Diff]
SET Δf ≤ [25.f_Di ff]
≥1
SET [25.En_fDiffChk] = Disabl ed
SET Δδ ≤ [25.phi_Diff] & 25.SynChk_OK
SET U_Ref ≤ [25.U_UV]
SET U_Ref ≥ [25.U_OV]
≥1
SET U_Syn ≤ [25.U_UV]
SET U_Syn ≥ [25.U_OV]
SET f_Ref ≤ [25.f_UV]

SET f_Ref ≥ [25.f_OV]
≥1
4 SET
SET
f_Syn ≤ [25.f_UV]
f_Syn ≥ [25.f_OV]
SIG 25.SynChk_OK
SIG Cmd with synchro-check
SET [25.Opt_Valid Mo de] = Se tting & SynChk Success
&
EN [25.En_ Syn Ch k] ≥1
≥1
SET [25.Opt_Valid Mo de] = Config
&
SIG in_S yn _Ch k
&
SIG Cmd without synchro-check
Figure 4.2-2 Synchro-check logic
SIG in_2 5_Blk

SIG in_Dd_ Blk
SIG in_L v_ Blk
SET Valu e.[25.Opt_Mode _Dd Ch k] & 25.DdChk_OK
SET U_Ref ≤ [25.U_DdChk] Dead

check
SET U_Syn ≤ [25.U_DdChk] crite ria
selectio n
SET U_Ref ≥ [25.U_LvChk]
SET U_Syn ≥ [25.U_LvChk]
SIG Cmd with d ead charge check
SIG Cmd with d ead charge check DdChk Success

&
SET [25.Opt_Valid Mo de] = Se tting
& ≥1
EN [25.En_DdChk]
≥1
SET [25.Opt_Valid Mo de] = Config
&
SIG in_Dd_ Ch k
&
SIG Cmd without d ead ch arge check
Figure 4.2-3 Dead charge check logic

Date: 2019-04-24
4 Control Functions
4.2.5 Settings
Table 4.2-3 Settings of synchronism check

Selection of decision
1 25.Opt_ValidMode Setting Setting or Config - - mode for synchronism
check
Logic setting for
synchro-check (valid
2 25.En_SynChk Enabled Disabled or Enabled - - only if the setting
[25.Opt_ValidMode] =
Setting)
Logic setting for dead
charge check (valid
3 25.En_DdChk Enabled Disabled or Enabled - - only if the setting 4
Setting)
Percentage threshold
4 25.U_UV 80.00 0~100 0.01 % of under voltage for
CB closing blocking
5 25.U_OV 170.00 100~170 0.01 % of over voltage for CB
closing blocking
6 25.f_UF 45.000 45~65 0.001 Hz of under frequency for
CB closing blocking
7 25.f_OF 65.000 45~65 0.001 Hz of over frequency for
CB closing blocking
Selection of voltage
8 25.Opt_U_SynChk Ua Ua, Ub, Uc, Uab, Ubc, Uca - -
for synchronism check
Threshold of voltage
9 25.U_Diff_Set 10.00 0~100 0.01 V difference for
synchronism check
Logic setting for
10 25.En_f_Diff_Chk Enabled Disabled or Enabled - - frequency difference
check
Threshold of
11 25.f_Diff_Set 0.50 0~2 0.01 Hz frequency difference
Logic setting for
12 25.En_df/dt_Chk Enabled Disabled or Enabled - - frequency variation
difference check
13 25.df/dt_Set 1.00 0~2 0.01 Hz/s Threshold of

Date: 2019-04-24
4 Control Functions

frequency variation for
synchronism check.
Threshold of phase
14 25.phi_Diff_Set 15.00 0~180 0.01 ° difference for
synchronism check
Compensation angle
15 25.phi_Comp 0.00 0~360 0.01 ° of phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead
16 25.Opt_Mode_DdChk AnySideDd RefDd - -
charge check mode
SynDd
4 SynLvRefDd/SynDdRefLv
AnySideDd
Threshold for voltage
17 25.U_DdChk 17.32 0~100 0.01 V
dead check
18 25.U_LvChk 34.64 0~100 0.01 V
live check
Threshold of duration
19 25.t_Reset 5 0~60 1 s
for synchro-check
Circuit breaker closing
time. It is the time
from receiving closing
20 25.t_Close_CB 20 0~2000 1 ms
command pulse till the
CB is completely
closed.
 25.Opt_Mode_DdChk
No. Setting Value Dead charge check mode
1 SynDdRefDd Dead check for both the reference and the synchronization sides
2 SynLvRefDd Live check for synchronization side and dead check for reference side
3 SynDdRefLv Dead check for synchronization side and live check for reference side
4 RefDd Dead check for reference side
5 SynDd Dead check for synchronization side
6 SynLvRefDd/SynDdRefLv Option 2 or 3
7 AnySideDd Option 1, 2 or 3
4.3 Voltage Selection

The voltage selection function can be used to switch the reference and synchronization voltages
for the synchronism check function in double busbars and one-and-half circuit breakers scenarios,

Date: 2019-04-24
4 Control Functions
or to switch three-phase voltages among double busbars used by protection calculations or

measurements. The "Near priority" principle is adopted by default, and the user interface for
programmable switching logic is also reserved.
4.3.1 Functional Description
The voltage selection module is used in the following scenarios:
 For double busbars, selection of appropriate voltage signals from Bus1 and Bus2 for
synchronizing are required. Line VT signal is taken as reference to check synchronizing with
the voltage after voltage selection function. Selection approach is as follows.
Bus2
Bus1
DS1 DS2
4
UB1
UB2
DS1.DPS
CB
DS2.DPS
 Ua
UL1 Ub
Line
Uc
Figure 4.3-1 Voltage connection for double busbars 1
 For double busbars, three-phases voltages from Bus1 VT and Bus2 VT via switching is used
for protection calculations or measurements and meanwhile used as reference side of
synchronism check. Single-phase voltage from line VT is used as synchronizing side of
synchronism check. Selection approach is as follows.

Date: 2019-04-24
4 Control Functions
Bus2
Bus1
DS1 DS2
Ua
UB1 Ub
Uc
Ua
UB2 Ub
Uc
CB
DS1.DPS
DS2.DPS
4
UL1
Line
Figure 4.3-2 Voltage connection for double busbars 2
 For one-and-half breakers arrangement, selection of appropriate voltage signals among

Line1 VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1
voltage signal for closing breaker at Bus 1 side.

Date: 2019-04-24
4 Control Functions
Bus1
UB1
Bus1_CB.DPS Bus1_CB
Line 1
 Ua
UL1 Ub
Uc DS1
DS1.DPS
Tie_CB.DPS Tie_CB
Line 2
UL2 4
DS2.DPS
DS2
Bus2_CB.DPS Bus2_CB
UB2
Bus2
Figure 4.3-3 Voltage connection for one-and-half breakers arrangement

Date: 2019-04-24
4 Control Functions
VolSwitch
in_UB1_A_Chn Ref_Chn_A
in_UB1_B_Chn Ref_Chn_B
in_UB1_C_Chn Ref_Chn_C
in_UB2_A_Chn Syn_Chn_A
Syn_Chn_B
in_UB2_B_Chn
Syn_Chn_C
in_UB2_C_Chn
in_UL1_A_Chn
in_UL1_B_Chn
in_UL1_C_Chn
in_UL2_A_Chn
4 in_UL2_B_Chn
in_UL2_C_Chn
in_Bus1_CB
in_Tie_CB
in_Bus2_CB
in_DS1
in_DS2
4.3.3 I/O Signals

Table 4.3-1 Input signals of voltage selection

1 in_UB1_A_Chn Voltage input for Bus1 (phase A)
2 in_UB1_B_Chn Voltage input for Bus1 (phase B)
3 in_UB1_C_Chn Voltage input for Bus1 (phase C)
4 in_UB2_A_Chn Voltage input for Bus2 (phase A)
5 in_UB2_B_Chn Voltage input for Bus2 (phase B)
6 in_UB2_C_Chn Voltage input for Bus2 (phase C)
7 in_UL1_A_Chn Voltage input for Line1 (phase A)
8 in_UL1_B_Chn Voltage input for Line1 (phase B)
9 in_UL1_C_Chn Voltage input for Line1 (phase C)
10 in_UL2_A_Chn Voltage input for Line2 (phase A)
11 in_UL2_B_Chn Voltage input for Line2 (phase B)
12 in_UL2_C_Chn Voltage input for Line2 (phase C)
13 in_Bus1_CB DPS position for the Bus 1 side CB in 3/2 arrangement
14 in_Tie_CB DPS position for the tie CB in 3/2 arrangement
15 in_Bus2_CB DPS position for the Bus 2 side CB in 3/2 arrangement
16 in_DS1 DPS position for the Bus 1 side DS in 3/2 or double busbars arrangement
17 in_DS2 DPS position for the Bus 2 side DS in 3/2 or double busbars arrangement

Date: 2019-04-24
4 Control Functions

18 in_bus1_sel Bus1-selected input for customized programmable voltage selection logic
19 in_bus2_sel Bus2-selected input for customized programmable voltage selection logic
20 in_line1_sel Line1-selected input for customized programmable voltage selection logic
21 in_line2_sel Line2-selected input for customized programmable voltage selection logic
Table 4.3-2 Output signals of voltage selection

1 Ref_Chn_A Reference voltage channel (Phase A)
2 Ref_Chn_B Reference voltage channel (Phase B)
3 Ref_Chn_C Reference voltage channel (Phase C)
4 Syn_Chn_A Synchronization voltage channel (Phase A)
5 Syn_Chn_B Synchronization voltage channel (Phase B)
6 Syn_Chn_C Synchronization voltage channel (Phase C)
4
4.3.4 Logics
SIG DS1.DPS=ON &

UB1_Sel
SIG DS2.DPS=OFF
SIG DS1.DPS=OFF &

UB2_Sel
SIG DS2.DPS=ON
&
Alm_Invalid_Sel
UB1 U_Syn
UB2
Figure 4.3-4 Voltage selection for double busbar arrangement

Date: 2019-04-24
4 Control Functions
SIG DS1.DPS=ON
SIG DS1.DPS=OFF
SIG Bus1_CB.DPS=ON
SIG DS2.DPS=ON
SIG DS2.DPS=OFF
SIG Bus2_CB.DPS=ON
UL1_Sel
&
UL2_Sel
&
UB2_Sel
4 &
Alm_Invalid_Sel
UL1 U_Ref
UL2
UB2
UB1 U_Syn
Figure 4.3-5 Voltage selection for 3/2 breakers arrangement (closing a bus CB)

Date: 2019-04-24
4 Control Functions
SIG DS1.DPS=ON UL1_Sel
SIG DS1.DPS=OFF &

UB1_Sel
SIG Bus1_CB.DPS=ON
UL1 Uref
UB1
SIG DS2.DPS=ON UL2_Sel
SIG DS2.DPS=OFF &

UB2_Sel
SIG Bus2_CB.DPS=ON
UL2 Usyn
4
UB2
&
>=1
& Alm_Invalid_Sel
Figure 4.3-6 Voltage selection for 3/2 breakers arrangement (closing the tie CB)
4.3.5 Settings
Table 4.3-3 Settings of voltage selection

Selection of circuit breaker
NoVolSel, DblBusOneCB,
1 Opt_CBConfig NoVolSel - - arrangement for voltage
3/2BusCB, 3/2TieCB
selection

Date: 2019-04-24
4 Control Functions

Date: 2019-04-24
5 Measurement
5 Measurement
Table of Contents
5.1 Primary Values ................................................................................................. 5-1

5.1.1 General Values ..................................................................................................................... 5-1
5.1.2 Angle Values ......................................................................................................................... 5-1
5.1.3 Sequence Components Values ............................................................................................ 5-2
5.1.4 Power Values ........................................................................................................................ 5-2
5.1.5 Harmonics ............................................................................................................................ 5-3
5.2 Secondary Values ............................................................................................ 5-3

5.2.1 General Values ..................................................................................................................... 5-3
5.2.2 Angle Values ......................................................................................................................... 5-4 5

5.2.3 Sequence Components Values ............................................................................................ 5-5
5.2.4 Power Values ........................................................................................................................ 5-5
5.2.5 Harmonics ............................................................................................................................ 5-6
5.3 Calculation Values ........................................................................................... 5-6

5.3.1 Synchrocheck ....................................................................................................................... 5-6
5.4 Energy Metering............................................................................................... 5-7

5.5 Power Quality ................................................................................................... 5-7

Date: 2019-04-24
5 Measurement

Date: 2019-04-24
5 Measurement
5.1 Primary Values

Access path: MainMenu  “Measurements”  “Primary Values”
5.1.1 General Values
No. Symbol Definition Unit
1 Ia_Pri Phase-A current A
2 Ib_Pri Phase-B current A
3 Ic_Pri Phase-C current A
4 Ua_Pri Phase-A protection voltage kV
5 Ub_Pri Phase-B protection voltage kV
6 Uc_Pri Phase-C protection voltage kV
7 Uab_Pri Phase-AB protection voltage kV
8 Ubc_Pri Phase-BC protection voltage kV
9 Uca_Pri Phase-CA protection voltage kV
10
11
f
Neu.I_Pri
Frequency of protection voltage
External measured residual current

Hz
A
5
12 SEF.I_Pri The sensitive residual current measured from the high-precision CT A
13 Neu2.I_Pri Another group of residual current A
14 60/50.I_Pri Unbalance current A
15 Delt.U_Pri External measured residual voltage kV
16 Syn.U_Pri Voltage for synchronism check kV
17 60/59.U_Pri Unbalance voltage kV
5.1.2 Angle Values
1 Ang (Ua-Ia) Phase angle between phase-A voltage and phase-A current °
2 Ang (Ub-Ib) Phase angle between phase-B voltage and phase-B current °
3 Ang (Uc-Ic) Phase angle between phase-C voltage and phase-C current °
4 Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °
5 Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °
6 Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °
7 Ang (Ia-Ib) Phase angle between phase-A current and phase-B current °
8 Ang (Ib-Ic) Phase angle between phase-B current and phase-C current °
9 Ang (Ic-Ia) Phase angle between phase-C current and phase-A current °
Phase angle between phase-A voltage and the referenced angle,

10 Ang (Ua) °
currently, the angle of phase-A voltage is used as the referenced angle.

Date: 2019-04-24
5 Measurement
11 Ang (Ub) Phase angle between phase-B voltage and the referenced angle °
12 Ang (Uc) Phase angle between phase-C voltage and the referenced angle °
13 Ang (Ia) Phase angle between phase-A current and the referenced angle °
14 Ang (Ib) Phase angle between phase-B current and the referenced angle °
15 Ang (Ic) Phase angle between phase-C current and the referenced angle °
Phase angle between the external measured residual current and the
16 Neu.Ang (I) °
referenced angle
17 SEF.Ang (I) °
referenced angle
Phase angle between another group of external measured residual

18 Neu2.Ang (I) °
current and the referenced angle
19 60/50.Ang (I) Phase angle between the unbalance current and the referenced angle °
Phase angle between the external measured residual voltage and the
20 Delt.Ang (U) °
referenced angle
5 21 Syn.Ang (U)
Phase angle between the synchronism check used voltage and the
referenced angle
°
22 60/59.Ang (U) Phase angle between the unbalance voltage and the referenced angle °
5.1.3 Sequence Components Values
1 I1_Pri The positive-sequence current A
2 I2_Pri The negative-sequence current A
3 3I0_Pri Residual current A
4 U1_Pri The positive-sequence voltage kV
5 U2_Pri The negative-sequence voltage kV
6 3U0_Pri The calculated residual voltage kV
5.1.4 Power Values
No. Sign Description Unit
1 Pa_Pri
2 Pb_Pri The primary values of three-phases active powers. MW
3 Pc_Pri
4 Qa_Pri
5 Qb_Pri The primary values of three-phases reactive powers. MVAr
6 Qc_Pri
7 Sa_Pri The primary values of three-phases apparent powers. MVA

Date: 2019-04-24
5 Measurement
8 Sb_Pri
9 Sc_Pri
10 P_Pri The primary value of active power. MW
11 Q_Pri The primary value of reactive power. MVAr
12 S_Pri The primary value of apparent power. MVA
13 Cosa
14 Cosb Three-phases power factors.
15 Cosc
16 Cos Power factor
5.1.5 Harmonics
1 U_Hm01_Pri kV
2 U_Hm02_Pri kV
3 U_Hm03_Pri kV 5
4 U_Hm04_Pri kV
5 U_Hm05_Pri kV
6 U_Hm06_Pri kV
7 U_Hm07_Pri kV
8 U_Hm08_Pri The primary value of the 1st~15th voltage harmonic kV
9 U_Hm09_Pri kV
10 U_Hm10_Pri kV
11 U_Hm11_Pri kV
12 U_Hm12_Pri kV
13 U_Hm13_Pri kV
14 U_Hm14_Pri kV
15 U_Hm15_Pri kV
5.2 Secondary Values

Access path: MainMenu  “Measurements”  “Secondary Values”
5.2.1 General Values
1 Ia_Sec Phase-A current (summation current for double circuit breakers mode) A
2 Ib_Sec Phase-B current (summation current for double circuit breakers mode) A
3 Ic_Sec Phase-C current (summation current for double circuit breakers mode) A

Date: 2019-04-24
5 Measurement
4 Ua_Sec Phase-A protection voltage V
5 Ub_Sec Phase-B protection voltage V
6 Uc_Sec Phase-C protection voltage V
7 Uab_Sec Phase-AB protection voltage V
8 Ubc_Sec Phase-BC protection voltage V
9 Uca_Sec Phase-CA protection voltage V
10 f Frequency of protection voltage Hz
11 Neu.I_Sec External measured residual current A
12 SEF.I_Sec The sensitive residual current measured from the high-precision CT A
13 Neu2.I_Sec Another group of residual current A
14 60/50.I_Sec Unbalance current A
15 Delt.U_Sec External measured residual voltage V
16 Syn.U_Sec Voltage for synchronism check V
17 60/59.U_Sec Unbalance voltage V

5
5.2.2 Angle Values
1 Ang (Ua-Ia) Phase angle between phase-A voltage and phase-A current °
2 Ang (Ub-Ib) Phase angle between phase-B voltage and phase-B current °
3 Ang (Uc-Ic) Phase angle between phase-C voltage and phase-C current °
4 Ang (Ua-Ub) Phase angle between phase-A voltage and phase-B voltage °
5 Ang (Ub-Uc) Phase angle between phase-B voltage and phase-C voltage °
6 Ang (Uc-Ua) Phase angle between phase-C voltage and phase-A voltage °
7 Ang (Ia-Ib) Phase angle between phase-A current and phase-B current °
8 Ang (Ib-Ic) Phase angle between phase-B current and phase-C current °
9 Ang (Ic-Ia) Phase angle between phase-C current and phase-A current °
Phase angle between phase-A voltage and the referenced angle,

10 Ang (Ua) °
currently, the angle of phase-A voltage is used as the referenced angle.
11 Ang (Ub) Phase angle between phase-B voltage and the referenced angle °
12 Ang (Uc) Phase angle between phase-C voltage and the referenced angle °
13 Ang (Ia) Phase angle between phase-A current and the referenced angle °
14 Ang (Ib) Phase angle between phase-B current and the referenced angle °
15 Ang (Ic) Phase angle between phase-C current and the referenced angle °
16 Neu.Ang (I) °
referenced angle
17 SEF.Ang (I) Phase angle between the external measured residual current and the °

Date: 2019-04-24
5 Measurement
referenced angle
Phase angle between another group of external measured residual

18 Neu2.Ang (I) °
current and the referenced angle
19 60/50.Ang (I) Phase angle between the unbalance current and the referenced angle °
Phase angle between the external measured residual voltage and the
20 Delt.Ang (U) °
referenced angle
Phase angle between the synchronism check used voltage and the
21 Syn.Ang (U) °
referenced angle
22 60/59.Ang (U) Phase angle between the unbalance voltage and the referenced angle °
5.2.3 Sequence Components Values
1 I1_Sec The positive-sequence current A
2 I2_Sec The negative-sequence current A
4
3I0_Sec
U1_Sec
Residual current
The positive-sequence voltage

A
V
5
5 U2_Sec The negative-sequence voltage V
6 3U0_Sec The calculated residual voltage V
5.2.4 Power Values
1 Pa_Sec
2 Pb_Sec The secondary values of three-phases active powers. W
3 Pc_Sec
4 Qa_Sec
5 Qb_Sec The secondary values of three-phases reactive powers. Var
6 Qc_Sec
7 Sa_Sec
8 Sb_Sec The secondary values of three-phases apparent powers. VA
9 Sc_Sec
10 P_Sec The primary value of active power. W
11 Q_Sec The primary value of reactive power. Var
12 S_Sec The primary value of apparent power. VA
13 Cosa
14 Cosb Three-phases power factors.
15 Cosc

Date: 2019-04-24
5 Measurement
16 Cos Power factor
5.2.5 Harmonics
1 U_Hm01_Sec V
2 U_Hm02_Sec V
3 U_Hm03_Sec V
4 U_Hm04_Sec V
5 U_Hm05_Sec V
6 U_Hm06_Sec V
7 U_Hm07_Sec V
8 U_Hm08_Sec The secondary value of the 1st~15th voltage harmonic V
9 U_Hm09_Sec V
10 U_Hm10_Sec V
5 11 U_Hm11_Sec V
12 U_Hm12_Sec V
13 U_Hm13_Sec V
14 U_Hm14_Sec V
15 U_Hm15_Sec V
5.3 Calculation Values

Access path: MainMenu  “Measurements”  “Function Values”
5.3.1 Synchrocheck
1 25.U_Ref_Sec Secondary voltage of reference side V
2 25.U_Ref_Pri Primary voltage of reference side kV
3 25.f_Ref Frequency of reference side Hz
4 25.U_Syn_Sec Secondary voltage of synchronization side V
5 25.U_Syn_Pri Primary voltage of synchronization side kV
6 25.f_Syn Synchronization side frequency Hz
7 25.U_Diff_Sec Secondary voltage difference for CB synchronism check V
8 25.U_Diff_Pri Primary voltage difference for CB synchronism check kV
9 25.phi_Diff Phase angle difference for CB synchronism check Deg
10 25.f_Diff Frequency difference for CB synchronism check Hz
11 25.df/dt Frequency variation difference for CB synchronism check Hz/s

Date: 2019-04-24
5 Measurement
12 25.RSYN_OK Synchronism check is passed.
13 25.SynChk_OK Synchro-check is passed.
14 25.DdChk_OK Dead charge check is passed.
15 25.U_Diff_OK Voltage difference criteria is satisfied.
16 25.f_Diff_OK Frequency difference criteria is satisfied.
17 25.dfdt_OK Voltage variation difference criteria is satisfied.
18 25.phi_Diff_OK Phase difference criteria is satisfied.
19 25.RefDd Dead check of reference side is passed.
20 25.RefLv Live check of reference side is passed.
21 25.SynDd Dead check of synchronization side is passed.
22 25.SynLv Live check of synchronization side is passed.
5.4 Energy Metering

Access path: MainMenu  “Measurements”  “Energy Metering”

5
1 EA_Accu_Fwd Positive active energy kWh
2 EA_Accu_Rev Negative active energy kWh
3 ER_Accu_Fwd Positive reactive energy kVarh
4 ER_Accu_Rev Negative reactive energy kVarh
5.5 Power Quality

Access path: MainMenu  “Measurements”  “Power Quality”
1 PwrQual.UnbalRate_U Voltage unbalance rate %
2 PwrQual.UnbalRate_I Current unbalance rate %
3 PwrQual.THD Total harmonic distortion %
U a  3  U nn
4 Ua_Devn Deviation of phase A voltage  %
U nn
U b  3  U nn
5 Ub_Devn Deviation of phase B voltage  %
U nn
U c  3  U nn
6 Uc_Devn Deviation of phase C voltage  %
U nn
7 f_Devn Deviation of frequency = f_meas - fn Hz

Date: 2019-04-24
5 Measurement
8 UnbalRate_U2 Unbalance rate of negative-sequence voltage = U2/U1 %
Unbalance rate of zero-sequence voltage (calculated) =

9 UnbalRate_3U0 %
3U0/U1
Total Harmonic Distortion (THD) of phase A voltage
15
10 THD_Ua U
i 2
2
Hm _ i %
THD 
U Hm _1
11 UnbalRate_I2 Unbalance rate of negative-sequence current = I2/I1 %
12 UnbalRate_3I0 Unbalance rate of zero-sequence current (calculated) = 3I0/I1 %

Date: 2019-04-24
6 Supervision
6 Supervision
Table of Contents
6.1 Overview ........................................................................................................... 6-1

6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-2
6.2.2 Hardware Status Supervision ............................................................................................... 6-2
6.2.3 Hardware Configuration Supervision ................................................................................... 6-3
6.2.4 Device Firmware Supervision .............................................................................................. 6-3
6.2.5 CPU Process and Module Supervision ................................................................................ 6-3
6.3 Analog Input Supervision ............................................................................... 6-3

6.4 Secondary Circuit Supervision....................................................................... 6-4
6.5 Binary Input Supervision ................................................................................ 6-5
6.5.1 Debounce Time .................................................................................................................... 6-5
6.5.2 Jitter Processing ................................................................................................................... 6-7

6
6.6 Circuit Breaker Supervision ........................................................................... 6-9
6.6.1 Tripped Position Contact Supervision .................................................................................. 6-9
6.7 Tripping Counter Statistics ............................................................................. 6-9

6.8 Supervision Alarms and Handling Suggestion ............................................. 6-9
List of Figures
Figure 6.4-1 Principle of the TCS function with two binary inputs ........................................ 6-4
Figure 6.5-1 Sequence chart of debounce technique ............................................................. 6-5
Figure 6.5-2 Debounce time configuration page...................................................................... 6-6
Figure 6.5-3 Sequence chart of jitter processing..................................................................... 6-8
List of Tables
Table 6.8-1 Alarm description..................................................................................................... 6-10

Date: 2019-04-24
6 Supervision

Date: 2019-04-24
6 Supervision
6.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before
the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore,
the automatic supervision function, which checks the health of the protection system when startup
and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed if required.
6.2 Device Hardware Supervision
All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For
peripherals, it can monitor the status of the interface module, check the input and output data,
send the communication interface and receive self-loop detection. Memory self-check is used to
detect unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.
The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is judged
whether the interface work is abnormal.
The hardware supervision also includes the power supply status monitoring. The voltage
monitoring chip is used by all the power supplies. The reset voltage threshold is preset to the reset
monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will output the
reset signal to control CPU to be in the reset state and avoid the wrong operation.

Date: 2019-04-24
6 Supervision
6.2.1 Hardware Resource Consumption Supervision

1. Logic component total execution time monitoring
In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the
PCS-Studio automatically calculates the time required for the theoretical execution of the
configured components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.
2. Module data exchange monitoring
During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.
3. Configuration file size monitoring
The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the
PCS-Studio prompts the configuration error.
6.2.2 Hardware Status Supervision

6 1. Memory ECC and parity functions.
The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and
eliminate the logic abnormity caused by memory errors.
2. Memory error monitoring in code area and constant data area
In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device
hardware, only at the moment and not restart.
3. Binary output relay drive monitoring
The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from mal-operation when the device is not given a
tripping order and the binary output relay driver is detected in the effective state.
4. CPU temperature monitoring
The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature

Date: 2019-04-24
6 Supervision
monitored by CPU.
6.2.3 Hardware Configuration Supervision
The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.
6.2.4 Device Firmware Supervision
1. Each hardware module configuration check code needs to be consistent with CPU module.
The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.
2. The hardware modules and process interface versions need to be consistent with the CPU
module.
If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.
3. Configuration text is correct.
The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not. 6
4. Whether any setting is over the range, whether it needs to confirm the settings.
If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.
6.2.5 CPU Process and Module Supervision

1. Monitor the heartbeat of the module.
In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.
2. Check whether the settings of other modules are consistent with the CPU module.
The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".
6.3 Analog Input Supervision
The sampling circuit of this device is designed as dual-design scheme. Each analog sampling

Date: 2019-04-24
6 Supervision
channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal [Alm_Sample],
and the protection function related to the sampling channel is disabled at the same time. When
the sampling circuit returns to normal state, the related protection is not blocked after 10s.
6.4 Secondary Circuit Supervision
The secondary circuit supervision function includes current transformer supervision (CTS),
voltage transformer supervision (VTS) and tripping/closing circuit supervision.
 CTS function
The purpose of the CTS function is to detect whether the current transformer circuit is failed. In
some cases, if the CT is failed (broken-conductor, short-circuit), related protective element should
be blocked for preventing this device from mal-operation.
See further details about the CTS function, please refer Chapter 3.
 VTS function
The purpose of the VTS function is to detect whether the VT analog input is normal. Because
some function, such as synchronism check, will be influenced by a voltage input failure.
The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit
6 fault, poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and
then issue an alarm signal and block relevant function.
See further details about the VTS function, please refer Chapter 3.
 Tripping circuit function
The tripping circuit supervision function can be realized by program the logic function of this
device through the PCS-Studio according to the practical application experience of the user. In
this manual, a scheme which uses two independent binary inputs to supervise the tripping circuit
is recommended.
The following figure show the recommended scheme for tripping circuit supervision and the logic
diagram of the TCS function.
DC+ DC-
52a TC
BTJ
52b
Protection Device Circuit Breaker

[BI_01]
& 600ms [Alm_TCS]
[BI_02]
Figure 6.4-1 Principle of the TCS function with two binary inputs

Date: 2019-04-24
6 Supervision
Where:
“BTJ” is the protection tripping output contact;
“TC” is the tripping coil of the circuit breaker;
[BI_01] is the binary input which is parallel connected with “BTJ”;
[BI_02] is the binary input which is serial connected with the “52b” contact.
6.5 Binary Input Supervision
6.5.1 Debounce Time
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.5-1.
Binary input
state
SOE report SOE report

timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1
0
6
Debounce time of Debounce time of
delayed pickup delayed dropout
Time
Figure 6.5-1 Sequence chart of debounce technique
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.
In order to meet flexible configurable requirement for different project field, all binary inputs
provided by the device are configurable. Through the configuration tool, this device provides two
parameters to setup debounce time of delayed pickup and dropout based on specific binary
signal.

Date: 2019-04-24
6 Supervision
Figure 6.5-2 Debounce time configuration page
The configurable binary signals can be classified as follows:
1. Type 1
This type of binary inputs includes enable/disable of protection functions, AR mode selection,
“BI_RstTarg”, “BI_Maintenance”, disconnector position, settings group switch, open and
close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They are on the premise of reliability, and the
debounce time of delayed pickup and delayed dropout is recommended to set as 100ms at
least.
6 2. Type 2
This type of binary inputs include breaker failure initiating binary inputs,
“CSWIxx.Cmd_LocCtrl”, “CSWIxx.Cmd_RmtCtrl” and so on.
Debounce time
BI Input Signal.X1 t1 t2 &

Time delay Output
SIG Operation condition
 Time delay is equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as
15ms, in order to prevent binary signals from mal-operation due to mixed connection of
AC system and DC system.
 Time delay is not equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as
(-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from mal-operation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed dropout.
3. Type 3

Date: 2019-04-24
6 Supervision
This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 5ms.
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.
6.5.2 Jitter Processing
This device can handle repetitive signal or so-called jitter via binary input module with the following
settings:
[Mon_Window_Jitter] T, monitoring window of binary input jitter processing
[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter
[Blk_Window_Jitter] T', blocking window of binary input status change due to jitter
[Num_Reblk_Jitter] N', times threshold to initiate immediately another blocking

window of binary input status change due to continuous jitter
For a binary input voltage variation, if the jitter processing function is enabled, its handling
principle is:
1. During the T,
 If the actual jitter times < N, the block will not be initiated and the status change of this
6
binary input will be considered.
 If the actual jitter times ≥ N, the T' is initiated, and the status change of binary input will
be ignored during the T'.
2. During the T',
 If the actual jitter times < N', the block window will expire. The final status of this binary
input will be compared to the original one before T', so as to determine whether there is a
change or not.
 If the actual jitter times ≥ N', the T' will be initiated again immediately (i.e. restart the
timer), and the status change of binary input will be ignored during the next T'.
An example of jitter processing is shown in the following sequence chart:

Date: 2019-04-24
6 Supervision
Debounce time Input voltage level

(falling edge)
Debounce time
(rising edge)
Jitter blocking flag
n=N
initiate jitter block
Signal after
debounce & jitter
n=N processing
n=5<N=7 Prolong blocking
window
T
T t7 t8
t11
t5 t6
T T T
t1 t2 t3 t4 t9 t10 t
Figure 6.5-3 Sequence chart of jitter processing
①Red line Voltage variation of binary input
6 ②Green line Blocking signal of binary input status change due to jitter
③Blue line Binary input status after debounce and jitter processing
n Actual jitter times
We take N = 7 and N' = 5 in this example.
3. T = t2 - t1
 n=5<N
 No blocking, ② stays at 0 and ③ is tracing the voltage variation to create SOE events.
4. T = t4 - t3, at t5
 n=7=N
 The processing initiates the blocking immediately due to jitter
 Jitter blocking, no more SOE event, ② changes its status to 1 and ③ stops the tracing.
5. T' = t6 - t5
 At t7, n = 5 =N', the processing prolongs the blocking immediately due to jitter

Date: 2019-04-24
6 Supervision
 Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
6. T'= t8 - t7
 At t9, n = 5 =N', the processing prolongs the blocking immediately due to jitter.
 Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
7. T'= t10 - t9
 n = 2 < N'
 At t10, jitter unblocking, ② changes its status to 0 and ③ keeps its status.
8. At t11
 Debounce time = t11 - t10
 ③ restarts to trace the voltage variation to create SOE events.
6.6 Circuit Breaker Supervision
6.6.1 Tripped Position Contact Supervision 6

If the relay detects that the tripped auxiliary contact position is on (i.e., the value of [BI_52b] is “1”.),
meanwhile any phase current is greater than 0.04In, and such a condition keeps for longer than
10 seconds, the alarm signals [Alm_Device] and [Alm_52b] will be issued, and the LED indicator
“ALARM” will be on at the same time.
6.7 Tripping Counter Statistics
The tripping counter statistics function supports statistics of the tripping operation, such as circuit
breakers, disconnectors and so on. For phase separation circuit breaker, when the position of
phase A, B, and C is detected from close state to open state, the total position tripping counter is
added, and the tripping counter is added once when the position of the disconnector is detected
from close state to open state.
In addition, the statistics of the number of state change of circuit breakers and disconnectors are
also provided. The state change counter will add one when the position is detected from close
state to open state or from open state to close state.
6.8 Supervision Alarms and Handling Suggestion
Hardware circuit and operation status of this device are self-supervised continuously. If any

Date: 2019-04-24
6 Supervision
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
If the device is blocked or alarm signal is sent during operation, please do find out its reason with
the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
Table 6.8-1 Alarm description
No
Item Description Handling suggestion
.
Fail Signals (Device will be blocked)
The signal is issued with other
This signal will be issued if any fail
specific fail signals, and please
1 Fail_Device signal picks up and it will drop off when
refer to the handling suggestion
all fail signals drop off.
other specific alarm signals.
6 This signal will be issued if any
Please inform the manufacture
2 Fail_DeviceInit hardware or software failure is detected
or the agent for repair.
in the device initialization process.
1. Go to the menu
“Information→Borad Info”,
check the abnormality
This signal will be issued due to information.
mismatch between the configuration of 2. For the abnormality board, if
3 Fail_BoardConfig
plug-in modules and the designing the board is not used, then
drawing of an applied-specific project. remove, and if the board is
used, then check whether the
board is installed properly and
work normally.
Check whether the CCD
process level configuration file
This signal will be issued if the CCD
of this device is exist and
process level configure file is parsed
4 Fail_ProcLevelConfig whether the file content is
wrongly or the type in the file is
correct. May need to download
inconsistent with the actual device.
and update the correct CCD
process level configuration file.
After configuration file is updated, Please check the settings
5 Fail_SettingItem_Chgd
settings of the file and settings saved mentioned in the prompt

Date: 2019-04-24
6 Supervision
No
.
on the device are not matched. This message on the LCD, and go to
signal will be issued instantaneously the menu “Settings” and select
and will be latched unless the “Confirm_Settings” item to
recommended handling suggestion is confirm settings. Then, the
adopted. device will restore to normal
operation stage.
Please reset setting values
The value of any setting is out of scope. according to the range
This signal will be issued described in the instruction
6 Fail_Setting_OvRange instantaneously and will be latched manual, then re-power or reboot
unless the recommended handling the device and the device will
suggestion is adopted. restore to normal operation
state.
The alarm signal will be issued
instantaneously when an error is found
7 Fail_Memory
during checking memory data, and
usually, it will automatically drop out. Please inform the manufacture
The board fails to register the variable, or the agent for repair.
because of abnormal board, insufficient
8 Fail_BoardRegister
memory space, or incorrect
configuration. 6
The configuration process does not run
9 Fail_ProcessConfig
properly. View the menu "Initialization
The board fails to be initialized, Error" to check the detailed
because of abnormal board, insufficient reason, and send the reason to
10 Fail_BoardInit
memory space, or incorrect the manufacture or the agent.
configuration.
Error is found during checking settings.
It means inappropriate or incorrect
settings for some application scenarios
are checked.
11 Fail_Settings Please check the settings
This signal will be issued
instantaneously and will be latched
unless the recommended handling
suggestion is adopted.
Sampling error, it means that the DC 1. Please make the device out
component contained in the sample is of service.
too large or there is some problem 2. Then check if the analog input
12 Fail_Sample during the mutual-check of double AD modules and wiring connectors
sample value. connected to those modules are
This signal will be issued installed at the position.
instantaneously and will be latched 3. Re-power the device, if it is

Date: 2019-04-24
6 Supervision
No
.
unless the recommended handling still invalid, please replace the
suggestion is adopted. CPU module.
Alarm Signals (Device will not be blocked)
The signal is issued with other
The device is abnormal. This signal will
specific alarm signals, and
be issued if any alarm signal picks up
13 Alm_Device please refer to the handling
and it will drop off when all alarm
suggestion other specific alarm
signals drop off.
signals.
This signal will be issued if any
hardware or software configuration Please inform the manufacture
14 Alm_DeviceInit
wrong is detected in the device or the agent to deal with it.
initialization process.
Users may pay no attention to
the alarm signal in the project
commissioning stage, but it is
needed to download the latest
package file (including correct
The error is found during checking the version checksum file) provided
version of software downloaded to the by R&D engineer to make the
15 Alm_Version device. This signal will be issued alarm signal disappear. Then
6 instantaneously and will drop off users get the correct software
instantaneously. version. It is not allowed that the
alarm signal is issued on the
device already has been put into
service. The devices having
being put into service so that
the alarm signal disappears.
Alarm signal indicating that the
equipment is in maintenance state (the Check the binary input
16 Alm_Maintenance
binary input [BI_Maintenance] is [BI_Maintenance].
energized.
The device is in the communication test No special treatment is needed,
mode. This signal will be issued and disable the communication
17 Alm_CommTest
instantaneously and will drop off test function after the completion
instantaneously. of the test.
Management procedure will upload and
check the parameters and settings of
Put the protective device out of
each protection plug-in module
18 Alm_Settings_MON service at once. Inform the
regularly, if the parameters and settings
factory or agency to maintain it.
are inconsistent, the alarm signal will be
issued.
19 Alm_BI_SettingGrp The active group set by settings in Please check the value of

Date: 2019-04-24
6 Supervision
No
.
device and that set by binary input are setting [Active_Grp] and binary
not matched. This signal will issued input of indicating active group,
instantaneously and will drop off and make them matched. Then
instantaneously. the “ALARM” LED will be
extinguished and the
corresponding alarm message
will disappear and the device
will restore to normal operation
state.
1. Check whether the selected
clock synchronization mode
matches the clock
synchronization source;
2. Check whether the wiring
connection between the device
and the clock synchronization
source is correct
3. Check whether the setting for
selecting clock synchronization
The time synchronization abnormality (i.e. [Opt_TimeSyn]) is set
20 Alm_TimeSyn
alarm. correctly. If there is no clock 6
synchronization, please set the
setting [Opt_TimeSyn] as ”No
TimeSyn”.
After the abnormality is
removed, the “ALARM” LED will
be extinguished and the
corresponding alarm message
will disappear and the device
will restore to normal operation
state.
The memory of CPU plug-in module is Please inform the manufacture
21 Alm_Insuf_Memory
insufficient. or the agent to deal with it.
The configuration file of IEC103 is
detected to be not correct when this file Please inform the manufacture
22 Alm_CfgFile_IEC103
is parsed in the device initialization or the agent to deal with it.
process.
CPU module detects that some module
23 Alm_Board is reset due to the abnormality during
Please inform the manufacture
the device operating.
or the agent to deal with it.
An abnormality is detected during the
24 Bx.Alm_Board
module self-check.

Date: 2019-04-24
6 Supervision
No
.
No sufficient NOR flash space used to
25 Alm_Insuf_NORflash
store the program in CPU module
The settings which are stored in CPU
26 Alm_Settings module are different with the settings
which are used by other modules.
Please refer to the fault
Disturbance fault recording settings are
27 Alm_Settings_DFR recording configuration related
set wrongly
contents, i.e. Section 7.4.
Check the setting of network
The network mode is inconsistent, such
mode, or upload the device log
as the setting is set as HSR mode, but
28 Alm_NetMode_Unmatched and confirm with the
the actual operation mode is PRP
manufacturer or agent whether
mode.
the network mode is supported.
The device's master process is
Please check the load of the
29 Alm_master abnormal and it is blocked for more
device.
than 1 minute.
The configuration file of DNP client 1 is
30 Alm_CfgFile_TCP1_DNP
incorrect.
The configuration file of DNP client 2 is Please contact the configuration
incorrect. engineer to check and confirm
6 32 Alm_CfgFile_TCP3_DNP
The configuration file of DNP client 3 is the contents of DNP
incorrect. configuration file.
The configuration file of DNP client 4 is
incorrect.
No special treatment is needed,
The device is in the binary output test and disable the binary output
34 Alm_BOTest
mode. test function after the completion
of the test.
Sampling abnormality alarm, indicating
Please check the data sampling
35 Alm_Sample that the data sampling quality is sent
quality
abnormally.
DPS abnormality signal, if the circuit
breaker position is intermediate or bad,
this alarm will be issued.
36 Breaker.DPS.Alm
This signal will pick up and drop off with
a time delay defined by
Check the corresponding DPS
[CSWI**.DPS.t_Alm].
signal
DPS abnormality signal, if the switch 0x
position is intermediate or bad, this
Switch0x.DPS.Alm
37 alarm will be issued.
(x=1~9)
This signal will pick up and drop off with
a time delay defined by

Date: 2019-04-24
6 Supervision
No
.
[CSWI**.DPS.t_Alm].
The initiating signal of breaker failure Check the initiating contact of
38 50BF.Alm_Init
protection is energized consistently. breaker failure protection
Please check the corresponding
CT circuit fails.
CT secondary circuit. After the
This signal will pick up with a time delay
39 CTS.Alm abnormality is eliminated, the
[CTS.t_DPU] and will drop off with a
device returns to normal
time delay [CTS.t_DDO].
operation state.
Please check the corresponding
VT circuit fails.
VT secondary circuit. After the
This signal will pick up with a time delay
40 VTS.Alm abnormality is eliminated, the
[VTS.t_DPU] and will drop off with a
device returns to normal
time delay [VTS.t_DDO].
operation state.
GOOSE alarm signals
It is an overall alarm signal and will be
issued if any of the following alarm Please check Ethernet switch of
signals is generated: GOOSE network, GOOSE
41 GAlm_Overall
“GAlm_AStorm”, “GAlm_BStorm”, configuration file and GOOSE
“GAlm_CfgFile”, “XX.GAlm_ADisc”, network.
“XX.GAlm_BDisc”, “XX.GAlm_Cfg”
GOOSE alarm signal indicating that

Inform commissioning personnel 6
42 GAlm_CfgFile to check the GOOSE
GOOSE configuration file is incorrect.
configuration file.
@Bx.Name_n_GCommLink. Network A of corresponding GOOSE
43
GAlm_ADisc link is disconnected
@Bx.Name_n_GCommLink. Network B of corresponding GOOSE
44 Please check the GOOSE
GAlm_BDisc link is disconnected
network and GOOSE
The GOOSE control blocks received on
configuration file.
@Bx.Name_n_GCommLink. network and GOOSE control blocks
45
GAlm_Cfg defined in GOOSE configuration file are
unmatched.
Where:
@Bx.Name_n_GCommLink is the set value of the label setting of [Bx.Name_n_GCommLink]

(n=000~127)

Date: 2019-04-24
6 Supervision

Date: 2019-04-24
7 System Functions
7 System Functions
Table of Contents
7.1 Clock Synchronization .................................................................................... 7-1

7.1.1 Clock Synchronization Mode ................................................................................................ 7-1
7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1
7.1.3 Clock Synchronization Priority ............................................................................................. 7-1
7.1.4 SNTP Setup .......................................................................................................................... 7-2
7.2 State Information ............................................................................................. 7-3

7.2.1 Overview ............................................................................................................................... 7-3
7.2.2 Access Method ..................................................................................................................... 7-3
7.3 Event Recording .............................................................................................. 7-4

7.3.1 Overview ............................................................................................................................... 7-4
7.3.2 Disturbance Records ............................................................................................................ 7-4
7.3.3 Supervision Events ............................................................................................................... 7-4
7.3.4 Binary Events ....................................................................................................................... 7-4
7.3.5 Device Logs .......................................................................................................................... 7-4 7

7.3.6 Control Logs ......................................................................................................................... 7-5
7.3.7 Access Method ..................................................................................................................... 7-5
7.4 Fault Recording ............................................................................................... 7-5

7.4.1 Overview ............................................................................................................................... 7-5
7.4.2 Fault Report .......................................................................................................................... 7-6
7.4.3 Fault Waveform .................................................................................................................... 7-6
7.4.4 Access Method ..................................................................................................................... 7-7
7.5 Maintenance State ........................................................................................... 7-7

7.6 Communication Test ....................................................................................... 7-8
7.7 Output Test ....................................................................................................... 7-8
7.8 Target Reset ..................................................................................................... 7-9
7.9 Switch Setting Groups .................................................................................... 7-9

Date: 2019-04-24
7 System Functions

Date: 2019-04-24
7 System Functions
7.1 Clock Synchronization
7.1.1 Clock Synchronization Mode
The device supports various kinds of clock synchronization methods, including hardware clock
synchronization and software clock synchronization.
1. Hardware clock synchronization ([Opt_TimeSyn]=Conventional)
 IRIG-B: IRIG-B via RS-485 differential level, TTL level or optical fiber interface
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 PPM: Pulse per minute (PPM) via RS-485 differential level or binary input
 IEEE1588: Clock message based on IEEE1588 via optical fiber interface
2. Software clock synchronization ([Opt_TimeSyn]=SAS)
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol, Modbus

protocol and DNP3.0 protocol
7.1.2 Clock Synchronization Abnormality

The device provide an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source.
7
If the setting [Opt_TimeSyn] is set as "Conventional" and no hardware clock synchronization
signal is connected, the device will automatically switch into software clock synchronization and
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "SAS" and neither hardware clock
synchronization signal nor software clock synchronization signal is connected, the device will
issue the alarm signal. If the setting [Opt_TimeSyn] is set as "NoTImeSyn" and no clock
synchronization signal is connected, the device will not issue the alarm signal. The clock
synchronization is still fulfilled when valid clock synchronization signal is received.
7.1.3 Clock Synchronization Priority
The device provides a priority-based adaptive clock synchronization scheme, which means that
the device can automatically identify multiple clock synchronization sources in the same clock
synchronization mode and choose the highest priority of lock synchronization sources.
When the setting [Opt_TimeSyn] is set as "Conventional", the device can automatically identify
clock synchronization signal among IRIG-B, PPS, PPM and IEC1588. If IRIG-B, PPS, PPM and
IEC1588 exist at the same time, the device selects IRIG-B in priority. If PPS, PPM and IEC1588
exist at the same time, the device selects IEEE1588 in priority.

Date: 2019-04-24
7 System Functions
When the setting [Opt_TimeSyn] is set as "SAS", the device can automatically identify whether
there is valid hardware clock synchronization signal. The device selects hardware clock
synchronization signal or the combination of hardware clock synchronization signal plus software
clock synchronization signal in priority.
Clock synchronization mode Clock synchronization signal Priority selection

IRIG-B + IEEE1588 + PPS/PPM IRIG-B
IRIG-B + IEEE1588 IRIG-B
Hardware clock synchronization
IRIG-B + PPS/PPM IRIG-B
IEEE1588 + PPS/PPM IEEE1588
Priority 1: IRIG-B
Priority 2: SNTP
Priority 3: Message
IRIG-B + SNTP + Message
Only one kind of clock
synchronization signal is valid
according to the priority
Priority 1: IEEE1588
Priority 2: SNTP
Priority 3: Message
IEEE1588 + SNTP + Message
Only one kind of clock
Software clock synchronization
synchronization signal is valid
Priority 1: PPS/PPM + SNTP
Priority 2: PPS/PPM + Message
Priority 3: PPS/PPM
Priority 4: SNTP
PPS/PPM + SNTP + Message
7 Priority 5: Message
Select clock synchronization signal
(including combination mode)
7.1.4 SNTP Setup
When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.
[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the

device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

Date: 2019-04-24
7 System Functions
device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP
synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.
7.2 State Information
7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary
measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the
device is healthy.
7.2.2 Access Method

7.2.2.1 Access by Local HMI (Human Machine Interface)
These state information can be gained via local HMI. The menu path is:
1. Analog quantities
7
 MainMenu  "Measurements"  "Primary Values"
 MainMenu  "Measurements"  "Secondary Values"
 MainMenu  "Measurements"  "Function Values"
 MainMenu  "Measurements"  "Synchrocheck"
 MainMenu  "Measurements"  "Energy Metering"
 MainMenu  "Measurements"  "Power Quality"
 MainMenu  "Measurements"  "UserDef Values"
2. Status quantities
 MainMenu  "Status"  "Inputs"
 MainMenu  "Status"  "Outputs"
 MainMenu  "Status"  "Superv Status"
 MainMenu  "Status"  "Running Status"

Date: 2019-04-24
7 System Functions
 MainMenu  "Status"  "UserDef Status"
7.2.2.2 Access by Virtual HMI
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
7.2.2.3 Access by Communication Client
Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.
7.2.2.4 Access by Printer
The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:
MainMenu  "Print"  "Device Status"
7.3 Event Recording
7.3.1 Overview
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped
binary events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024
time-stamped device logs. All the records are stored in non-volatile memory, and when the
available space is exhausted, the oldest record is automatically overwritten by the latest one.
7.3.2 Disturbance Records

7
When any protection element operates or drops out, such as fault detector, distance protection
etc., they will be logged in event records. Disturbance records include signal name, its value
before and after changing, and the time precision is up to 1ms.
7.3.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records. Supervision events include signal name, its value before and after changing, and the
time precision is up to 1ms.
7.3.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records. Binary events include signal name, its value
7.3.5 Device Logs

If an operator executes some operations on the device, such as reboot protective device, modify

Date: 2019-04-24
7 System Functions
setting, etc., they will be logged in event records. Device logs include signal name, its value
7.3.6 Control Logs
When an operator executes a control command via local LCD, PCS-Studio or communication
client, it will be logged in control logs. Control logs include time stamp, controlled object, control
origination, control position, operation condition ,interlocking condition, control command and
operation result.
7.3.7 Access Method

7.3.7.1 Access by Local HMI
The device provides corresponding menus to view event recorders. The menu path is:
MainMenu  "Test"  "Disturb Item"
MainMenu  "Records"  "Superv Events"
MainMenu  "Records"  "IO Events"
MainMenu  "Records"  "Device Logs"
MainMenu  "Records"  "Control Logs"
as local LCD.
Event recorders can be uploaded into clients through corresponding communication service of the 7
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Superv Events"
MainMenu  "Print"  "IO Events"
7.4 Fault Recording
7.4.1 Overview
Fault recorder can be used to have a better understanding of the behavior of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
recorded data provides valuable information that can be used to improve existing equipment. This
information can also be used when planning for and designing new installations.

Date: 2019-04-24
7 System Functions
The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal [BI_TrigDFR].
The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most
recent recordings are always stored safely. The maximum number of recordings is 32.
7.4.2 Fault Report

For each fault report, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The date and time is recorded when a system fault is detected. The time resolution is 1ms.
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.
4. Fault information
Including faulty phase, fault location and protection elements
7.4.3 Fault Waveform

A fault waveform contains all analog and digital quantities related to protection such as currents,
7 voltages, differential current, alarm elements, and binary inputs and etc.
The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording
parameter, these components can be individually set. The pre-trigger waveform recorded duration
is configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].
4. [MaxRecDur_PostTrigDFR]
1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]
Trigger point
Total recording time
1. Pre-trigger recording time
Use the setting [RecDur_PreTrigDFR] to set this time.

Date: 2019-04-24
7 System Functions
2. Pickup recording time
The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).
3. Post-fault recording time
The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.
4. Maximal post-trigger recording time
Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the
post-trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].
7.4.4 Access Method

7.4.4.1 Access by Local HMI
The device provides corresponding menus to check fault recording. The menu path is:
MainMenu  "Records"  "Disturb Records"
as local LCD.
Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3.0).
7
The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Disturb Records"
7.5 Maintenance State
The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized,
which is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and
binary outputs, maintenance state has no influence on protection logics. For binary inputs and
binary outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types

Date: 2019-04-24
7 System Functions
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.
For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in
the application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality
attribute set as "1". For DNP3.0 and ModBus protocol, they are not affected.
7.6 Communication Test
The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During
communication test, protection functions are not affected, the signals generated by
communication test are recorded in relevant reports, and event recording and fault recording will
not stop recording disturbance information. The alarm signal "Alm_CommTest" will be issued to
indicate the operator when activating Test Mode and exiting Test Mode.
Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:
 Events Simulation
Main Menu  "Test"  "Device Test"  "Disturb Events"
Main Menu  "Test"  "Device Test"  "Superv Events"
Main Menu  "Test"  "Device Test"  "IO Events"
7  Forced Measurements
Main Menu  "Test"  "Device Test"  "Measurements"
Forced measurement ONLY affects the values modified and transmitted to

station control or control center. Primary circuit, secondary circuit and
device local logic will not be influenced. Forced value will remain during the
test until the exit of this menu.
If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7.7 Output Test

The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the

Date: 2019-04-24
7 System Functions
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.
Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:
 Contacts Outputs
Main Menu  "Test"  "Device Test"  "Contact Outputs"
 GOOSE Outputs
Main Menu  "Test"  "Device Test"  "GOOSE Outputs"
7.8 Target Reset
The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.
1. Reset via local HMI
 Access menu path: MainMenu  "Local Cmd"  "Reset Target"
 Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface
 Press the command pushbutton " TARGET RESET" on operation panel of the device
2. Reset via virtual HMI
Access menu path: MainMenu  "Local Cmd"  "Reset Target" 7

3. Reset via binary input
Energize the binary input "BI_RstTarg"
4. Reset via IEC61870-5-103
Use ASDU20, INF19 of IEC61870-5-103 protocol
5. Reset via remote control
Use standard remote service of corresponding protocol
7.9 Switch Setting Groups
For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 10 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.

Date: 2019-04-24
7 System Functions
The device will be temporarily blocked during switching setting groups. During temporary device
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.
1. Switch via local HMI
 Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

change the value of the setting [Active_Grp]
 Press the command pushbutton “MENU” under main interface (password is required)
2. Switch via virtual HMI
Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

modify the setting [Active_Grp]
3. Switch via binary inputs
There are 2 appropriate input signals available for switching setting group via binary inputs.
These input signals allow selection of the settings group via a binary code. If one of two
signals changes, the signal image present will result in switching over to the appropriate
settings group. If only 2 settings groups must be switched over, only 1 binary input is required.
The following table shows the possible binary codes and applicable setting groups.
External input signals can be connected with "setting_grp_bit0" and "setting_grp_bit1"

respectively by PCS-Studio.
Binary codes Group 1 Group 2 Group 3 Group 4

setting_grp_bit1 0 0 1 1
setting_grp_bit0 0 1 0 1
7 4. Switch via communication client
The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.
 Use "General Service" of IEC61870-5-103 protocol to modify the setting [Active_Grp]
 Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.

Date: 2019-04-24
8 Hardware
8 Hardware
Table of Contents
8.1 Overview ........................................................................................................... 8-1

8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirement ............................................................................................... 8-7
8.3.1 CT Types .............................................................................................................................. 8-7
8.3.2 CT Requirement ................................................................................................................... 8-8
8.4 Plug-in Module Description ............................................................................ 8-9

8.4.1 Human-machine Interface Module (NR6855/NR6856) ........................................................ 8-9
8.4.2 Power Supply Module (NR6305/NR6310) ........................................................................... 8-9
8.4.3 CPU Module (NR6106) ...................................................................................................... 8-12
8.4.4 Analog Input Module (NR6641) .......................................................................................... 8-16
8.4.5 Binary Input Module (NR6601/NR6610) ............................................................................ 8-19
8.4.6 Binary Output Module (NR6651/NR6652/NR6660) ........................................................... 8-23
List of Figures
Figure 8.1-1 Hardware diagram .................................................................................................. 8-1
Figure 8.1-2 Front view of this device.......................................................................................... 8-3
Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules) ............................ 8-3 8
Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules) ........................... 8-4
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules) ......................... 8-4
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules) ...................................................... 8-5
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules) ........................ 8-6
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules) .................................................... 8-7
Figure 8.4-1 View of power supply module ............................................................................... 8-10
Figure 8.4-2 View of CPU module .............................................................................................. 8-14
Figure 8.4-3 Connection of communication terminal ............................................................ 8-15
Figure 8.4-4 Jumpers of printer/RS-485 port .......................................................................... 8-15

Date: 2019-04-24
8 Hardware
Figure 8.4-5 Schematic diagram of CT circuit automatically closed ................................... 8-16
Figure 8.4-6 Terminal definition of analog input module ...................................................... 8-17
Figure 8.4-7 Current connection examples ............................................................................ 8-18
Figure 8.4-8 Voltage connection examples............................................................................. 8-19
Figure 8.4-9 Voltage dependence for binary inputs............................................................... 8-20
Figure 8.4-10 View of binary input module (NR6601A) ......................................................... 8-21
Figure 8.4-11 View of binary input module (NR6610A/B) ...................................................... 8-22
Figure 8.4-12 View of binary output module NR6651A ......................................................... 8-24
Figure 8.4-13 View of binary output module NR6651B ......................................................... 8-25
Figure 8.4-14 View of binary output module NR6652A ......................................................... 8-26
Figure 8.4-15 View of binary output module (NR6660A) ....................................................... 8-27
List of Tables
Table 8.4-1 Terminal definition and description of power supply module ............................... 8-11
Table 8.4-2 Terminal definition and description of power supply module ............................... 8-11
Table 8.4-3 Configuration and terminal definition of CPU module........................................... 8-14
Table 8.4-4 Terminal definition and description of binary input module (NR6601A) ............... 8-21
Table 8.4-5 Terminal definition and description of binary input module (NR6610A/B) .......... 8-23

Date: 2019-04-24
8 Hardware
8.1 Overview
The modular design of this device allows this device to be easily upgraded or repaired by a
qualified service person. The faceplate is hinged to allow easy access to the configurable
modules, and back-plugging structure design makes it easy to repair or replace any module.
This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 8.1-1 for the hardware diagram.
External
Binary Input
Conventional CT/VT A/D

Output
ARM1
Relay
A/D
Pickup
ECVT Relay
ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45
Keypad
PRINT
Figure 8.1-1 Hardware diagram 8

The working process of the device is shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signals are
sent to the device without small signal and A/D conversion). The ARM1 core carries out fault
detector, protection logic calculation, tripping output, and the ARM2 core performs SOE
(sequence of event) record, waveform recording, printing, communication between the device and
SAS and communication between HMI and CPU. When the fault detector detects a fault and picks
up, the positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS S series based on microcomputer
are classified into standard and optional modules.

Date: 2019-04-24
8 Hardware
Table 8.1-1 Module configuration of this device
Module ID Module description Remark

NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/6310 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
NR6641 Analog input module (AI module) Mandatory
NR6601/NR6610 Binary input module (BI module) Mandatory
NR6651/NR6652/NR6660 Binary output module (BO module) Mandatory
 HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
 PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.
 CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.
 AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
 BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V/48V/110V/125V/220V/250V (configurable).
 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
Following figures show front and rear views of this device respectively.

Date: 2019-04-24
8 Hardware
Figure 8.1-2 Front view of this device
Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules)

Date: 2019-04-24
8 Hardware
Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules)
8.2 Typical Wiring
B01 B02 & B03 B04 B05 B06 P1 B01 B02 & B03 B04 P1
NR6106AA NR6641-6I5U Option Option Option NR6310A NR6106AA NR6641-6I5U Option NR6310A
BI_01+ 01 BI_01+ 01
01 I1 I1n 02 01 I1 I1n 02
BI_01- 02 BI_01- 02
03 I2 I2n 04 BI_02+ 03 03 I2 I2n 04 BI_02+ 03
BI_02- 04 BI_02- 04
NET 05 I3 I3n 06 BI_COM 05 NET 05 I3 I3n 06 BI_COM 05
BI_03 06 BI_03 06
LC 07 I4 I4n 08 LC 07 I4 I4n 08
BI_04 07 BI_04 07
LC BI_05 08 LC BI_05 08
09 I5 I5n 10 09 I5 I5n 10
BI_06 09 BI_06 09
11 I6 I6n 12 BI_07 10 11 I6 I6n 12 BI_07 10
BI_08 11 BI_08 11
13 14 BI_09 12 13 14 BI_09 12
13 13
8
15 U1 U1n 16 BO_01 15 U1 U1n 16 BO_01
14 14
17 U2 U2n 18 15 17 U2 U2n 18 15
BO_02 BO_02
16 16
01 1A 19 U3 U3n 20 17 01 1A 19 U3 U3n 20 17
BO_03 BO_03
02 1B 18 02 1B 18
03 SGND 21 U4 U4n 22 19 03 SGND 21 U4 U4n 22 19
BO_04 BO_04
04 2A 20 04 2A 20
23 U5 U5n 24 23 U5 U5n 24
05 2B 21 05 2B 21
06 SGND BO_05 06 SGND
BO_05
22 22
07 SYN+ 07 SYN+
23 23
08 SYN- BO_Fail 08 SYN- BO_Fail
24 24
09 SGND 09 SGND
PWR+ 25 PWR+ 25
10 SYN-TTL 10 SYN-TTL
PWR- 26 PWR- 26
CONSOLE Ground CONSOLE Ground
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

Date: 2019-04-24
8 Hardware
Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 Ia
0202
SGND 0103
0203
485-2A 0104 Ib
0204
COM
485-2B 0105
0205
SGND 0106
Ic
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 I0
0208
TTL 0110
0209
I0
Multiplex RJ45 0210
0211
AI plug-in module
Isef
P101 + BI_01 0212
0213
P102 -
0214
- P103 + BI_02
0215
P104 - U0
0216
P106 + BI_03 0217
Ux
0218
P107 + BI_04 0219
Ua
0220
PWR plug-in module
…
0221
P112 + BI_09 Ub
0222
P105 0223
P113 Uc
BO_01 0224
P114
P115
P116 BO_02
…
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
External DC power Power
supply
PWR- P126 Supply
8
Grounding Bus
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules)

Date: 2019-04-24
8 Hardware
B01 B02 & B03 B04 B05 B06 P1 B01 B02 & B03 B04 P1
NR6106AA NR6641-6I5U Option Option Option NR6305A NR6106AA NR6641-6I5U Option NR6305A
01 I1 I1n 02 01 BI_01+ BI_01- 02 01 I1 I1n 02 01 BI_01+ BI_01- 02
03 I2 I2n 04 03 BI_02+ BI_02- 04 03 I2 I2n 04 03 BI_02+ BI_02- 04
NET 05 I3 I3n 06 05 BI_COM BI_03 06 NET 05 I3 I3n 06 05 BI_COM BI_03 06
LC 07 I4 I4n 08 07 BI_04 BI_05 08 LC 07 I4 I4n 08 07 BI_04 BI_05 08
LC 09 BI_06 BI_07 10 LC 09 BI_06 BI_07 10

09 I5 I5n 10 09 I5 I5n 10
11 I6 I6n 12 11 BI_08 BI_09 12 11 I6 I6n 12 11 BI_08 BI_09 12
13 14 13 BO_01 14 13 14 13 BO_01 14
15 U1 U1n 16 15 BO_02 16 15 U1 U1n 16 15 BO_02 16
17 U2 U2n 18 17 BO_03 18 17 U2 U2n 18 17 BO_03 18
01 1A 19 U3 U3n 20 19 BO_04 20 01 1A 19 U3 U3n 20 19 BO_04 20

02 1B 02 1B
03 SGND 21 U4 U4n 22 21 BO_05 22 03 SGND 21 U4 U4n 22 21 BO_05 22
04 2A 04 2A
23 U5 U5n 24 23 BO_Fail 24 23 U5 U5n 24 23 BO_Fail 24
05 2B 05 2B
06 SGND 06 SGND
25 PWR+ PWR- 26 25 PWR+ PWR- 26
07 SYN+ 07 SYN+
08 SYN- 08 SYN-
09 SGND 09 SGND
10 SYN-TTL 10 SYN-TTL
CONSOLE CONSOLE
Ground Ground
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

Date: 2019-04-24
8 Hardware
Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 Ia
0202
SGND 0103
0203
485-2A 0104 Ib
0204
COM
485-2B 0105
0205
SGND 0106
Ic
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 I0
0208
TTL 0110
0209
I0
Multiplex RJ45 0210
0211
AI plug-in module
Isef
P101 + BI_01 0212
0213
P102 -
0214
- P103 + BI_02
0215
P104 - U0
0216
P106 + BI_03 0217
Ux
0218
P107 + BI_04 0219
Ua
0220
PWR plug-in module
…
0221
P112 + BI_09 Ub
0222
P105 0223
P113 Uc
BO_01 0224
P114
P115
P116 BO_02
…
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
External DC power Power
supply
PWR- P126 Supply
8
Grounding Bus
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules)
8.3 CT Requirement
8.3.1 CT Types
Generally there are three types of CT: high remanence, low remanence and no
remanence.
 High remanence: TPX, TPS, P, PX.
 Low remanence: TPY, PR, and the residual magnetism does not exceed 10% of the
saturation flux.

Date: 2019-04-24
8 Hardware
 No remanence: TPZ level, residual magnetism can actually be ignored.
The high residual magnetism CT may have large residual magnetism. When the fault
non-periodic component and residual magnetism are in the same direction, the CT
saturation degree will be more serious. The following CT type checking calculation takes
into account the maximum residual magnetism of CT and the maximum non periodic
component on the site.
8.3.2 CT Requirement
Rated secondary limit e.m.f (volts) formula:
Esl = Kalf × Isn × (Rct + Rbn)
Kalf Accuracy limit factor: Kalf = Ipal / Ipn
Isn Rated secondary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Sbn Rated burden (VAs)

Rbn Rated resistance burden (ohms): Rbn = Sbn / Isn2
Actual secondary limit e.m.f (volts) under different fault conditions:
Esl1′ = k1×Ipcf1 ×Isn×(Rct+Rb)/Ipn
Esl2′ = k2×Ipcf2 ×Isn×(Rct+Rb)/Ipn
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
Esl4′ = k4×Ipcf4×Isn×(Rct+Rb)/Ipn
k1, k2, k3, k4 are transient factors.
Ipcf1 Maximum through fault current when out-zone fault (amps)
Maximum fault current through two bridge CB but not transformer when
Ipcf2
8 out-zone fault (amps)
Ipcf4 Maximum fault current when in-zone fault (amps)
Ipnt Transformer rated primary current (amps)
Ipn CT rated primary current (amps)
Isn CT rated secondary current (amps)
Rct Current transformer secondary winding resistance (ohms)
Rb Real resistance burden (ohms): Rb = Rr + 2RL
RL Resistance of a single lead from relay to the CT (ohms)
Rr Impedance of relay phase current input (ohms)
1. K Value Requirement
1) Single CB connection, the following condition should be fulfilled
Esl > Esl1′

Date: 2019-04-24
8 Hardware
Esl > min (Esl3′, Esl4′)
While: k1=2，k3=30，k4=1.
2) Double CB connection, the following condition should be fulfilled:
Esl > Esl1′
Esl > Esl2′
Esl > min (Esl3′, Esl4′)
If both CTs of double CB are low remanence type, and with the same model, then k1=2,
k2=1.5, k3=30, k4=1.
Otherwise: k1=2，k2=2，k3=30，k4=1.
2. Example
Kalf=30, Isn=5A, Rct=1Ω, Sbn=60VA
Ipcf1=40000A, RL=0.5Ω, Rr=0.1Ω, Rc=0.1Ω, Ipn=2000A, Ipnt=1500A
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/Isn2)
= 30×5×(1+60/25)=510V
Esl1′ = k1×Ipcf1×Isn×(Rct+Rb)/Ipn
= 2×Ipcf1 ×Isn×(Rct+(Rr+2×RL))/Ipn
= 2×40000×5×(1+(0.1+2×0.5))/2000=420V
Esl3′ = k3×Ipnt×Isn×(Rct+Rb)/Ipn
=30×1500*5*(1+(0.1+2×0.5)) /2000=236.25V
Thus, Esl > Esl1′ and Esl > Esl3′
8.4 Plug-in Module Description 8

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module, CH plug-in module and NET-DSP plug-in module. Terminal
definitions and application of each plug-in module are introduced as follows.
8.4.1 Human-machine Interface Module (NR6855/NR6856)

The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the
user.
8.4.2 Power Supply Module (NR6305/NR6310)

The power supply module is a DC/DC converter with electrical insulation between input and

Date: 2019-04-24
8 Hardware
output. It has an input voltage range as described in Chapter 2 Technical Data. The standardized
output voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously
monitored.
The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.
8
Figure 8.4-1 View of power supply module
Three types of power supply modules are provided: NR6305A, NR6305B and NR6310A. The
NR6305B is same as the NR6305A except that the NR6105B can support at least 500ms power
supply interruption.
 NR6305A & NR6305B
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 26-pin connector is fixed on the power supply module. The terminal definition of
the connector is described as below.

Date: 2019-04-24
8 Hardware
Table 8.4-1 Terminal definition and description of power supply module
Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
06 BI_03 The No.3 programmable binary input
13
BO_01 The No.1 programmable binary output
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply 8

 NR6310A
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure
binary output. A 22-pin connector and a 4-pin connector are fixed on the power supply module.
The terminal definition of the connector is described as below.
Table 8.4-2 Terminal definition and description of power supply module

01 BI_01+
02 BI_01-
22-pin 03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09

Date: 2019-04-24
8 Hardware

13
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
The standard rated voltage of the PWR module is self-adaptive to

88~300Vdc or 88~275Vac. For a non-standard rated voltage power supply
module please specify when place order, and check if the rated voltage of
8 power supply module is the same as the voltage of power source before
the device being put into service.
The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent

EMI, so effective grounding must be ensured before the device is put into
service.
8.4.3 CPU Module (NR6106)

The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
function and so on. There are several A/D conversion circuits on this module, which are used to

Date: 2019-04-24
8 Hardware
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the
electrical level standard. A high-accuracy clock chip is contained in this module, it provide
accurate current time for this device.
The main functional details of the CPU module are listed as below:
 Protection calculation and logical judgment function
The CPU module can calculate protective elements (such as overcurrent element) on the
basis of the analog sampled values (voltages and currents) and binary inputs, then it does
logical judgment function and decides whether the device needs to trip or close.
 Communication function
The CPU module can effectively manage all communication procedures, and reliably send
out some useful information through its various communication interfaces. These interfaces
are used to communicate with a SAS or a RTU. It also can communicate with the human
machine interface module. If an event occurs (such as SOE, protective tripping event etc.),
this module will send out the relevant event information through these interfaces, and make it
be easily observed by the user.
 Auxiliary calculation
Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.
 Human-machine interface function
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.
 Time synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B
8
signal. Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on
the IRIG-B signal, this module can synchronize local clock with the standard clock.

Date: 2019-04-24
8 Hardware
Figure 8.4-2 View of CPU module
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.

8 The configuration and terminal definition of the CPU modules are listed in following table.
Table 8.4-3 Configuration and terminal definition of CPU module
Module ID Memory Interface Terminal No. Usage Physical Layer

2 RJ45 Ethernet Ethernet
Twisted pair wire
2 SFP Ethernet communication
01 A
RS-485 02 B To SCADA Twisted pair wire
03 SGND
NR6106AA 1G DDR
04 A
RS-485 05 B To SCADA Twisted pair wire
06 SGND
07 SYN+ To clock
RS-485 Cable
08 SYN- synchronization

Date: 2019-04-24
8 Hardware
09 SGND
TTL 10 SYN-TTL Cable
The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire

A 01
B 02
COM
SGND 03
cable with single point earthing
04
To the screen of other coaxial
Twisted pair wire

SYN+ 01
Clock SYN
SYN- 02
SGND 03
04
Cable
RTS 05
PRINT
TXD 06
SGND 07
Figure 8.4-3 Connection of communication terminal
Figure 8.4-4 Jumpers of printer/RS-485 port
The 2nd RS-485 port also can be configured as a printer port through the

Date: 2019-04-24
8 Hardware
jumpers “J10” and “J11”.
Jumper RS-485 Printer

J10 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
J11 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
8.4.4 Analog Input Module (NR6641)

The analog input module is applicable for power plant or substation with conventional VT and CT,
and it can transform high AC input values to relevant low AC output value, which are suited to the
analog inputs of the CPU module. The transformers are used both to step-down the currents and
voltages to levels appropriate to the device’s electronic circuitry and to provide effective isolation
between this device and the power system. A low pass filter circuit is connected to each
transformer (CT or VT) secondary circuit for reducing the noise of each analog AC input signal.
For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.
Plug
Socket
In
Out
plug is not put in the socket
8 In
Out
Put the plug in the socket
Figure 8.4-5 Schematic diagram of CT circuit automatically closed
There are several types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current
converter is 40In.
 NR6641-6I5U: 6CT+5VT

Date: 2019-04-24
8 Hardware
 NR6641-4I4U: 4CT+4VT
 NR6641-4I7U: 4CT+7VT
The terminal definition of the analog input module is shown as below.
NR6641-6I5U NR6641-4I4U NR6641-4I7U

01 I1 I1n 02 01 I1 I1n 02 01 I1 I1n 02
03 I2 I2n 04 03 I2 I2n 04 03 I2 I2n 04
05 I3 I3n 06 05 I3 I3n 06 05 I3 I3n 06
07 I4 I4n 08 07 I4 I4n 08 07 I4 I4n 08
09 I5 I5n 10 09 10 09 10
11 I6 I6n 12 11 12 11 U1 U1n 12
13 14 13 14 13 U2 U2n 14
15 U1 U1n 16 15 16 15 U3 U3n 16
17 U2 U2n 18 17 U1 U1n 18 17 U4 U4n 18
19 U3 U3n 20 19 U2 U2n 20 19 U5 U5n 20
21 U4 U4n 22 21 U3 U3n 22 21 U6 U6n 22
23 U5 U5n 24 23 U4 U4n 24 23 U7 U7n 24
Figure 8.4-6 Terminal definition of analog input module
NEVER allow the current transformer (CT) secondary circuit connected to 8

this device to be opened while the primary system is energized. The
opened CT secondary circuit will produce a dangerously high voltage. If
this safety precaution is disregarded, personal death, severe personal
injury or considerable equipment damage will occur.
Each analog input channel can be configured according to practical

application through PCS-Studio.
Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.

Date: 2019-04-24
8 Hardware
1. Current connections examples
A B C A B C
Ia Ia
Ian Ian
Ib Ib
Ibn Ibn
Ic Ic
Icn Icn
I01
I01n I01
(1) I01n
A B C (3)
Ia
Ian
Ib I0s
Ibn I0sn
Ic
(4)
Icn
I01 I02
I01n I02n
(2) (5)
Figure 8.4-7 Current connection examples
Where:
(1) Current connections to three current transformers with a star-point connection for ground
current (zero-sequence current or residual current).
(2) Current connections to three current transformers with a separate ground current
8 transformer (summation current transformer or core balance current transformer).
(3) Current connections to two current transformers with a separate ground current
transformer (summation current transformer or core balance current transformer), only
for ungrounded or compensated networks.
(4) Current connection to a core balance neutral current transformer for sensitive ground
fault detection, only for ungrounded or compensated networks.
(5) Current connection to a separate ground current transformer (summation current

transformer or core balance current transformer) for the No.2 zero-sequence current
input of this relay.
2. Voltage connections examples

Date: 2019-04-24
8 Hardware
A B C A B C
Ux
52 52 52 Ux 52 52 52
Uxn
Uxn
Ua Ua
Ub Ub
Uc Uc
Un Un
U0 U0
U0n U0n
(1) (2)
Figure 8.4-8 Voltage connection examples
Where:
(1) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase voltage (for synchronism check).
(2) Voltage connections to three star-connected voltage transformers with open-delta

windings and additionally to any phase-to-phase voltage (for synchronism check).
8.4.5 Binary Input Module (NR6601/NR6610)

The binary input module contains some optical isolated binary inputs which are used to monitor
the contact positions of the corresponding bay, and all the binary inputs are configurable through
PCS-Studio according to practical application.
There are three kinds of BI modules available, NR6601A, NR6610A and NR6610B. The binary
input module can respectively provide 25 or 32 binary inputs.
8
The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc,
125V, 220V, 110Vac or 220Vac (@50Hz), which must be specified when
placed order. It is necessary to check whether the rated voltage of binary
input module complies with site DC power supply rating before put this
device in service.

Date: 2019-04-24
8 Hardware
Voltage
300
157.5
138.6
125
110
78.75
69.3
62.5
55 Operation
30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V
Figure 8.4-9 Voltage dependence for binary inputs
 NR6601A
Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and dropout voltages of the binary
8 inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un.

Date: 2019-04-24
8 Hardware
01 BI_01 BI_02 02
03 BI_03 BI_04 04
05 BI_05 BI_06 06
07 BI_07 BI_08 08
09 BI_09 BI_10 10
11 BI_11 BI_12 12
13 BI_13 BI_14 14
15 BI_15 BI_16 16
17 BI_17 BI_18 18
19 BI_19 BI_20 20
21 BI_21 BI_22 22
23 BI_23 BI_24 24
25 BI_25 BI_COM 26
Figure 8.4-10 View of binary input module (NR6601A)
A 26-pin connector is fixed on the binary input module. The terminal definition of the connector is
described as below.
Table 8.4-4 Terminal definition and description of binary input module (NR6601A)

02
03
BI_02
BI_03
8

Date: 2019-04-24
8 Hardware

26 BI_COM The common negative connection of the BI_01 to BI_25.
 NR6610A & NR6610B
Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and dropout voltages of the
binary inputs are settable by the setting [U_Pickup_BI] and [U_Dropoff_BI], and the range is from
50%Un to 80%Un. The difference between NR6610A and NR6610B is that NR6610A equips
single AD sampling and NR6610B equips dual AD sampling.
01 BI_01 19 BI_17
02 BI_02 20 BI_18
03 BI_03 21 BI_19
04 BI_04 22 BI_20
05 BI_05 23 BI_21
06 BI_06 24 BI_22
07 BI_07 25 BI_23
08 BI_08 26 BI_24
8 09
10
BI_09
BI_10
27
28
BI_25
BI_26
11 BI_11 29 BI_27
12 BI_12 30 BI_28
13 BI_13 31 BI_29
14 BI_14 32 BI_30
15 BI_15 33 BI_31
16 BI_16 34 BI_32
17 BI_COM 35 BI_COM
18 BI_COM 36 BI_COM
Figure 8.4-11 View of binary input module (NR6610A/B)
The terminal definition of the connector is described as below.

Date: 2019-04-24
8 Hardware
Table 8.4-5 Terminal definition and description of binary input module (NR6610A/B)

18-pin
17
BI_COM The common negative connection of the BI_01 to BI_16.
18
18-pin
27
28
BI_25
BI_26
8
35
BI_COM The common negative connection of the BI_17 to BI_32.
36
8.4.6 Binary Output Module (NR6651/NR6652/NR6660)

The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal
outputs. It can receive tripping commands or closing commands from the CPU module, and then

Date: 2019-04-24
8 Hardware
executes these commands. It also can output some alarm signals from the CPU module.
The device can provide four types of binary output modules: NR6651A, NR6651B, NR6652A and
NR6660A.
 NR6651A
The NR6651A provides 13 normal open contacts (NOC) with pickup relay control.
A 26-pin connector is fixed on the binary input module.
The terminal definition of the connector is shown as below.
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
8 BO_13 25 26
Figure 8.4-12 View of binary output module NR6651A
 NR6651B
The NR6651B provides 11 normal open contacts (NOC, the first 11 contacts) and 2 normal close
contacts (NCC, the last 2 contacts). These binary outputs are controlled by pickup relay.
The terminal definition of the connector is shown in as below.

Date: 2019-04-24
8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-13 View of binary output module NR6651B
 NR6652A
The NR6652A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts). These binary outputs are controlled by pickup relay.
The terminal definition of the connector is shown in as below. 8

Date: 2019-04-24
8 Hardware
BO_01 01 02
03 04
BO_02 05 06
07 08
BO_03 09 10
11 12
BO_04 13 14
15 16
17 18
BO_05 19 20
BO_06 21 22
BO_07 23 24
BO_08 25 26
Figure 8.4-14 View of binary output module NR6652A
 NR6660A
The NR6660A provides 17 normally open contacts (NOC, the first 17 contacts) and 2 normally
close contacts (NCC, the 16th and the 17th contacts). These binary outputs are controlled by
pickup relay.
Two 18-pin connectors are fixed on the binary input module.
8 The terminal definition of the connector is shown in Figure 8.4-15.

Date: 2019-04-24
8 Hardware
BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
BO_14 27 28
BO_15 29 30
BO_16 32
31
BO_16 33
BO_17 35
34
BO_17 36
Figure 8.4-15 View of binary output module (NR6660A)
Each binary output can be set as a specified tripping output contact or a

signal output contact through PCS-Studio according to practical
application.

Date: 2019-04-24
8 Hardware

Date: 2019-04-24
9 Settings
9 Settings
Table of Contents
9.1 Global Settings ................................................................................................ 9-1

9.1.1 System Settings.................................................................................................................... 9-1
9.1.2 Device Settings..................................................................................................................... 9-2
9.1.3 Communication Settings ...................................................................................................... 9-4
9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-16
9.1.5 Label Settings ..................................................................................................................... 9-16
9.1.6 Clock Synchronization Settings .......................................................................................... 9-16
9.1.7 Supervision Settings ........................................................................................................... 9-18
9.1.8 OutMap Settings ................................................................................................................. 9-19
9.2 Protection Settings ........................................................................................ 9-20

9.2.1 Phase Overcurrent Protection Settings .............................................................................. 9-20
9.2.2 Earth Fault Overcurrent Protection Settings ...................................................................... 9-36
9.2.3 Another Group of Earth Fault Overcurrent Protection Settings ......................................... 9-51
9.2.4 Negative-sequence Overcurrent Protection Settings......................................................... 9-63
9.2.5 Sensitive Earth Fault Protection Settings ........................................................................... 9-69
9.2.6 RMS Overcurrent Protection Settings ................................................................................ 9-80
9.2.7 Phase Overvoltage Protection Settings ............................................................................. 9-81
9.2.8 Residual Overvoltage Protection Settings ......................................................................... 9-84
9.2.9 Negative-sequence Overvoltage Protection Settings ........................................................ 9-85

9
9.2.10 Positive-sequence Overvoltage Protection Settings ........................................................ 9-86
9.2.11 Phase Undervoltage Protection Settings ......................................................................... 9-86
9.2.12 Frequency Protection Settings ......................................................................................... 9-91
9.2.13 Reverse Power Protection Settings ................................................................................. 9-94
9.2.14 Cold Load Pickup Logic Settings ..................................................................................... 9-95
9.2.15 Undercurrent Settings ...................................................................................................... 9-98
9.2.16 Breaker Failure Protection Settings ................................................................................. 9-98

Date: 2019-04-24
9 Settings
9.2.17 Switch-on-to-Fault ProtectionSettings .............................................................................. 9-99
9.2.18 Unbalance Current Protection Settings .......................................................................... 9-101
9.2.19 Unbalance Voltage Protection Settings .......................................................................... 9-101
9.2.20 Fault Location Settings ................................................................................................... 9-102
9.3 Measurement and Control Settings ........................................................... 9-102

9.3.1 Function Settings .............................................................................................................. 9-102
9.3.2 Synchronism Check Settings ........................................................................................... 9-103
9.3.3 Double Point Status Settings ........................................................................................... 9-105
9.3.4 Control Settings ................................................................................................................ 9-106
9.3.5 Interlocking Logic Settings ............................................................................................... 9-107
9.4 Logic Links ................................................................................................... 9-109

9.4.1 GOOSE Receiving Links .................................................................................................. 9-109
List of Tables
Table 9.1-1 System settings ....................................................................................................... 9-1
Table 9.1-2 Device settings......................................................................................................... 9-3
Table 9.1-3 General communication settings ........................................................................... 9-4
Table 9.1-4 IEC61850 communication settings ........................................................................ 9-7
Table 9.1-5 DNP communication settings ................................................................................. 9-8
Table 9.1-6 IEC103 communication settings .......................................................................... 9-14
Table 9.1-7 GOOSE communication settings ......................................................................... 9-15
Table 9.1-8 Disturbance fault recording settings ................................................................... 9-16
Table 9.1-9 Label settings ......................................................................................................... 9-16

9 Table 9.1-10 Clock synchronization settings ......................................................................... 9-16
Table 9.1-11 Supervision settings ............................................................................................ 9-19
Table 9.2-1 Settings of phase overcurrent protection ........................................................... 9-20
Table 9.2-2 Settings of earth fault overcurrent protection .................................................... 9-36
Table 9.2-3 Settings of another group of earth fault overcurrent protection...................... 9-51
Table 9.2-4 Settings of negative-sequence overcurrent protection..................................... 9-64
Table 9.2-5 Settings of sensitive earth fault protection ........................................................ 9-69

Date: 2019-04-24
9 Settings
Table 9.2-6 Settings of RMS overcurrent protection ............................................................. 9-80
Table 9.2-7 Settings of phase overvoltage protection ........................................................... 9-81
Table 9.2-8 Settings of residual overvoltage protection ....................................................... 9-84
Table 9.2-9 Settings of negative-sequence overvoltage protection .................................... 9-85
Table 9.2-10 Settings of positive-sequence overvoltage protection ................................... 9-86
Table 9.2-11 Settings of phase undervoltage protection ...................................................... 9-87
Table 9.2-12 Settings of overfrequency protection................................................................ 9-91
Table 9.2-13 Settings of reverse power protection ................................................................ 9-94
Table 9.2-14 Settings of cold load pickup logic ..................................................................... 9-95
Table 9.2-15 Settings of undercurrent protection .................................................................. 9-98
Table 9.2-16 Settings of breaker failure protection................................................................ 9-98
Table 9.2-17 Settings of SOTF protection ............................................................................... 9-99
Table 9.2-18 Settings of unbalance current protection ....................................................... 9-101
Table 9.2-19 Settings of unbalance voltage protection ....................................................... 9-101
Table 3.34-3 Settings of fault location ................................................................................... 9-102
Table 9.4-1 GOOSE receiving links ........................................................................................ 9-109
PCS-9611S Feeder Relay 9-c

Date: 2019-04-24
9 Settings
9-d PCS-9611S Feeder Relay

Date: 2019-04-24
9 Settings
9.1 Global Settings
9.1.1 System Settings

 Access path:
Table 9.1-1 System settings
Default
value
The number of active setting group,
several setting groups can be configured
1 Active_Grp 1~30 1 - 1
for protection settings, and only one is
active at a time.
Name of the protected primary
Max 20
2 PrimaryEquip_Name - - - equipment, such as feeder, transformer,
characters
etc.
3 Opt_SysFreq 50, 60 50Hz Hz The system frequency.
Rated primary value of protection phase
4 Prot.I1n 0~9999 1000 A 1
CT
Rated secondary value of protection
5 Prot.I2n 1, 5 1 A -
phase CT
Rated primary value of the No.1
6 Neu.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of the No.1
7 Neu.I2n 1, 5 1 A -
zero-sequence CT
Rated primary value of the No.2
8 Neu2.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of the No.2
9 Neu2.I2n 1, 5 1 A -
zero-sequence CT
Rated primary value of sensitive
10 SEF.I1n 0~9999 1000 A 1
zero-sequence CT
Rated secondary value of sensitive
11 SEF.I2n 1 1 A -
zero-sequence CT 9
12 60/50.I1n 0~9999 1000 A 1 Rated primary value of unbalance CT
13 60/50.I2n 1, 5 1 A - Rated secondary value of unbalance CT
14 Prot.U1n 0~1100 10 kV 0.001 Rated primary value of protection VT
15 Prot.U2n 1~200 100 V 0.001 Rated secondary value of protection VT
16 Syn.U1n 0~1100 10 kV 0.001 Rated primary value of synchro-check VT
Rated secondary value of synchro-check
17 Syn.U2n 1~200 100 V 0.001
VT
18 Delt.U1n 0~1100 10 kV 0.001 Rated primary value of zero-sequence VT
19 Delt.U2n 1~200 100 V 0.001 Rated secondary value of zero-sequence

Date: 2019-04-24
9 Settings
Default
value
VT
20 60/59.U1n 0~1100 10 kV 0.001 Rated primary value of the unbalance VT

Rated secondary value of the unbalance
21 60/59.U2n 1~200 100 V 0.001
VT
The logic setting determines that whether
the CT polarity of the three-phase
Disabled;
22 Prot.En_RevCT Disabled - - protection CT is reversed.
Enabled
Enabled: The CT polarity is reversed
Disabled: The CT polarity is not reversed
the CT polarity of the No.1
Disabled;
23 Neu.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the No.2
Disabled;
24 Neu2.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the sensitive
Disabled;
25 SEF.En_RevCT Disabled - - zero-sequence CT is reversed.
Enabled
the CT polarity of the unbalance CT is
Disabled;
26 60/50.En_RevCT Disabled - - reversed.
Enabled
ABC;
27 Opt_PhSeq ABC - - Phase sequence of system.
ACB
9 28 En_VT
Disabled;
Enabled
Enabled - - Logic setting to put VT into service
9.1.2 Device Settings

 Access path:
MainMenu  Settings  Global Settings  Device Settings

Date: 2019-04-24
9 Settings
Table 9.1-2 Device settings
Default
value
Logic setting to enable/disable the
Disabled debugging port. Used for debugging
1 En_DebugPort Enabled - -
Enabled tool connection, program download,
variable debugging, etc.
Disabled Logic setting to enable/disable the
2 En_TelnetPort Enabled - -
Enabled Telnet port.
Enabled: Connecting to the device via
Disabled the software Teldevice is supported
3 En_VirtualLCDPort Enabled - -
Enabled Disabled: Connecting to the device via
the software Teldevice is not supported
Enabled: printing data to the software
Disabled Netpts is supported
4 En_NetPrintPort Enabled - -
Enabled Disabled: printing data to the software
Netpts is not supported
Disabled Override control password via local
5 En_NoCtrlPwd Enabled - -
Enabled LCD
6 Ctrl_Password 000~999 111 - - The control password via local LCD.
This setting is used to set the voltage
7 Un_BinaryInput 24~250 220 V -
level of the binary input module.
DC
Power supply mode of binary input
8 Opt_Pwr_BI AC50Hz DC - -
module
AC60Hz
This setting is used to set pickup
9 U_Pickup_BI 50%Un~80%Un 63 % 0.1
voltage of the binary input module.
This setting is used to set drop-off
10 U_Dropoff_BI 50%Un~80%Un 55 % 0.1
voltage of the binary input module.
Monitoring window of binary input jitter
11 Mon_Window_Jitter 0.000~500.000 1 0.001 s
processing
Times threshold to block binary input
12 Num_Blk_Jitter 2~500000 10 1 -
status change due to jitter
Blocking window of binary input status 9
13 Blk_Window_Jitter 0.000~500.000 1 0.001 s
change due to jitter
Times threshold to initiate immediately
14 Num_Reblk_Jitter 1~500000 10 1 - another blocking window of binary input
status change due to continuous jitter
The logic setting to enable/disable the
Disabled
15 En_Jitter_Blk Disabled - - jitter processing function in case of
Enabled
binary input voltage variation

Date: 2019-04-24
9 Settings
9.1.3 Communication Settings

9.1.3.1 General Communication Settings
 Access path:
MainMenu  Settings  Global Settings  Comm Settings  General Comm Settings
Table 9.1-3 General communication settings
No. Settings Range Default value Unit Step Remark

0.0.0.0~
1 IP_LAN1 198.120.0.100 - - IP address of Ethernet port A
255.255.255.255
0.0.0.0~ Subnet mask of Ethernet port
2 Mask_LAN1 255.255.0.0 - -
255.255.255.255 A
0.0.0.0~
3 IP_LAN2 198.121.0.100 - - IP address of Ethernet port B
255.255.255.255
4 Mask_LAN2 255.255.0.0 - -
255.255.255.255 B
Disabled Put Ethernet port B into
5 En_LAN2 Enabled - -
Enabled service
0.0.0.0~
6 IP_LAN3 198.122.0.100 - - IP address of Ethernet port C
255.255.255.255
7 Mask_LAN3 255.255.0.0 - -
255.255.255.255 C
Disabled Put Ethernet port C into
8 En_LAN3 Disabled - -
Enabled service
0.0.0.0~
9 IP_LAN4 198.123.0.100 - - IP address of Ethernet port D
255.255.255.255
10 Mask_LAN4 255.255.0.0 - -
255.255.255.255 D
Disabled Put Ethernet port D into
11 En_LAN4 Disabled - -
Enabled service
0.0.0.0~ IP address of the gateway
12 Gateway 0.0.0.0 - -
255.255.255.255 (router)
4800
9 9600
19200
13 Baud_Printer 19200 bps - Baud rate of printer port
38400
57600
115200
Disabled Enable/disable automatic
14 En_AutoPrint Disabled - -
Enabled printing function
Communication protocol of
IEC103
15 Protocol_RS485-1 IEC103 - - rear RS-485 serial port 1.
Modbus
IEC103: IEC60870-5-103

Date: 2019-04-24
9 Settings

protocol
Modbus: Modbus protocol
Communication protocol of
rear RS-485 serial port 2.
IEC103
16 Protocol_RS485-2 IEC103 - - IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
4800
9600
19200 Baud rate of rear RS-485
17 Baud_RS485-1 19200 bps -
38400 serial port 1.
57600
115200
4800
9600
19200 Baud rate of rear RS-485
18 Baud_RS485-2 19200 bps -
38400 serial port 2.
57600
115200
Communication address
between the device and the
19 Addr_RS485-1 0~255 100 - 1
SCADA or RTU via RS-485
serial port 1.
Communication address
between the device and the
20 Addr_RS485-2 0~255 100 - 1
SCADA or RTU via RS-485
serial port 2.
The setting is used to set the
21 Cfg_NetPorts_Bond 0~255 0 - - Ethernet ports that are used
as hot standby each other.
Normal;
The network method of the
1-2:Normal,3-4:HSR;
22 B01.Opt_NetMode Normal - - CPU module located in slot
1-2:Normal,3-4:PRP;
1-2:Normal,3-4:RSTP
No.1 9
1. [Cfg_NetPorts_Bond]
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any two
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the

Date: 2019-04-24
9 Settings
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.
Bonding Bonding Bonding
Ethernet port 1 Ethernet port 2 Ethernet port 1 Ethernet port 3 Ethernet port 1 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 0 1 1 3 0 1 0 1 5 1 0 0 1 9
Bonding Bonding Bonding
Ethernet port 2 Ethernet port 3 Ethernet port 2 Ethernet port 4 Ethernet port 3 Ethernet port 4
Setting Setting Setting

Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0
Value Value Value
0 1 1 0 6 1 0 1 0 10 1 1 0 0 12
Ethernet port 1: Bit0, Ethernet port 2: Bit1, Ethernet port 3: Bit2, Ethernet port 4: Bit3
The switching logic is as below.
 After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.
 When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.
9  When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.
 When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal.
9.1.3.2 IEC61850 Communication Settings
 Access path:
MainMenu  Settings  Global Settings  Comm Settings  IEC61850 Settings

Date: 2019-04-24
9 Settings
Table 9.1-4 IEC61850 communication settings
Default
value
The identification of the IED in
IEC 61850 protocol.
It cannot be an empty string and
shall be unique within an SCL
file. IEDNAME should be less
than 20 characters comprising
1 IEDNAME - TEMPLATE - -
letters or digits or underline ( _ ),
and it is case sensitive.
If this setting is modified, the IED
name in ".cid" file will be
changed simultaneously and
vice versa.
It is used to set the change
detection threshold for suddenly
sending measurement value to
2 Threshold_Measmt_Net 0~100.00 1 % 0.01
the SCADA via the device's
Ethernet port using IEC 61850
protocol
Measurement values zero drift
3 ThAbs_Measmt 0.001~0.5 0.02 - 0.001
suppression threshold
If users need to support the
Disabled quality change upload function,
4 En_Send_MMS_Qual_Chg Disabled - -
Enabled this parameter should be set as
“1”
It is used to select the network
mode of MMS network for the
communication with SCADA
SingleNet
0: Single network
5 Opt_DualNetMode_MMS HotStdby SingleNet - -
1: Hot standby mode (always
ColdStdby
two ports in service)
2: Cold standby mode (only one 9
port in service)
The logic setting to
Disabled
6 En_IEC62351_TCP_Port Disabled - - enable/disable TCP port in
Enabled
IEC62351 protocol
Disabled
7 En_IEC61850_TCP_Port Enabled - - enable/disable TCP port in
Enabled
IEC61850 protocol
9.1.3.3 DNP Communication Settings
 Access path:

Date: 2019-04-24
9 Settings
MainMenu  Settings  Global Settings  Comm Settings  DNP Settings
Table 9.1-5 DNP communication settings
Default
value
Disabled
1 En_TCP1_DNP Disabled - - enable/disable the No.1
Enabled
network DNP client
The local address of the
2 Addr_Slave_TCP1_DNP 0~65519 2 - 1
No.1 network DNP client
The master address of the
3 Addr_Master_TCP1_DNP 0~65519 1 - 1
The IP address of the
0.0.0.0~
4 IP_Master_TCP1_DNP 0.0.0.0 - - master of the No.1 network
255.255.255.255
DNP client
The communication map
5 Opt_Map_TCP1_DNP 0~4 0 - 1 of the No.1 network DNP
client
The timeout of the
6 t_AppLayer_TCP1_DNP 1~5 3 s 1 application layer of the
The heartbeat time interval
7 t_KeepAlive_TCP1_DNP 0~7200 120 s 1 of the No.1 network DNP
client
enable/disable the
Disabled
8 En_UR_TCP1_DNP Disabled - - unsolicited message
Enabled
function of the No.1
network DNP client
The online retransmission
number for sending the
9 Num_URRetry_TCP1_DNP 2~10 3 - 1
unsolicited message of the
9 The offline retransmission

interval for sending the
10 t_UROfflRetry_TCP1_DNP 1~5000 60 s 1
The default class level of
11 Class_BI_TCP1_DNP 0~3 1 - 1 the “Binary Input” of the
12 Class_AI_TCP1_DNP 0~3 2 - 1 the “Analog Input” of the
13 t_Select_TCP1_DNP 0~240 30 s 1 The selection timeout of

Date: 2019-04-24
9 Settings
Default
value
the remote control and
remote adjustment of No.1
network DNP client
The time interval of the
time synchronization
14 t_TimeSynIntvl_TCP1_DNP 0~3600 180 s 1
network DNP client
The “OBJ1” default
1-BISingleBit
15 Obj01DefltVar_TCP1_DNP 1-BISingleBit - - variation of the No.1
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
2-BIChWithA
16 Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime - - variation of the No.1
bsTime
3-BIChWithRelTime network DNP client
1-AI32Int
2-AI16Int The “OBJ30” default
3-AI32IntWo
17 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF - - variation of the No.1
utF
4-AI16IntWoutF network DNP client
5-AI32Flt
1-AI32IntEvWoutT The “OBJ32” default
1-AI32IntEv
18 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT - - variation of the No.1
WoutT
5-AI32FltEvWoutT network DNP client
1-AO32Int The “OBJ40” default
19 Obj40DefltVar_TCP1_DNP 2-AO16Int 1-AO32Int - - variation of the No.1
3-AO32Flt network DNP client
Disabled
Enabled
network DNP client
23 IP_Master_TCP2_DNP
0.0.0.0~
0.0.0.0 - -
master of the No.2 network
9
255.255.255.255
DNP client
client
The timeout of the
26 t_KeepAlive_TCP2_DNP 0~7200 120 s 1
of the No.2 network DNP

Date: 2019-04-24
9 Settings
Default
value
client
enable/disable the
Disabled
Enabled
network DNP client
The offline retransmission
The selection timeout of
32 t_Select_TCP2_DNP 0~240 30 s 1
network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
9 35 Obj02DefltVar_TCP2_DNP
1-BIChWoutT
2-BIChWithAbsTime
2-BIChWithA
- -
The
variation
“OBJ2”
of the
default
No.2
bsTime
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT

Date: 2019-04-24
9 Settings
Default
value
Disabled
Enabled
network DNP client
0.0.0.0~
42 IP_Master_TCP3_DNP 0.0.0.0 - - master of the No.3 network
255.255.255.255
DNP client
client
The timeout of the
45 t_KeepAlive_TCP3_DNP 0~7200 120 s 1 of the No.3 network DNP
client
enable/disable the
Disabled
Enabled
network DNP client
9
51 t_Select_TCP3_DNP 0~240 30 s 1 The selection timeout of

Date: 2019-04-24
9 Settings
Default
value
network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
1-BIChWoutT The “OBJ2” default
2-BIChWithA
54 Obj02DefltVar_TCP3_DNP 2-BIChWithAbsTime - - variation of the No.3
bsTime
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT
Disabled
Enabled
network DNP client
9 61 IP_Master_TCP4_DNP
0.0.0.0~
0.0.0.0 - -
master of the No.4 network
255.255.255.255
DNP client
client
The timeout of the
64 t_KeepAlive_TCP4_DNP 0~7200 120 s 1
of the No.4 network DNP

Date: 2019-04-24
9 Settings
Default
value
client
enable/disable the
Disabled
Enabled
network DNP client
The selection timeout of
70 t_Select_TCP4_DNP 0~240 30 s 1
network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
73 Obj02DefltVar_TCP4_DNP
1-BIChWoutT
2-BIChWithAbsTime
2-BIChWithA
- -
The
variation
“OBJ2”
of the
default
No.4
9
bsTime
1-AI32Int
3-AI32IntWo
utF
5-AI32Flt
1-AI32IntEv
WoutT

Date: 2019-04-24
9 Settings
Default
value
9.1.3.4 IEC103 Communication Settings
 Access path:
MainMenu  Settings  Global Settings  Comm Settings  IEC103 Settings
Table 9.1-6 IEC103 communication settings

Current
The language of group caption of
Language;
IEC103 protocol
Fixed Current
1 Opt_Caption_103 - - It is recommended to be set as “1” if the
Chinese; Language
device communicate with SCADA in
Fixed
Chinese.
English
This setting is only used for IEC 103
protocol. If NR network IEC103 protocol
is used, the setting must be set as “1”.
Disabled
2 En_Broadcast_LAN1 Disabled - - 0: the device does not send UDP
Enabled
messages through Ethernet port A;
1: the device sends UDP messages
through Ethernet port A.
protocol. If NR network IEC103 protocol
Disabled
Enabled
messages through Ethernet port B;
through Ethernet port B.
9 protocol. If NR network IEC103 protocol
Disabled
Enabled
messages through Ethernet port C;
through Ethernet port C.
Disabled protocol. If NR network IEC103 protocol
5 En_Broadcast_LAN4 Disabled - -
Enabled is used, the setting must be set as “1”.
0: the device does not send UDP

Date: 2019-04-24
9 Settings

messages through Ethernet port D;
through Ethernet port D.
This setting is used to set the data
format for sending waveform list using
IEC 60870-5-103.
DisturbData;
6 Fmt_Wave_Sent File - - DisturbData: Send the waveform list in
File
ASDU23 mode;
File: Send the waveform list in ASDU222
mode.
It is used to set the change detection
threshold for suddenly sending
7 Threshold_Measmt_Net 0~100.00 1.00 % 0.01 measurement value to the SCADA via
the device's Ethernet port using IEC
60870-5-103
It is used to set the time period for
sending the measurement value to
8 Period_Measmt_Net 0~65535 30 s 1
SCADA via the device's Ethernet port
using IEC 60870-5-103 or IEC 61850.
9.1.3.5 GOOSE Communication Settings
 Access path:
MainMenu  Settings  Global Settings  Comm Settings  GOOSE Settings
Table 9.1-7 GOOSE communication settings

The GOOSE receiving mode.
DoubleFrameChk: double frame
DoubleFrameChk
1 Opt_RecvMode_GOOSE SingleFrameChk - - check mode;
SingleFrameChk
SingleFrameChk: single frame
check mode;
Disabled Logic setting to enable/disable
2 En_NetA_GOOSE
Enabled
Enabled - -
GOOSE net A 9
Disabled Logic setting to enable/disable
3 En_DualNet_GOOSE Disabled - -
Enabled GOOSE double-net mode
Logic setting to enable/disable
GOOSE complex-net mode.
GOOSE complex-net mode: for
Disabled
4 En_ComplexNet_GOOSE Disabled - - the GOOSE receiving, some
Enabled
control blocks adopt dual-net
receiving and other control blocks
adopt single-net receiving.

Date: 2019-04-24
9 Settings
9.1.4 Disturbance Fault Recording Settings

 Access path:
MainMenu  Settings  Global Settings  DFR Settings
Table 9.1-8 Disturbance fault recording settings
Default
value
Waveform recorded duration before the
1 RecDur_PreTrigDFR 0~1 0.1 s 0.001
trigger element operating
Waveform recorded duration after the
2 RecDur_PostFault 0~10 5 s 0.001
fault happens
The maximum waveform recorded
3 MaxRecDur_PostTrigDFR 0~10 10 s 0.001 duration after the trigger element
operating
9.1.5 Label Settings

 Access path:
MainMenu  Settings  Global Settings  Label Settings
Table 9.1-9 Label settings
No. Symbol Default value Description
GOOSE_Link0 Label setting of GOOSE communication link 000 of the

1 Bx.Name_000_GCommLink
module located in slot No.x.
2 …… …… ……
GOOSE_Link127 Label setting of GOOSE communication link 127 of the

3 Bx.Name_127_GCommLink
module located in slot No.x.
These settings are used to definite the label of each GOOSE communication link. The label of
each GOOSE communication link will influence the displayed contents of all reports, settings and
metering that related with each GOOSE communication link.
9.1.6 Clock Synchronization Settings

9  Access path:
MainMenu  Settings  Global Settings  ClockSyn Settings
Table 9.1-10 Clock synchronization settings
No Default
Settings Range Unit Step Remark
. value
Conventional Select the time
1 Opt_TimeSyn SAS NoTimeSyn - - synchronization mode of the
NoTimeSyn device.

Date: 2019-04-24
9 Settings
No Default
. value
The local time zone also
2 OffsetHour_UTC -12~12 8 - 1 refered to as the hour offset
hour from UTC .
The offset minute of local time
3 OffsetMinute_UTC 0~60 0 - 1
from UTC.
The IP address of the server
0.0.0.0~ when SNTP time
4 IP_Server_SNTP 0.0.0.0 - -
255.255.255.255 synchronization mode is
selected
The subnet mask of the server
0.0.0.0~ when SNTP time
5 Mask_Server_SNTP 0.0.0.0 - -
0.0.255.255 synchronization mode is
selected
The IP address of the standby
IP_StandbyServer_S 0.0.0.0~ server when SNTP time
6 0.0.0.0 - -
NTP 255.255.255.255 synchronization mode is
selected
The logic setting is used to
Disabled
7 DST.En Disabled - - enable or disable Daylight
Enabled
Saving Time (DST)
It is used to set the minute
offset of DST, i.e. the
8 DST.OffsetMinute 0~255 60 - 1
difference between DST time
and local time
Jan, Feb, Mar,
DST.MonthInYear_St Apr, May, Jun, It is used to set the start month
9 Mar - -
art Jul, Aug, Sep, of DST.
Oct, Nov, Dec
DST.WeekInMonth_S 1st, 2nd, 3nd, It is used to set the start week
10 1st - -
tart 4th, Last of DST.
Sunday, Monday,
11
DST.DayInWeek_Star
Tuesday,
Wednesday, Sunday - -
It is used to set the start day of 9
t DST.
Thursday, Friday,
Saturday
It is used to set the start hour
12 DST.HourInDay_Start 0~23 3 - 1
of DST.
Jan, Feb, Mar,
DST.MonthInYear_En Apr, May, Jun, It is used to set the end month
13 Oct - -
d Jul, Aug, Sep, of DST.
Oct, Nov, Dec
14 DST.WeekInMonth_E 1st, 2nd, 3nd, 1st - - It is used to set the end week

Date: 2019-04-24
9 Settings
No Default
. value
nd 4th, Last of DST.
Sunday, Monday,
Tuesday,
It is used to set the end day of
15 DST.DayInWeek_End Wednesday, Sunday - -
DST.
Thursday, Friday,
Saturday
It is used to set the end hour of
16 DST.HourInDay_End 0~23 9 - 1
DST.
1. [Opt_TimeSyn]
There are three selections for clock synchronization of the device, each selection includes
different time clock synchronization signals shown in following table.
Item Description
IRIG-B (RS-485): IRIG-B via RS-485 differential level.
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B (Fiber): IRIG-B via optical-fibre interface.
Conventional PPS (Fiber): Pulse per second (PPS) via optical-fibre interface.
IEEE1588 (Fiber): Clock message via IEEE1588.
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SNTP(BC): Broadcast SNTP mode via Ethernet network.
SAS
IEC103: Clock messages through IEC103 protocol.
MODBUS: Clock messages through MODBUS protocol.
If time synchronization function is not needed for the device, this option can be
NoTimeSyn
selected.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] being issued simultaneously.
9 2) When “NoTimeSyn” mode is selected, the device will not send time synchronization alarm
signal.
The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.
9.1.7 Supervision Settings

 Access path:

Date: 2019-04-24
9 Settings
Table 9.1-11 Supervision settings
Default
value
The calculated residual current
1 CTS.3I0_Set 0~200 0.1 A 0.001 setting of CT circuit supervision
function.
The calculated residual voltage
2 CTS.3U0_Set 0~200 30 V 0.001 setting of CT circuit supervision
function.
Delay pick-up time setting for CT
3 CTS.t_DPU 0~100 10 s 0.001
circuit failure
Delay drop-off time setting for CT
4 CTS.t_DPO 0~100 10 s 0.001
circuit failure
Disabled Enabling/disabling CT circuit
5 CTS.En Disabled - -
Positive-sequence voltage setting
6 VTS.U1_Set 0~100 30 V 0.01
of VT circuit supervision function.
Residual voltage setting of VT
7 VTS.3U0_Set 0~100 8 V 0.01
circuit supervision function.
Negative-sequence voltage
8 VTS.U2_Set 0~100 8 V 0.01 setting of VT circuit supervision
function.
Delay pick-up time setting for VT
9 VTS.t_DPU 0~30 1.25 s 0.001
circuit failure
Delay drop-off time setting for VT
10 VTS.t_DDO 0~30 10 s 0.001
circuit failure
Disabled Enabling/disabling VT circuit
11 VTS.En Disabled - -
9.1.8 OutMap Settings

 Access path:
MainMenu  Settings  Global Settings  OutMap Settings 9

No. Name Range Unit Default Description
OutMapxxx 00000000~ Tripping logic setting of programmable trip
1 - 0
(xxx=001, 002…120) FFFF FFFF output map xxx
t_Dwell_xxx_OutMap The pulse width setting of programmable
2 0.000~0.500 s 0.060
(xxx=001, 002…032) trip output map xxx

Date: 2019-04-24
9 Settings
9.2 Protection Settings

9.2.1 Phase Overcurrent Protection Settings
 Access path:
MainMenu  Settings  Protection Settings  OC Settings
Table 9.2-1 Settings of phase overcurrent protection
Default
value
The low voltage blocking setting
1 50/51P.VCE.Upp 10~100 70 V 0.001 of the voltage control element of
The negative-sequence voltage
blocking setting of the voltage
2 50/51P.VCE.U2 2~57 8 V 0.001
The residual voltage setting (set
according to 3U0) of voltage
3 50/51P.VCE.3U0 2~57 8 V 0.001
4 50/51P.DIR.RCA -180~179 45 deg 1 the direction control element of
The relay negative-sequence
50/51P.DIR.RCA_N characteristic angle of the
5 -180~179 45 deg 1
egOC direction control element of
50/51P.DIR.phi_Min
_Fwd
50/51P.DIR.phi_Ma
x_Fwd
9 The minimum boundary of the
50/51P.DIR.phi_Min
_Rev
50/51P.DIR.phi_Ma
x_Rev

Date: 2019-04-24
9 Settings
Default
value
The voltage polarization mode
for direction control element of
Upp; Upp: phase-to-phase voltage
50/51P.DIR.Opt_Pol
10 Up; Upp - - polarized
arizedVolt
U1 Up: phase-to-ground voltage
polarized
U1: positive-sequence voltage
polarized
11 50/51P.DIR.I_Min (0.05~1)In 0.05 - 0.001
protection
12 50/51P.DIR.U_Min 1~10 4 V 0.001
protection
behavior of phase overcurrent
Disabled; Disabled: phase overcurrent
13 50/51P.En_VTS_Blk Disabled - -
Enabled protection will not effected by VT
circuit failure
phase overcurrent protection will
be blocked by VT circuit failure
signal
50/51P.HMB.K_Hm
14 0.1~1 0.2 - 0.001 harmonic control element of
2
The current setting for releasing
9
15 50/51P.HMB.I_Rls 2~150 20 A 0.001 the harmonic control element of
harmonic blocking mode of
PhaseBlk phase overcurrent protection
50/51P.HMB.Opt_Bl
16 CrossBlk PhaseBlk - - PhaseBlk: phase blocking
k
MaxPhaseBlk CrossBlk: cross blocking
MaxPhaseBlk: maximum phase
blocking

Date: 2019-04-24
9 Settings
Default
value
17 50/51P1.I_Set 0.05~200 15 A 0.001
protection
protection
20 Disabled - -
element
element
Non_Directio
nal
22 Disabled - -
control element

control element
Disabled;
Enabled

Date: 2019-04-24
9 Settings
Default
value
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P1.Opt_Curve
_DropOut
protection
28 50/51P1.tmin 0 ~10 0.02 s 0.001

setting of stage 1 of phase
9
0.000
1
protection

Date: 2019-04-24
9 Settings
Default
value
0.000
1
protection
0.000
1
protection
32 50/51P1.I_Set 0.05~200 15 A 0.001
protection
protection
35 Disabled - -
element
element
Non_Directio
9 36 50/51P2.Opt_Dir Forward
Reverse
nal
- - directional mode of stage 2 of

Date: 2019-04-24
9 Settings
Default
value
37 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
9
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
50/51P2.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
47 50/51P3.I_Set 0.05~200 15 A 0.001
9 48 50/51P3.t_Op 0 ~100 0.1 s 0.001 stage 3 of phase overcurrent

protection
protection

Date: 2019-04-24
9 Settings
Default
value
50 Disabled - -
element
element
Non_Directio
nal
52 Disabled - -
control element
control element
Disabled;
Enabled
54
Trp - -
to trip or alarm.
9
m Alm

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P3.Opt_Curve
_DropOut
protection
0.000
9
1
protection
0.000
1
protection

Date: 2019-04-24
9 Settings
Default
value
0.000
1
protection
62 50/51P4.I_Set 0.05~200 15 A 0.001
protection
protection
65 Disabled - -
element
element
Non_Directio
nal
9
67 Disabled - -
control element
control element

Date: 2019-04-24
9 Settings
Default
value
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P4.Opt_Curve
_DropOut
9
protection
0.000
1
protection

Date: 2019-04-24
9 Settings
Default
value
0.000
1
protection
0.000
1
protection
77 50/51P5.I_Set 0.05~200 15 A 0.001
protection
protection
80 Disabled - -
element
element
Non_Directio
81 50/51P5.Opt_Dir Forward
Reverse
nal
- - directional mode of stage 5 of
9

Date: 2019-04-24
9 Settings
Default
value
82 Disabled - -
control element
control element
Disabled;
Enabled
m Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
9
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
50/51P5.Opt_Curve
_DropOut
protection
0.000
1
protection
0.000
1
protection
0.000
1
protection
92 50/51P6.I_Set 0.05~200 15 A 0.001
protection
9
protection

Date: 2019-04-24
9 Settings
Default
value
95 Disabled - -
element
element
Non_Directio
nal
97 Disabled - -
control element
control element
Disabled;
Enabled
9
m Alm

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51P6.Opt_Curve
_DropOut
protection
0.000
104 50/51P6.K 0.001~120 0.14 -
1
operation characteristic of stage
9
protection
0.000
1
protection

Date: 2019-04-24
9 Settings
Default
value
0.000
1
protection
9.2.2 Earth Fault Overcurrent Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  ROC Settings
Table 9.2-2 Settings of earth fault overcurrent protection
Default Uni
value t
1 50/51G.DIR.RCA -180~179 45 deg 1
50/51G.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
protection
50/51G.DIR.phi_Max_ forward direction element of
3 10~90 90 deg 1
protection
50/51G.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
protection
50/51G.DIR.phi_Max_ reverse direction element of
9 5
Rev
10~90 90 deg 1
protection
6 50/51G.DIR.I_Min (0.05~1)In 0.05 - 0.001
7 50/51G.DIR.U_Min 1~10 4 V 0.001

Date: 2019-04-24
9 Settings
Default Uni
value t
behavior of earth fault
failure happens.
Disabled;
8 50/51G.En_VTS_Blk Disabled - - Disabled: earth fault
Enabled
protection will be blocked by
VT circuit failure signal
9 50/51G.HMB.K_Hm2 0.1~1 0.2 - 0.001
protection
The current setting for
releasing the harmonic control
10 50/51G.HMB.I_Rls 2~150 20 A 0.001
11 50/51G1.Opt_3I0 Ext - -
current
current
protection
9

Date: 2019-04-24
9 Settings
Default Uni
value t
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse
Disabled;
Enabled
control element
control element
protection
Trp;
Alm

Date: 2019-04-24
9 Settings
Default Uni
value t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT
23 50/51G1.K 0.001~120 0.14 - 0.0001

customized
operation
inverse-time
characteristic of
9

Date: 2019-04-24
9 Settings
Default Uni
value t
26 50/51G2.Opt_3I0 Ext - -
current
current
protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse
9 harmonic control element of

Disabled;
Enabled
control element
control element

Date: 2019-04-24
9 Settings
Default Uni
value t
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT
9

Date: 2019-04-24
9 Settings
Default Uni
value t
41 50/51G3.Opt_3I0 Ext - -
current
current
protection
9 overcurrent protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse

Date: 2019-04-24
9 Settings
Default Uni
value t
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
protection. 9
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default Uni
value t
Inst;
DropOut protection
IDMT
9 Ext;
stage 4 of
earth fault
56 50/51G4.Opt_3I0 Ext - -
current
current
protection

Date: 2019-04-24
9 Settings
Default Uni
value t
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse
Disabled;
Enabled
control element
control element
protection
63 50/51G4.Opt_Trp/Alm
Trp;
Trp - -
to trip or alarm.
9
Alm

Date: 2019-04-24
9 Settings
Default Uni
value t
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT
9

Date: 2019-04-24
9 Settings
Default Uni
value t
71 50/51G5.Opt_3I0 Ext - -
current
current
protection
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse
9
Disabled;
Enabled
control element
control element

Date: 2019-04-24
9 Settings
Default Uni
value t
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
DropOut protection
IDMT
9

Date: 2019-04-24
9 Settings
Default Uni
value t
86 50/51G6.Opt_3I0 Ext - -
current
current
protection
9
Non_Direction
al; Non_Directio
Forward; nal
1: no direction;
Reverse

Date: 2019-04-24
9 Settings
Default Uni
value t
Disabled;
Enabled
control element
control element
protection
Trp;
Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
9
IECV;
protection.
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default Uni
value t
Inst;
DropOut protection
IDMT
9.2.3 Another Group of Earth Fault Overcurrent Protection Settings

 Access path:
9
MainMenu  Settings  Protection Settings  ROC2 Settings
Table 9.2-3 Settings of another group of earth fault overcurrent protection
Default
value
1 A.50/51G1.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
2 A.50/51G1.t_Op 0 ~100 0.1 s 0.001
protection
3 A.50/51G1.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 1 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
8 A.50/51G1.TMS 0.04~ 20 1 - 0.001
protection
9 A.50/51G1.tmin 0 ~10 0.02 s 0.001
10 A.50/51G1.K 0.001~120 0.14 - 0.0001
protection
11 A.50/51G1.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
12 A.50/51G1.C 0 ~1 0 - 0.0001
protection
13 A.50/51G2.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
14 A.50/51G2.t_Op 0 ~100 0.1 s 0.001
protection
15 A.50/51G2.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 2 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
20 A.50/51G2.TMS 0.04~ 20 1 - 0.001
protection
21 A.50/51G2.tmin 0 ~10 0.02 s 0.001
22 A.50/51G2.K 0.001~120 0.14 - 0.0001
protection
23 A.50/51G2.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
24 A.50/51G2.C 0 ~1 0 - 0.0001
protection
25 A.50/51G3.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
26 A.50/51G3.t_Op 0 ~100 0.1 s 0.001
protection
27 A.50/51G3.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 3 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
32 A.50/51G3.TMS 0.04~ 20 1 - 0.001
protection
33 A.50/51G3.tmin 0 ~10 0.02 s 0.001
34 A.50/51G3.K 0.001~120 0.14 - 0.0001
protection
35 A.50/51G3.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
36 A.50/51G3.C 0 ~1 0 - 0.0001
protection
37 A.50/51G4.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
38 A.50/51G4.t_Op 0 ~100 0.1 s 0.001
protection
39 A.50/51G4.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 4 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
44 A.50/51G4.TMS 0.04~ 20 1 - 0.001
protection
45 A.50/51G4.tmin 0 ~10 0.02 s 0.001
46 A.50/51G4.K 0.001~120 0.14 - 0.0001
protection
47 A.50/51G4.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
48 A.50/51G4.C 0 ~1 0 - 0.0001
protection
49 A.50/51G5.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
50 A.50/51G5.t_Op 0 ~100 0.1 s 0.001
protection
51 A.50/51G5.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 5 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
56 A.50/51G5.TMS 0.04~ 20 1 - 0.001
protection
57 A.50/51G5.tmin 0 ~10 0.02 s 0.001
58 A.50/51G5.K 0.001~120 0.14 - 0.0001
protection
59 A.50/51G5.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
60 A.50/51G5.C 0 ~1 0 - 0.0001
protection
61 A.50/51G6.3I0_Set 0.05~200 15 A 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
62 A.50/51G6.t_Op 0 ~100 0.1 s 0.001
protection
63 A.50/51G6.t_DropOut 0 ~100 0 s 0.001
protection
Disabled;
Enabled
protection
Enabling stage 6 of
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
IEC; protection.
IECE;
9
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
ropOut
dropout
dropout
68 A.50/51G6.TMS 0.04~ 20 1 - 0.001
protection
69 A.50/51G6.tmin 0 ~10 0.02 s 0.001
70 A.50/51G6.K 0.001~120 0.14 - 0.0001
protection
71 A.50/51G6.Alpha 0.01 ~3 0.02 - 0.0001
protection
9
72 A.50/51G6.C 0 ~1 0 - 0.0001
protection
9.2.4 Negative-sequence Overcurrent Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  NegOC Settings

Date: 2019-04-24
9 Settings
Table 9.2-4 Settings of negative-sequence overcurrent protection
Default
value
1 50/51Q.DIR.RCA -180~179 45 deg 1
element of negative-sequence
50/51Q.DIR.phi_Min_ forward direction element of
2 10~90 90 deg 1
Fwd negative-sequence
50/51Q.DIR.phi_Max forward direction element of
3 10~90 90 deg 1
_Fwd negative-sequence
50/51Q.DIR.phi_Min_ reverse direction element of
4 10~90 90 deg 1
Rev negative-sequence
50/51Q.DIR.phi_Max reverse direction element of
5 10~90 90 deg 1
_Rev negative-sequence
6 50/51Q.DIR.I_Min (0.05~1)In 0.05 - 0.001 control element of
negative-sequence
7 50/51Q.DIR.U_Min 1.0~10.0 4 V 0.001 control element of
negative-sequence
9

Date: 2019-04-24
9 Settings
Default
value
behavior of
negative-sequence
failure happens.
Disabled;
8 50/51Q.En_VTS_Blk Disabled - - Disabled: negative-sequence
Enabled
negative-sequence
overcurrent protection will be
blocked by VT circuit failure
signal
Non_Direction
negative-sequence
al Non_Directio
Forward nal
1: no direction;
Reverse
Disabled;
The logic setting
enabling/disabling the stage 1
for
9
Enabling stage 1 of
negative-sequence

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
18 50/51Q1.tmin 0 ~10 0.02 s 0.001
negative-sequence
9

Date: 2019-04-24
9 Settings
Default
value
Non_Direction
negative-sequence
al Non_Directio
Forward nal
1: no direction;
Reverse
Enabling stage 2 of
negative-sequence

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
ANSILTV;
ANSILT;
IECN;
IECV;
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
Inst;
IDMT
31 50/51Q2.tmin 0 ~10 0.02 s 0.001
negative-sequence
9

Date: 2019-04-24
9 Settings
Default
value
9.2.5 Sensitive Earth Fault Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  SEF Settings
Table 9.2-5 Settings of sensitive earth fault protection
Default
value
1 50/51SEF.DIR.RCA -180~179 45 deg 1 the direction control element of
50/51SEF.DIR.phi_Mi
n_Fwd
50/51SEF.DIR.phi_M
ax_Fwd
50/51SEF.DIR.phi_Mi
n_Rev
50/51SEF.DIR.phi_M
ax_Rev
6 50/51SEF.DIR.I_Min (0.05~1)In 0.05 - 0.001
protection 9
7 50/51SEF.DIR.U_Min 1.0~10.0 4 V 0.001
protection

Date: 2019-04-24
9 Settings
Default
value
behavior of sensitive earth fault
50/51SEF.En_VTS_Bl Disabled; Disabled: sensitive earth fault
8 Disabled - -
k Enabled protection will not effected by VT
circuit failure
will be blocked by VT circuit
failure signal
9 50/51SEF1.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF1.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
15 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF1.Opt_Curv
e_DropOut
protection
9
protection
protection

Date: 2019-04-24
9 Settings
Default
value
protection
22 50/51SEF2.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF2.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
9 28
50/51SEF2.Opt_Curv
e
ANSILT;
IECN;
IECDefTi
me
- -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
50/51SEF2.Opt_Curv
e_DropOut
protection
protection
protection
protection
35 50/51SEF3.3I0_Set 0.005~2 1 A 0.001
protection
9
50/51SEF3.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2019-04-24
9 Settings
Default
value
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
41 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF3.Opt_Curv
e_DropOut
protection
9
protection

Date: 2019-04-24
9 Settings
Default
value
protection
protection
48 50/51SEF4.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF4.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm

Date: 2019-04-24
9 Settings
Default
value
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
54 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF4.Opt_Curv
e_DropOut
protection
9
protection
protection

Date: 2019-04-24
9 Settings
Default
value
protection
61 50/51SEF5.3I0_Set 0.005~2 1 A 0.001
protection
50/51SEF5.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
67
50/51SEF5.Opt_Curv
e
ANSILT;
IECN;
IECDefTi
me
- -
9
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2019-04-24
9 Settings
Default
value
50/51SEF5.Opt_Curv
e_DropOut
protection
protection
protection
protection
74 50/51SEF6.3I0_Set 0.005~2 1 A 0.001
9 75 50/51SEF6.t_Op 0 ~100 0.1 s 0.001 stage 6 of sensitive earth fault

protection
50/51SEF6.t_DropOu
t
protection
Non_Dire
ctional
Disabled;
Enabled

Date: 2019-04-24
9 Settings
Default
value
Alm Alm
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE;
80 - -
IEC;
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
50/51SEF6.Opt_Curv
e_DropOut
protection
83 50/51SEF6.tmin 0 ~10 0.02 s 0.001

setting of stage 6 of sensitive
9
protection

Date: 2019-04-24
9 Settings
Default
value
protection
protection
9.2.6 RMS Overcurrent Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  RMS OC Settings
Table 9.2-6 Settings of RMS overcurrent protection
Default
value
1 50/51R1.I_Set 0.05~200 15 A 0.001
2 50/51R1.t_Op 0 ~100 0.1 s 0.001
3 50/51R1.t_DropOut 0 ~100 0 s 0.001
9 6 50/51R2.I_Set 0.05~200 15 A 0.001
7 50/51R2.t_Op 0 ~100 0.1 s 0.001
8 50/51R2.t_DropOut 0 ~100 0 s 0.001

Date: 2019-04-24
9 Settings
Default
value
9.2.7 Phase Overvoltage Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  OV Settings
Table 9.2-7 Settings of phase overvoltage protection
Default
value
voltage or phase voltage for
Up; overvoltage protection
1 59P.Opt_Up/Upp Upp - -
Upp Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode or
3-out-of-3 mode for
3P;
2 59P.Opt_1P/3P 3P - - overvoltage protection
1P
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
protection
overvoltage protection 9
protection

Date: 2019-04-24
9 Settings
Default
value
Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
DefTime protection
dropout
11 59P1.TMS 0.04~ 20 1 - 0.001 stage 1 of phase
stage 1 of phase
9 14 59P1.Alpha 0.01 ~3 1 - 0.0001 operation characteristic of

stage 1 of phase
stage 1 of phase
protection

Date: 2019-04-24
9 Settings
Default
value
protection
Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
InvTime_U
protection.
DefTime protection
dropout
24 59P2.TMS 0.04~ 20 1 - 0.001

stage 2 of phase
9
stage 2 of phase

Date: 2019-04-24
9 Settings
Default
value
stage 2 of phase
stage 2 of phase
9.2.8 Residual Overvoltage Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  ROV Settings
Table 9.2-8 Settings of residual overvoltage protection
Default
value
Option of measured residual voltage or
calculated residual voltage for residual
Ext;
1 59G.Opt_3U0 Cal - - overvoltage protection
Cal
Ext: the measured residual voltage
Cal: the calculated residual voltage
2 59G1.3U0_Set 1~200 50 V 0.001
3 59G1.K_DropOut 0.93 ~1 0.98 - 0.001
4 59G1.t_Op 0.1 ~100 1 s 0.001
5 59G1.t_DropOut 0 ~100 0 s 0.001
9 The logic setting for enabling/disabling the
1: enabling
8 59G2.3U0_Set 1~200 50 V 0.001

Date: 2019-04-24
9 Settings
Default
value
9 59G2.K_DropOut 0.93 ~1 0.98 - 0.001
10 59G2.t_Op 0.1 ~100 1 s 0.001
11 59G2.t_DropOut 0 ~100 0 s 0.001
The logic setting for enabling/disabling the
1: enabling
9.2.9 Negative-sequence Overvoltage Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  NegOV Settings
Table 9.2-9 Settings of negative-sequence overvoltage protection

1 59Q1.U2_Set 2~100 15 V 0.001
protection
3 59Q1.t_Op 0.1~100 1 s 0.001
4 59Q1.t_DropOut 0~100 0 s 0.001
9
7 59Q2.U2_Set 2~100 15 V 0.001
protection

Date: 2019-04-24
9 Settings

9 59Q2.t_Op 0.1~100 1 s 0.001
10 59Q2.t_DropOut 0~100 0 s 0.001
9.2.10 Positive-sequence Overvoltage Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  PosOV Settings
Table 9.2-10 Settings of positive-sequence overvoltage protection

1 59Pos.U1_Set 2~100 60 V 0.001
The dropout coefficient setting of the
2 59Pos.K_DropOut 0.93~1 0.98 - 0.001
The time setting of the positive-sequence
3 59Pos.t_Op 0.1~100 1 s 0.001
The dropout time setting of the
4 59Pos.t_DropOut 0~100 0 s 0.001
Disabled; The logic setting of the positive-sequence
5 59Pos.En Enabled - -
Enabled overvoltage protection
Enabling the positive-sequence
6 59Pos.Opt_Trp/Alm Trp - -
9.2.11 Phase Undervoltage Protection Settings

9  Access path:
MainMenu  Settings  Protection Settings  UV Settings

Date: 2019-04-24
9 Settings
Table 9.2-11 Settings of phase undervoltage protection
Default
value
voltage or phase voltage
for stage x of
Up;
1 27P.Opt_Up/Upp Upp - - undervoltage protection
Upp
Up: phase voltage
Upp: phase-to-phase
voltage
Option of 1-out-of-3 mode
or 3-out-of-3 mode for
3P; stage x of undervoltage
2 27P.Opt_1P/3P 3P - -
1P protection
3P: 3-out-of-3 mode
1P: 1-out-of-3 mode
Breaker closed position
check mode
None: no check
Curr: check the current
None; CBPos: check the
Curr; normally open auxiliary
3 27P.Opt_LogicMode CBPos; Curr - - contact
CurrOrCBPos; CurrOrCBPos: check the
CurrAndCBPos current and normally open
auxiliary contact
CurrAndCBPos: check the
current or normally open
auxiliary contact
5 27P1.K_DropOut 1~1.2 1.03 - 0.001 stage 1 of phase 9

Date: 2019-04-24
9 Settings
Default
value
phase undervoltage
Disabled;
Enabled
failure happens.
circuit failure
0: disabling
1: enabling
Trp;
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
stage 1 of phase
InvTime_U
stage 1 of phase
Inst;
9
DefTime
Inst: instantaneous
dropout
dropout
13 27P1.TMS 0.04~ 20 1 - 0.001 of stage 1 of phase

Date: 2019-04-24
9 Settings
Default
value
14 27P1.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
protection
stage 1 of phase
stage 1 of phase
stage 1 of phase
9
phase undervoltage
Disabled;
Enabled
failure happens.
circuit failure

Date: 2019-04-24
9 Settings
Default
value
0: disabling
1: enabling
Trp;
24 27P2.Opt_Trp/Alm Trp - operate to trip or alarm.
Alm
ANSIDefTime;
IECDefTime;
UserDefine;
stage 2 of phase
InvTime_U
stage 2 of phase
Inst;
DefTime
Inst: instantaneous
dropout
dropout
27 27P2.TMS 0.04~ 20 1 0.001 of stage 2 of phase
28 27P2.tmin 0.03 ~10 0.03 s 0.001
phase undervoltage
9 protection
stage 2 of phase
stage 2 of phase

Date: 2019-04-24
9 Settings
Default
value
stage 2 of phase
9.2.12 Frequency Protection Settings

 Access path:
Table 9.2-12 Settings of overfrequency protection

2 81O1.f_Set 50~65 52 Hz 0.001
3 81O1.t_Op 0.1~100 0.3 s 0.001
5 81O2.f_Set 50~65 52 Hz 0.001
6 81O2.t_Op 0.1~100 0.3 s 0.001
8 81O3.f_Set 50~65 52 Hz 0.001
9 81O3.t_Op 0.1~100 0.3 s 0.001
9
11 81O4.f_Set 50~65 52 Hz 0.001
12 81O4.t_Op 0.1~100 0.3 s 0.001
14 81O5.f_Set 50~65 52 Hz 0.001

Date: 2019-04-24
9 Settings

15 81O5.t_Op 0.1~100 0.3 s 0.001
17 81O6.f_Set 50~65 52 Hz 0.001
18 81O6.t_Op 0.1~100 0.3 s 0.001
26 81U1.f_Set 45~60 48 Hz 0.001
27 81U1.t_Op 0.1~100 0.3 s 0.001
29 81U2.f_Set 45~60 48 Hz 0.001
30 81U2.t_Op 0.1~100 0.3 s 0.001
32 81U3.f_Set 45~60 48 Hz 0.001
33 81U3.t_Op 0.1~100 0.3 s 0.001
35 81U4.f_Set 45~60 48 Hz 0.001
36 81U4.t_Op 0.1~100 0.3 s 0.001
9 Enabled underfrequency protection
38 81U5.f_Set 45~60 48 Hz 0.001
39 81U5.t_Op 0.1~100 0.3 s 0.001
41 81U6.f_Set 45~60 48 Hz 0.001
42 81U6.t_Op 0.1~100 0.3 s 0.001

Date: 2019-04-24
9 Settings

The rate-of-change setting of the stage x of
44 81R1.df/dt_Set -5~5 0.5 Hz/s 0.001
The time setting of the stage x of frequency
45 81R1.t_Op 0.1~100 0.1 s 0.001
The pickup frequency setting of the stage x
46 81R1.f_Pkp 45~65 50 Hz 0.001
Disabled; The logic setting of the stage x of frequency
48 81R2.df/dt_Set -5~5 0.5 Hz/s 0.001
49 81R2.t_Op 0.1~100 0.1 s 0.001
50 81R2.f_Pkp 45~65 50 Hz 0.001
52 81R3.df/dt_Set -5~5 0.5 Hz/s 0.001
53 81R3.t_Op 0.1~100 0.1 s 0.001
54 81R3.f_Pkp 45~65 50 Hz 0.001
56 81R4.df/dt_Set -5~5 0.5 Hz/s 0.001
57 81R4.t_Op 0.1~100 0.1 s 0.001
58 81R4.f_Pkp 45~65 50 Hz 0.001
Enabled rate-of-change protection 9
60 81R5.df/dt_Set -5~5 0.5 Hz/s 0.001
61 81R5.t_Op 0.1~100 0.1 s 0.001
62 81R5.f_Pkp 45~65 50 Hz 0.001
64 81R6.df/dt_Set -5~5 0.5 Hz/s 0.001

Date: 2019-04-24
9 Settings

65 81R6.t_Op 0.1~100 0.1 s 0.001
66 81R6.f_Pkp 45~65 50 Hz 0.001
9.2.13 Reverse Power Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  RevPower Settings
Table 9.2-13 Settings of reverse power protection

1 32R.U1_VCE 5~60 5 V 0.001 positive-sequence voltage control element
The positive-sequence current setting of
2 32R.I1_CCE 0.01~1 0.1 p.u. 0.001 the current control element of the reverse
power protection
3 32R.U2_VCE 8~60 8 V 0.001 negative-sequence voltage control element
4 32R1.P_Set 0.1~10 0.15 p.u. 0.001
power protection
5 32R1.t_Op 0.01~100 0.1 s 0.001
power protection
9 8 32R2.P_Set 0.1~10 0.15 p.u. 0.001
power protection
9 32R2.t_Op 0.01~100 0.1 s 0.001
power protection

Date: 2019-04-24
9 Settings
9.2.14 Cold Load Pickup Logic Settings

 Access path:
MainMenu  Settings  Protection Settings  CLP Settings
Table 9.2-14 Settings of cold load pickup logic

The setting for selecting the cold load
Curr;
1 CLP.Opt_LogicMode CBPos - - initiation condition.
CBPos
Curr: current; CBPos: CB position.
The time setting for ensuring the cold
2 CLP.t_Cold 0~4000 3 s 0.001
load condition is met
The time setting for resetting the cold
3 CLP.t_Rst 0~4000 3 s 0.001
load pickup logic
The time setting for fast resetting the cold
4 CLP.t_ShortRst 0~600 1 s 0.001
load pickup logic
Disabled; The logic setting of the cold load pickup
5 CLP.En Enabled - -
Enabled logic function
active
active
is active
when CLP is active
when CLP is active
11 50/51G1.CLP.TMS 0.05~100 1 s 0.001

of zero-sequence IDMT overcurrent
9
active
active

Date: 2019-04-24
9 Settings

is active
when CLP is active
when CLP is active
active
active
is active
when CLP is active
when CLP is active
active
9 25 50/51P4.CLP.t_Op 0~100 0.1 s 0.001

overcurrent protection when CLP is
active
is active
when CLP is active

Date: 2019-04-24
9 Settings

when CLP is active
active
active
is active
when CLP is active
when CLP is active
active
active
is active
39 50/51G6.CLP.IMult 1~10 1 - 0.001

zero-sequence overcurrent protection
9
when CLP is active
when CLP is active

Date: 2019-04-24
9 Settings
9.2.15 Undercurrent Settings

 Access path:
MainMenu  Settings  Protection Settings  UC Settings
Table 9.2-15 Settings of undercurrent protection

The current setting of the
1 37.I_Set 0.1~5 0.5 A 0.001
undercurrent protection
The time setting of the undercurrent
2 37.t_Op 0.1~100 0.1 s 0.001
protection
1P;
3 37.Opt_1P/3P 3P - - three-phase criterion (3P) or
3P
single-phase criterion (1P)
None;
Curr;
CurrAnd The setting of the CB position check
4 37.Opt_LogicMode CBPos; - -
CBPos mode.
CurrAndCBPos;
CurrOrCBPos
Disabled; The logic setting of the undercurrent
5 37.En Enabled - -
Enabled protection
Enabling undercurrent protection
Trp; operate to trip or alarm.
6 37.Opt_Trp/Alm Trp - -
9.2.16 Breaker Failure Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  BFP Settings
Table 9.2-16 Settings of breaker failure protection

The phase current setting of breaker
9 1 50BF.I_Set 0.05~200 1.000 A 0.001
failure protection
The zero-sequence current setting of
2 50BF.3I0_Set 0.05~200 1.000 A 0.001
The negative-sequence current setting of
3 50BF.I2_Set 0.05~200 1.000 A 0.001
The re-trip time delay of breaker failure
4 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
5 50BF.t1_Op 0~20 0.100 s 0.001
protection

Date: 2019-04-24
9 Settings
The second time delay of breaker failure

6 50BF.t2_Op 0~20 0.200 s 0.001
protection
Disabled Enabling/disabling breaker failure
7 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
8 50BF.En_ReTrp Enabled - -
Disabled Enabling/disabling first time delay of
Disabled Enabling/disabling second time delay of
Enabling/disabling phase overcurrent
Disabled
11 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
three-phases initiating signal
12 50BF.En_3I0_3P Disabled - -
signal
Enabling/disabling negative-sequence
13 50BF.En_I2_3P Disabled - -
signal
Enabling/disabling breaker failure
Disabled
14 50BF.En_CB_Ctrl Disabled - - protection be initiated by normally closed
Enabled
contact of circuit breaker
Disabled Enabling/disabling abnormality check of
15 50BF.En_Alm_Init Disabled - -
Enabled breaker failure initiating signal
9.2.17 Switch-on-to-Fault ProtectionSettings

 Access path:
MainMenu  Settings  Protection Settings  SOTF Settings
Table 9.2-17 Settings of SOTF protection

The initiating time for the SOTF 9
1 SOTF.t_En 0.2~100 3 s 0.001
protection
Option of manual SOTF mode
ManClsBI:initiated by input signal of
ManClsBI
manual config
SOTF.Opt_Mode_Man CBPos
2 CBPos - - CBPos:initiaed by CB position
Cls ManClsBI/
ManClsBI/CBPos:initiated by either
CBPos
input signal of manual closing or CB
postition

Date: 2019-04-24
9 Settings
Current setting of phase overcurrent

3 50PSOTF.I_Set 0.05~200 1 A 0.001
SOTF protection
Voltage setting for phase
4 50PSOTF.Up_Set 0~200 1 V 0.001
Voltage setting for phase-to-phase
5 50PSOTF.Upp_Set 0~200 1 V 0.001
Voltage setting for negative-sequence
6 50PSOTF.U2_Set 0~200 1 V 0.001
Voltage setting for zero-sequence
7 50PSOTF.3U0_Set 0~200 1 V 0.001
Time delay for phase overcurrent
8 50PSOTF.t_Op 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling phase overcurrent
9 50PSOTF.En Enabled - -
Enabled SOTF protection
Enabling/disabling second harmonic
Disabled
10 50PSOTF.En_Hm2_Blk Enabled - - blocking for phase overcurrent SOTF
Enabled
protection
Enabling/disabling phase
Disabled
11 50PSOTF.En_Up_UV Enabled - - undervoltage supervision logic for
Enabled
Enabling/disabling phase-to-phase
Disabled
12 50PSOTF.En_Upp_UV Enabled - - undervoltage supervision logic for
Enabled
Enabling/disabling
Disabled negative-sequence overvoltage
13 50PSOTF.En_U2_OV Enabled - -
Enabled supervision logic for phase
Disabled
14 50PSOTF.En_3U0_OV Enabled - - overvoltage supervision logic for
Enabled
The option of the residual current
used by earth fault overcurrent SOTF
Ext
15 50GSOTF.Opt_3I0 Cal - - protection
Cal
9 Ext: the measured residual current
Cal: the calculated residual current
Current setting of earth fault
16 50GSOTF.3I0_Set 0.05~200 1 A 0.001
Time delay for earth fault overcurrent
17 50GSOTF.t_Op_3P 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling earth fault
18 50GSOTF.En Enabled - -
Enabled overcurrent SOTF protection
Enabling/disabling earth fault
Disabled
19 50GSOTF.En_Hm2_Blk Disabled - - overcurrent SOTF protection blocked
Enabled
by harmonic

Date: 2019-04-24
9 Settings
9.2.18 Unbalance Current Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  UnbalCurr Settings
Table 9.2-18 Settings of unbalance current protection

1 60/50-1.I_Set 0.02~200 1 A 0.001
2 60/50-1.t_Op 0.05~100 0.1 s 0.001
3 60/50-1.En Enabled - -
5 60/50-2.I_Set 0.02~200 1 A 0.001
6 60/50-2.t_Op 0.05~100 0.1 s 0.001
7 60/50-2.En Enabled - -
9.2.19 Unbalance Voltage Protection Settings

 Access path:
MainMenu  Settings  Protection Settings  UnbalVolt Settings
Table 9.2-19 Settings of unbalance voltage protection
No. Setting Range Default Unit Step Description 9

1 60/59-1.U_Set 1~63.5 50 V 0.001
2 60/59-1.t_Op 0.1~100 1 s 0.001
3 60/59-1.En Enabled - -

Date: 2019-04-24
9 Settings

5 60/59-2.U_Set 1~63.5 50 V 0.001
6 60/59-2.t_Op 0.1~100 1 s 0.001
7 60/59-2.En Enabled - -
9.2.20 Fault Location Settings

 Access path:
MainMenu  Settings  Protection Settings  FL Settings
Table 9.2-20 Settings of fault location
Default
value
Positive-sequence reactance of the whole
1 X1L (0~4Unn)/In 10 Ω 0.001
line (secondary value)
Positive-sequence resistance of the whole
2 R1L (0~4Unn)/In 1 Ω 0.001
Zero-sequence reactance of the whole
3 X0L (0~4Unn)/In 20 Ω 0.001
Zero-sequence resistance of the whole
4 R0L (0~4Unn)/In 3 Ω 0.01
5 LineLength 0~1000 100 km 0.01 Total length of the whole line
9.3 Measurement and Control Settings

9
In this section, the "XXXX" stands for bay indication. By default, it could be
BayMMXU, BusMMXU, etc. and it is configurable through the configuration
tool PCS-Studio.
9.3.1 Function Settings

 Access path:

Date: 2019-04-24
9 Settings
Main Menu  Settings  Meas Control Settings  Function Settings
No. Setting Default Range Step Unit Remark

Ia-Ib-Ic or
1 Opt_CT_Measmt Ia-Ib-Ic - - Source selection of current measurement
Ia-Ic
2 ZeroDrift_U 0.20 0.00~1.00 0.01 %

Threshold to limit the zero-drift influence of
voltage, current or power due to temperature or
3 ZeroDrift_I 0.20 0.00~1.00 0.01 % other environmental factors. A measured value
less than this setting will be regarded as a zero
drift and ignored.
4 ZeroDrift_PQ 0.50 0.00~1.00 0.01 %
5 Neu.ZeroDrift_I 0.20 0.00~1.00 0.01 % Threshold to limit the zero-drift influence of

6 Neu2.ZeroDrift_I 0.20 0.00~1.00 0.01 % corresponding current due to temperature or
other environmental factors. A measured value
7 60/50.ZeroDrift_I 0.20 0.00~1.00 0.01 % less than this setting will be regarded as a zero
drift and ignored.
8 Delt.ZeroDrift_U 0.20 0.00~1.00 0.01 % Threshold to limit the zero-drift influence of
9 Syn.ZeroDrift_U 0.20 0.00~1.00 0.01 % corresponding voltage due to temperature or

other environmental factors. A measured value
10 60/59.ZeroDrift_U 0.20 0.00~1.00 0.01 % less than this setting will be regarded as a zero
drift and ignored.
9.3.2 Synchronism Check Settings

 Access path:
Main Menu  Settings  Meas Control Settings  Syn Settings

Selection of circuit
NoVolSel, DblBusOneCB,
1 Opt_CBConfig NoVolSel - - breaker arrangement
3/2BusCB, 3/2TieCB
for voltage selection
Selection of decision
2 25.Opt_ValidMode Setting Setting or Config - - mode for synchronism
check
Logic setting for 9
synchro-check (valid
3 25.En_SynChk Enabled Disabled or Enabled - - only if the setting
Setting)
Logic setting for dead
charge check (valid
4 25.En_DdChk Enabled Disabled or Enabled - - only if the setting
Setting)

Date: 2019-04-24
9 Settings

5 25.U_UV 80.00 0~100 0.01 % of under voltage for
CB closing blocking
6 25.U_OV 170.00 100~170 0.01 % of over voltage for CB
closing blocking
7 25.f_UF 45.000 45~65 0.001 Hz of under frequency for
CB closing blocking
8 25.f_OF 65.000 45~65 0.001 Hz of over frequency for
CB closing blocking
Selection of voltage
9 25.Opt_U_SynChk Ua Ua, Ub, Uc, Uab, Ubc, Uca - -
Threshold of voltage
10 25.U_Diff_Set 10.00 0~100 0.01 V difference for
synchronism check
Logic setting for
11 25.En_f_Diff_Chk Enabled Disabled or Enabled - - frequency difference
check
Threshold of
12 25.f_Diff_Set 0.50 0~2 0.01 Hz frequency difference
Logic setting for
13 25.En_df/dt_Chk Enabled Disabled or Enabled - - frequency variation
difference check
Threshold of
14 25.df/dt_Set 1.00 0~2 0.01 Hz/s frequency variation for
synchronism check.
Threshold of phase
15 25.phi_Diff_Set 15.00 0~180 0.01 ° difference for
synchronism check
9 16 25.phi_Comp 0.00 0~360 0.01 °

Compensation angle
of phase difference for
synchronism check
SynDdRefDd
SynLvRefDd
SynDdRefLv
Selection of dead
17 25.Opt_Mode_DdChk AnySideDd RefDd - -
charge check mode
SynDd
SynLvRefDd/SynDdRefLv
AnySideDd
18 25.U_DdChk 17.32 0~100 0.01 V Threshold for voltage

Date: 2019-04-24
9 Settings

dead check
19 25.U_LvChk 34.64 0~100 0.01 V
live check
Threshold of duration
20 25.t_Reset 5 0~60 1 s
for synchro-check
Circuit breaker closing
time. It is the time
from receiving closing
21 25.t_Close_CB 20 0~2000 1 ms
command pulse till the
CB is completely
closed.
9.3.3 Double Point Status Settings

 Access path:
Main Menu  Settings  Meas Control Settings  DPS Settings

1 Breaker.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of the circuit
breaker
2 Breaker.DPS.En_Alm Disabled - -
Enabled circuit breaker
3 Breaker.DPS.t_Alm 500 0~60000 1 ms
the circuit breaker
4 Switch01.DPS.t_DPU 500 0~60000 1 ms
debounce time, for DPS of switch 01
Disabled or Logic setting for DPS alarm of switch
5 Switch01.DPS.En_Alm Disabled - -
Enabled 01
6 Switch01.DPS.t_Alm 500 0~60000 1 ms
switch 01
8 Switch02.DPS.En_Alm Disabled
Disabled or
- -
Logic setting for DPS alarm of switch 9
Enabled 02
switch 02
Enabled 03
switch 03

Date: 2019-04-24
9 Settings

Enabled 04
switch 04
Enabled 05
switch 05
Enabled 06
switch 06
Enabled 07
switch 07
Enabled 08
switch 08
9 Enabled 09
switch 09
9.3.4 Control Settings

 Access path:
Main Menu  Settings  Meas Control Settings  Control Settings

1 Breaker.t_PW_Opn 500 0~60000 1 ms Pulse Width (PW), i.e. holding time, for opening

Date: 2019-04-24
9 Settings

output of the circuit breaker
Pulse Width (PW), i.e. holding time, for closing
2 Breaker.t_PW_Cls 500 0~60000 1 ms
output of the circuit breaker
Pulse Width (PW), i.e. holding time, for direct
3 Switch01.t_PW_Opn 500 0~60000 1 ms
opening output of switch 01
4 Switch01.t_PW_Cls 500 0~60000 1 ms
closing output of switch 01
5 Switch02.t_PW_Opn 500 0~60000 1 ms
6 Switch02.t_PW_Cls 500 0~60000 1 ms
7 Switch03.t_PW_Opn 500 0~60000 1 ms
8 Switch03.t_PW_Cls 500 0~60000 1 ms
9 Switch04.t_PW_Opn 500 0~60000 1 ms
10 Switch04.t_PW_Cls 500 0~60000 1 ms
11 Switch05.t_PW_Opn 500 0~60000 1 ms
12 Switch05.t_PW_Cls 500 0~60000 1 ms
13 Switch06.t_PW_Opn 500 0~60000 1 ms
14 Switch06.t_PW_Cls 500 0~60000 1 ms
15 Switch07.t_PW_Opn 500 0~60000 1 ms
16 Switch07.t_PW_Cls 500 0~60000 1 ms
9
17 Switch08.t_PW_Opn 500 0~60000 1 ms
18 Switch08.t_PW_Cls 500 0~60000 1 ms
19 Switch09.t_PW_Opn 500 0~60000 1 ms
20 Switch09.t_PW_Cls 500 0~60000 1 ms
9.3.5 Interlocking Logic Settings

 Access path:

Date: 2019-04-24
9 Settings
Main Menu  Settings  Meas Control Settings  Interlock Settings

Disabled or
1 Breaker.En_CILO_Opn Disabled - - control of opening output of the circuit
Enabled
breaker.
Disabled or
2 Breaker.En_CILO_Cls Disabled - - control of closing output of the circuit
Enabled
breaker.
Disabled or
3 Switch01.En_CILO_Opn Disabled - - control of direct opening output of
Enabled
switch 01.
Disabled or
4 Switch01.En_CILO_Cls Disabled - - control of direct closing output of
Enabled
switch 01.
Disabled or
Enabled
switch 02.
Disabled or
Enabled
switch 02.
Disabled or
Enabled
switch 03.
Disabled or
Enabled
switch 03.
Disabled or
Enabled
switch 04.
Disabled or
Enabled
switch 04.
9 11 Switch05.En_CILO_Opn Disabled
Disabled
Enabled
or
- - control of direct opening output of
switch 05.
Disabled or
Enabled
switch 05.
Disabled or
Enabled
switch 06.
Disabled or Logic setting for interlocking logic
14 Switch06.En_CILO_Cls Disabled - -
Enabled control of direct closing output of

Date: 2019-04-24
9 Settings

switch 06.
Disabled or
Enabled
switch 07.
Disabled or
Enabled
switch 07.
Disabled or
Enabled
switch 08.
Disabled or
Enabled
switch 08.
Disabled or
Enabled
switch 09.
Disabled or
Enabled
switch 09.
9.4 Logic Links
Logic link is a special logic setting which can be configured through local HMI or remote PC.
These logic links provide a convenient way for the operator to put the function in service or out of
service remotely away from an unattended substation.
9.4.1 GOOSE Receiving Links

 Access path:
MainMenu  Settings  Logic Links  GOOSE Recv Links
Table 9.4-1 GOOSE receiving links
No. Settings Range

Default
Remark
9
value
@Bx.Name_000_GCommLink. Disabled
1 Enabled GOOSE receiving link 000 is enabled or disabled
GLink_Recv Enabled
Disabled
2 …… Enabled ……
Enabled
@Bx.Name_127_GCommLink. Disabled
3 Enabled GOOSE receiving link 127 is enabled or disabled
GLink_Recv Enabled
@Bx.Name_000_GCommLink is the set value of the label setting of [Bx.Name_000_GCommLink],

Date: 2019-04-24
9 Settings
@Bx.Name_127_GCommLink is the set value of the label setting of

[Bx.Name_127_GCommLink].

Date: 2019-04-24
Appendix A Glossary
Appendix A Glossary
The abbreviations adopted in this manual are listed as below.
A BOM Binary Output Module
"a" Contact is breaker auxiliary contact (ANSI C

Standard Device Number 52A) that closes
when the breaker is closed and opens when C37.94 IEEE/ANSI protocol used when
the breaker is open. sending binary signals between IEDs
AC Alternating current CB Circuit breaker
A/D converter Analog-to-digital converter CID Configured IED Description
AI Analog input COMTRADE Standard Common Format for

Transient Data Exchange format for
ANSI American National Standards Institute
Disturbance recorder according to IEEE/ANSI
AR Autoreclosing C37.111, 1999 / IEC 60255-24
ASDU Application Service Data Unit – An CPU Central Processing Unit

ASDU can consist of one or more identical
CRC Cyclic Redundancy Check
information objects. A sequence of the same
information elements, for example measured CT Current Transformer
values, is identified by the address of the
CTS Current Circuit Supervision
information object. The address of the
information object defines the associated
D
address of the first information element of the
sequence. A consecutive number identifies the
DBDL Dead Bus Dead Line
subsequent information elements. The number
builds on this address in integral increments DBLL Dead Bus Live Line
(+1).
DC Direct Current
B DLLB Dead Line Live Bus
DNP Distributed Network Protocol as per IEEE

"b" Contact is breaker auxiliary contact (ANSI
Std 1815-2012
Standard Device Number 52B) that closes
when the breaker is open and opens when the DPFC Deviation of Power Frequency
breaker is closed. Component–In case of a fault occurred in the
power system, the fault component could be
BFP Breaker failure protection
analyzed into three parts: the power frequency
BI Binary Input components before the fault, the power
frequency variables during the fault and the
BO Binary Output
transient variables during the fault. DPFC is A
BIM Binary Input Module the power frequency variable during the fault.
PCS-9611S Feeder Relay 1

Date: 2019-04-24
Appendix A Glossary
DSP Digital Signal Processor L

DTT Direct Transfer Trip Scheme
LCD Liquid Crystal Display
E LED Light-emitting Diode
EHV Extra High Voltage M

EMC Electromagnetic Compatibility
MCB Miniature Circuit Breaker
F MMS Manufacturing Message Specification
MOV Metal-oxide Varistor

FL Fault Location
FR Fault Recorder O
G OLTC On-load Tap Changer
OOS Out-of-Step
G.703 Electrical and functional description for
digital lines used by local telephone
P
companies. Can be transported over balanced
and unbalanced lines
PD Pole Discrepancy
GIS Gas-insulated Switchgear
PDTT Permissive Direct Transfer Trip
GOOSE Generic Object-Oriented Substation
PL Programmable Logic
Event
POTT Permissive Overreaching Transfer Trip
GPS Global Positioning System
PPM Pulse Per Minute
H
PPS Pulse Per Second
HMI Human-machine Interface PRP Parallel Redundancy Protocol
HSR High-availability Seamless Redundancy PUTT Permissive Underreaching Transfer Trip
HV High-voltage
R
HVDC High-voltage Direct Current
RMS Root Mean Square
I
RSTP Rapid Spanning Tree Protocol
ICD IED Capability Description RTD Resistance Temperature Detector
IEC International Electrotechnical Commission RTU Remote Terminal Unit
IED Intelligent Electronic Device

S
A IRIG-B InterRange Instrumentation Group
Time code format B SA Substation Automation
2 PCS-9611S Feeder Relay

Date: 2019-04-24
Appendix A Glossary
SCADA Supervision, Control And Data SOTF Switch-Onto-Fault

Acquisition
STP Rapid Spanning Tree Protocol
SCD Substation Configuration Description
T
SCL Substation Configuration Description
Language
TCS Trip Circuit Supervision
SLD Single-line Diagram
TCP/IP Transmission Control Protocol over
SIR Source-to-line Impedance Ratio Internet Protocol
SNMP Simple Network Management Protocol

U
–An Internet standard protocol and serves for
the administration of nodes in an IP network.
UTC Coordinated Universal Time
SNTP Simple Network Time Protocol – A
protocol for the synchronization of clocks via W
the Internet. With SNTP, client computers can
synchronize their clocks via the Internet with a WI Weak end infeed
time server.
V
SOE Sequence of Events – An ordered,
time-stamped log of status changes at binary
VT Voltage transformer
inputs (also referred to as state inputs). SOE is
used to restore or analyze the performance, or VTS Voltage Circuit Supervision
an electrical power system itself, over a certain
period of time.
A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:
21 Distance element 52 AC circuit breaker
25 Synchronism-check element 59 Overvoltage element
27 Undervoltage element 67 Directional overcurrent element
32 Power element 68 Power swing blocking element
37 Undercurrent element 78 Out-of-step element
46 Phase-balance current element 79 Reclosing element
49 Thermal overload element 81 Frequency element
50 Instantaneous overcurrent element 85 Pilot element
51 Definite-time or inverse-time overcurrent 87 Differential element

element
A
These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:
PCS-9611S Feeder Relay 3

Date: 2019-04-24
Appendix A Glossary
P Phase element N Neutral/Ground element
G Residual/Ground element Q Negative-sequence element
4 PCS-9611S Feeder Relay

Date: 2019-04-24

PCS-9611S - X - Technical Manual - EN - Overseas General - X - R1.01

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

PCS-9611S - X - Technical Manual - EN - Overseas General - X - R1.01

Uploaded by

Copyright:

Available Formats

Copyright © 2019 NR. All rights reserved.

About This Manual

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, may result

in minor or moderate injury or equipment damage.

Important information about the device, product handling or a certain

Instructions and Warnings

Disconnect or de-energize all external connections BEFORE opening this

PCS-9611S Feeder Relay I

can cause electrical shock resulting in injury or death.

This device is shipped with default passwords. Default passwords should

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical

DO NOT perform any procedures or adjustments that this instruction

During installation, maintenance, or testing of the optical ports, ONLY use

II PCS-9611S Feeder Relay

Incorporated components, such as LEDs, transceivers, and laser emitters,

Equipment components are SENSITIVE to electrostatic discharge (ESD).

Insufficiently rated insulation can deteriorate under abnormal operating

SEVERE power and ground problems can occur on the communications

Use of controls or adjustments, or performance of procedures other than

The firmware may be upgraded to add new features or enhance/modify

PCS-9611S Feeder Relay III

 Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection

 Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

 Cross-references are presented in italics.

For example: press the button "ENT".

& & &

>=1 >=1 >=1

 Binary signal Input

IV PCS-9611S Feeder Relay

Optional definite-time or inverse-time characteristics

Fixed delay pickup (10ms), fixed delay dropout (2ms)

Settable delay pickup, fixed delay dropout

Fixed delay pickup, settable delay dropout

Settable delay pickup, settable delay dropout

PCS-9611S Feeder Relay V

VI PCS-9611S Feeder Relay

Three-phase Corresponding Relationship

PCS-9611S Feeder Relay VII

Document Revision History

Current version: R1.01

R1.00 R1.00 2019-01-31  Form the original manual.

 Positive-sequence overvoltage protection is added;

VIII PCS-9611S Feeder Relay

1.1 Application ....................................................................................................... 1-1

Figure 1.1-1 Functional diagram of PCS-9611S ....................................................................... 1-1

PCS-9611S Feeder Relay 1-a

1-b PCS-9611S Feeder Relay

The function diagram of this relay is shown in Figure 1.1-1.

27P 59P 59Q VTS 59G 81U 81O 81R 25 79

50P 51P CTS 50BF 51Q

50G 51G SOTF 67G 37

51SEF 60/59 60/50 67SEF FR

Figure 1.1-1 Functional diagram of PCS-9611S

PCS-9611S Feeder Relay 1-1

ANSI Protection Functions Remark

1-2 PCS-9611S Feeder Relay