COMPUTER

ORGANIZATION
SEMESTER 3
UNIT - 1

HI COLLEGE
SYLLABUS
UNIT - 1

HI COLLEGE
 BOOLEAN ALGEBRA AND LOGIC:

1. Basics Laws of Boolean Algebra:

2. Logic Gates:
A logic gate is a digital gate that allows data to be transferred. Logic gates, use
logic to determine whether or not to pass a signal. Logic gates, on the other
hand, govern the flow of information based on a set of rules. The following types
of logic gates are commonly used:

TYPES OF LOGIC GATES

1. AND
2. OR
3. NOT
4. NOR
5. NAND
6. XOR
7. XNOR

HiCollege Click Here For More Notes 01

 BASIC LOGIC GATES

AND GATE
An AND gate has a single output and two or more inputs.
When all of the inputs are 1, the output of this gate is 1
The AND gate’s Boolean logic is Y=A.B if there are two inputs A and B.
An AND gate’s symbol and truth table are as follows:

SYMBOL OF AND GATE

Therefore, in And gate, the output is high when all the inputs are high.

HiCollege Click Here For More Notes 02

OR GATE
Two or more inputs and one output can be used in an OR gate.
1. The logic of this gate is that if at least one of the inputs is 1, the output will be 1
2. The OR gate’s output will be given by the following mathematical procedure
if there are two
inputs A and B: Y=A+B

SYMBOL OF OR GATE

Therefore, in the OR gate, the output is high when any of the inputs is high.

HiCollege Click Here For More Notes 03

NOT GATE
The NOT gate is a basic one-input, one-output gate.
When the input is 1, the output is 0, and vice versa. A NOT gate is sometimes
called an inverter because of its feature.
If there is only one input A, the output may be calculated using the Boolean
equation Y=A’.

SYMBOL OF NOT GATE

A NOT gate, as its truth table shows, reverses the input signal.

HiCollege Click Here For More Notes 04

 UNIVERSAL LOGIC GATES

NOR GATE
A NOR gate, sometimes known as a “NOT-OR” gate, consists of an OR gate
followed by a NOT gate.
1. This gate’s output is 1 only when all of its inputs are 0. Alternatively, when all
of the inputs are low, the output is high.
2. The Boolean statement for the NOR gate is Y=(A+B)’ if there are two inputs A
and B.

SYMBOL OF NOR GATE

The NOR gate is sometimes known as a universal gate since it may be used to
implement the OR, AND, and NOT gates.

HiCollege Click Here For More Notes 05

NAND GATE
A NAND gate, sometimes known as a ‘NOT-AND’ gate, is essentially a Not gate
followed by an AND gate.
1. This gate’s output is 0 only if none of the inputs is 0. Alternatively, when all of
the inputs are not high and at least one is low, the output is high.
2. If there are two inputs A and B, the Boolean expression for the NAND gate is
Y=(A.B)’

Symbol of NAND gate

The NAND gate is known as a universal gate because it may be used to
implement the AND, OR,
and NOT gates.

HiCollege Click Here For More Notes 06

 OTHER LOGIC GATES

XOR GATE
The Exclusive-OR or ‘Ex-OR’ gate is a digital logic gate that accepts more than
two inputs but only outputs one value.
1. If any of the inputs is ‘High,’ the output of the XOR Gate is ‘High.’ If both inputs
are ‘High,’ the output is ‘Low.’ If both inputs are ‘Low,’ the output is ‘Low.’
2. The Boolean equation for the XOR gate is Y=A’.B+A.B’ if there are two inputs A
and B.

SYMBOL OF XOR GATE

Its outputs are based on OR gate logic, as we can see from the truth table.

HiCollege Click Here For More Notes 07

XNOR GATE
The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that accepts more
than two inputs but only outputs one.
1. If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If both inputs
are ‘Low,’ the output is ‘High.’ If one of the inputs is ‘Low,’ the output is ‘Low.’
2. If there are two inputs A and B, then the XNOR gate’s Boolean equation is:
Y=A.B+A’B’.

SYMBOL OF XNOR GATE

The truth table shows that its outputs are based on NOR gate logic.

HiCollege Click Here For More Notes 08

 LOGIC GATES HAVE WIDESPREAD
APPLICATIONS:

1. Integrated Circuits (ICs): Logic gates are crucial components within ICs,
which are the building blocks of computers, smartphones, laptops, and
electronic devices.

2. Innovative Technologies: Logic gates can be combined in numerous ways to

create cutting-edge devices like gadgets, satellites, and robots.

3. Everyday Devices: Simple logic gate combinations play roles in everyday

items like burglar alarms, buzzers, switches, and street lights, making decisions
based on logic.

4. Data Handling: Logic gates are vital in data transport, calculations, and
processing. They are extensively used in technologies like transistor-transistor
logic and CMOS circuitry.

SIMPLIFICATIONS OF BOOLEAN EQUATIONS:

Karnaugh Maps (K-maps) help simplify Boolean expressions.

Sum-of-Products (SOP) and Product-of-Sums (POS) representations.
Grouping adjacent 1s in K-maps to find minimal expressions.

HiCollege Click Here For More Notes 09

 STEPS TO SIMPLIFY A BOOLEAN EXPRESSION
USING K-MAP

Choose the Right K-map:

Select a K-map that matches the number of variables you are working with.

Identify Terms:
Determine the minterms (for Sum of Products - SOP) or maxterms
(forProduct of Sums - POS) as given in the problem.

Fill the Grid:

In SOP, mark 1's in the K-map cells corresponding to the minterms; put
everywhere else. In POS, do the opposite: mark for maxterm cells and
elsewhere.

Create Groups:
Group adjacent 1's or 0's into rectangles. These groups should
contain a total number of terms that's a power of two (2, 4, 8, etc.),
except for 1.

Find Product Terms:

From the groups formed in step 4, determine the product termsand
combine them for the SOP form.

K-map SOP form for 3 variables

HiCollege Click Here For More Notes 10

Z= ∑A,B,C(1,3,6,7)
From red group we get product term— A’C
From green group we get product term— AB
Summing these product terms we get- Final expression (A’C+AB)

K-map for 4 variables –

K-map 4 variable SOP form
F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)

From red group we get product term

— QS
From green group we get product
term— Q’S’
Summing these product terms we
get-
Final expression (QS+Q’S’)

HiCollege Click Here For More Notes 11

POS FORM :

From red group we find terms - A B

Taking complement of these two - A’ B’
Now sum up them - (A’+ B’)

HiCollege Click Here For More Notes 12

From brown group we find terms - B C
Taking complement of these two terms - B’ C’
Now sum up them - (B’+C’)
From yellow group we find terms -A’ B’ C’
Taking complement of these two - A B C
Now sum up them - (A + B + C)
We will take product of these three terms : Final
expression –
(A’ + B’) (B’ + C’) (A + B + C)

K-MAP OF 4 VARIABLES –

HiCollege Click Here For More Notes 13

From green group we find terms - C’ D B
Taking their complement and summing them - (C+D’+B’)
From red group we find terms - C D A’
Taking their complement and summing them - (C’+D’+A)
From blue group we find terms - A C’ D’
Taking their complement and summing them - (A’+C+D)
From brown group we find terms -A B’ C
Taking their complement and summing them - (A’+B+C’)
Finally we express these as product –
(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)

PITFALL– *Always remember POS ≠ (SOP)’

*The correct form is (POS of F)=(SOP of F’)

HiCollege Click Here For More Notes 14

DON’T CARE CONDITION:
Don’t Care Conditions in K-Maps simplify digital circuits:
They represent undefined inputs as’’X’’,’’-” or ‘’Φ”
Enable larger groupings for simplification.
Can be treated as 1, 0, or ignored.
Convert SOP to POS with Don’t Cares.

Example-1 (SOP Minimal Form): Minimize the function: f = m(1, 5, 6, 11, 12, 13, 14) +
d(4)

Explanation: The SOP K-map for the expression is shown.

SOP minimal form is:
f = BC’+ BD’+ A’C’D + AB’CD

POS FORM :

Simplification of the Output: Don’t Care conditions help simplify the

Boolean output expression
of digital circuits.
Reduction in Gates: Simplification reduces the number of gates needed,
making digital circuit
design more cost-effective.

HiCollege Click Here For More Notes 15

 Reduced Power Consumption: Grouping terms with Don’t Care conditions
reduces state switching and consequently power consumption.
Representing Invalid States: Don’t Care conditions are used to represent
invalid input combinations in code converters, such as in a BCD to-XS-3
code converter.
Preventing Hazards: Don’t Care conditions also play a role in preventing
hazards in digital systems.

ARITHMETIC CIRCUITS:

1. ADDER:
Full Adder and Half Adder circuits.

Addition of binary numbers using these circuits.

Design of Half Adders and Full Adders:

A combinational logic circuit that performs the addition of two single bits is
called Half Adder.
A combinational logic circuit that performs the addition of three single bits
is called Full Adder.

1. Half Adder:

It is a arithmetic combinational logic circuit designed to perform addition of

two single bits.
It contain two inputs and produces two outputs.
Inputs are called Augend and Added bits and Outputs are called Sum and
Carry.

HiCollege Click Here For More Notes 16

Let us observe the addition of single bits,
0+0=0
0+1=1
1+0=1
1+1=1

Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,
0+0=00
0+1=01
1+0=01
1+1=10

The result of 1+1 is 10, where ‘1’ is carry-output (C out ) and ‘0’ is Sum-output
(Normal Output).

Truth Table of Half Adder:

Next Step is to draw the Logic Diagram.

To draw Logic Diagram, We need Boolean Expression, which can be
obtained using K-map (karnaugh map).
Since there are two output variables ‘S’ and ‘C’, we need to define K-map for
each output variable.
K-map for output variable Sum ‘S’:

HiCollege Click Here For More Notes 17

K-map is of Sum of products form.
The equation obtained is S = AB’ + A’B which can be logically written as,
S = A xor B
K-map for output variable Carry ‘C’:

The equation obtained from K-map is,

C = AB
Using the Boolean Expression, we can draw logic diagram as follows..

Limitations:
Adding of Carry is not possible in Half adder.

HiCollege Click Here For More Notes 18

FULL ADDER:

To overcome the above limitation faced with Half adders, Full Adders are
implemented.
It is a arithmetic combinational logic circuit that performs addition of three
single bits.
It contains three inputs (A, B, C in ) and produces two outputs (Sum and C
out ).
Where,C in Carry In and C out - Carry Out

K-map Simplification for output variable Sum ‘S’ :

The equation obtained is,

S = A’B’C in + AB’C in’ + ABC + A’BC in’
The equation can be simplified as,
S = B’(A’C in +AC in’) + B(AC + A’C in’)
S = B’;(A xor C in ) + B (A xor C in )'
S = A xor B xor C in

HiCollege Click Here For More Notes 19

K-map Simplification for output variable ‘C out ‘

The equation obtained is C out = BC in + AB + AC in

Logic Diagram of FullAdder:

1. Subtractor:

Full Subtractor and Half

Subtractor circuits.
Subtraction of binary numbers
using these circuits.

HiCollege Click Here For More Notes 20

 It is a combinational logic circuit designed to perform the subtraction of
two single bits.
 It contains two inputs (A and B) and produces two outputs (Difference and
Borrow-output).

Truth Table of Half Subtractor:

HiCollege Click Here For More Notes 21

The equation obtained is, D = A’B + AB’ which can be logically written as,
D = A xor B
K-map Simplification for output variable ‘B out ‘ :

The equation obtained from above K-map is,

B out = A’B

Logic Diagram of Half Subtractor:

HiCollege Click Here For More Notes 22

It is a Combinational logic circuit designed to perform subtraction of three
single bits.
 It contains three inputs(A, B, B in ) and produces two outputs (D, B out ).
 Where, A and B are called Minuend and Subtrahend bits.
 And, B in -> Borrow-In and B out -> Borrow-Out

Truth Table of Full Subtractor:

Obtained from above K-map is, D = A’B’B in + AB’B in’ + ABB in + A’BB in’
Which can be simplified as :
D = B’(A’B in + AB in’) + B(AB in + A’B in’)
D = B’(A xor B in ) + B(A xor B in )’
D = A xor B xor B in

HiCollege Click Here For More Notes 23

Subtractor Applications:
1. For performing arithmetic calculations in electronic calculators and other
digital devices.
2. In Timers and Program Counters.
3. Useful in Digital Signal Processing.

HiCollege Click Here For More Notes 24

2. Parallel Binary Adder/Subtractor:
Combining adder and subtractor circuits.
Parallel processing for both addition and subtraction.

Parallel Adder –
Parallel Adder performs binary addition with parallel processing using full
adders in a chain, with each
full adder managing a pair of bits and an input carry. This enables n-bit parallel
adders using n full
adders, with carry lookahead logic for faster addition.

Working of Parallel Adder –

As shown in the figure, firstly the full adder FA1 adds A1 and B1 along with
the carry C1 to generate the sum S1 (the first bit of the output sum) and the
carry C2 which is connected to the next adder in chain.

Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2
and B2 to generate the sum S2(the second bit of the output sum) and the
carry C3 which is again further connected to the next adder in chain and so
on.

The process continues till the last full adder FAn uses the carry bit Cn to add
with its input An and Bn to generate the last bit of the output along last
carry bit Cout.

HiCollege Click Here For More Notes 25

Parallel Subtractor –
A Parallel Subtractor computes the difference between two binary numbers
using parallel processing, employing a combination of half and full subtractors
or all full adders with subtrahend complement input.

Working of Parallel Subtractor –

Utilizes all full adders with subtrahend complement input.
Performs subtraction by adding the minuend to the 2's complement of the
subtrahend.
Obtains the 1's complement of B using a NOT gate and adds 1 through the
carry to obtain the 2's complement of B.
Continues this process until the last full adder generates the final output bit
along with the carry-out bit, using the carry bit from the previous stage.

Advantages of parallel Adder/Subtractor –

The parallel adder/subtractor performs the addition operation faster as
compared to serial adder/subtractor.
Time required for addition does not depend on the number of bits.
The output is in parallel form i.e all the bits are added/subtracted at the
same time.
It is less costly.

Disadvantages of parallel Adder/Subtractor –

Each adder has to wait for the carry which is to be generated from the
previous adder in chain.
The propagation delay( delay associated with the travelling of carry bit) is
found to increase with the increase in the number of bits to be added.

HiCollege Click Here For More Notes 26