A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_P/GM+ATI M52-T + ICH7-M core logic
3
2006-04-28 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 1 of 54
A B C D E
 A B C D E

Compal confidential
File Name : LA-2951P
Caymus
1 64/128 MB VRAM Accelerometer
1
Fan Control
page 4
DDR1 Mobile Yonah/Merom Thermal Sensor Clock Generator LIS3LV02DQ
page 22
uFCPGA-478 CPU ADM1032AR ICS954306
page 30
page 4,5,6 page 4 page 15

FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
ATI M52-T DDR2 -400/533/667 DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 page 13,14
PCI-E x 16
page 19,20,21,22,23
Intel Calistoga MCH Dual Channel
945PM PCBGA 1466 USB conn x2
CRT / TV-OUT/DVI (Docking) page 38
page 7,8,9,10,11,12
page 16
FingerPrinter AES2501
2
USBx1 page 35 2

LCD CONN USB2.0

USB conn x3
page 17 DMI page 33

PCI-E BUS BT Conn

page 33

PCI BUS Mini-Card WWAN

page 30
AC-LINK/Azalia
daughter board Intel ICH7-M MDC
page 34

Mini-Card Audio CKT

CardBus Controller mBGA-652 AD1981HD page 31 AMP & Audio Jack
10/100/1000 LAN WLAN MAX9710 page 32
LED BCM5753M page 30 TI PCI6612 page 24,25,26,27 SATA
page 35 page 28/29 SATA HDD Connector
3
SPI page 25 Docking CONN.
3

SPI ROM PATA Slave

*RJ-45(LED*2)
RTC CKT. Slot 0/Smart Card SD/MMC Slot Multi-bay II Connector *RJ-11(Pass Through)
page 25
RJ45/11 CONN 25LF080A
page 35 page 25 *CRT
page 29
*COMPOSITE Video Out
LPC BUS *TVOUT
*DVI
Power OK CKT. *LINE IN
page 40 *LINE OUT
*PCI-E x2
TPM 1.2 SMSC Super I/O *Serial Port
Power On/Off CKT. SMSC KBC 1021 LPC47N217
*Parallel Port
page 35 page 36 page 34 *PS/2 x2
page 37 *USB x2
*DC JACK
Int.KBD COM1 LPT
page 34
DC/DC Interface CKT. Touch Pad CONN. ( Docking ) ( Docking )
4
page 37 page 37 page 38 page 38 4

page 39

Power Circuit DC/DC

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

Page 41,42,43,44,45,46,47,48,49,50 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 2 of 54
A B C D E
 5 4 3 2 1

Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground

VIN Adapter power supply (18.5V) N/A N/A N/A

D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D

+CPU_CORE Core voltage for CPU ON OFF OFF

+VCCP 1.05V power rail for Processor I/O and MCH/ICH core power ON OFF OFF
+0.9VS 0.9V switched power rail for DDRII Vtt ON OFF OFF

+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
@ : means just reserve , no build
+1.8V 1.8V power rail for DDRII ON ON OFF
M52@ : means build discrete sku with ATI VGA M52 .
+1.8VS 1.8V switched power rail ON OFF OFF
UMA@ : means build UMA sku with Intel 945GM .
SPI@ : means just build when SPI I/F BIOS function reserve.
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF FWH@ : means just build when FWH I/F BIOS function reserve.
+3VALW 3.3V always on power rail ON ON ON* NOXDP@ : means just build when XDP function disable.
+3VS 3.3V switched power rail ON OFF OFF XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
1021@ : means just build when SMsC KBC1021 chip selected.
+RTC_VCC RTC power ON ON ON
LP@ : means just build when Low power clock gen. install
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
NOLP@ : means just build when Low power clock gen. NO install

C C

45@ : means need be mounted when 45 level assy or rework stage.

Internal PCI Devices
DEVICE Bus PCI Device ID IDSEL #
LAN 1 D8 AD24
Azalia 0 D27 AD11
PCI-E 0 D28 AD12
USB1.1/2.0 0 D29 AD13
PCI to PCI (DMI to PCI) 0 D30 AD14
AC97 MODEM 0 D30 AD14
AC97 Audio 0 D30 AD14
PATA/SATA 0 D31 AD15
LPC I/F 0 D31 AD15
SMBUS 0 D31 AD15
CPU I/F 0 D31 AD15
B
DMA 0 D31 AD15 B

PMU 0 D31 AD15

External PCI Devices

DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ
CARD BUS D6 AD22 2 CDEG

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
A
DDR SO-DIMM 1 A4 10100100 A

CLOCK GENERATOR (EXT.) D2 11010010

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 3 of 54
5 4 3 2 1
 5 4 3 2 1

ITPFLEX700 Connector
+3VS
<7> H_A#[3..31] H_D#[0..63] <7> +VCCP
JP12A
JP19
H_A#3 J4 E22 H_D#0 XDP_TDI 1 27 0.1U_0402_16V4Z XDP_DBRESET# 2 1
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
XDP_TMS
XDP_TCK
2
TDI
TMS
VTT0
VTT1 28 1
C948
2 R243 @ 200_0402_1%
+VCCP
M3 A5# D2# E26 5 TCK VTAP 26
H_A#6 K5 H22 H_D#3 XDP_TDO_R 7
H_A#7 A6# D3# H_D#4 XDP_TRST# TDO XDP_DBRESET#
M1 A7# D4# F23 3 TRST# DBR# 25
H_A#8 N2 G25 H_D#5 24 XDP_TDI R143 1 2 150_0402_1%
H_A#9 A8# D5# H_D#6 H_RESET#_R DBA#
J1 A9# D6# E25 12 RESET#
D H_A#10 H_D#7 XDP_BPM#0 XDP_TMS R236 D
N3 A10# D7# E23 BPM#0 23 1 2 39.2_0603_1%
H_A#11 P5 K24 H_D#8 XDP_TCK 11 21 XDP_BPM#1
H_A#12 A11# D8# H_D#9 FBO BPM#1 XDP_BPM#2 XDP_BPM#5 R241 56_0402_5%
P2 A12# D9# G24 BPM#2 19 1 2
H_A#13 L1 J24 H_D#10 CLK_CPU_XDP# 8 17 XDP_BPM#3
H_A#14 A13# D10# H_D#11 <15> CLK_CPU_XDP# CLK_CPU_XDP BCLK# BPM#3 XDP_BPM#4 XDP_TRST# R237 680_0402_5%
P4 A14# D11# J23 9 BCLK BPM#4 15 1 2
H_A#15 P1 H26 H_D#12 <15> CLK_CPU_XDP 13 XDP_BPM#5
H_A#16 A15# D12# H_D#13 BPM#5 XDP_TCK R239 27.4_0402_1%
R1 A16# D13# F26 10 GND0 1 2
H_A#17 Y2 K22 H_D#14 14
H_A#18 A17# D14# H_D#15 GND1
U5 A18# D15# H25 16 GND2 NC1 4
H_A#19 R3 N22 H_D#16 18 6
H_A#20 A19# D16# H_D#17 GND3 NC2
W6 A20# D17# K25 20 GND4
H_A#21 U4 P26 H_D#18 22
H_A#22 A21# D18# H_D#19 GND5
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21 ITP700-FLEXCON
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26 A25# D22# H_D#23
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24
H_A#28 A27# D24# H_D#25
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26 +VCCP
H_A#30 A29# D26# H_D#27 +VCCP
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28
<7> H_REQ#[0..4] A31# D28#

2
L26 H_D#29
D29#

2
H_REQ#0 K3 T25 H_D#30 R171
H_REQ#1 REQ0# D30# H_D#31 R104
H2 REQ1# D31# N24 54.9_0402_1%
H_REQ#2 K2 AA23 H_D#32 54.9_0402_1%
H_REQ#3 REQ2# D32# H_D#33
J3 AB24

1
H_REQ#4 REQ3# D33# H_D#34 R142
L5 V24

1
REQ4# D34# H_D#35 H_RESET# H_RESET#_R XDP_TDO XDP_TDO_R
D35# V26 2 1 2 1
H_ADSTB#0 L2 W25 H_D#36 22.6_0402_1%
<7> H_ADSTB#0 ADSTB0# D36#
H_ADSTB#1 V4 U23 H_D#37 R170 22.6_0402_1%
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK D42# H_D#43
<15> CLK_CPU_BCLK A22 BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
Y22
D45#
D46# AC26
AA24
H_D#46
H_D#47
Thermal Sensor ADM1032AR-2
H_ADS# D47# H_D#48
<7> H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49 +3VS
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52 2
<7> H_DEFER# DEFER# D52#
H_DRDY# F21 AC25 H_D#53 C273
<7> H_DRDY# DRDY# D53#
R172 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#

1
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55 0.1U_0402_16V4Z
<7> H_HITM# HITM# D55# 1
1 2 H_IERR# D20 AF23 H_D#56 R227
+VCCP H_LOCK# IERR# D56# H_D#57 U16
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 1 8 ICH_SMBCLK 10K_0402_5%
<7> H_RESET# RESET# D58# VDD SCLK
AD21 H_D#59

2
D59# H_D#60 H_THERMDA ICH_SMBDATA
<7> H_RS#[0..2] D60# AE25 2 D+ SDATA 7
H_RS#0 F3 AF25 H_D#61 C264
H_RS#1 RS0# D61# H_D#62 H_THERMDC THERM_SCI#
F4 RS1# D62# AF22 1 2 3 D- ALERT# 6 THERM_SCI# <23,26>
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63# 2200P_0402_50V7K THERM#
<7> H_TRDY# G2 TRDY# 4 THERM# GND 5

J26 H_DINV#0 R228

DINV0# H_DINV#0 <7>
M26 H_DINV#1 +3VS 1 2 ADM1032AR-2_MSOP8
DINV1# H_DINV#1 <7>
XDP_BPM#0 AD4 V23 H_DINV#2
BPM0# DINV2# H_DINV#2 <7>
XDP_BPM#1 AD3 BPM1# DINV3# AC20 H_DINV#3
H_DINV#3 <7>
10K_0402_5% Address:1001_101
XDP_BPM#2 AD1
B XDP_BPM#3 BPM2# ICH_SMBCLK B
AC4 BPM3# H_DSTBN#[0..3] <7> <13,14,15,23,26,28,30> ICH_SMBCLK
H23 H_DSTBN#0 ICH_SMBDATA
DSTBN0# <13,14,15,23,26,28,30> ICH_SMBDATA
<26> XDP_DBRESET# XDP_DBRESET# C20 M24 H_DSTBN#1
H_DBSY# DBR# DSTBN1# H_DSTBN#2
<7> H_DBSY# E1 DBSY# DSTBN2# W24
H_DPSLP# B5 AD23 H_DSTBN#3
<25> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0
<25,49> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
<7> H_DPWR# DPWR# DSTBP1#
XDP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<49> H_PROCHOT# PRDY# DSTBP2# +5VS
XDP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
1 R410 2 H_PROCHOT# D21
+VCCP 56_0402_5%
<25> H_PWRGOOD H_PWRGOOD D6
PROCHOT#
PWM Fan Control circuit
H_CPUSLP# PWRGOOD JP8
<7> H_CPUSLP# D7 SLP#

1
XDP_TCK AC5 1 1
XDP_TDI TCK H_A20M# D11 C122 C125 1
AA6 TDI A20M# A6 H_A20M# <25> 2
XDP_TDO AB3 A5 H_FERR#
TDO FERR# H_FERR# <25>
R1264 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# CH751H-40_SC76 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
TEST1 IGNNE# H_IGNNE# <25> 2 2
R1265 2 1 51_0402_5% TEST2 D25 B3 H_INIT#
H_INIT# <25>

2
XDP_TMS TEST2 INIT# H_INTR
AB5 TMS LINT0 C6 H_INTR <25>
XDP_TRST# AB6 B4 H_NMI
TRST# LINT1 H_NMI <25> +3VS
LEGACY CPU FAN
THERMAL
H_THERMDA A24 D5 H_STPCLK#
THERMDA DIODE STPCLK# H_STPCLK# <25>

1
2
5
6
H_THERMDC A25 A3 H_SMI#
THERMDC SMI# H_SMI# <25>

1
H_THERMTRIP# C7 U24 D
<7,25> H_THERMTRIP# THERMTRIP# G
1 Q33 @ ZD1

P
<36> FAN_PWM INB
H_THERMDA, H_THERMDC routing together. O 4 3
S
AO6402_TSOP6
FOX_PZ47903-2741-42_YONAH THERM# 2 RLZ5.1B_LL34
Trace width / Spacing = 10 / 10 mil INA

2
TC7SH00FU_SSOP5

3
A +VCCP A
1

R1266
R1255 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R1267 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2005/05/26 2006/07/26 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <26,50>
C

Q85 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 4 of 54
5 4 3 2 1
 5 4 3 2 1

+VCCP
Length match within 25 mils JP12B
+VCC_CORE
JP12C
D
The trace width 18 mils space D

1
<49> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
+VCC_CORE 7 mils <49> VSSSENSE VSSSENSE AE7
VCCSENSE
VSSSENSE
VSS
VSS AA25 AE17
VCC
VCC
VSS
VSS J2
R1268 R1269 AD25 AB15 M2
V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R1270 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C520

C531
N6 AD22 AA13 D26
R1271
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21 VCCP VSS AC19 AA12 VCC YONAH VSS E24
Close to CPU pin AD26 T21 VCCP VSS AF19 AD12 VCC VSS B21
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22
W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<49> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
<49> CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
<49> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<49> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<49> CPU_VID3 VID3 VSS VCC VSS
C
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 <49> CPU_VID4
CPU_VID4 AE3 VID4 VSS AB11 AE10 VCC POWER, GROUND VSS F16
C
CPU_VID5 AF2 AA11 AE9 E16
<49> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<49> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 1 <15> CPU_BSEL1
CPU_BSEL1 B23 BSEL1 VSS AD8 F20 VCC VSS B11
CPU_BSEL2 C21 AC8 E20 A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+VCC_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R1220
R244

R245

R355

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 5 of 54
5 4 3 2 1
 5 4 3 2 1

D +VCC_CORE D

1 1 1 1 1 1 1 1
C899 C900 C901 C902 C903 C904 C905 C906
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+VCC_CORE

1 1 1 1 1 1 1 1
C907 C908 C909 C910 C911 C912 C913 C914
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+VCC_CORE

1 1 1 1 1 1 1 1
C915 C916 C917 C918 C919 C920 C921 C922
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+VCC_CORE

1 1 1 1 1 1 1 1
C923 C924 C925 C926 C927 C928 C929 C930
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+VCC_CORE

330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7

1 1 1 1 1 1 ESR <= 1.5m ohm

C931 + C932 + C933 + C935 + C936 + C937 +
Capacitor > 1980uF
@330U_D2E_2.5VM_R7
2 2 2 2 2 2
B B

@ 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7

CPU right side

CPU left side

+VCCP

1
1 1 1 1 1 1
C983 + C940 C941 C942 C943 C944 C945

330U_D2E_2.5VM_R9 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 6 of 54
5 4 3 2 1
 5 4 3 2 1

<4> H_D#[0..63] H_A#[3..31] <4> Description at page11.

U15A U15B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <26> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <26> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <26> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T72
HD4# HA7# <26> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T73
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T74
HD7# HA10# <26> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <26> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T75
HD9# HA12# <26> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <26> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T76
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <26> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <26> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T77
HD15# HA18# <26> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T78
HD16# HA19# <26> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T79
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <26> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <26> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <26> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <26> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 R103 1 2 10K_0402_5%

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 R105 1 2 10K_0402_5%
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0 R107 1
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 2 10K_0402_5%
H_D#31 T5 M_CLK_DDR#1 AT1 D41 R110 1 2 10K_0402_5%
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 GMCH_H32
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ#
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
L H_D#48 AA1
HD47#
HD48#
HDSTBN#2
HDSTBN#3 AC4 H_DSTBN#3
H_DSTBP#[0..3] <4> +1.8V <13> M_ODT0
M_ODT0 BA13 SM_ODT0
NC10
NC11 BA40
H_D#49 AB4 K3 H_DSTBP#0 M_ODT1 BA12 BA41
HD49# HDSTBP#0 <13> M_ODT1 SM_ODT1 NC12
H_XSCOMP/H_YSCOMP trace H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
width and spacing is 5/20. HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R1194 1 SMRCOMPN NC15
AB3 HD53# 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R1195 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 <26> PM_BMBUSY# T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

HD59# RESERVED2
R1196

R1197

H_D#60 AB5 <13,14> DDR_THERM# PM_BMBUSY# G28 F3

H_D#61 HD60# H_RESET# DDR_THERM# PM_BMBUSY# RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> F25 PM_EXTTS0# RESERVED4 F7

PM

RESERVED
H_D#62 AD4 E8 H_ADS# <26,49> DPRSLPVR R1309 1 2 0_0402_5% PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# <4> PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,25> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# PWROK PM_THERMTRIP# RESERVED6

HDPWR# J9 H_DPWR# <4> AH33 PWROK RESERVED7 H7
H8 H_DRDY# 2 1 PLTRST_R# AH34 J19
HDRDY# H_DRDY# <4> <24,25,26,28,30,36> PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R1198 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
H_VREF K13 D4 H_HITM# <24> MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# <4> ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# <26,49> VGATE_INTEL R1304 1 2 @ 0_0402_5% PWROK A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR# <26,36> PM_POK R1305 1 2 0_0402_5%
HYSCOMP HBNR# H_BNR# <4>
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4> +3VS
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# <4>
HCPUSLP# E3 H_CPUSLP#
H_CPUSLP# <4> Layout Note:
24.9_0402_1%

24.9_0402_1%

V_DDR_MCH_REF
1

Layout Note: R1205

trace width and
R1199

R1200

B4 H_RS#0 DDR_THERM# 2 1
HRS0# Route as short
E6 H_RS#1 spacing is 20/20. 10K_0402_5%
HRS1#
D6 H_RS#2 as possible
HRS2# R1209
H_RS#[0..2] <4>
2

PM_EXTTS#1 2 1
CALISTOGA_FCBGA1466~D +1.8V @ 10K_0402_5%

1
M_OCDOCMP0
R1201 M_OCDOCMP1
@ 100_0402_1%
Layout Note:

40.2_0402_1%

40.2_0402_1%
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /

1
V_DDR_MCH_REF
<13,14,47> V_DDR_MCH_REF
H_SWNG1 trace width and spacing is 18/20.
0.1U_0402_16V4Z

R1344

R1202

R1203
GMCH_H32 1 2 CLKREQC# CLKREQC# <15>
1 R1204 0_0402_5%
+VCCP +VCCP @ 100_0402_1%

2
C895

@ @
+VCCP
2

2
221_0603_1%

221_0603_1%
1

1
100_0402_1%
1

R1206

R1207
R1208

A A
2

H_SWNG0 H_SWNG1
2

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%

Stuff R1202 & R1203 for A1 Calistoga

0.1U_0402_16V4Z

1 1
1

200_0402_1%

R1210

R1211

1
R1212

C898

C896

C897

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 7 of 54
5 4 3 2 1
 5 4 3 2 1

D D

U15D U15E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T68 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T69 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T70 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T71 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 8 of 54
5 4 3 2 1
 5 4 3 2 1

D D

PEGCOMP trace width

and spacing is 18/25 mils. R1176 +1.5VS_PCIE
U15C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38 PEG_RXN[0..15] <18>
F34 PEG_RXN0
EXP_RXN0 PEG_RXN1
B37 LA_DATA0 EXP_RXN1 G38
B34 H34 PEG_RXN2
LA_DATA1 EXP_RXN2 PEG_RXN3
A36 LA_DATA2 EXP_RXN3 J38
L34 PEG_RXN4
EXP_RXN4 PEG_RXN5
C37 LA_DATA#0 EXP_RXN5 M38
B35 N34 PEG_RXN6
LA_DATA#1 EXP_RXN6 PEG_RXN7
A37 LA_DATA#2 EXP_RXN7 P38
R34 PEG_RXN8
EXP_RXN8 PEG_RXN9
F30 LB_DATA0 EXP_RXN9 T38
PEG_RXN10

LVDS
D29 LB_DATA1 EXP_RXN10 V34
F28 W38 PEG_RXN11
LB_DATA2 EXP_RXN11 PEG_RXN12
EXP_RXN12 Y34
G30 AA38 PEG_RXN13
LB_DATA#0 EXP_RXN13 PEG_RXN14
D30 LB_DATA#1 EXP_RXN14 AB34
F29 AC38 PEG_RXN15
LB_DATA#2 EXP_RXN15 PEG_RXP[0..15] <18>
A32 D34 PEG_RXP0
LA_CLK EXP_RXP0 PEG_RXP1
A33 LA_CLK# EXP_RXP1 F38
E26 G34 PEG_RXP2
LB_CLK EXP_RXP2 PEG_RXP3
E27 H38

PCI-EXPRESS GRAPHICS
LB_CLK# EXP_RXP3 PEG_RXP4
EXP_RXP4 J34
D32 L38 PEG_RXP5
C LBKLT_CTL EXP_RXP5 PEG_RXP6 C
J30 LBKLT_EN EXP_RXP6 M34
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 LCTLB_DATA EXP_RXP8 P34
G26 R38 PEG_RXP9
LDDC_CLK EXP_RXP9 PEG_RXP10
G25 LDDC_DATA EXP_RXP10 T34
F32 V38 PEG_RXP11
LVDD_EN EXP_RXP11 PEG_RXP12
B38 LIBG EXP_RXP12 W34
C35 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 LVREFH EXP_RXP14 AA34
C32 AB38 PEG_RXP15 PEG_M_TXN[0..15] <18>
+1.5VS LVREFL EXP_RXP15
F36 PEG_TXN0 C1066 1 2 0.1U_0402_16V4Z PEG_M_TXN0
EXP_TXN0 PEG_TXN1 C1067 1 0.1U_0402_16V4Z PEG_M_TXN1
A16 TVDAC_A EXP_TXN1 G40 2
C18 H36 PEG_TXN2 C1068 1 2 0.1U_0402_16V4Z PEG_M_TXN2
TVDAC_B EXP_TXN2 PEG_TXN3 C1069 1 0.1U_0402_16V4Z PEG_M_TXN3
A19 TVDAC_C EXP_TXN3 J40 2

TV
L36 PEG_TXN4 C1070 1 2 0.1U_0402_16V4Z PEG_M_TXN4
EXP_TXN4 PEG_TXN5 C1071 1 0.1U_0402_16V4Z PEG_M_TXN5
J20 TV_IREF EXP_TXN5 M40 2
N36 PEG_TXN6 C1072 1 2 0.1U_0402_16V4Z PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C1073 1 0.1U_0402_16V4Z PEG_M_TXN7
B16 TV_IRTNA EXP_TXN7 P40 2
B18 R36 PEG_TXN8 C1074 1 2 0.1U_0402_16V4Z PEG_M_TXN8
TV_IRTNB EXP_TXN8 PEG_TXN9 C1075 1 0.1U_0402_16V4Z PEG_M_TXN9
B19 TV_IRTNC EXP_TXN9 T40 2
V36 PEG_TXN10 C1076 1 2 0.1U_0402_16V4Z PEG_M_TXN10
EXP_TXN10 PEG_TXN11 C1077 1 0.1U_0402_16V4Z PEG_M_TXN11
J29 TV_DCONSEL1 EXP_TXN11 W40 2
K30 Y36 PEG_TXN12 C1078 1 2 0.1U_0402_16V4Z PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C1079 1 0.1U_0402_16V4Z PEG_M_TXN13
EXP_TXN13 AA40 2
AB36 PEG_TXN14 C1080 1 2 0.1U_0402_16V4Z PEG_M_TXN14
EXP_TXN14 PEG_TXN15 C1081 1 0.1U_0402_16V4Z PEG_M_TXN15
EXP_TXN15 AC40 2
C26 DDCCLK PEG_M_TXP[0..15] <18>
CRT

C25 D36 PEG_TXP0 C1082 1 2 0.1U_0402_16V4Z PEG_M_TXP0

DDCDATA EXP_TXP0 PEG_TXP1 C1083 1 0.1U_0402_16V4Z PEG_M_TXP1
EXP_TXP1 F40 2
H23 G36 PEG_TXP2 C1084 1 2 0.1U_0402_16V4Z PEG_M_TXP2
VSYNC EXP_TXP2 PEG_TXP3 C1085 1 0.1U_0402_16V4Z PEG_M_TXP3
G23 HSYNC EXP_TXP3 H40 2
B PEG_TXP4 C1086 1 0.1U_0402_16V4Z PEG_M_TXP4 B
E23 BLUE EXP_TXP4 J36 2
D23 L40 PEG_TXP5 C1087 1 2 0.1U_0402_16V4Z PEG_M_TXP5
BLUE# EXP_TXP5 PEG_TXP6 C1088 1 0.1U_0402_16V4Z PEG_M_TXP6
C22 GREEN EXP_TXP6 M36 2
B22 N40 PEG_TXP7 C1089 1 2 0.1U_0402_16V4Z PEG_M_TXP7
GREEN# EXP_TXP7 PEG_TXP8 C1090 1 0.1U_0402_16V4Z PEG_M_TXP8
+VCCP A21 RED EXP_TXP8 P36 2
B21 R40 PEG_TXP9 C1091 1 2 0.1U_0402_16V4Z PEG_M_TXP9
RED# EXP_TXP9 PEG_TXP10 C1092 1 0.1U_0402_16V4Z PEG_M_TXP10
EXP_TXP10 T36 2
V40 PEG_TXP11 C1093 1 2 0.1U_0402_16V4Z PEG_M_TXP11
EXP_TXP11 PEG_TXP12 C1094 1 0.1U_0402_16V4Z PEG_M_TXP12
J22 CRT_IREF EXP_TXP12 W36 2
Y40 PEG_TXP13 C1095 1 2 0.1U_0402_16V4Z PEG_M_TXP13
EXP_TXP13 PEG_TXP14 C1096 1 0.1U_0402_16V4Z PEG_M_TXP14
EXP_TXP14 AA36 2
AB40 PEG_TXP15 C1097 1 2 0.1U_0402_16V4Z PEG_M_TXP15
EXP_TXP15

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 9 of 54
5 4 3 2 1
 5 4 3 2 1

Place close to Pin G41

+2.5VS

0.1U_0402_16V4Z
1

C831
D D
U15H
+VCCP 2
VCC_SYNC H22

AC14 VTT0
AB14 VTT1 VCCTX_LVDS0 B30
W14 C30 +1.5VS_PCIE
VTT2 VCCTX_LVDS1 R1163
V14 VTT3 VCCTX_LVDS2 A30
T14 0_0805_5%
VTT4 10U_0805_6.3V6M
R14 VTT5 VCC3G0 AB41 2 1 +1.5VS
P14 AJ41
N14
VTT6
VTT7
VCC3G1
VCC3G2 L41 W=40 mils 1
M14 VTT8 VCC3G3 N41 1 C824 1 C825
L14 R41 +
VTT9 VCC3G4
AD13 VTT10 VCC3G5 V41
AC13 Y41 10U_0805_6.3V6M
VTT11 VCC3G6 2 2 2
220U_D2_2VM_R9

AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
Y13 VTT14 VCCA_3GBG G41 +2.5VS
+
C830

W13 H41 C981

VTT15 VSSA_3GBG 220U_D2_2VM_R9
V13 VTT16
U13 VTT17
2
T13 VTT18 VCCA_CRTDAC0 E21 +VCCP
R13 VTT19 VCCA_CRTDAC1 F21
N13 VTT20 VSSA_CRTDAC2 G21
M13 VTT21
L13 VTT22
AB12 VTT23 VCCA_DPLLA B26
AA12 VTT24 VCCA_DPLLB C39
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
W12 VTT26
V12 VTT27
U12 VTT28 VCCA_LVDS A38
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
P12 VTT31
N12
M12
VTT32
VTT33
P O W E R VCCA_MPLL AF2 +1.5VS_MPLL
PCI-E/MEM/PSB PLL decoupling
4.7U_0805_10V4Z

2.2U_0805_16V4Z

L12 VTT34 VCCA_TVBG H20 +1.5VS

R11 VTT35 VSSA_TVBG G20
1 1 P11 VTT36
C836

C837

N11 VTT37
M11 E19 +1.5VS_3GPLL +1.5VS
VTT38 VCCA_TVDACA0 +1.5VS
R10 F19 R1339 R1168
2 2 VTT39 VCCA_TVDACA1 3GPLL 2
P10 VTT40 VCCA_TVDACB0 C20 1 2 1
0.5_0805_1% 0_0805_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N10 VTT41 VCCA_TVDACB1 D20
M10 VTT42 VCCA_TVDACC0 E20
P9 VTT43 VCCA_TVDACC1 F20 1 1 1
N9 C839
VTT44

C838

C841
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 AH2 2 2 2
VTT47 VCCD_HMPLL1
N8 VTT48
M8 @
VTT49 10U_0805_6.3V6M
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28
M7 VTT52 VCCD_LVDS2 C28
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS
M6 VTT55 VCCDQ_TVDAC H19
MCH_A6 +1.5VS_MPLL +1.5VS_HPLL
A6 VTT56 R1173 R1174
0.47U_0603_10V7K

R5 VTT57 VCCHV0 A23 +3VS

P5 VTT58 VCCHV1 B23 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
0_0805_5% 0_0805_5%
0.1U_0402_16V4Z

1 N5 VTT59 VCCHV2 B25

C844

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M5 VTT60 1 1
P4 AK31 C846
VTT61 VCCAUX0
N4 VTT62 VCCAUX1 AF31 1 1 1 1
2
C845

M4 AE31 10U_0805_6.3V6M C860 C862

VTT63 VCCAUX2 2 2

C859

C861
R3 VTT64 VCCAUX3 AC31
B P3 AL30 10U_0805_6.3V6M 10U_0805_6.3V6M B
VTT65 VCCAUX4 2 2 2 2
N3 VTT66 VCCAUX5 AK30
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30

R2 AH30 +1.5VS
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
0.1U_0402_16V4Z

1 M2 VTT70 VCCAUX9 AF30

C849

MCH_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1
0.22U_0603_10V7K

R1 VTT73 VCCAUX12 AC30

MCH_AB1

2
C850

1 P1 VTT74 VCCAUX13 AG29

+VCCP +1.5VS
C853

N1 VTT75 VCCAUX14 AF29

2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

VCCAUX16 AD29

2
2
1 VCCAUX17 AC29
C856

AG28 D12 D21

VCCAUX18
VCCAUX19 AF28 CH751H-40_SOD323 CH751H-40_SOD323
VCCAUX20 AE28 @ @
2 AH22

1 1

1 1
VCCAUX21
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 AJ20 R127 +2.5VS R520 +3VS
VCCAUX33 VCCAUX24
AE14 VCCAUX34 VCCAUX25 AH20
Y14 AH19 @ 10_0402_5% @ 10_0402_5%
VCCAUX35 VCCAUX26
AF13 P19

2
VCCAUX36 VCCAUX27
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
VCCAUX38 VCCAUX29
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14

CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 10 of 54
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U15F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U15G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 VCC_NCTF1 VCCAUX_NCTF1 AF27 W33 VCC1 VCC_SM1 AT41 VCCSM_LF4 CFG[2:0] 001 = 533MT/s FSB
AB27 AG26 P33 AM41 VCCSM_LF5
VCC_NCTF2 VCCAUX_NCTF2 VCC2 VCC_SM2
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2
CFG5 1 = DMI x 4 *(Default)

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved
CFG7 1 = Mobile Yonah CPU *(Default)

C794
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34

C795
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0 = Lane Reversal Enable *
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30 0 = Calistoga *
C796

C797

C798

AA26 AF21 L32 AW30 (According to Intel Napa Schematic Checklist & CRB
VCC_NCTF13 VCCAUX_NCTF13 VCC13 VCC_SM13
2 2 2
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30 CFG11 Rev1.301 document 2.2Kohm pull-down resistor request)
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 1 = Reserved
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29
+1.8V
11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
0 = 1.05V *(Default)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28
10U_0805_6.3V6M U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG18 1 = 1.5V
1U_0603_10V4Z

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)
CFG19 1 = DMI Lane Reversal Enable

C799

C800

C801

C802
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26
C803 C804 AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
P O W E R 0 = No SDVO Device Present *
C805

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 VCC_SM32 AW26

2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
10U_0805_6.3V6M U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is
C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
C
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
330U_D2E_2.5VM_R9

R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
220U_D2_2VM_R9

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22

C980

1 1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1

T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
+ +

C807
R22 VCC_NCTF49 VCCAUX_NCTF49 AC15 R28 VCC49 VCC_SM49 AU22
C806

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22

2 R1151
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2 2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R1152 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
@ R21 V15 P27 AJ22
VCC_NCTF54 VCCAUX_NCTF54 VCC54 VCC_SM54 R1153
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N27 VCC55 VCC_SM55 AK21 <7> CFG9 1 2 @ 2.2K_0402_5%
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R1154 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R1155 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
V19 AE26 N25 AU19 1 1 R1156 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + C808 <7> CFG13
330U_D2E_2.5VM_R9

U19 AE25 M25 AT19 C809 C810

VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62 R1157
T19 VCC_NCTF63 VSS_NCTF3 AE24 L25 VCC63 VCC_SM63 AR19 <7> CFG16 1 2 @ 2.2K_0402_5%
1 AD18 AE23 P24 AP19 @ 220U_D2_4VM
C811 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19 10U_0805_6.3V6M
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 AE19 AA23 AJ17 10U_0805_6.3V6M
2 VCC_NCTF68 VSS_NCTF8 VCC68 VCC_SM68
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
@ VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R1158 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R1159 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R1160 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C812
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C813

C814

AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 11 of 54
5 4 3 2 1
 5 4 3 2 1

U15I U15J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39
T39
VSS29
VSS30
VSS129
VSS130
AJ31
AG31
AP17
AM17
VSS229
VSS230
P O W E R VSS309
VSS310
G7
D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39
L39
VSS34
VSS35
P O W E R VSS134
VSS135
E30
AT29
AL16
J16
VSS234
VSS235
VSS314
VSS315
Y6
U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 12 of 54
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14,47>

<8> DDR_A_D[0..63] JP34

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D7 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C363

C362
DDR_A_D0 5 6 DDR_A_D1
DDR_A_D4 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D6
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D9
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D21 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D16
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC DDR_THERM# <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C458

C498

C473

C491

C465

C255

C242

C280

C235
53 VSS VSS 54
DDR_A_D22 55 56 DDR_A_D18
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D25 61 62 DDR_A_D29
DDR_A_D24 DQ24 DQ28 DDR_A_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D27 73 74 DDR_A_D26
DDR_A_D30 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9V 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9V <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D34 123 124 DDR_A_D36
DDR_A_D38 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C229

C239

C250

C257

C272

C279

C281

C274

C268

C252

C241

C234

C227

133 134 DDR_A_D37

DDR_A_D39 VSS DQ38 DDR_A_D32
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D40
139 VSS DQ44 140
DDR_A_D45 141 142 DDR_A_D44
B DDR_A_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D47
DDR_A_D43 DQ42 DQ46 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D52 157 158 DDR_A_D48
DDR_A_D53 DQ48 DQ52 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9V NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP27 RP22 56_0404_4P2R_5%
Place these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP34,all 171 172
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D51 173 DQ50 DQ54 174 DDR_A_D50
DDR_A_D55 175 176 DDR_A_D54
RP29 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D57
183 VSS VSS 184
RP32 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP31 56_0404_4P2R_5% RP28 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 <4,14,15,23,26,28,30> ICH_SMBDATA
ICH_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 ICH_SMBCLK 197 198
<4,14,15,23,26,28,30> ICH_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP33 56_0404_4P2R_5% RP30 56_0404_4P2R_5% 203 204
GND GND

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C308 FOX_ASOA426-M4R-TR

R455

R453
A A
RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2
0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 M_ODT0
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP24 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA Top side
3 2 DDR_A_MA11 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 13 of 54
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13,47>
<8> DDR_B_DM[0..7] JP10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D1
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C89

C90
DDR_B_D5 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D2
15 VSS DQ7 16
D DDR_B_D7 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP34 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D21 43 44 DDR_B_D16
DDR_B_D20 DQ16 DQ20 DDR_B_D18
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C236

C265

C247

C159

C164

C166

C219

C188

C161
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC DDR_THERM# <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D22 55 56 DDR_B_D17
DDR_B_D23 DQ18 DQ22 DDR_B_D19
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9V 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9V A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D37 123 124 DDR_B_D33
DDR_B_D36 DQ32 DQ36 DDR_B_D32
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C176

C179

C186

C197

C213

C220

C183

C210

C199

C173

C218

C163

C177

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D43
DDR_B_D47 DQ42 DQ46 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D49
DDR_B_D53 DQ48 DQ52 DDR_B_D52
Layout Note: 159 DQ49 DQ53 160
Place these resistor 161 VSS VSS 162
+0.9V 163 164 M_CLK_DDR2
closely JP10,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP14 RP10 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_CKE3_DIMMB 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D60 VSS VSS DDR_B_D56
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP16 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D58 189 190
RP18 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 193 194 DDR_B_D63
DDR_CS2_DIMMB# 2 DDR_B_MA6 ICH_SMBDATA VSS DQ63
3 3 2 <4,13,15,23,26,28,30> ICH_SMBDATA 195 SDA VSS 196
ICH_SMBCLK 197 198 R257
<4,13,15,23,26,28,30> ICH_SMBCLK SCL SA0
RP19 56_0404_4P2R_5% RP15 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 203 204
GND GND

1
10K_0402_5%
DDR_B_WE# 2 3 3 2 DDR_B_MA2 1 10K_0402_5%

R254
A RP23 C301 FOX_ASOA426-M2RN-7F A
56_0404_4P2R_5% RP21 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 M_ODT2
DDR_B_MA13
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2
STANDARD

2
56_0404_4P2R_5% RP9
4 1 DDR_B_BS#2 Bottom side
3 2 DDR_CKE2_DIMMB

56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 14 of 54
5 4 3 2 1
 5 4 3 2 1

+CK_VDD_MAIN1

FSLC FSLB FSLA CPU SRC PCI 1 2

C353 2 1 CLK_48M_ICH
@ 5P_0402_50V8C
Place close to U25
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz R1066 0_0805_5% 1
C730
1 1 1 C354 2 1 CLK_48M_CB
@ 5P_0402_50V8C
C731 C732 C733 C355 2 1 CLK_14M_ICH
0 0 1 133 100 33.3 2
10U_0805_10V4Z
2
0.01U_0402_16V7K
2
0.01U_0402_16V7K
2
0.01U_0402_16V7K 4.7P_0402_50V8C
C356 2 1 CLK_PCI_ICH
4.7P_0402_50V8C
+CK_VDD_MAIN2
0 1 1 166 100 33.3 C357 2 1 CLK_14M_KBC
R1068 4.7P_0402_50V8C
+3VS 1 2 1 2 CK_VDD_REF C358 2 1 CLK_14M_SIO
Table : ICS954306 R1067 0_0805_5% 1 1 1 1_0805_1% 4.7P_0402_50V8C
C737 C738 C739 C368 2 1 CLK_PCI_EC
1 2 CK_VDD_48 4.7P_0402_50V8C
D
FSB Frequency Selet: 2
10U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z R1069
2.2_0805_1%
C369 2 1 CLK_PCI_TCG
4.7P_0402_50V8C
D

C371 2 1 CLK_PCI_PCM
+CK_VDD_DP
Stuff CLK_Ra CLK_Rb CLK_Rc 4.7P_0402_50V8C
CPU Driven R1389 C372 2 1 CLK_PCI_SIO
+3VS 1 2 4.7P_0402_50V8C
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf NOXDP@0_0805_5% 1
C1062
1
C734
1
C735
1 0.1U_0402_16V4Z
C736
C373 2 1 CLK_DEBUG_PORT
@ 5P_0402_50V8C
R1390
Stuff CLK_Rd CLK_Re CLK_Rf +VCCP 1 2
2
10U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
Place crystal within
533MHz XDP@ 0_0805_5%
500 mils of CK410 C361 2 1
18P_0402_50V8J

1
+CK_VDD_DP +CK_VDD_MAIN1
No Stuff CLK_Ra CLK_Rb CLK_Rc U25
Y3 Routing the trace at least 10mil
16 57 CLK_XTAL_IN 14.31818MHZ_16P
VDD X1
Stuff CLK_Rd CLK_Rf

2
CK_VDD_48 10 56 CLK_XTAL_OUT 2 1
VDD48 X2
667MHz 1 C364 18P_0402_50V8J
No Stuff CLK_Ra CLK_Rb CLK_Rc +CK_VDD_DP
C742 5 VDDPCI
28 R1352 1 2 LP@0_0402_5%
SATACLKT
CLK_Re 0.1U_0402_16V4Z
2
24 VDDSRC
2 R1393 1 CLKIREF
SATACLKC 29 R1333 1 2 LP@0_0402_5%
@ 0_0402_5% 1 33
+VCCP C743 VDDSATA
1 41 52 CPU_BCLK 1 2 CLK_CPU_BCLK
VDDSRC CPUCLKT0 CLK_CPU_BCLK <4>
C1061 0.1U_0402_16V4Z R1070 24_0402_5%
2

2 CK_VDD_REF CPU_BCLK# CLK_CPU_BCLK#

50 VDDCPU CPUCLKC0 51 1 2 CLK_CPU_BCLK# <4>
@ R1074 @ 0.1U_0402_16V4Z R1072 24_0402_5%
56_0402_5% 2
55 VDDREF
R1078 CLK_Rd R1077 12_0402_5%
CPUCLKT1 49 MCH_BCLK 1 2 CLK_MCH_BCLK
CLK_MCH_BCLK <7>
8.2K_0402_5% <26> CLK_48M_ICH CLK_48M_ICH 2 1 R1075 24_0402_5%
1

FSA 2 1 1 2 CLK_48M_CB 2 1 FSA 11 48 MCH_BCLK# 1 2 CLK_MCH_BCLK#

C MCH_CLKSEL0 <7> <30> CLK_48M_CB FSLA/USB_48MHz CPUCLKC1 CLK_MCH_BCLK# <7> C
R1080 12_0402_5% R1081 24_0402_5%
1 2 R1079 FSB 15
<5> CPU_BSEL0 FSLB/TEST_MODE
R1083 1K_0402_5%
0_0402_5% <26> CLK_14M_ICH CLK_14M_ICH 2 1 CLKREF1 59 FSLC/TEST_SEL/REF1
1

CLK_Ra R1087 33_0402_5%

*CLKREQA# 64 CLKREQA#
CLKREQA# <28>
R1086
18 PCIE_M52 1 2 CLK_PCIE_M52
LCDCLK_SST/SRCCLKT0 CLK_PCIE_M52 <18>
1K_0402_5% CLKIREF 46 R1093 24_0402_5%
R1092 910_0402_1% IREF PCIE_M52# CLK_PCIE_M52#
19 1 2 CLK_PCIE_M52# <18>
2

LCDCLK_SSC/SRCCLKC0 R1095 24_0402_5%

61 CPU_STOP#
H_STP_CPU#
<26> H_STP_CPU#
H_STP_PCI# 8 22 PCIE_LOM 1 2 CLK_PCIE_LOM
+VCCP <26> H_STP_PCI# PCI/SRC_STOP# SRCCLKT2 CLK_PCIE_LOM <28>
R1118 24_0402_5%
CLK_ENABLE# 9 23 PCIE_LOM# 1 2 CLK_PCIE_LOM#
<40,49> CLK_ENABLE# Vtt_PwrGd#/PD SRCCLKC2 CLK_PCIE_LOM# <28>
R1121 24_0402_5%
2

CLK_PCI_ICH 2 R1097 1 PCI_ICH 7

<24> CLK_PCI_ICH **SEL_LCDCLK#/PCICLK_F1
R1098 33_0402_5% 30 PCIE_SATA 1 2 CLK_PCIE_SATA
SATA1/SRCCLKT4 CLK_PCIE_SATA <25>
R1101 12_0402_5% R1257 24_0402_5%
1K_0402_5% CLK_14M_KBC 2 1 CLKREF0 60 31 PCIE_SATA# 1 2 CLK_PCIE_SATA#
<36> CLK_14M_KBC REF0/PCICLK1 SATA1/SRCCLKC4 CLK_PCIE_SATA# <25>
<34> CLK_14M_SIO CLK_14M_SIO 2 1 R1259 24_0402_5%
1

FSB 1 2 R1104 12_0402_5% 62

MCH_CLKSEL1 <7> *REQ_SEL/PCICLK2
CLK_DEBUG_PORT 2 1 R1117 PCI_MINI
<30> CLK_DEBUG_PORT
1 2 R1105 DEBUG@ 33_0402_5% 1 63 CLKREQB# 2 1 CPPE#
<5> CPU_BSEL1 *SEL_PCI1/PCICLK3 *CLKREQB# CPPE# <24,38>
R1107 1K_0402_5% 10K_0402_5%2 1 R1109 PCI_CLK3 R1106 10K_0402_5% C740
0_0402_5% CLK_PCI_EC 2 1 R1110 PCI_EC 2 20 T80 PAD CLKREQA# 1 2 @ 1000P_0402_50V4Z
<36> CLK_PCI_EC **SEL_SATA1/PCICLK4 SRCCLKT1
1

CLK_Rb 33_0402_5%
@ R1113 CLK_PCI_TCG 2 1 R1140 PCI_CLK5 3 21 T92 PAD C741
<35> CLK_PCI_TCG **SEL_SATA2/PCICLK5 SRCCLKC1
33_0402_5% CLKREQB# 1 2 @ 1000P_0402_50V4Z
0_0402_5% +3VS CLK_PCI_PCM 2 1 R1141 PCI_PCM 6
<30> CLK_PCI_PCM PCICLK6
CLK_Re 33_0402_5% 26 PCIE_DOCK 1 2 CLK_PCIE_DOCK
CLK_PCIE_DOCK <38>
C744
2

SRCCLKT3
R1394 2 1@ 10K_0402_5% PCI_EC R1144 24_0402_5% CPU_XDP 1 2 @ 1000P_0402_50V4Z
27 PCIE_DOCK# 1 2 CLK_PCIE_DOCK#
B SRCCLKC3 CLK_PCIE_DOCK# <38> B
ICH_SMBDATA 54 R1145 24_0402_5% C745
+VCCP <4,13,14,23,26,28,30> ICH_SMBDATA SDATA CPU_XDP# 1 2 @ 1000P_0402_50V4Z
<4,13,14,23,26,28,30> ICH_SMBCLK ICH_SMBCLK 53 35 PCIE_ICH 1 2 CLK_PCIE_ICH
SCLK SATA2/SRCCLKT5 CLK_PCIE_ICH <26>
R1123 24_0402_5%
2

34 PCIE_ICH# 1 2 CLK_PCIE_ICH#
SATA2/SRCCLKC5 CLK_PCIE_ICH# <26>
R1128 R1126 24_0402_5%
R1120 2 1 NOXDP@10K_0402_5% +3VS
R1130 1K_0402_5% 13 2 1 CLKREQC#
DOTT_96MHz CLKREQC# <7>
8.2K_0402_5% R1142 NOXDP@0_0402_5%
1

CLKREF1 2 1 1 2 14 45 CPU_XDP 1 2 CLK_CPU_XDP

DOTC_96MHz *CPUCLKT2_ITP/CLKREQC# CLK_CPU_XDP <4>
R1133 XDP@ 24_0402_5%
MCH_CLKSEL2 <7>
1 2 R1131 37 MCH_3GPLL 1 2 CLK_MCH_3GPLL
<5> CPU_BSEL2 SRCCLKT6 CLK_MCH_3GPLL <7>
R1135 1K_0402_5% CLK_PCI_SIO 2 1 PCI_CLK3 R1111 24_0402_5%
<34> CLK_PCI_SIO
0_0402_5% R1114 33_0402_5% 36 MCH_3GPLL# 1 2 CLK_MCH_3GPLL#
SRCCLKC6 CLK_MCH_3GPLL# <7>
1

CLK_Rc 4 GND
R1115 24_0402_5%
@ R1139
NOXDP@ : means just build when XDP function disable. 12 43 T93 PAD
0_0402_5% GND SRCCLKT8
CLK_Rf XDP@ : means just build when XDP function enable. 17 42 T94 PAD R1147 2 1 NOXDP@10K_0402_5% +3VS
2

GND SRCCLKC8
CLKREQD#
When this time, docking PCI express will not work. 58 GND 2 1
R1254 NOXDP@0_0402_5%
CLKREQD# <30>
47 44 CPU_XDP# 1 2 CLK_CPU_XDP#
+3VS GNDCPU *CPUCLKC2_ITP/CLKREQD# CLK_CPU_XDP# <4>
LCD(Low)/SRC(High) R1143 XDP@ 24_0402_5%
clock select Pin44/45 function select 25 GNDSRC SRCCLKT7 39 PCIE_MCARD 1 2 CLK_PCIE_MCARD
CLK_PCIE_MCARD <30>
R1249 24_0402_5%
1

+3VS +3VS 40 38 PCIE_MCARD# 1 2 CLK_PCIE_MCARD#

GNDSRC SRCCLKC7 CLK_PCIE_MCARD# <30>
R1146 R1251 24_0402_5%
32 GNDSATA
1

@ 10K_0402_5%
R1108 R1245
2

CLK_ENABLE#
A 10K_0402_5% 10K_0402_5% ICS9LP306_TSSOP64 A
1

* Internal Pull-Up Resistor

2

R1351 PCI_ICH PCI_MINI ** Internal Pull-Down Resistor

1

300_0402_5%
R1246 R1247
1 2

@ 10K_0402_5%
@ 10K_0402_5%
J29 Security Classification Compal Secret Data Compal Electronics, Inc.
2

NO SHORT PADS 2005/05/26 2006/07/26 Title

Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
*High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz
High:Pin44/45 = CLKREQ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
*Low:Pin44/45 = CPUCLK2_ITP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2951 1.0

Date: Friday, April 28, 2006 Sheet 15 of 54

5 4 3 2 1
 A B C D E

+5VS +RCRT_VCC +CRTVDD

F1 D18
CRT Connector 1

1.1A_6VDC_FUSE
2 2

CH491D_SC59
1 W=40mils BLUE_R
GREEN_R
RED_R

DAN217_SC59

DAN217_SC59

@ DAN217_SC59
1
C315

D19

D20
1

1
D4
0.1U_0402_16V4Z
2
<38> BLUE
JP2
<38> GREEN 6
1 R542 @ @ 1
11
RED_R +CRTVDD
<38> RED 1 2 1

3
BK1608LL560-T 7

18P_0402_50V8C
R543 12
1 2 GREEN_R 2

18P_0402_50V8C
C313
BK1608LL560-T 8
R544 13

C314
1 2 BLUE_R 3
BK1608LL560-T 9

18P_0402_50V8C
+5VS +5VS 14 16
C359 C370
1 1 1 4 17

C310
1 2 1 2 10
15
0.1U_0402_16V4Z 0.1U_0402_16V4Z 5 +3VS
2 2 2
SUYIN_070912FR015S207CR

5
1
U33
SN74AHCT1G125GW_SOT353-5 R545

P
OE#
2 4 HSYNC_G_A 1 2 D_HSYNC
<19> M_HSYNC A Y

2
2.2K_0402_5%

2.2K_0402_5%
0_0603_5%

5
1
D_HSYNC <38>

R2

R4
R546

P
OE#
3
2 4 VSYNC_G_A 1 2 D_VSYNC +CRTVDD +CRTVDD
<19> M_VSYNC A Y 0_0603_5%

1
G
U54
D_VSYNC <38>

1
R53 51K_0402_5%

R54 51K_0402_5%

SN74AHCT1G125GW_SOT353-5 1 1 Place close to docking connector

3
C351 C352 R162 R183
2

@ 5P_0402_50V8C @ 5P_0402_50V8C 2.2K_0402_5% 2.2K_0402_5%

2 2

2
Q46

G
Place close to docking connector
1

2 D_DDCDATA 2
<38> D_DDCDATA 1 3 DDC1_DATA <19>

S
2
RHU002N06_SOT323

G
D_DDCCLK 1 3
<38> D_DDCCLK DDC1_CLK <19>

S
Q52
RHU002N06_SOT323

TV-Out Connector

3 3

Place close to JP1

D3 D5 D1 +3VS
@ DAN217_SC59
@ DAN217_SC59
@ DAN217_SC59
1

1
2

JP1
1
2
R547 C_LUMA 3
<19,38> LUMA 1 2 4
0_0603_5%
R548 C_CRMA 5
<19,38> CRMA 1 2 6
0_0603_5%
R549 C_COMP 7
<19,38> COMP 1 2
0_0603_5%

SUYIN_33007SR-07T1-C

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 16 of 54
A B C D E
 5 4 3 2 1

LVDS CONN B+_LCD

1 2
LCD POWER CIRCUIT LCDVDD +3VALW
C586 0.1U_0603_50V4Z
1 2 LCDVDD
C587 68P_0402_50V8J

S
1 3

D
1
JP35
R19 Q8
SI2301BDS_SOT23 R12
40 2 1

G
2
40 L76 @ KC FBM-L11-201209-221LMA30T_0805 100_0402_1%
39 39 1 2
D D
38 2 1

1 2
38 B+
37 L62 KC FBM-L11-201209-221LMA30T_0805 1M_0402_5%
37 D R474 C28
36 36
35 +3VS Q5 2 1 2 1 2
35 G
34 34
33 RHU002N06_SOT323 S 47K_0402_5% 1 1 0.047U_0402_16V7K 1

3
33 C29 C31 C20
32 32 LCDVDD
31 31

1
30 4.7U_0805_10V4Z @ 4.7U_0805_10V4Z
30 Q6 2 2 2
29 29 +5VS_INV
28 DTC124EK_SC59
28 BKLT_PWM ALS_EN <24>
27 27
26 2 0.1U_0402_16V4Z
26 DDC2_CLK <19> <19> M52_ENAVDD
25 25
24 DDC2_DATA <19>
24
23 23 TXCLK_U+ <19>
22 TXCLK_U- <19>

3
22
21 21
20 20 TXOUT_U2+ <19>
19 19 TXOUT_U2- <19>
18 18
17 17 TXOUT_U1+ <19>
16 Q53
16 TXOUT_U1- <19>
15 DTA114YKA_SC59
15
14 14 TXOUT_U0+ <19>
13 13 TXOUT_U0- <19>
12 12 +5VS 3 1 +5VS_INV
11

47K
11 TXOUT_L0- <19>

10K
10 10 TXOUT_L0+ <19>
9 9
8 +3VS
8 TXOUT_L1- <19>
7 TXOUT_L1+ <19>

2
C 7 U43A C
6 6
SN74LVC08APW_TSSOP14

14
5 5 TXOUT_L2- <19>
4 4 TXOUT_L2+ <19>

1
LID_SW# D
3 1

P
3 <26,37> LID_SW# A
2 3 2 Q36
2 TXCLK_L- <19> O
1 2 G BSS138_SOT23
1 TXCLK_L+ <19> <19> OPT_BL_ENA B

2
S

3
2
R360

7
ACES_88316-4000 100K_0402_5%

1
R501

1
@ 100K_0402_5%

<36> INV_PWM R131 1 2 @ 0_0402_5%

B R102 1 0_0402_5% BKLT_PWM B

<19> BLON_PWM 2

Support 3V inverter

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 17 of 54
5 4 3 2 1
 5 4 3 2 1

D D

U1A
PART 1 OF 6
PEG_M_TXP0 AE26 W21 PEG_M_RXP0 C968 0.1U_0402_16V4Z PEG_RXP0
PEG_M_TXN0 PCIE_RX0P PCIE_TX0P PEG_M_RXN0 C1032 0.1U_0402_16V4Z PEG_RXN0
AD26 PCIE_RX0N PCIE_TX0N V21

PEG_M_TXP1 AB26 PCIE_RX1P P PCIE_TX1P V22 PEG_M_RXP1 C973 0.1U_0402_16V4Z PEG_RXP1

PEG_M_TXN1 AA26 U22 PEG_M_RXN1 C965 0.1U_0402_16V4Z PEG_RXN1
PCIE_RX1N C PCIE_TX1N
I
PEG_M_TXP2 PEG_M_RXP2 C1033 0.1U_0402_16V4Z PEG_RXP2
PEG_M_TXN2
AA25
Y25
PCIE_RX2P - PCIE_TX2P U23
T23 PEG_M_RXN2 C1035 0.1U_0402_16V4Z PEG_RXN2
PCIE_RX2N E PCIE_TX2N

PEG_M_TXP3
X PEG_M_RXP3 C969 0.1U_0402_16V4Z PEG_RXP3
W26 T21
PEG_M_TXN3 V26
PCIE_RX3P
PCIE_RX3N
P PCIE_TX3P
PCIE_TX3N R21 PEG_M_RXN3 C1037 0.1U_0402_16V4Z PEG_RXN3
R CLK_PCIE_M52
PEG_M_TXP4 V25 E R22 PEG_M_RXP4 C1030 0.1U_0402_16V4Z PEG_RXP4
<15> CLK_PCIE_M52
<15> CLK_PCIE_M52#
CLK_PCIE_M52#
PCIE_RX4P PCIE_TX4P
PEG_M_TXN4 U25 PCIE_RX4N S PCIE_TX4N P22 PEG_M_RXN4 C972 0.1U_0402_16V4Z PEG_RXN4

S PEG_RXP[0..15]
<9> PEG_RXP[0..15]
PEG_M_TXP5 T26 P23 PEG_M_RXP5 C963 0.1U_0402_16V4Z PEG_RXP5
PEG_M_TXN5 PCIE_RX5P PCIE_TX5P PEG_M_RXN5 C1031 0.1U_0402_16V4Z PEG_RXN5 PEG_RXN[0..15]
R26 N23
PCIE_RX5N I PCIE_TX5N <9> PEG_RXN[0..15]
N <9> PEG_M_TXP[0..15]
PEG_M_TXP[0..15]
PEG_M_TXP6 R25 N21 PEG_M_RXP6 C947 0.1U_0402_16V4Z PEG_RXP6
PEG_M_TXN6 P25
PCIE_RX6P T PCIE_TX6P
M21 PEG_M_RXN6 C1040 0.1U_0402_16V4Z PEG_RXN6 PEG_M_TXN[0..15]
PCIE_RX6N PCIE_TX6N <9> PEG_M_TXN[0..15]
C
E C
PEG_M_TXP7 N26
R M22 PEG_M_RXP7 C1029 0.1U_0402_16V4Z PEG_RXP7
PCIE_RX7P PCIE_TX7P
PEG_M_TXN7 M26 PCIE_RX7N
F PCIE_TX7N L22 PEG_M_RXN7 C1028 0.1U_0402_16V4Z PEG_RXN7
A
PEG_M_TXP8 M25 PCIE_RX8P
C PCIE_TX8P L23 PEG_M_RXP8 C946 0.1U_0402_16V4Z PEG_RXP8
PEG_M_TXN8 PEG_M_RXN8 C1034 0.1U_0402_16V4Z PEG_RXN8
L25 PCIE_RX8N E PCIE_TX8N K23

PEG_M_TXP9 K26 K21 PEG_M_RXP9 C951 0.1U_0402_16V4Z PEG_RXP9

PEG_M_TXN9 PCIE_RX9P PCIE_TX9P PEG_M_RXN9 C971 0.1U_0402_16V4Z PEG_RXN9
J26 PCIE_RX9N PCIE_TX9N J21

PEG_M_TXP10 J25 J22 PEG_M_RXP10 C1039 0.1U_0402_16V4Z PEG_RXP10

PEG_M_TXN10 PCIE_RX10P PCIE_TX10P PEG_M_RXN10 C967 0.1U_0402_16V4Z PEG_RXN10
H25 PCIE_RX10N PCIE_TX10N H22

PEG_M_TXP11 G26 H23 PEG_M_RXP11 C950 0.1U_0402_16V4Z PEG_RXP11

PEG_M_TXN11 PCIE_RX11P PCIE_TX11P PEG_M_RXN11 C1038 0.1U_0402_16V4Z PEG_RXN11
F26 PCIE_RX11N PCIE_TX11N G23

PEG_M_TXP12 F25 G21 PEG_M_RXP12 C964 0.1U_0402_16V4Z PEG_RXP12

PEG_M_TXN12 PCIE_RX12P PCIE_TX12P PEG_M_RXN12 C970 0.1U_0402_16V4Z PEG_RXN12
E25 PCIE_RX12N PCIE_TX12N F21

PEG_M_TXP13 D26 F22 PEG_M_RXP13 C1041 0.1U_0402_16V4Z PEG_RXP13

PEG_M_TXN13 PCIE_RX13P PCIE_TX13P PEG_M_RXN13 C966 0.1U_0402_16V4Z PEG_RXN13
C26 PCIE_RX13N PCIE_TX13N E22

PEG_M_TXP14 C25 E23 PEG_M_RXP14 C961 0.1U_0402_16V4Z PEG_RXP14

PEG_M_TXN14 PCIE_RX14P PCIE_TX14P PEG_M_RXN14 C949 0.1U_0402_16V4Z PEG_RXN14
B25 PCIE_RX14N PCIE_TX14N D23
B B
PEG_M_TXP15 B23 C22 PEG_M_RXP15 C1036 0.1U_0402_16V4Z PEG_RXP15
PEG_M_TXN15 PCIE_RX15P PCIE_TX15P PEG_M_RXN15 C962 0.1U_0402_16V4Z PEG_RXN15
A23 PCIE_RX15N PCIE_TX15N B22

Clock Calibration
CLK_PCIE_M52 AA22
CLK_PCIE_M52# PCIE_REFCLKP R1365 2K_0402_1%
Y22 PCIE_REFCLKN
PCIE_CALRN V19 1 2 PCIE_1.2V
PCIE_CALRP Y20 1 2
R1366 562_0402_1%
<26> VGA_RST# Y21 PERSTb PCIE_CALI W19 1 2
R1367 1.47K_0402_1%
AA21 PCIE_TEST

1 2 W20 Tie To VSS

R1368 PERSTb_MASK
1.1K_0402_5%
216PLAKB11FG

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T PCIE interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 18 of 54
5 4 3 2 1
 5 4 3 2 1

U1F
1 2
U1B R126 100_0402_5% PART 6 OF 6 R23 10K_0402_5%
PART 2 OF 6 1 2
R124 100_0402_5% Forward Control and External SSC AA8
VARY_BL BLON_PWM <17>
Integrated 1 2 AC8
Compatibility DIGON M52_ENAVDD <17>
D3 TMDS AD20 2 1
NC_MEMVMODE_0 GENERICD R661 4.7K_0402_5%
D2 NC_MEMVMODE_1 TXCM AF8 DVI_CLK- <38>
TXCP AE8 DVI_CLK+ <38>
TX0M AF9 DVI_TX0- <38> TXCLK_UP AB16 TXCLK_U+ <17>
TX0P AE9 DVI_TX0+ <38> TXCLK_UN AB15 TXCLK_U- <17>
V TX1M AE10 DVI_TX1- <38> TXOUT_U3P AC16
AE11 AC15
AE7 I TX1P
AF11
DVI_TX1+ <38> TXOUT_U3N
AA15
NC_DVOVMODE TX2M DVI_TX2- <38> TXOUT_U2P TXOUT_U2+ <17>
AA2 DVPCNTL_0 D TX2P AF12 DVI_TX2+ <38> TXOUT_U2N AA14 TXOUT_U2- <17>
AA3 1 2 AE17
D
AB2
DVPCNTL_1 E 1 2 R132 100_0402_5% TXOUT_U1P
AE16
TXOUT_U1+ <17> D
DVPCNTL_2 TXOUT_U1N TXOUT_U1- <17>
AC1 DVPCNTL_3 O R178 100_0402_5% LVDS channel
TXOUT_U0P AE15 TXOUT_U0+ <17>
AA1 DVPDATA_0 TXOUT_U0N AE14 TXOUT_U0- <17>
AA4 DVPDATA_1
AB3 DVPDATA_2
& TXOUT_L0N AD11 TXOUT_L0- <17>
AC2 VDD_PNL_PLL L22 AD12
DVPDATA_3 TXOUT_L0P TXOUT_L0+ <17>
AF3 1 2 +VDD25 T19 AE12
+2.5VS TXOUT_L1- <17>
+3VS AD1
DVPDATA_4
DVPDATA_5
M 0_0603_5% U8
VDD25_4
VDD25_5
TXOUT_L1N
TXOUT_L1P AE13 TXOUT_L1+ <17>
AB4 DVPDATA_6 U 1 1 W16 VDD25_6 TXOUT_L2N AB12 TXOUT_L2- <17>
AC3 AB13 TXOUT_L2+ <17>
AE2
DVPDATA_7
DVPDATA_8
L 1 C601 TXOUT_L2P
TXOUT_L3N AF15
AC4 T C600 AF14
DVPDATA_9 TXOUT_L3P

1
C168 2
2
AF5 AD9 AC12
R5 R3 AB5
DVPDATA_10 I TPVDD
AD8 0.001U_0402_50V7M TXCLK_LN
AC13
TXCLK_L- <17>
TXCLK_L+ <17>
DVPDATA_11 TPVSS 2 TXCLK_LP
2.2K_0402_5% 2.2K_0402_5% AD5 DVPDATA_12 M 1U_0402_6.3V4Z 10U_0805_10V4Z
LVDS AE3
AE4
DVPDATA_13 E AB10 216PLAKB11FG

2
DVPDATA_14 TXVDDR_1
AD2 DVPDATA_15 D TXVDDR_2 AB9 VDD_PNL_IO2.5
AD4 1
T1 PAD
AB6
DVPDATA_16 I AC10
T2 PAD DVPDATA_17 TXVSSR_1
<17> DDC2_DATA AE6 DVPDATA_18 A TXVSSR_2 AC9 C165
<17> DDC2_CLK AD7 DVPDATA_19 TXVSSR_3 AD10
2 1U_0402_6.3V4Z
<23> VRAM_ID0 AC6 DVPDATA_20
<23> VRAM_ID1 AE5 DVPDATA_21
<23> VRAM_ID2 AD6 DVPDATA_22
<23> VRAM_ID3 AB8 DVPDATA_23
AF23 M52_RED
DAC / CRT R M52_GRN
G AE23
L23 L18 AE22 M52_BLU
M52_RED M52_RED_L M_RED B
1 2 1 2 M_RED <38>
0_0603_5% MCI1608HQ39NJA_0603 AE21 M_HSYNC <16>

VIP Host/External TMDS

L24 L19 HSYNC
VSYNC AF21 M_VSYNC <16>
C M52_GRN C
1 2 M52_GRN_L 1 2 M_GRN M_GRN <38> GENERICA AD21
0_0603_5% MCI1608HQ39NJA_0603 AB18 T10 PAD
L25 L20 GENERICB
M52_BLU 1 2 M52_BLUE_L 1 2 M_BLU M_BLU <38>
0_0603_5% MCI1608HQ39NJA_0603 AD22 1 2
RSET R21 499_0402_1%
1

1 1 1
R180 R182 C182 C180 C181 AD19
AVDD AVDD_2.5
75_0402_1% 75_0402_1%
AVSSN AD18
2 2 2
Y18
2

AVSSQ
12P_0402_50V8J
R181 12P_0402_50V8J AA19
VDD1DI VDDDI_2.5
75_0402_1% 12P_0402_50V8J W6
<23> GPIO0 GPIO_0 General
<23> GPIO1 V6 GPIO_1 VSS1DI AA20
Purpose
Place those components as close T9 PAD
T22 PAD
Y3
W5
GPIO_2 I/O
GPIO_3 DAC2 (TV/CRT2)
as U1 within 500 mils. <23> GPIO4 Y4
V4
GPIO_4
<23> GPIO5 GPIO_5
2
R658
1
10K_0402_5%
T23 PAD Y2 GPIO_6 Place close to U1
<17> OPT_BL_ENA V5 GPIO_7_BLON H2SYNC AE20
W3 AF20 L5 1 2 LUMA <16,38>
<23> GPIO8 GPIO_8 V2SYNC
Y1 AF17 LUMA_M CHB1608U301_0603
<23> ROM_ID3 GPIO_9 Y_G
W2 AE18 CRMA_M
T8 PAD GPIO_10 C_R_PR
V1 L3 1 2 CRMA <16,38>
+3VS <23> ROM_ID0 GPIO_11
V3 AF18 COMP_M CHB1608U301_0603
<23> ROM_ID1 GPIO_12 COMP_B_PB
U4 R20 715_0402_1%
<23> ROM_ID2 GPIO_13
V2 AD17 1 2 L4 1 2 COMP <16,38>
GPIO_14 R2SET
1

<23> M52_THERM# U2 CHB1608U301_0603

<48> POW_SW GPIO_15
GPIO16 U1 AA16
GPIO_16 A2VDD_1

1
R11 1 2 AB17 1 1 1 1 1 1
B A2VDD_2 VDD_DAC2.5 B
499_0402_1% R659 R185 R187 C14 C6 C30 C317 C316 C318
10K_0402_5% AC17 75_0402_1% 75_0402_1% 82P_0402_50V8J
2

A2VSSN_1 82P_0402_50V8J 82P_0402_50V8J

W4 VREFG A2VSSN_2 AD16
2 2 2 2 2 2

2
<23> D+ AB7 216PLAKB11FG
DPLUS NC_A2VDDQ AB19 82P_0402_50V8J
AA7 DMINUS Thermal
<23> D-
1

Diode AC20 R186 82P_0402_50V8J <BOM Structure>

A2VSSQ 82P_0402_50V8J
R13 AD24 AA18 75_0402_1%
VDD_PLL PVDD PLL & VDD2DI VDDDI_2.5
499_0402_1% Y5
4 3 XOUT AE24 XTAL AA17
2

GND OUT PVSS VSS2DI +3VS

XIN 1 2 B2
IN GND VDD_MEM_PLL MPVDD
1 1 18P_0402_50V8J C2 MPVSS
27MHz_16PF_6P27000126 Monitor AF6
HPD1 DVI_DETECT <38>

1
18P_0402_50V8J C611 XXTALIN AF24 Interface
XTALIN
C610
2 2
AF25 XTALOUT
AC21
CRT R17
4.7K_0402_5%
R1
4.7K_0402_5%
DDC1DATA DDC1_DATA <16>
AB21 PLLTEST DDC1CLK AB20 DDC1_CLK <16>
R39
DVI

2
1 2 AD23 TESTEN DDC2DATA AA10 DVI_DAT <38>
1.1K_0402_5% Test AA9
R46 DDC2CLK DVI_CLK <38>

+3VS 1 2 Y5 ROMCSb DDC3DATA AC19 I2C_DAT <23>

+3VS ROM
DDC3CLK AC18 I2C_CLK <23> thermal
10K_0402_5% R18 10K_0402_5%
External
GENERICC AE19 2 1
AB14 LVSSR_1
SSC
AC11 LVSSR_2 LVDS PLL LPVSS AD14
AC14 LVSSR_3 and I/O
U2 R49 AD13
A XTALIN 1 LVSSR_4 GND A
7 VDD REF 5 2 XXTALIN
R662 130_0402_1% LVDS PLL
XIN GPIO16 and I/O
1 XIN MODOUT 4 1 2 GND
1

0_0402_5%
XOUT 8 3 R189
XOUT NC 75_0402_1%
1
2 VSS PD# 6
C612
Security Classification Compal Secret Data Compal Electronics, Inc.
2

ASM3P1819N-SR_SO8 @ 22P_0402_50V8J 1
2
2005/05/26 2006/07/26 Title
Issued Date Deciphered Date M52-T CRT/LVDS/TV-OUT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C613 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1U_0402_16V4Z DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 19 of 54
5 4 3 2 1
 5 4 3 2 1

U1C

Part 3 of 6

MDB0 F16 D10 MAB0

MDB1 DQB_0 MAB_0 MAB1
E20 DQB_1 MAB_1 B8
MDB2 E16 E9 MAB2
MDB3 DQB_2 MAB_2 MAB3
E19 DQB_3 MAB_3 C8
MDB4 F19 B10 MAB4
MDB5 DQB_4 MAB_4 MAB5
E17 DQB_5 MAB_5 B7
MDB6 E15 C7 MAB6
MDB7 DQB_6 MAB_6 MAB7

MEMORY INTERFACE B
F18 DQB_7 MAB_7 E7
MDB8 F14 G6 MAB8
MDB9 DQB_8 MAB_8 MAB9
F13 DQB_9 MAB_9 F9
D MDB10 MAB10 D
E14 DQB_10 MAB_10 E8
MDB11 E13 F8 MAB11
MDB12 DQB_11 MAB_11 MAB12
F10 DQB_12 MAB_12 C6
MDB13 E10 F7 MAB13
MDB14 DQB_13 MAB_13 MAB14
F11 DQB_14 MAB_14 H7
MDB15 E11
MDB16 DQB_15
C20 DQB_16
MDB17 B19
MDB18 DQB_17 DQMB#0
B20 DQB_18 DQMBb_0 F17
MDB19 C19 F12 DQMB#1
MDB20 DQB_19 DQMBb_1 DQMB#2
C16 DQB_20 DQMBb_2 B18
MDB21 C17 B13 DQMB#3
MDB22 DQB_21 DQMBb_3 DQMB#4
B16 DQB_22 DQMBb_4 J5
MDB23 B17 J2 DQMB#5
MDB24 DQB_23 DQMBb_5 DQMB#6
B12 DQB_24 DQMBb_6 P5
MDB25 C15 P2 DQMB#7
MDB26 DQB_25 DQMBb_7
C11 DQB_26
MDB27 B15
MDB28 DQB_27
C14 DQB_28
MDB29 B11 E18 QSB0
MDB30 DQB_29 QSB_0 QSB1
B14 DQB_30 QSB_1 E12
MDB31 C12 C18 QSB2
MDB32 DQB_31 QSB_2 QSB3
F5 DQB_32 QSB_3 C13
MDB33 G5 J6 QSB4
MDB34 DQB_33 QSB_4 QSB5
H6 DQB_34 QSB_5 H3
MDB35 QSB6

read strobe
H5 DQB_35 QSB_6 P6
MDB36 K6 P3 QSB7
MDB37 DQB_36 QSB_7 QSB[7..0]
K5 DQB_37 <22> QSB[7..0]
MDB38 L6
MDB39 DQB_38
L5 DQB_39
MDB40 F2
MDB41 DQB_40 DQMB#[7..0]
G2 DQB_41 <22> DQMB#[7..0]

write strobe
C MDB42 C
H2 DQB_42
MDB43 G3 MDB[63..0]
DQB_43 <22> MDB[63..0]
MDB44 K2
MDB45 DQB_44 MAB[15..0]
L2 DQB_45 <22> MAB[15..0]
MDB46 J3
MDB47 DQB_46
K3 DQB_47
MDB48 M5
MDB49 DQB_48
M6 DQB_49
MDB50 N6
MDB51 DQB_50
N5 DQB_51
MDB52 R6 C9 CLKB0
DQB_52 CLKB0 CLKB0 <22>
MDB53 U5 B9 CLKB0#
DQB_53 CLKB0b CLKB0# <22>
MDB54 R5
MDB55 DQB_54 CKEB0
T5 DQB_55 CKEB B6 CKEB0 <22>
MDB56 M2
MDB57 DQB_56 RASB#0
M3 DQB_57 RASBb C5 RASB#0 <22>
MDB58 N2
MDB59 DQB_58 CASB#0
N3 DQB_59 CASBb E6 CASB#0 <22>
VDD_MEM18 MDB60 R2
MDB61 DQB_60 WEB#0
R3 DQB_61 WEBb C4 WEB#0 <22>
MDB62 T2 DQB_62
1

MDB63 T3 B5 CSB0#
DQB_63 CSBb_0 CSB0# <22>
R51 F6 CSB1#
CSBb_1 CSB1# <22>
100_0402_1%

B4 CLKB1
CLKB1 <22>
2

VDD_MEM18_REFD CLKB1 CLKB1#

C3 MVREFD_1 CLKB1b A4 CLKB1# <22>
VDD_MEM18_REFS B3 MVREFS_1
1

1 C10
R55 0.1U_0402_16V4Z
100_0402_1%

B 2 B
E3
2

VDD_MEM18 TEST_MCLK
E5 TEST_YCLK
1

E2 MEMTEST
1

R56 R223
100_0402_1% 4.7K_0402_5%
R221
4.7K_0402_5% 216PLAKB11FG
2

1
2

R112
243_0603_1%
1

1
R57
2

100_0402_1% C8
0.1U_0402_16V4Z
2
2

M52@ R51,R55,C10,R56,R57,C8,R223,R221,R112
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 20 of 54
5 4 3 2 1
 U1E 5 4 3 2 1

Part 5 of 6 U1D

PART 4 OF 6 L2
A25 CHB1608U301_0603
PCIE_VSS_1 VDD_MEM18 PCIE_PVDD_12
AB22 PCIE_VSS_2 A12 VDDR1_1 PCIE_PVDD_12_1 AA24 2 1
AB25 G19 C119 A15 AB23 1 1 1 1
PCIE_VSS_3 VSS_1 0.01U_0402_16V7K VDDR1_2 PCIE_PVDD_12_2
AC22 PCIE_VSS_4 VSS_2 A10 A18 VDDR1_3 PCIE_PVDD_12_3 AB24
AC26 A13 1 1 A21 AC23 C109 C113 C107 C143
PCIE_VSS_5 VSS_3 VDDR1_4 PCIE_PVDD_12_4
B24 PCIE_VSS_6 VSS_4 A16 A3 VDDR1_5
C124 2 2 2 2
B26 PCIE_VSS_7 VSS_5 A19 A6 VDDR1_6 PCIE_VDDR_12_10 N19
C23 A2 0.01U_0402_16V7K A9 N20 1000P_0402_50V7K 22U_0805_6.3V4Z
PCIE_VSS_8 VSS_6 2 2 VDDR1_7 PCIE_VDDR_12_11 1U_0402_6.3V7K 0.1U_0402_16V4Z
C24 PCIE_VSS_9 VSS_7 A7 C1 VDDR1_8 PCIE_VDDR_12_12 P19
D22 PCIE_VSS_10 VSS_8 AC5 D11 VDDR1_9 PCIE_VDDR_12_13 P20
D D
D24 PCIE_VSS_11 VSS_9 AC7 D13 VDDR1_10 PCIE_VDDR_12_14 R19 PCIE_VDD12
D25 PCIE_VSS_12 VSS_10 AE1 D15 VDDR1_11 PCIE_VDDR_12_15 T20
E24 PCIE_VSS_13 VSS_11 AF2 D17 VDDR1_12 PCIE_VDDR_12_16 U20
F23 PCIE_VSS_14 VSS_12 B1 D19 VDDR1_13 PCIE_VDDR_12_17 L19
0.1U_0402_16V4Z 0.1U_0402_16V4Z L21

PCI-Express
F24 PCIE_VSS_15 VSS_13 B21 D5 VDDR1_14 PCIE_VDDR_12_18 L20
G22 C10 D8 CHB1608U301_0603
PCIE_VSS_16 VSS_14 VDDR1_15 1U_0402_6.3V7K
G24 PCIE_VSS_17 VSS_15 C21 1 1 1 1 E1 VDDR1_16 PCIE_VDDR_12_1 AC24 2 1 PCIE_1.2V
G25 D12 C98 C99 C101 C102 E4 AC25 1 1 1 1
PCIE_VSS_18 VSS_16 1000P_0402_50V7K VDDR1_17 PCIE_VDDR_12_2
H20 PCIE_VSS_19 VSS_17 D14 F20 VDDR1_18 PCIE_VDDR_12_3 AD25
H21 D16 G12 AE25 C116 C112 C117 C108
PCIE_VSS_20 VSS_18 2 2 2 2 VDDR1_20 PCIE_VDDR_12_4

Memory I/O
H24 D18 G15 J19 0.1U_0402_16V4Z
PCIE_VSS_21 VSS_19 1000P_0402_50V7K VDDR1_21 PCIE_VDDR_12_5 2 2 2 2
J23 PCIE_VSS_22 VSS_20 D20 G18 VDDR1_22 PCIE_VDDR_12_6 J20
J24 D21 G4 K19 22U_0805_6.3V4Z 1000P_0402_50V7K
PCIE_VSS_23 VSS_21 VDDR1_23 PCIE_VDDR_12_7
K22 PCIE_VSS_24 VSS_22 D4 G9 VDDR1_24 PCIE_VDDR_12_8 K20
K24 D6 0.1U_0402_16V4Z 0.1U_0402_16V4Z H1 M19
PCIE_VSS_25 VSS_23 VDDR1_25 PCIE_VDDR_12_9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
K25 PCIE_VSS_26 VSS_24 D7 H12 VDDR1_26 1 VDD_CORE
L21 PCIE_VSS_27 VSS_25 D9 1 1 1 1 H15 VDDR1_27 PCIE_PVSS AA23 1 1 1 1 1
L24 E21 C135 C136 C85 H18 +
PCIE_VSS_28 VSS_26 VDDR1_28
PCI-Express GND

M20 F1 C137 H8 L11 C133 C95 C126 C96 C138 C139

PCIE_VSS_29 VSS_27 1000P_0402_50V7K VDDR1_29 VDDC_1 @ 470U_D2_2.5VM
M23 PCIE_VSS_30 VSS_28 F15 H9 VDDR1_30 VDDC_2 L12
2 2 2 2 2 2 2 2 2 2
M24 PCIE_VSS_31 VSS_29 F3 J4 VDDR1_31 VDDC_3 L16
N22 F4 J8 M11 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCIE_VSS_32 VSS_30 0.1U_0402_16V4Z VDDR1_32 VDDC_4
N24 PCIE_VSS_33 VSS_31 G10 L1 VDDR1_33 VDDC_5 M12
N25 G13 L4 M13 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCIE_VSS_34 VSS_32 VDDR1_34 VDDC_6
P21 PCIE_VSS_35 VSS_33 G16 L8 VDDR1_35 VDDC_7 M15 1 1 1 1 1
P24 PCIE_VSS_36 VSS_34 G8 N4 VDDR1_36 P VDDC_8 N12

Core
R20 H10 1 1 1 N8 N13 C24 C22 C82 C27 C38
PCIE_VSS_37 VSS_35 VDDR1_37 VDDC_9
R23 PCIE_VSS_38 VSS_36 H13 C129 C130 C131 R1 VDDR1_38 O VDDC_10 N14
2 2 2 2 2
R24 H16 R7 P13
T22
PCIE_VSS_39
PCIE_VSS_40
VSS_37
VSS_38 H17 0.1U_0402_16V4Z
2 2 2
1000P_0402_50V7K R8
VDDR1_39
VDDR1_40 W VDDC_11
VDDC_12 P14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
T24 H4 T6 P15
T25
PCIE_VSS_41
PCIE_VSS_42
VSS_39
VSS_40 J1 0.1U_0402_16V4Z VDDR1_41 E VDDC_13
VDDC_14 R12 1 1 1 1
C C
U21
U24
PCIE_VSS_43 VSS_41 K4
L13 R VDDC_15 R14
R15 C240 C245 C246 C244
PCIE_VSS_44 VSS_42 VDDC_16
V20 PCIE_VSS_45 VSS_43 L15 VDDC_17 R16
2 2 2 2
V23 PCIE_VSS_46 VSS_44 L3 VDDC_18 T11
V24 M1 T15 0.1U_0402_16V4Z 10U_0805_10V4Z
PCIE_VSS_47 VSS_45 VDDC_19 0.1U_0402_16V4Z 0.1U_0402_16V4Z
W22 PCIE_VSS_48 VSS_46 M14 VDDC_20 T16
W23 M16 W11 0.1U_0402_16V4Z
PCIE_VSS_49 VSS_47 VDDC_21 M52_VDD25 0.1U_0402_16V4Z 2
W24 PCIE_VSS_50 VSS_48 M4 VDDC_22 W9 1 +2.5VS
W25 M7 Y11 1 1 1 1 L1
PCIE_VSS_51 VSS_49 VDDC_23
Y23 PCIE_VSS_52 VSS_50 M8 VDDC_24 Y9
Y24 N11 M52_VDDR 0.01U_0402_16V7K 0.1U_0402_16V4Z V8 C134 C118 C121 C97 CHB1608U301_0603
PCIE_VSS_53 VSS_51 VDDR3_1
VSS_52 N15 1 1 1 1 1 W15 VDDR3_2 VDD25_1 H11
2 2 2 2
P1 W17 H14

I/O Internal
VSS_53 C110 C114 C111 C106 C115 VDDR3_3 VDD25_2 0.01U_0402_16V7K 0.1U_0402_16V4Z
VSS_54 P12 W18 VDDR3_4 VDD25_3 H19
P16 2.2U_0603_6.3V6K W7 K8
VSS_55 2 2 2 2 2 VDDR3_5 VDD25_4
VSS_56 P4 Y15 VDDR3_6 VDD25_5 P8
P7 Y17 W13 M52_VDDPLL
VSS_57 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR3_7 VDDPLL M52_VDDC 1U_0402_6.3V7K
VSS_58 R11 VDDCI_1 L14 2 1
R13 N16 1 1 1 1 1 L63 CHB1608U301_0603
VSS_59 VDDCI_2

I/0
R4 P11 C100
VSS_60 VDDCI_3 C104 C103 C105 C144
VSS_61 T12 VDDCI_4 T13
T14 @ R137 0_0402_5% AA5 22U_0805_6.3V4Z
VSS_62 VDDR4_1 2 2 2 2 2
VSS_63 T4 2 1 +3VS AA6 VDDR4_2
T8 AD3 AD15 1U_0402_6.3V7K 1U_0402_6.3V7K 0.1U_0402_16V4Z
VSS_64 VDDR4_3 LPVDD VDD_PNL_PLL
VSS_65 U3 Y6 VDDR4_4 1
U6 Q34 AA11
VSS_66 LVDDR C169
U7 AA12
CORE GND VSS_67 LVDDR 1U_0402_6.3V4Z
S

W10 1 3 AA13
D

VSS_68 LVDDR 2
VSS_69 W12
W14 SI2301BDS_SOT23 1

LVDS PLL, I/O

VSS_70
2

W8 R138 AB11
G

VDD_PNL_IO2.5
2

VSS_71 100K_0402_5% LVDDR C167

VSS_72 Y12
B
Y14 1U_0402_6.3V4Z B
VSS_73 VDD_MEM_CLK 2

Clock
I/O
Memory
VSS_74 Y8 1 L7 VDDRH1
1

C123 VDD_PNLIO2.5
0.1U_0402_16V4Z
216PLAKB11FG 2
J7 VSSRH1
1

<36,39,40,49,50> PWR_GD 2
G 216PLAKB11FG
S Q20
3

RHU002N06_SOT323
PLACE ALL CAPS ON THIS PAGE CLOSE TO ASIC M52_VDDPLL 2 1 PCIE_1.2V
L17
1 1 1 CHB1608U301_0603
C172 C141
C140 10U_0805_10V4Z
0.1U_0402_16V4Z 1U_0402_6.3V4Z
2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 21 of 54
5 4 3 2 1
 5 4 3 2 1

DDR VRAM: 8Mx32/16Mx32 2 pcs

G10

G10
H10

D11
D10

D10
D11

H10
K10

B11

B11

K10
F10

F10
J10

J10
G5

G5
H5

D9
D6
D5
D4

D4
D5
D6
D9

H5
K5

E9
E6

B4

B4

E6
E9

K5
F5

F5
J5

J5
U67 U68

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDB27 B7 N5 MAB0 N5 B7 MDB56
MDB25 DQ0 A0 MAB1 A0 DQ0 MDB57 QSB[7..0]
C6 DQ1 A1 N6 N6 A1 DQ1 C6 <20> QSB[7..0]
MDB30 B6 M6 MAB2 M6 B6 MDB59
MDB28 DQ2 A2 MAB3 A2 DQ2 MDB58 DQMB#[7..0]
B5 DQ3 A3 N7 N7 A3 DQ3 B5 <20> DQMB#[7..0]
MDB24 C2 N8 MAB4 N8 C2 MDB60
MDB31 DQ4 A4 MAB5 A4 DQ4 MDB61 MDB[63..0]
Place VREF divider and CAP D3 DQ5 A5 M9 M9 A5 DQ5 D3 <20> MDB[63..0]
D MDB26 MAB6 MDB63 D
close to memory D2 DQ6 A6 N9 N9 A6 DQ6 D2
MDB29 E2 N10 MAB7 N10 E2 MDB62 MAB[15..0]
DQ7 A7 A7 DQ7 <20> MAB[15..0]
MDB15 K13 N11 MAB8 N11 K13 MDB42
VDD_MEM18 MDB10 DQ8 A8/AP MAB9 A8/AP DQ8 MDB47
K12 DQ9 A9 M8 M8 A9 DQ9 K12
MDB13 J13 L6 MAB10 L6 J13 MDB43
MDB11 DQ10 A10 MAB11 A10 DQ10 MDB45
J12 DQ11 A11 M7 M7 A11 DQ11 J12
1

MDB9 G13 N4 MAB12 N4 G13 MDB41

MDB8 DQ12 BA0 MAB13 BA0 DQ12 MDB40
G12 DQ13 BA1 M5 M5 BA1 DQ13 G12
R1369 MDB12 F13 F13 MDB46 CLKB0
DQ14 DQ14 CLKB0 <20>
10K_0402_5% MDB14 F12 B3 DQMB#3 DQMB#7 B3 F12 MDB44 CLKB0#
DQ15 DM0 DM0 DQ15 CLKB0# <20>
MDB16 F3 H12 DQMB#1 DQMB#5 H12 F3 MDB48
2

MDB17 DQ16 DM1 DQMB#2 DQMB#6 DM1 DQ16 MDB49 CKEB0

F2 DQ17 DM2 H3 H3 DM2 DQ17 F2 CKEB0 <20>
10mil VREFA MDB18 G3 B12 DQMB#0 DQMB#4 B12 G3 MDB50
MDB19 DQ18 DM3 DM3 DQ18 MDB51 RASB#0
G2 DQ19 DQ19 G2 RASB#0 <20>
1

MDB20 J3 B2 QSB3 QSB7 B2 J3 MDB55

MDB21 DQ20 DQS0 QSB1 QSB5 DQS0 DQ20 MDB54 CASB#0
1 C997 J2 DQ21 DQS1 H13 H13 DQS1 DQ21 J2 CASB#0 <20>
R1370 MDB22 K2 H2 QSB2 QSB6 H2 K2 MDB53
10K_0402_5% MDB23 DQ22 DQS2 QSB0 QSB4 DQS2 DQ22 MDB52 WEB#0
K3 DQ23 DQS3 B13 B13 DQS3 DQ23 K3 WEB#0 <20>
0.1U_0402_16V4Z MDB6 E13 E13 MDB33
2

2 MDB0 DQ24 VREFA DQ24 MDB32 CSB0#

D13 DQ25 VREF N13 N13 VREF DQ25 D13 CSB0# <20>
MDB2 D12 M13 M13 D12 MDB35 CSB1#
DQ26 MCL MCL DQ26 CSB1# <20>
MDB5 C13 L9 MAB14 L9 C13 MDB34
MDB1 DQ27 NC2 NC2 DQ27 MDB37
B10 DQ28 NC3 M10 M10 NC3 DQ28 B10
MDB3 B9 B9 MDB36 CLKB1
DQ29 DQ29 CLKB1 <20>
MDB4 C9 M2 RASB#0 M2 C9 MDB38 CLKB1#
DQ30 RAS# RAS# DQ30 CLKB1# <20>
MDB7 B8 L2 CASB#0 L2 B8 MDB39
DQ31 CAS# WEB#0 CAS# DQ31
WE# L3 L3 WE#
N2 CSB0# N2
CS0# CS0#
C3 VDDQ VDDQ C3
C5 N12 CKEB0 N12 C5
VDDQ CKE CKE VDDQ
C7 VDDQ VDDQ C7
C8 M11 CLKB0 CLKB1 M11 C8 Place close to U67
C VDDQ CK CLKB0# CLKB1# CK VDDQ C
C10 VDDQ CK# M12 M12 CK# VDDQ C10
C12 C12 CLKB0
VDDQ VDDQ
E3 VDDQ NC C4 C4 NC VDDQ E3
E12 C11 C11 E12 CLKB0#
VDDQ NC NC VDDQ
F4 VDDQ NC H4 H4 NC VDDQ F4
VDD_MEM18 F11 VDDQ NC H11 H11 NC VDDQ F11

1
G4 VDDQ NC L12 L12 NC VDDQ G4
G11 VDDQ NC L13 L13 NC VDDQ G11 VDD_MEM18
J4 M3 M3 J4 R1371 R1372
VDDQ NC CSB1# NC VDDQ 56_0402_5% 56_0402_5%
J11 VDDQ CS1# M4 M4 CS1# VDDQ J11
K4 N3 N3 K4

2
VDDQ NC NC VDDQ
K11 VDDQ VDDQ K11
VSS E7 E7 VSS 1
D7 VDD VSS E8 E8 VSS VDD D7
D8 E10 E10 D8 C998
VDD VSS VSS VDD 470P_0402_50V7K
E4 VDD VSS K6 K6 VSS VDD E4
2
E11 VDD VSS K7 K7 VSS VDD E11
L4 VDD VSS K8 K8 VSS VDD L4
L7 VDD VSS K9 K9 VSS VDD L7
L8 VDD VSS L5 L5 VSS VDD L8
L11 VDD VSS L10 L10 VSS VDD L11
VSS E5 E5 VSS Place close to U68
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
CLKB1

CLKB1#
HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
J9
J8
J7
J6
H9
H8
H7
H6
G9
G8
G7
G6
F9
F8
F7
F6

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

1
R1375 R1376
56_0402_5% 56_0402_5%
B B

2
Place close to U68
Place close to U67 C999
1

VDD_MEM18 470P_0402_50V7K
VDD_MEM18 2
1U_0603_10V6K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0603_10V6K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 C1004
C1013
C1000 C1001 C1002 C1003 C1005 C1006 C1007 C1008
C1009 C1010 C1011 C1012 C1014 C1015 C1016 C1017 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDD_MEM18
VDD_MEM18
1U_0603_10V6K 0.01U_0402_16V7K
1U_0603_10V6K 0.1U_0402_16V4Z
1 1 1 1 1
1 1 1 1 1 C1022
C1027
C1018 C1019 C1020 C1021
C1023 C1024 C1025 C1026 2 2 2 2 2
2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_6.3V6M
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 22 of 54
5 4 3 2 1
 5 4 3 2 1

+2.5VS
+3VS

<4,13,14,15,26,28,30> ICH_SMBCLK R161 1 2 0_0402_5% L6

1 C202 CHB1608U301_0603
R145 1 2 0_0402_5% 0.1U_0402_16V4Z 2 1
<4,13,14,15,26,28,30> ICH_SMBDATA VDD_PLL
1 1 1
C203 2200P_0603_50V7K (20mA 2.5V)
U22 2 C207 C201
1 2
R146 1 2 @ 0_0402_5% 8 1 10U_0805_10V4Z 0.001U_0402_50V7M
<19> I2C_CLK SCLK VDD 2 2 2
R147 1 2 @ 0_0402_5% 7 2 C200
<19> I2C_DAT SDATA D+ D+ <19>
0.1U_0402_16V4Z
6 ALERT# D- 3 D- <19>
D @ R160 0_0402_5% L7 D
5 4 1 2 CHB1608U301_0603
GND THERM#
2 1 VDD_PNL_IO2.5
+3VS
1 1 1
ADM1032ARMZ (200mA 2.5V)
C211 C254
10U_0805_10V4Z 0.001U_0402_50V7M

1
2 2 2

1
1 2 R144 C258
R148 @ 4.7K_0402_5% 0.1U_0402_16V4Z
0_0402_5% R703
@ 10K_0402_5% L9

2
CHB1608U301_0603
M52_THERM# <19>

2
2 1 VDD_PNL_PLL

1
C 1 1 1
2 Q12 (40mA 2.5V)
B @ PMST3904_SOT323 C212 C256
E 10U_0805_10V4Z 0.001U_0402_50V7M

3
2 2 2
C259
0.1U_0402_16V4Z

+3VS 1 2 L12
THERM_SCI# <4,26>
R154 @ 10K_0402_5% R173 CHB1608U301_0603
1 2 0_0402_5% 2 1
<19> GPIO0 AVDD_2.5
1 1 1
R152 @ 10K_0402_5% (65mA 2.5V)
1 2 C209 C208
<19> GPIO1 10U_0805_10V4Z 0.001U_0402_50V7M
R6 2 2 2
R149 @ 10K_0402_5%
1 2 1 2 STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED C225
<19> GPIO4
0.1U_0402_16V4Z
C R174 10K_0402_5% @ 2.2K_0402_5% C
1 2 TX_PWRS_ENB GPIO0 FULL SWING 1 L13
<19> GPIO5
CHB1608U301_0603
2 1 VDDDI_2.5
TX_DEEMPH_EN GPIO1 TRANSMITTER DE-EMPHASIS ENABLE 1 1 1
- TX DE-EMPHASIS DISABLED FOR MOBILE 0 (40mA 2.5V)
R157 @ 10K_0402_5% C216 C214
1 2 10U_0805_10V4Z 0.001U_0402_50V7M
<19> GPIO8 2 2 2
DEBUG_ACCESS GPIO4 Strap to set the debug muxes to bring out
DEBUG signals even if registers are inaccessible 0 C215
0.1U_0402_16V4Z
R153 @ 10K_0402_5%
1 2 FORCE_COMPLIANCE GPIO8 Force chip to get to compliance state 0 L11
<19> ROM_ID0
queckly for tester pruposes CHB1608U301_0603
R150 @ 10K_0402_5% 2 1 VDD_PNLIO2.5
<19> ROM_ID1 1 2 1 1
No ROM , with 128M frame buffer 0 0 0 X (200MA 2.5V)
R155 F64@ C221 C224
1 2 10K_0402_5% GPIO 10U_0805_10V4Z 0.1U_0402_16V4Z
<19> ROM_ID2 0 1 0 X 2 2
ROMIDCFG(3:0) (9,13,12,11) No ROM , with 64M frame buffer
R156 @ 10K_0402_5%
<19> ROM_ID3 1 2
L14
CHB1608U301_0603
2 1 VDD_DAC2.5
R158 @ 10K_0402_5% (130mA 2.5V)
1 1 1
<19> VRAM_ID0 1 2
C217 C222
10U_0805_10V4Z 0.1U_0402_16V4Z
R159 @ 10K_0402_5% 2 2 2
1 2 Samsung 8Mx32 1.8V F die K4D553235F-VC33 0 0 0 0 C223
B <19> VRAM_ID1 B
VRAM_ID[0:3] 0.1U_0402_16V4Z
R165 Hynix 16Mx32 1.8V HY5DS113222FMP-28 0 0 0 1
1 2 DVPDATA
<19> VRAM_ID2 Hynix 8Mx32 1.8V HY5DS573222F-33 0 0 1 0
128M@ 10K_0402_5% (20,21,22,23)

R166 Hynix 16Mx32 1.8V HY5DS113222FMP-33 0 0 1 1

<19> VRAM_ID3 1 2
128M@ 10K_0402_5%
L15
CHB1608U301_0603
VDD_CORE 2 1 VDD_MEM_PLL
1 1 1
(20mA 1.2V)
C185 C189
10U_0805_10V4Z 0.001U_0402_50V7M
2 2 2
Samsung 64MB Hynix 128MB Hynix 64MB C187
Hynix 128MB 0.1U_0402_16V4Z
(300MHz) (350MHz) (300MHz) (300MHz)

R165 0 0 1 1
VDD_MEM18
R166 0 1 0 1 L16 L66
CHB1608U301_0603 CHB1608U301_0603
2 1 VDD_MEM_CLK PCIE_1.2V 2 1 PCIE_VDD12
1 1 1 1 1
C196 C198 C190 C195
10U_0805_10V4Z 0.1U_0402_16V4Z 22U_0805_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2 2
A C194 A
0.001U_0402_50V7M

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T Filters / Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 23 of 54
5 4 3 2 1
 5 4 3 2 1

D D
+5VS
+3VS

2
R433
R1041 1 2 8.2K_0402_5% PCI_DEVSEL#
330_0402_5%
R1042 1 2 8.2K_0402_5% PCI_STOP#

1
ALS_EN
ALS_EN <17>
R1043 1 2 8.2K_0402_5% PCI_TRDY#

1
D
R1044 1 2 8.2K_0402_5% PCI_FRAME# <30> PCI_AD[0..31] U26B ALS_EN# 2
PCI_AD0 E18 D7 PCI_REQ0# G Q45
AD0 REQ0# PCI_REQ0#
R1045 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT0# S
PCI_GNT0#

3
AD1 GNT0#
R1046 1 2 8.2K_0402_5% PCI_IRDY#
PCI_AD2
PCI_AD3
A16
F18
AD2 PCI REQ1# C16
D16
PCI_REQ1# RHU002N06_SOT323

PCI_AD4 AD3 GNT1# PCI_REQ2#

E16 AD4 REQ2# C17 PCI_REQ2# <30>
R1047 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2# <30>
PCI_AD6 E17 E13 PCI_REQ3#
R1048 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4#
R1049 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 IDE_RESET# +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14 IDE_RESET# <25>
PCI_AD10 E14 C8 CPPE# CPPE# <15,38>
R1050 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8 ALS_EN#

5
PCI_AD12 B12 U56
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 1

P
AD13 C/BE0# PCI_CBE#0 <30> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <30> Y PCI_RST# <25,30>
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 <30> A

G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 <30>
PCI_AD17 C11 @ TC7SH08FU_SSOP5

3
PCI_AD18 AD17 PCI_IRDY# R1051
D11 AD18 IRDY# A7 PCI_IRDY# <30>
C PCI_AD19 PCI_PAR 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR <30>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <30>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <30> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# <30,36>
R1052 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# <30>

5
PCI_AD26 A8 F14 PCI_TRDY# U59
AD26 TRDY# PCI_TRDY# <30>
R1053 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1

P
AD27 FRAME# PCI_FRAME# <30> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# <7,25,26,28,30,36>
R1054 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R1055 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# @ TC7SH08FU_SSOP5
PCI_PME#

3
AD31 PME#
R1056 1 2 8.2K_0402_5% PCI_PIRQE# R1057

R1058 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3

Interrupt I/F G8 PCI_PIRQE# 2
0_0402_5%
1
PIRQA# GPIO2 / PIRQE# PCI_PIRQE# <30>
PCI_PIRQB# B4 F7 PCI_PIRQF#
R1059 1 PCI_PIRQG# PCI_PIRQC# PIRQB# GPIO3 / PIRQF# PCI_PIRQG#
2 8.2K_0402_5% <30> PCI_PIRQC# C5 PIRQC# GPIO4 / PIRQG# F8 PCI_PIRQG# <30>
PCI_PIRQD# B5 G7 PCI_PIRQH#
<30> PCI_PIRQD# PIRQD# GPIO5 / PIRQH#
R1060 1 2 8.2K_0402_5% PCI_PIRQH#

R1061 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
2 1
0_0402_5%
ACCEL_INT <30>
RSVD[1] RSVD[6] R1388
AD5 RSVD[2] RSVD[7] AG8
R1062 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R1063 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R1064 1 2 8.2K_0402_5% CPPE# Place closely pin A9
ICH7_BGA652~D
R1262 1 2 @ 8.2K_0402_5% IDE_RESET#
CLK_PCI_ICH
B B

2
R1065

@10_0402_5%

1
1
C729

@ 8.2P_0402_50V
2

Boot BIOS destination ALS_EN#

1

SPI@ LPC@ R1290

1K_0402_5%
BIOS_SEL1 Short Open
2

A A

L The pad must be placed on PCB easily

contact space for BIOS team setting.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 24 of 54
5 4 3 2 1
 5 4 3 2 1

C516
+3VS
C641 Multi Bay II connector
1 2 ICH_RTCX1 1 2
15P_0402_50V8J
<24> IDE_RESET# JP5
0.1U_0402_16V4Z

14
1
1 1

4
R432 12 R301 2

P
Y4 A 2
O 11 2 1 ODD_RST# 3 3
10M_0402_5% PLT_RST_B# 2 1 13 33_0402_5% 4
B 4

G
U26A R1036 0_0402_5% 5 ODD_RST#
LPC_AD[0..3] <30,34,35,36>

2
32.768KHZ_12.5P_MC-146 U43D 5 PD_D8
6

7
6

RTC
AB1 AA6 LPC_AD0 SN74LVC08APW_TSSOP14 7 PD_D7
C528 ICH_RTCX2 RTXC1 LAD0 LPC_AD1 7 PD_D9
1 2 AB2 RTCX2 LAD1 AB5 <24,30> PCI_RST# 2 1 8 8
15P_0402_50V8J AC4 LPC_AD2 R1037 @ 0_0402_5% 9 PD_D6
D R230 1 ICH_RTCRST# AA3 LAD2 LPC_AD3 9 PD_D10 D
+RTCVCC 2 RTCRST# LAD3 Y6 10 10

LPC
20K_0402_5% 11 PD_D5
R1026 11
ICH_INTVRMENW4 AC3 LPC_DRQ#0 12 PD_D11
INTVRMEN LDRQ0# LPC_DRQ#0 <34> 12
CMOS_CLR1 +RTCVCC 1 2 SM_INTRUDER#Y5 AA5 PAD T88 13 PD_D4
1M_0402_5% INTRUDER# LDRQ1# / GPIO23 13 PD_D12
1 2 14 14
AB3 LPC_FRAME# 15 PD_D3
LFRAME# LPC_FRAME# <30,34,35,36> 15
NO SHORT PADS W1 16 PD_D13
EE_CS 16 PD_D2
Y1 EE_SHCLK 2 1 R1243 10K_0402_5% +3VS 17 17
C287 Y2 AE22 GATEA20 18 PD_D14
EE_DOUT A20GATE GATEA20 <36> 18

LAN
1U_0603_10V4Z W3 AH28 H_A20M# 19 PD_D1
EE_DIN A20M# H_A20M# <4> 19

CPU
1 2 20 PD_D15
H_CPUSLP_R# 20 PD_D0
V3 LAN_CLK CPUSLP# AG27 PAD T86 21 21
22 PD_DREQ
C721 R1028 DPRSLP# R1025 2 22
U3 LAN_RSTSYNC TP1 / DPRSTP# AF24 1 0_0402_5% H_DPRSTP# <4,49> 23 23
2 1 1 2 AH25 DPSLP# R1035 2 1 0_0402_5% 24 PD_IOR#
TP2 / DPSLP# H_DPSLP# <4> 24
@ 10_0402_5% U5 R1027 2 1 56_0402_5% +VCCP 25 PD_IOW#
@ 10P_0402_25V8K LAN_RXD0 H_FERR# 25
V4 LAN_RXD1 FERR# AG26 H_FERR# <4> 26 26
T5 27 PD_IORDY
33_0402_5% 1 LAN_RXD2 27
<37> AC97_BITCLK_MDC 2 R1314 GPIO49 / CPUPWRGD AG24 H_PWRGOOD
H_PWRGOOD <4> 28 28 PD_DACK#
U7 29 PD_IRQ
33_0402_5% 1 LAN_TXD0 H_IGNNE# 29
<31> AC97_BITCLK_CODEC 2 R371 V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# <4> 30 30
V7 AG21 FWH_INIT# 31 PD_A1
LAN_TXD2 INIT3_3V# FWH_INIT# 31
<37> AC97_SYNC_MDC 33_0402_5% 1 2 R402 AF22 H_INIT# 32
INIT# H_INIT# <4> +3VS +VCCP 32
AF25 H_INTR 33 PD_A0
INTR H_INTR <4> 33
<31> AC97_SYNC_CODEC 33_0402_5% 2 1 R376 34 PD_A2
34

AC-97/AZALIA
AC97_BITCLK U1 R1244 2 1 10K_0402_5% 35 PD_CS#1
33_0402_5% 1 ACZ_BCLK 35
<37> AC97_RST#_MDC 2 R1315 AC97_SYNC R6 ACZ_SYNC RCIN# AG23 KB_RST#
KB_RST# <36> 36 36 PD_CS#3
37 MB2_LED#
37

1
<31> AC97_RST#_CODEC 33_0402_5% 2 1 R1029 AC97_RST# R5 AF23 H_SMI# 38
ACZ_RST# SMI# H_SMI# <4> 38
AH24 H_NMI R1030 39
NMI H_NMI <4> +3VS 39
AC97_SDIN0 T2 40
<31> AC97_SDIN0 ACZ_SDIN0 40
AC97_SDIN1 T3 AH22 2 1 H_STPCLK# 56_0402_5% 41
C <37> AC97_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# <4> 41 C
T1 R1408 0_0402_5% 42 +5VS_MB

2
ACZ_SDIN2 42

1
+5VS +3VS AF26 THRMTRIP_ICH# 1 2 43
THERMTRIP# H_THERMTRIP# <4,7> 43
<31> AC97_SDOUT_CODEC 33_0402_5% 2 1 R367 AC97_SDOUT T4 R1031 24.9_0402_1% R72 44
ACZ_SDOUT 4.7K_0402_5% 44 MBAY_DET#
45 45
<37> AC97_SDOUT_MDC 33_0402_5% 2 1 R405 AH17 PD_A0 Place close to ICH7 46
SATA_LED# DA0 PD_A1 46
AF18 AE17 47

2
SATALED# DA1 47
1

AF17 PD_A2 48
DA2 48

1
R88 MBAY_DET# 49
<26> MBAY_DET# 49
R90 10K_0402_5% SATA_RXN0_C AF3 AE16 PD_CS#1 1 50 R1032
10K_0402_5% SATA_RXP0_C SATA0RXN DCS1# PD_CS#3 C628 50 0_0402_5%
AE3 SATA0RXP DCS3# AD16 55 GND 51 51
SATA_TXN0_C AG2 56 52
2

SATA0TXN GND 52

SATA
SATA_TXP0_C AH2 0.1U_0402_16V4Z 57 53

2
SATA0TXP PD_D0 2 GND 53
DD0 AB15 58 GND 54 54
SATA_LED# 1 2 IDE_LED# AF7 AE14 PD_D1
D16 CH751H-40_SC76 IDE_LED# <30> SATA2RXN DD1 PD_D2
AE7 SATA2RXP DD2 AG13
AG6 AF13 PD_D3 JAE_WM2M054JKB
MB2_LED# SATA2TXN DD3 PD_D4 +5VS +5VS_MB
1 2 AH6 SATA2TXP DD4 AD14 Q92
D15 CH751H-40_SC76 AC13 PD_D5 +5VS
CLK_PCIE_SATA# AF1 DD5 PD_D6 AO4407_SO8
<15> CLK_PCIE_SATA# SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 PD_D7 1 8
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 PD_D8 2 7
R1256 DD8 PD_D9
AH10 SATARBIASN DD9 AF12 3 6 1 1

1
1 2 AG10 AB13 PD_D10 1 5 C625
SATARBIASP DD10 PD_D11 R83 C640
DD11 AC14
24.9_0402_1% AF14 PD_D12 470K_0402_5%

4
DD12 PD_D13 10U_0805_10V4Z C624 2 2
DD13 AH13
2
IDE AH14 PD_D14
R93
10U_0805_10V4Z

2
+3VALW +RTCVCC 4.7K_0402_5% 2 DD14
+3VS 1 R1033 PD_IORDY AG16 IORDY DD15 AC15 PD_D15 0.1U_0402_16V4Z
8.2K_0402_5% 2 1 R1034 PD_IRQ AH16 IDEIRQ 1 2
PD_DACK# AF16 DDACK#

1
PD_IOW# PD_DREQ D
AH15 DIOW# DDREQ AE15 220K_0402_5% 1C633
1

PD_IOR# AF15 2
B DIOR# <26> MB_PWR B
R1263 R1240 G
Q38 S 0.1U_0402_16V4Z

3
@ 332K_0402_1% 332K_0402_1% ICH7_BGA652~D RHU002N06_SOT323 2
2

ICH_INTVRMEN +5VS_MB
+3VL JP42
1

JP45 +RTCVCC ACES_85205-0200

R1241 +5VS_MB

1
2
-
D14 1 1
R133
@ 0_0402_5% S1 3 C626 C627
GND

1
S2 SATA_TXP0 1 2 1
SATA CONN
2

RX+ SATA_TXN0 RTC_R 1 RTC R98 0.1U_0402_16V4Z 0.1U_0402_16V4Z

RX- S3 1 2 2
C665 R976 1K_0402_5% 2 2
GND S4 100_0402_5%
S5 SATA_RXN0 DAN202U_SC70 100_0402_5%
TX- SATA_RXP0 1U_0603_10V4Z
S6 W=20mils

1 2
TX+ 2
GND S7 D
C955 3900P_0402_50V7K 2
SATA_TXN0_C 1 2 SATA_TXN0
3.3V P1
P2 Q39
G
S
Place close to JP37

3
C956 3900P_0402_50V7K 3.3V RHU002N06_SOT323
3.3V P3
SATA_TXP0_C 1 2 SATA_TXP0 P4 +3VS
GND
GND P5
GND P6
5V P7
P8
Near ICH7(U26) side. 5V

14
5V P9 +5VS
GND P10
P11 4

P
Rsv <7,24,26,28,30,36> PLT_RST# A
P12 1 1 1 6 PLT_RST_B# PLT_RST_B# <30,34,35> ZZZ ZZZ
GND C630 C631 O
12V P13 5 B

G
A 0.1U_0402_16V4Z A
12V P14
P15 U43B 7
C957 3900P_0402_50V7K 12V C629 2 2 2 SN74LVC08APW_TSSOP14
SATA_RXN0_C 1 2 SATA_RXN0 10U_0805_10V4Z
GND
GND

boss
boss

0.1U_0402_16V4Z PCB-MB Audio-wire

C958 3900P_0402_50V7K
SATA_RXP0_C 1 2 SATA_RXP0
26
25

24
23

OCTEK_SAT-22DD1G Security Classification Compal Secret Data Compal Electronics, Inc.

2005/05/26 2006/07/26 Title
Near Device(JP45) side. Issued Date Deciphered Date
ICH7-M(2/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 25 of 54
5 4 3 2 1
 5 4 3 2 1

HDD_HALTLED# <30>
Place closely pin B2 Place closely pin AC1

1
D CLK_48M_ICH CLK_14M_ICH
+3VALW +3VALW HDD_HALTLED 2 Q43

2
G RHU002N06_SOT323

1
R213,R233 change from 2.2Kohm to R1437 S
L

3
100K_0402_5% R997 R998

1
10Kohm when Q23,Q24,R206,R204 stuffed.

2
R213 R233 @ 10_0402_5% @ 10_0402_5%

1
R1000 R1001

2
2.2K_0402_5% 2.2K_0402_5% U26C
10K_0402_5% 10K_0402_5% R1319 1 1

2
ICH_SMBCLK 1 2 0_0402_5% ICH_SMB_CLK C22 AF19 C706 C707
MB_PWR <25>

1
D ICH_SMBDATA ICH_SMB_DATA SMBCLK GPIO21 / SATA0GP HDD_HALTLED D
1 2 0_0402_5% B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
R1320 LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 2
+3VS ICH_SMLINK1 A25 R1002 100_0402_5%
SMLINK1
+3VALW
R1003 AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH <15>

Clocks
1 2 ICH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
R206 R204 8.2K_0402_5%
SB_SPKR A19
<31> SB_SPKR SPKR
@ 2.2K_0402_5% @ 2.2K_0402_5% LPC_PD# A27 C20 ICH_SUSCLK T67 PAD
<35,36> LPC_PD# SUS_STAT# SUSCLK
2 Q23 <4> XDP_DBRESET# XDP_DBRESET# A22

2
SYS_RST#

SYS
@ RHU002N06_SOT323 B24 SLP_S3#
SLP_S3# SLP_S3# <28,30,31,32,36,38,39,46,47,48>
PM_BMBUSY# AB18 D23 SLP_S4#
<7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S4# <47>
S

D
ICH_SMBDATA 3 1 ICH_SMB_DATA F22 SLP_S5#
<4,13,14,15,23,28,30> ICH_SMBDATA SLP_S5# SLP_S5# <39,47>
OCP# B23 R1011
<4,50> OCP# GPIO11 / SMBALERT#

D
ICH_SMBCLK 3 1 ICH_SMB_CLK AA4 PM_POK R1010 8.2K_0402_5%
<4,13,14,15,23,28,30> ICH_SMBCLK PWROK PM_POK <7,36>
H_STP_PCI# 2 10K_0402_5%
G

AC20 1 2 1

POWER MGT
<15> H_STP_PCI# +3VALW
2
GPIO18 / STPPCI#

GPIO
Q24 H_STP_CPU# AF21 AC22 DPRSLPVR
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR <7,49>
G @ RHU002N06_SOT323 D58
2 +5VS <30> WXMIT_OFF# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT# 2 1 LOW_BAT# <36>

PAD T95 B21 C23 ON/OFFBTN# CH751H-40_SC76

+3VS GPIO27 PWRBTN# ON/OFFBTN# <37>
VGARST# E23 R1013
GPIO28 PLT_RST# 10K_0402_5%
LAN_RST# C19
@ 10K_0402_5% PM_CLKRUN# AG18 2 1 +3VL
<30,34,35,36> PM_CLKRUN# GPIO32 / CLKRUN# PM_RSMRST#
R993 1 2 THERM_SCI# R532 Y4
RSMRST# PM_RSMRST# <36>
1K_0402_5% FWH_WP# AC19 R1014 10K_0402_5% DPRSLPVR 2 1
FWH_WP# GPIO33 / AZ_DOCK_EN#
10K_0402_5% +3VALW 1 2 FWH_TBL# U2 1 2 R1015
FWH_TBL# GPIO34 / AZ_DOCK_RST#
R994 1 2 SIRQ @ 100K_0402_5%
ICH_PCIE_WAKE# F20 E20 T89 PAD
<28,30> ICH_PCIE_WAKE# WAKE# GPIO9 CB_IN#
8.2K_0402_5% SIRQ AH21 A20 2 1
C <30,34,35,36> SIRQ SERIRQ GPIO10 LOM_LOW_PWR <28> C
R999 1 2 PM_CLKRUN# <4,23> THERM_SCI#
THERM_SCI# AF20 THRM# GPIO12 F19 MBAY_DET# <25>
R1017 @ 0_0402_5%
E19 LID_SW#
GPIO13 LID_SW# <17,37>
PWROK_ICH7 AD22 R4 LANLINK_STATUS# J28
VRMPWRGD GPIO14 LANLINK_STATUS# <28,29,38>
GPIO15 E22 T90 PAD 2 1 CABLE_DETECT <28,29>
R3 XMIT_OFF
GPIO24 XMIT_OFF <30>
+3VALW +3VALW <36> RUNSCI_EC#
RUNSCI_EC#
ISO_PREP#
AC21
AC18
GPIO6 GPIO GPIO25 D20
AD21
GPIO25
NPCI_RST#
PAD-SHORT 2x2m
<38> ISO_PREP# GPIO7 GPIO35 / SATAREQ# NPCI_RST# <34>
E21 GPIO8 GPIO38 AD20 1 2 DOCK_ID <38>
R1322 1 2 10K_0402_5% AE20 T91 R1386 @ 0_0402_5%
R1004 1 LINKALERT# GPIO39
2
10K_0402_5% <28> LP_EN# LP_EN# ICH7_BGA652~D PAD

R1005 2 1 XDP_DBRESET# <7,49> VGATE_INTEL R1374 1 2 0_0402_5% PWROK_ICH7 R1015 need be removed when ICH7M ES2 samples used,
200_0402_1%
<7,36> PM_POK R1373 1 2 @ 0_0402_5% but need be stuffed when ICH7M ES1 samples used.
R1006 1 2 OCP# U26D
10K_0402_5% PCIE_RXN1 F26 V26 DMI_RXN0
<28> PCIE_RXN1 PERn1 DMI0RXN DMI_RXN0 <7>
PCIE_RXP1 F25 V25 DMI_RXP0
<28> PCIE_RXP1 PERp1 DMI0RXP DMI_RXP0 <7>
R1009 1 2 LID_SW# <28> PCIE_TXN1 0.1U_0402_16V4Z 2 1 C708 PCIE_C_TXN1 E28 PETn1 DMI0TXN U28 DMI_TXN0
DMI_TXN0 <7>

DIRECT MEDIA INTERFACE

10K_0402_5% <28> PCIE_TXP1 0.1U_0402_16V4Z 2 1 C709 PCIE_C_TXP1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 <7>
PCIE_RXN2 H26 Y26 DMI_RXN1 GPIO25 R1395 1 2 0_0402_5% BT_OFF <33>
<30> PCIE_RXN2 PERn2 DMI1RXN DMI_RXN1 <7>
PCIE_RXP2 H25 Y25 DMI_RXP1
V_3P3_LAN +3VS <30> PCIE_RXP2 PERp2 DMI1RXP DMI_RXP1 <7>
<30> PCIE_TXN2 0.1U_0402_16V4Z 2 1 C710 PCIE_C_TXN2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
<30> PCIE_TXP2 0.1U_0402_16V4Z 2 1 C711 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 <7>
1

PCI-EXPRESS
K26 AB26 DMI_RXN2
PERn3 DMI2RXN DMI_RXN2 <7>
R1007 R1008 K25 AB25 DMI_RXP2
PERp3 DMI2RXP DMI_RXP2 <7>
J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
10K_0402_5% 10K_0402_5% J27 AA27 DMI_TXP2
D57 PETp3 DMI2TXP DMI_TXP2 <7>
2

PREP# 1 2 ISO_PREP# PCIE_RXN4 M26 AD25 DMI_RXN3

B <29,31,38> PREP# <38> PCIE_RXN4 PERn4 DMI3RXN DMI_RXN3 <7> B
PCIE_RXP4 M25 AD24 DMI_RXP3
<38> PCIE_RXP4 PERp4 DMI3RXP DMI_RXP3 <7>
<38> PCIE_TXN4 0.1U_0402_16V4Z 2 1 C952 PCIE_C_TXN4 L28 AC28 DMI_TXN3
PETn4 DMI3TXN DMI_TXN3 <7>
CH751H-40_SC76 <38> PCIE_TXP4 0.1U_0402_16V4Z 2 1 C953 PCIE_C_TXP4 L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
+3VS PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R1016 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
RP64
14

T25 PERn6
R1292/R1293 should be placed T24 F1 USB20_N0 USB_OC#3 4 5
9 VGARST# L R28
PERp6 USBP0N
F2 USB20_P0
USB20_N0 <33>
USB_OC#0 3 6
+3VALW
P

A less than 100 mils from U26. PETn6 USBP0P USB20_P0 <33>
8 R27 G4 USB20_N1 USB_OC#1 2 7
<18> VGA_RST# O PETp6 USBP1N USB20_N1 <30>
10 PLT_RST# 47_0402_5% G3 USB20_P1 USB_OC#2 1 8
B PLT_RST# <7,24,25,28,30,36> USBP1P USB20_P1 <30>
G

<35> SPI_CLK SPI_CLK R1292 1 2 R2 H1 USB20_N2

SPI_CLK USBP2N USB20_N2 <35>
U43C SPI_CS# P6 H2 USB20_P2 10K_1206_8P4R_5%
<35> SPI_CS# USB20_P2 <35>
7

SN74LVC08APW_TSSOP14 SPI_CS# SPI USBP2P USB20_N3

P1 SPI_ARB USBP3N J4 USB20_N3 <33>
47_0402_5% J3 USB20_P3 R1018
USBP3P USB20_P3 <33>
<35> SPI_SI SPI_SI R1293 1 2 P5 K1 USB20_N4 10K_0402_5%
SPI_MOSI USBP4N USB20_N4 <33>
SPI_SO P2 K2 USB20_P4 USB_OC#4 1 2
+3VALW <35> SPI_SO SPI_MISO USBP4P USB20_P4 <33>
L4 USB20_N5
USBP5N USB20_N5 <33>
L5 USB20_P5 R1261
USBP5P USB20_P5 <33>
R1284 USB_OC#0 D3 M1 USB20_N6 10K_0402_5%
OC0# USBP6N USB20_N6 <38>
1 2 SPI_CS#
10K_0402_5%
USB_OC#1
USB_OC#2
C4
D5
OC1# USB USBP6P M2
N4
USB20_P6
USB20_N7
USB20_P6 <38>
USB_OC#5 1 2
OC2# USBP7N USB20_N7 <38>
R1285 USB_OC#3 D4 N3 USB20_P7 R1020
OC3# USBP7P USB20_P7 <38>
1 2 SPI_SI USB_OC#4 E5 OC4#
10K_0402_5%
10K_0402_5% USB_OC#5 C3 R1019 22.6_0402_1% USB_OC#6 1 2
R1286 USB_OC#6 OC5# / GPIO29 USBRBIAS
A2 OC6# / GPIO30 USBRBIAS# D2 1 2
1 2 SPI_SO USB_OC#7 B3 OC7# / GPIO31 USBRBIAS D1 R1237
10K_0402_5% Within 500 mils 10K_0402_5%
USB_OC#7 1 2
A ICH7_BGA652~D A
L R1284,R1285 and R1286 should
be placed close to U26.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 26 of 54
5 4 3 2 1
 5 4 3 2 1

+VCCP
U26F U26E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C974 C975 + + C979 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z @ 330U_D2E_2.5VM_R9 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2 2

150U_D_6.3VM
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 C670 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]

C570
+ C672 C673 C674 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z 220U_D2_2VM_R9 VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R989 D55 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% CH751H-40_SC76 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
C676 C677 D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C678 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VS VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C679 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C680 G6 V28

R990 D56 Vcc1_5_B[26] Vcc3_3[5] C681 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% CH751H-40_SC76 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C682 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C684 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C685

C686

C687
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C688 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C691

C692
V23 A24 C689 C690 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R991 R992 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C695 C696 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C693

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C694

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C697 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C698

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C699

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C700 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C701 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T81 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T82 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T83 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C702 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C704 P15 AH3
0.1U_0402_16V4Z C703 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T84 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_Y7 0.1U_0402_16V4Z
T85 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3VALW W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C705
A A
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 27 of 54
5 4 3 2 1
 5 4 3 2 1

J7 1 2
Layout Notice : Place as close
PAD-NO SHORT 2x2m
<7,24,25,26,30,36> PLT_RST# +3VALW chip as possible.

D
3 1 V_3P3_LAN
V_3P3_LAN Q31

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
SI2301BDS_SOT23
R275 1 2 1K_0402_5% ICH_LAN_SMBCLK R1396 1 2 @ 0_0402_5% ICH_SMBCLK R267

G
ICH_SMBCLK <4,13,14,15,23,26,30> 2 2 2 2 2

2
R289 1 2 1K_0402_5% ICH_LAN_SMBDATA R1398 1 2 @ 0_0402_5% ICH_SMBDATA ICH_SMBDATA <4,13,14,15,23,26,30>

C324

C41

C39

C32

C44
4.7K_0402_5%
R1419

3
S
R1420

2
U7A
G
R268 2 1 1 1 1 1
2 1 2 1
BCM5753
D @ 0_0402_5% 47K_0402_5% D

LAN_TX3+ 220K_0402_5%
C12 LAN_TX3+ <29>

1
TRD3+ LAN_TX3-
D
C13 LAN_TX3- <29> NIC_PD <29>

1
TRD3-

1
D12 LAN_TX2+ LAN_TX2+ <29> Q40
TRD2+

1
R277 LAN_TX2- D
2 1 10K_0402_5% J10 D13 AO7407_SOT323 R1397

Media
GPIO0_TST_CLKOUT TRD2- LAN_TX2- <29>
5751_GPIO1 J12 E12 LAN_TX1+ LAN_TX1+ <29> 2 LP_EN#
GPIO1 TRD1+ LAN_TX1- @ 0_0402_5% G
ICH_LAN_SMBCLK D9 TRD1- E13
LAN_TX0+
LAN_TX1- <29>
PLT_RST_LAN# Q94
Must having maximized
F12 S
LAN_TX0+ <29>
L

3
ICH_LAN_SMBDATA D8 SMB_CLK TRD0+ LAN_TX0- RHU002N06_SOT323 copper under pin 2 & 4 of Q13
SMB_DATA TRD0- F13 LAN_TX0- <29>
5751_EECLK H10 V_3P3_LAN V_1P2_LAN
EECLK

1
5751_EEDAT D BCP69_SOT223
J11 EEDATA

Misc
2 Q13 4

Control
R1039 <36,43,44,45,50> ADP_PRES
F11 G REGSUP12 3 2

Power
SI LOM_LOW_PWR 1 Q30
E10 J5 2 S

3
SO LOW_PWR RHU002N06_SOT323 2 2 2 1

1
4.7K_0402_5% D C347 C55 C68
D10 SCLK
<26,30,31,32,36,38,39,46,47,48> SLP_S3# 2 C228

1
G 0.1U_0402_16V4Z 10U_0805_10V4Z
REGSUP12 Q29 1 1 1 2
D11 L13 S

3
CS# REGSUP12 VAUX_1.2_CTL RHU002N06_SOT323 4.7U_0805_10V4Z VAUX_1.2_CTL 0.1U_0402_16V4Z
K12

Regulator
REGCTL12
K13

Control
REGSEN12 V_1P2_LAN
N13 V_2P5_LAN NIC_PD
REGOUT25
M13 V_3P3_LAN
REGSUP25 V_3P3_LAN

2
G
Support LOM_PCIE_WAKE# 1 3 ICH_PCIE_WAKE# <26,30>
Hot Plug PCIE_C_RXN1 C17 1

D
N4 2

S
PCIE_TXDN PCIE_RXN1 <26> 2 2
V_3P3_LAN H2 0.1U_0402_16V4Z Q103 C348 C83
C PWR_IND# PCIE_C_RXP1 C18 1 AO7407_SOT323 C
J2 ATTN_IND# PCIE_TXDP M4 2 PCIE_RXP1 <26>
1 2 B3 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
R73 4.7K_0402_5% ATTN_BTTN# 1 1
PCIE_RXDN M8 PCIE_TXN1 <26> 1 2
@ 0_0402_5% R1091
PCIE_RXDP N8 PCIE_TXP1 <26>
B5 LOM_PCIE_WAKE#
PCI-E

WAKE# CLK_PCIE_LOM#
REFCLK- M6
CLK_PCIE_LOM
CLK_PCIE_LOM# <15>
NIC_PD_N L Place close U6 pin M13
REFCLK+ N6 CLK_PCIE_LOM <15>
C4 2 1 V_3P3_LAN R1082
REFCLK_SEL R36 4.7K_0402_5% 1 2
100K_0402_5%

1
LANLINK_STATUS# B10 D7 1 2 D Q104
<26,29,38> LANLINK_STATUS# LINKLED# PCIE_TST V_2P5_LAN
LED

C10 C2 PLT_RST_LAN# R71 4.7K_0402_5% @ AO7407_SOT323

SPD100LED# PERST#
B11 SPD1000LED#
<29,38> LAN_ACT# LAN_ACT# C9 2
TRAFFICLED# G

1
C6 S 0_0402_5% 1

3
TCK R1089 R1088
TDI G4 2 1
C5 1 2 C74 + C976
TEST

TDO V_3P3_LAN
F4 0_0402_5%
TMS 0.1U_0402_16V4Z 100U_B2_6.3VM
E5 1 2 +3VS

2
TRST# R1090 1 2 2
2 1 V_3P3_LAN @ 0_0402_5%
R14 200_0402_1%

1
Y1 XTALO N10 C243
XTALO
Clock

R1085 @10U_0805_10V4Z
Bias

B9 10K_0402_5%
XTALI RDAC
1 2 M10 XTALI NIC_PD#

1 2
2

V_3P3_LAN
25MHZ_20P_1BG25000CK1A D C580 L Place close U6 pin N13
B BCM5753MKFBG_P31_FPBGA196 R70 NIC_PD Q105 B
2 2 2 1 2
C16 C19 G RHU002N06_SOT323
Layout Notice : No high 1.21K_0402_1% S 0.1U_0402_16V4Z
1

5
27P_0402_50V8J 27P_0402_50V8J
1 1 speed signal should be U36 R503

P
routed near RDAC or on LOM_LOW_PWR 4 2 1 2
<26> LOM_LOW_PWR O I
adjacent layer to RDAC 1 NC

G
V_3P3_LAN 100K_0402_5%
C9 @ SN74LVC1G17DBVR_SOT23-5

3
2 1 1
C576
0.1U_0402_16V4Z
1

1
1K_0402_5%

1K_0402_5%

1K_0402_5%

0.1U_0402_16V4Z
2
R16

R35

R34

V_3P3_LAN +3VS +3VALW

U4
2

1
1 A0 VCC 8
2

2 7 5751_GPIO1 R506 +3VS

A1 WP 5751_EECLK R1021 R1022 R540
3 NC SCL 6
4 5 5751_EEDAT @ 0_0402_5% 0_0402_5% 10K_0402_5% 2 1
GND SDA

2
AT24C64AN-10SU-2.7_SO8 R507 10K_0402_5%
5 1

D63 1N4148_SOD80 CABLE_DETECT 1 2

<26,29> CABLE_DETECT
1 2

1
@ 0_0402_5% D
1
P

NIC_PD_N 2 1 1 2 2 4 2 1 CLKREQA# <15> C578 2 LP_EN#

I O LP_EN# <26>
0_0402_5% 121K_0402_1% R1024 2 1 R1076 0_0402_5% G
NC
G

+3VS R1023 C1042 0.1U_0402_16V4Z S Q54

3
SN74LVC1G17DBVR_SOT23-5 2 RHU002N06_SOT323
3

0.1U_0402_16V4Z U55
1
1

A A
R1392 R1403
@ 2.2K_0402_5% @ 2.2K_0402_5% CKT Notice : CABLE IN, CABLE_DETECT=0
CABLE OUT, CABLE_DETECT=1
Q96 @ RHU002N06_SOT323
2

Q93 @ RHU002N06_SOT323
S

ICH_SMBDATA 3 1 ICH_LAN_SMBDATA
Security Classification Compal Secret Data Compal Electronics, Inc.
S

ICH_SMBCLK 3 1 ICH_LAN_SMBCLK 2005/05/26 2006/07/26 Title

Issued Date Deciphered Date
G

BCM5751M
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
G

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

+5VS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 28 of 54
5 4 3 2 1
 5 4 3 2 1

LAN_TX0- 12
T66
TD4- MX4- 13 MDO0- RJ-45 CONN. Layout Notice : 1.2V filter. Place as close
chip as possible.
V_2P5_LAN
+3VS
LAN_TX0+ 11 14 MDO0+ V_2P5_LAN V_1P2_LAN
TD4+ 1:1 MX4+

2
2 1 TRM_CT 10 15 MCT0 2 R269 1
TCT4 MCT4 NIC_PD <28>
C330 75_0402_1% R871

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.01U_0402_16V7K LAN_TX1- 9 16 MDO1-
TD3- MX3-

2
10K_0402_5%

G
2 2 2 2 2 2 2 2 2 2 2 2

C65

C15
1

C341

C334

C340

C335

C336

C343

C337

C338
C66

C61
VMAINPRSNT 1 3 VMAINPRSNT_R
D D

S
LAN_TX1+ MDO1+ Q106 @ AO7407_SOT323 1 1 1 1 1 1 1 1 1 1 1 1
8 TD3+ 1:1 MX3+ 17
C333
2 1 TRM_CT 7 18 MCT1 2 R270 1 1 2
C327 TCT3 MCT3 75_0402_1% 1 2
0.01U_0402_16V7K LAN_TX2- 6 19 MDO2- 1000P_1808_3KV7K 0_0402_5% R1040
TD2- MX2-

LAN_TX2+ 5 20 MDO2+
TD21+ 1:1 MX2+
2 1 TRM_CT 4 21 2 R271 1
C328 TCT2 MCT2 75_0402_1%
0.01U_0402_16V7K LAN_TX3- 3 22 MDO3- V_1P2_LAN U7B
TD1- MX1-
E6 VDDC_0
BCM5753 VSS_0 A3
E7 VDDC_1 VSS_1 A8
Layout Notice : Filter place as close E8 VDDC_2 VSS_2 A12
LAN_TX3+ 2 23 MDO3+ E9 A14
TD1+ 1:1 MX1+ C320
chip as possible. VDDC_3 VSS_3
J6 VDDC_4 VSS_4 B1
2 1 TRM_CT 1 24 2 R272 1 1 2 J7 C1
C329 TCT1 MCT1 75_0402_1% VDDC_5 VSS_5
J9 VDDC_6 VSS_6 C3
0.01U_0402_16V7K 24HST1041-3 1000P_1808_3KV7K K5 C11
V_3P3_LAN VDDC_7 VSS_7
VSS_8 F1
A2 VDDIO_0 VSS_9 F5
0.1U_0402_16V4Z 1 2 C56 R50 1 2 49.9_0402_1% LAN_TX0- V_2P5_LAN A6 F6
LAN_TX0- <28> VDDIO_1 VSS_10
R63 1 2 49.9_0402_1% LAN_TX0+ LAN_TX0+ <28> A10 F7
VDDIO_2 VSS_11

Digial power
0.1U_0402_16V4Z 1 2 C54 R45 1 2 49.9_0402_1% LAN_TX1- LAN_TX1- <28> R985 B4 F8
R48 1 49.9_0402_1% LAN_TX1+ VDDIO_3 VSS_12
2 LAN_TX1+ <28> 2 1 XTALVDD D3 VDDIO_4 VSS_13 F9
0.1U_0402_16V4Z 1 2 C50 R42 1 2 49.9_0402_1% LAN_TX2- LAN_TX2- <28> 0_0603_5% 2 E11 F10
VDDIO_5 VSS_14
C
R44 1 2 49.9_0402_1% LAN_TX2+ LAN_TX2+ <28> C35 G2 VDDIO_6 GND VSS_15 G5
C
0.1U_0402_16V4Z 1 2 C49 R40 1 2 49.9_0402_1% LAN_TX3- LAN_TX3- <28> H11 G6
R41 1 49.9_0402_1% LAN_TX3+ 0.1U_0402_16V4Z VDDIO_7 VSS_16
2 LAN_TX3+ <28> K3 VDDIO_8 VSS_17 G7
1
M2 VDDIO_9 VSS_18 G8
R986 P12 G9
V_3P3_LAN XTALVDD V_2P5_LAN VDDIO_10 VSS_19
2 1 AVDD1 VSS_20 G10
0_0603_5% 2 B6 H6
C60 VDDP_0 VSS_21
Layout Notice : Place H4 VDDP_1 VSS_22 H7
termination as close as M12 VDDP_2 VSS_23 H8
0.1U_0402_16V4Z J13 H9
BCM5751M as possible 1 1K_0402_5% 1 R276 LAN_AUXPWR XTALVDD VSS_24
2 C7 VAUXPRSNT VSS_25 J1
R987 VMAINPRSNT H12 M3
VMAINPRSNT VSS_26
2 1 AVDD2 L5 PCIE_SDSVDD VSS_27 M7
0_0603_5% 2 N1
C46 VSS_28
PCIE_SDS_VDD A1 NC_0 VSS_29 N7
A4 NC_1 VSS_30 P11
0.1U_0402_16V4Z A5 P14
1 NC_2 VSS_31
A7 NC_3
A9 NC_4 DC_0 A11
V_1P2_LAN B2 A13
NC_5 DC_1
B7 NC_6 DC_2 B14
L33 B8 C14
JP4 NC_7 DC_3
2 1 AVDDL C8 NC_8 DC_4 D6
V_3P3_LAN_LED R266 2 1 300_0402_5% 13 BLM11A601S_0603 2 2 D1 D14
Yellow LED+ C342 C339 NC_9 DC_5
D2 NC_10 DC_6 E3
LAN_ACT# 14 D4 E14
<28,38> LAN_ACT# Yellow LED- NC_11 DC_7
16 4.7U_0805_10V4Z 0.1U_0402_16V4Z D5 F14
MDO3- SHLD1 1 1 V_3P3_LAN NC_12 DC_8
<38> MDO3- 8 PR4- E1 NC_13 DC_9 G14
DETECT PIN1 9 E2 NC_14 DC_10 H5
MDO3+ 7 CABLE_DETECT <26,28> L32 E4 H14
<38> MDO3+ PR4+ NC_15 DC_11

Disconnected
2 1 F2 J8

Don't care
GPHY_PLLVDD NC_16 DC_12
MDO1- 6 BLM11A601S_0603 2 2 R284 F3 J14
<38> MDO1- PR2- NC_17 DC_13
1 C331 C332 G1 K4
B MDO2- C579 @ 4.7K_0402_5% NC_18 DC_14 B
<38> MDO2- 5 PR3- G3 NC_19 DC_15 K6
4.7U_0805_10V4Z 0.1U_0402_16V4Z H1 K7

1
MDO2+ 0.1U_0402_16V4Z 1 1 NC_20 DC_16
<38> MDO2+ 4 PR3+ T59 H3 NC_21 DC_17 K8
2
J3 NC_22 DC_18 K9
MDO1+ 3 L30 J4 K10
<38> MDO1+ PR2+ NC_23 DC_19
2 1 PCIE_PLLVDD K1 NC_24 DC_20 K14
MDO0- 2 BLM11A601S_0603 2 2 K2 L6
<38> MDO0- PR1- PAD NC_25 DC_21
10 C323 C326 K11 L10
MDO0+ DETCET PIN2 NC_26 DC_22
<38> MDO0+ 1 PR1+ 4.7U_0805_10V4Z 0.1U_0402_16V4Z L T59 , T60 place together L1 NC_27 DC_23 L12
SHLD1 15 L2 NC_28 DC_24 L14
R265 2 1 1
V_3P3_LAN_LED 1 300_0402_5% 11 Green LED+ L3 NC_29 DC_25 M11
L29 V_3P3_LAN L4 M14
LANLINK_STATUS# NC_30 DC_26
<26,28,38> LANLINK_STATUS# 12 Green LED- 2 1 PCIE_SDS_VDD L8 NC_31 DC_27 N5
BLM11A601S_0603 1 2 R285 1 2 @ 4.7K_0402_5% L9 N11
FOX_JM36113-P1122-7F C322 C325 NC_32 DC_28
L11 NC_33 DC_29 N12
T60 M1 N14
4.7U_0805_10V4Z 0.1U_0402_16V4Z PAD NC_34 DC_30
M5 NC_35 DC_31 P3
2 1 R287 1 2 @ 4.7K_0402_5% M9 NC_36 DC_32 P4
N2 NC_37 DC_33 P5
N3 NC_38 DC_34 P6
R286 1 2 @ 4.7K_0402_5% N9 P7
NC_39 DC_35
P1 NC_40 DC_36 P8
P2 NC_41 DC_37 P9
DC_38 P10
AVDDL G11 AVDDL_0 DC_39 P13
G12 AVDDL_1 Analog
B12
V_3P3_LAN V_3P3_LAN_LED AVDD1
G13
AVDD_0 power
AVDD2 AVDD_1 V_2P5_LAN
S

L8
D

3 1 PCIE_PLLVDD L7 PCIE_PLLVDD
GPHY_PLLVDD H13 GPHY_PLLVDD PLL BIAS BIASVDD B13 BIASVDD_LAN 1 2
1

Q60 1 BLM11A601S_0603
A R525 SI2301BDS_SOT23 BCM5753MKFBG_P31_FPBGA196 C63 A
G
2

100K_0402_5% 0.1U_0402_16V4Z
2
2

D
2
<26,31,38> PREP#
Q61
G Security Classification Compal Secret Data Compal Electronics, Inc.
S Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
3

RHU002N06_SOT323
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 29 of 54
5 4 3 2 1
 A B C D E

+3V_MINI +1.5VS +3VALW

B/B connector with PCI / LED / FIR / SC interface

1 1 1 1 1 1
PCI_AD[0..31] C538 C542 C293 C294 C533 C954
PCI_AD[0..31] <24>
JP13 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
CLK_PCI_PCM 1 2 PCI_PIRQE#
<15> CLK_PCI_PCM 1 2 PCI_PIRQE# <24>
3 4 PCI_PIRQC#
3 4 PCI_PIRQC# <24>
PCI_PIRQG# 5 6 PCI_RST#
<24> PCI_PIRQG# 5 6 PCI_RST# <24,25>
PCI_PIRQD# 7 8 PCI_GNT2#
1 <24> PCI_PIRQD# 7 8 PCI_GNT2# <24> 1
9 10
<24> PCI_REQ2#
PCI_REQ2#
PCI_AD31
PCI_AD29
11
13
9
11
13
10
12
14
12
14
SIRQ <26,34,35,36>
CLK_48M_CB <15> Mini-Express Card---WLAN DEBUG@0_0402_5%
DEBUG@0_0402_5%
+1.5VS +3V_MINI

15 15 16 16 PLT_RST# <7,24,25,26,28,36>
PCI_AD27 17 18 PCI_AD30 DEBUG@0_0402_5%
PCI_AD25 17 18 PCI_AD28 DEBUG@0_0402_5%
19 19 20 20
21 22 PCI_AD26 DEBUG@0_0402_5%
<24> PCI_CBE#3 21 22 JP44
PCI_AD23 23 24 PCI_AD24
PCI_AD21 23 24 ICH_PCIE_WAKE#
25 25 26 26 PCM_SPK <31> <26,28> ICH_PCIE_WAKE# 1 1 2 2
27 28 PCI_AD22 CH_DATA 3 4
27 28 <33> CH_DATA 3 4
PCI_AD19 29 30 PCI_AD20 CH_CLK 5 6
29 30 <33> CH_CLK 5 6
PCI_AD17 31 32 <15> CLKREQD# 1 2 CLKREQD#_MC 7 8 R1413 1 2 LPC_FRAME# <25,34,35,36>
PCI_CBE#2 31 32 PCI_PAR R1336 0_0402_5% 7 8 R1414 LPC_AD3
<24> PCI_CBE#2 33 33 34 34 PCI_PAR <24> 9 9 10 10 1 2
PCI_IRDY# 35 36 PCI_AD18 CLK_PCIE_MCARD# 11 12 R1415 1 2 LPC_AD2
<24> PCI_IRDY# 35 36 <15> CLK_PCIE_MCARD# 11 12
37 38 PCI_AD16 CLK_PCIE_MCARD 13 14 R1416 1 2 LPC_AD1
<26,34,35,36> PM_CLKRUN# 37 38 <15> CLK_PCIE_MCARD 13 14
PCI_SERR# 39 40 PCI_FRAME# 15 16 R1417 1 2 LPC_AD0
<24,36> PCI_SERR# 39 40 PCI_FRAME# <24> 15 16
PCI_PERR# 41 42 PCI_TRDY# PLT_RST_B# 1 2 17 18
<24> PCI_PERR# 41 42 PCI_TRDY# <24> <25,34,35> PLT_RST_B# 17 18 LPC_AD[0..3] <25,34,35,36>
PCI_CBE#1 43 44 PCI_STOP# R1412 DEBUG@0_0402_5% 19 20 XMIT_OFF#
<24> PCI_CBE#1 43 44 PCI_STOP# <24> <15> CLK_DEBUG_PORT 19 20
45 46 PCI_DEVSEL# R1348 0_0402_5% 21 22 0_0402_5%
45 46 PCI_DEVSEL# <24> 21 22 PLT_RST_B# <25,34,35>
PCI_AD14 47 48 PCI_AD15 <26> PCIE_RXN2 PCIE_RXN2 1 2 PCIE_C_RXN2 23 24 R1363 1 2 V_3P3_LAN
PCI_AD12 47 48 PCIE_RXP2 PCIE_C_RXP2 25 23 24 R1364
49 49 50 50 <26> PCIE_RXP2 1 2 25 26 26 1 2 +3VS
PCI_AD10 51 52 PCI_AD13 R1349 0_0402_5% 27 28 @ 0_0402_5%
PCI_AD8 51 52 PCI_AD11 27 28
53 53 54 54 29 29 30 30 ICH_SMBCLK <4,13,14,15,23,26,28>
PCI_AD7 55 56 PCI_AD9 PCIE_TXN2 31 32
55 56 <26> PCIE_TXN2 31 32 ICH_SMBDATA <4,13,14,15,23,26,28>
PCI_AD5 57 58 PCI_CBE#0 PCIE_TXP2 33 34
PCI_AD3 57 58 PCI_AD6 PCI_CBE#0 <24> <26> PCIE_TXP2 33 34
59 59 60 60 35 35 36 36
PCI_AD1 61 62 PCI_AD4 37 38
61 62 PCI_AD2 37 38
63 63 64 64 39 39 40 40
65 66 PCI_AD0 41 42 WW_LED#
<26> HDD_HALTLED# 65 66 41 42 WW_LED# <35>
+3VL 67 68 43 44 WL_LED#
67 68 43 44 WL_LED# <35>
69 70 +3VL R1418 1 2 DEBUG@ 0_0402_5% 45 46 WP_LED#
<35,37> WL_BLUE_LED# 69 70 IRRX <34> 45 46 WP_LED# <35>
71 72 R1358 1 2 DEBUG@ 0_0402_5% 47 48
2 <36> GREEN_BATLED# 71 72 IRTXOUT <34> <36,37,38> STB_LED# 47 48 2
73 74 R1353 1 2 DEBUG@ 0_0402_5% 49 50
<36> AMBER_BATLED# 73 74 IRMODE <34> <36,37> NUM_LED# 49 50
75 76 R1360 1 2 DEBUG@ 0_0402_5% 51 52
<36,37,38> STB_LED# 75 76 <36,37> CAPS_LED# 51 52
77 78 SC_CD#
<25> IDE_LED# 77 78 SC_CD# <33> +3VALW
79 80 SC_FCB 53 54
79 80 SC_FCB <33> GND1GND2
CLK_48M_CB +3VS 81 82 SC_CLK
81 82 SC_CLK <33> +3VALW +3V_MINI +3VS
83 84 SC_RST Q41 MOLEX 67910-0002 52P
83 84 SC_RST <33>
1

85 85 86 86 +SC_PWR

1
R106 +5VS 87 88 SC_DATA @ SI2301BDS_SOT23
87 88 SC_DATA <33>
@ 10_0402_5% 89 90 SC_RFU L78 R517
89 90 SC_RFU <33>

1
S

D
3 1 1 2
R516 @ 100K_0402_5%
2

1 91 92 FBMA-L11-201209-102LMA10T
R519

2
GND GND @ 10K_0402_5% XMIT_OFF#

G
93 94

2
C142 GND GND
95 96 1 2

2
GND GND

1
@18P_0402_50V8J @ 100K_0402_5% D

1
2 D
<26> XMIT_OFF 2
88020-90101 <26,28,31,32,36,38,39,46,47,48> SLP_S3# 2 G
G Q58 S

3
Q42 S @ RHU002N06_SOT323

3
@ RHU002N06_SOT323
1 2
R1422 0_0402_5%
+1.5VS +3VS

Mini-Express Card--WWAN +3VS

R1355
+3VS_ACL
R1356
+3VS_ACL_IO

+3VALW +1.5VS +3VS

1 1 1 1 1 ACCELEROMETER 1 2 1 2
C295 C540 C544 C291 C547 @ 0_0805_5% 0_0603_5%
JP46
1
C959 1 2 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 2 1
1 2 2 2 2 2 2 D64
3 3 4 4
5 6 CH751H-40_SC76
3 2 5 6 UIM_PWR 0.01U_0402_16V7K 3

19

11
7 7 8 8

3
9 10 UIM_DATA U64
0.1U_0402_16V4Z 9 10 UIM_CLK +3VS_ACL_IO
11 12

Vdd

Vdd

Vdd_IO
11 12 UIM_RST
13 13 14 14
15 16 UIM_VPP +3VS 2 1 18 6
15 16 U72 Reserved2 RDY/INT ACCEL_INT <24>
17 18 R1357 0_0402_5%
17 18 M_WXMIT_OFF# +3VS_ACL
19 19 20 20 1 CH1 CH4 6
21 21 22 22 PLT_RST_B# <25,34,35> 2 1 20 Reserved3
23 24 1 2 +3VALW 2 5 R1359 0_0402_5% 9
23 24 R1382 @ 0_0402_5% Vn Vp SDO
25 25 26 26
27 27 28 28 1 2 +3VS 3 CH2 CH3 4 4 Reserved1
+3VS 29 30 R1383 0_0402_5%
29 30

1
31 32 S DIO(BR) NUP4301MR6T1 TSOP-6 +3VS 10
31 32 SDA/SDI/SDO ICH_SMBDATA <4,13,14,15,23,26,28>
33 34 R1361
33 34
35 35 36 36 USB20_N1 <26> 1 NC1 ICH_SMBCLK <4,13,14,15,23,26,28>
37 38 D13 0_0402_5% 7
37 38 USB20_P1 <26> NC2
1 2 39 40 JP50 8 12

2
R1071 39 40 NC3 SCL/SPC +3VS_ACL
1 20_0603_5% 41 41 42 42 WW_LED#
WW_LED# <35> 3 14 NC4
R1073 0_0603_5% 43 44 4 1 UIM_PWR 1 15 R1362
43 44 UIM_VPP GND VCC UIM_RST NC5
45 45 46 46 5 VPP RST 2 2 21 NC6 CS 13 1 2
47 48 UIM_DATA 6 3 UIM_CLK 22 10K_0402_5%
47 48 I/O CLK NC7
49 49 50 50 DAN217_SC59 23 NC8 R1391
51 51 52 52 SUYIN_254021MA006G100ZL 24 NC9
+3VS_ACL
0.1U_0402_16V4Z

25 NC10 CK 16 1 2
53 GND1GND2 54 26 NC11

PADDLE
1 1 27 0_0402_5%
MOLEX 67910-0002 52P C554 C960 NC12
28

GND

GND

GND
NC13
1 1 1
4.7U_0805_10V4Z C994 C995 C996
2 2 LIS3LV02DQ_QFN28

29

17
@ 0.01U_0402_16V7K 10U_0805_10V4Z
D66 2 2 2
@
4 +3VS 1 2 M_WXMIT_OFF# 4
<26> WXMIT_OFF# CH751H-40_SC76 0.1U_0402_16V4Z
SW1
2 1BD002-1101L_4P
1 1 2 Must be placed in the center of the system.
D65 CH751H-40_SC76
1

1
C986 R521

4 3
2
1K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
2

0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Mini-PCI/Accelerometer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 30 of 54
A B C D E
 A B C D E F G H

VDDA_CODEC VDDA_CODEC

1
<26,28,30,32,36,38,39,46,47,48> SLP_S3#

1
R329 +5VAMP
U18 R456
10K_0402_5% 1
C390 R341 IN 49.9K_0402_1% 1
1 5

2
10K_0402_5% MONO_IN OUT
1 2 1 2 1 2 2 2 3 1

2
C430 0.1U_0402_16V4Z + C548 C552 C551 EN + C309 C307
ADJ 4

1
D 0.1U_0402_16V4Z 150K_0402_1% 100P_0402_50V8J
2 2 GND

1
<30> PCM_SPK 2 R330 C377 22U_B_10V 1U_0603_10V4Z 2 22U_B_10V 0.1U_0402_16V4Z
G 2 1 1 MIC5205BM5_SOT23-5 C553 R457 2 2
1 2
1 Q35 S 0.01U_0402_16V7K R258 1

3
RHU002N06_SOT323 1 0_1206_5% 0.01U_0402_16V7K 143K_0402_1%

2
1

2
VDDA_CODEC
Place R258 between DGND & AGND & close to U14
1

R350

10K_0402_5%
C396 R359
2

1 2 1 2
1

D 0.1U_0402_16V4Z 150K_0402_1%
<26> SB_SPKR 2
G
Q37 S
3

RHU002N06_SOT323

Place close to U14

R1400
2 1

0_1206_5%
2 2
+3VS
2 1 VDDA_CODEC
C409 0.1U_0402_16V4Z R1399
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CODEC 1 2
0_0805_5%
2 1 1 1 1 1 2 1 1 1
C427 0.1U_0402_16V4Z C395 C147 C417 C148 C402 C156 C175
C393
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2 1 2 2 2

25

38
2 1

9
C431 0.1U_0402_16V4Z U14
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
GND GNDA 14 35 LINE_OUTL LINE_OUTL <32>
T16 PAD AUX_L LINE_OUT_L
15 36 LINE_OUTR LINE_OUTR <32>
T17 PAD AUX_R LINE_OUT_R
<32> INT_MIC INT_MIC C425 1 2 1U_0603_10V4Z 16 37 T14
MIC3 MONO_OUT PAD
C426 1 2 1U_0603_10V4Z 17 39 L_HP L_HP <32>
MIC4 HP_LOUT_L
<38> DLINE_IN_L R370 2 1 4.7K_0402_5% DLINE_IN_R_L C423 1 2 1U_0603_10V4Z DLINE_IN_RC_L 23 41 R_HP R_HP <32>
R375 4.7K_0402_5% LINE_IN_L HP_LOUT_R @ 10P_0402_25V8K
1 2 2 1 1 2
<38> DLINE_IN_R R369 2 1 4.7K_0402_5% DLINE_IN_R_R C422 1 2 1U_0603_10V4Z DLINE_IN_RC_R 24 R1038 @ 33_0402_5% C1064
R374 4.7K_0402_5% LINE_IN_R
1 2 BIT_CLK 6 AC97_BITCLK_CODEC <25>
18 CD_L
T18 PAD 8 AC97_SDIN0_CODEC 2 R373 1
SDATA_IN AC97_SDIN0 <25>
20 33_0402_5%
T19 PAD CD_R
3 3
19 CD_GND
T20 PAD 43 R168 1 2 @ 4.7K_0402_5%
GPIO_0 PORT_A_SNS <32>
<32> MIC1 MIC1 1 2 MIC1_C 21 44 R167 1 2 @ 4.7K_0402_5% PORT PLACE TO
C204 1U_0603_10V4Z MIC1 GPIO_1 R136 10K_0402_5%
GPIO_2 2 1 2
<32> MIC2 MIC2 1 2 MIC2_C 22 3 R32 1 2 @ 4.7K_0402_5% MONO_OUT X
MIC2 GPIO_3 PREP# <26,29,38>
C205 1U_0603_10V4Z
SENSE_A 13 PORT A HP OUT, DOCK HP LO
SENSE_B SENSEA
VDDA_CODEC 1 2 34 SENSEB
R231 2.2K_0402_1% PORT B M/B MIC
1 2
R169 @ 0_0402_5% 27 AUD_REF PORT C DOCK LI
VREF
<25> AC97_RST#_CODEC 11 RESET# 1 1
28 T21 C424 C416 PORT D M/B SPK
MIC_BIAS_B T13 PAD
<25> AC97_SYNC_CODEC 10 SYNC MIC_BIAS_C 29
30 T12 PAD 1U_0603_10V4Z 0.1U_0402_16V4Z PORT E X
MIC_BIAS_F T11 PAD 2 2
<25> AC97_SDOUT_CODEC 5 SDATA_OUT MIC_BIAS_D 32
VDDA_CODEC 12 MONO_IN PAD PORT F Internal MIC
PCBEEP
31 T6 PAD
N/C T7 PAD
N/C 33
<32,36> EAPD L53 1 2 47 40 T5 PAD
EAPD N/C
2

FBM-L10-160808-301-T_0603 45 T3 PAD
R969 NC T4 PAD
48 SPDIFO NC 46
2.67K_0402_1% T15 PAD
4 DVSS1 AVSS1 26
7 42
1

DVSS2 AVSS2
1 2 SENSE_A_A <32>
R970 39.2K_0402_1% AD1981HDJSTZ-REEL_LQFP48
VDDA_CODEC
SENSE_A 1 2 SENSE_A_B <32>
R972 20K_0402_1%
2

4 4
2

1 2 SENSE_A_C R974
R980 R973 10K_0402_1% @ 0_0402_5%
@ 0_0402_5% 2
1

Q97 D
1

C977 2 LINE_IN_SENSE LINE_IN_SENSE <38>

1

SENSE_B @ 1U_0402_6.3V4Z G 1
2

1 S C978
Security Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23 R988
0.1U_0402_16V4Z 2005/05/26 2006/07/26 Title
2 Issued Date Deciphered Date
AC97 CODEC AD1981B
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 31 of 54
A B C D E F G H
 A B C D E

AMP. FOR INTERNAL SPEAKER AMP. FOR INTERNAL MICROPHONE

+5VALW +5VAMP Place close to U14 audio CODEC D62
C230
1 2
R443 C659
1 2 10U_0805_10V4Z 2 680P_0402_50V7K
1 R190
C1098 1 0_1206_5% 1 1 1 1 3 1 2
C660 C539
C662 + @ MIC_REF VDDA_CODEC 100K_0402_5%
PACDN042_SOT23~D

0.1U_0402_16V4Z
10U_0805_10V4Z @ 0.1U_0402_16V4Z JP36
2 150U_D_6.3VM 2 2 2
2

100P_0402_50V8J
1U_0603_10V4Z INT_MIC_2 1
1

C441
1 C585 1

12

18
2 1

8
10 dB

C446
U39 1 2
Keep 10 mil width ACES_85205-0200

VDD
PVDD1
PVDD2
C503 R1410 @ 1200P_0402_50V7K 2
LINE_C_OUTR 1 LINE_C_R_OUTR C1044 2
<31> LINE_OUTR 1 2 2 5 INR BIAS 2 1 2 1U_0603_10V4Z
U27A

8
0.1U_0402_16V4Z 10K_0402_5% R1405 VDDA_CODEC
1 2 LINE_C_R_OUTR L57 TLV2462_SO8
12.1K_0402_1% 7.6 dB HLC0603CSCCR11JT_0603 3

P
C502 R1411 R_SPK+ R196 R193 C231 R388 + INT_MIC
OUTR+ 7 O 1
<31> LINE_OUTL 1 2 LINE_C_OUTL 1 2 LINE_C_R_OUTL 1 1 2INT_MIC_1 1 2 1 2INT_MIC_3
1 2 1 2 INT_MIC_4 2
INL -

G
9 R_SPK- 3K_0402_5% 1
0.1U_0402_16V4Z 10K_0402_5% OUTR- 3K_0402_5% 1 C226 0.22U_0603_10V7K C571 10K_0402_5%

4
10 dB R1406 1 2 LINE_C_R_OUTL INT_MIC <31>
R1407 12.1K_0402_1% 7.6 dB 68P_0402_50V8J
2
2 1 4 19 L_SPK+ 4.7U_0805_6.3V6K
0_0402_5% MUTE OUTL+ 2
17 L_SPK-
EAPD OUTL-
2 1
R1427 @ 0_0402_5%
3 C488
NC1
10 1 2
<26,28,30,31,36,38,39,46,47,48> SLP_S3# R430 1 2 10K_0402_5% 14 SHDN
NC2
NC3 13
16
C471
0.01U_0402_16V7K
AMP. FOR EXTERNAL MICROPHONE 100P_0402_50V8J

PGND1
PGND2
PGND3
PGND4
PGND5
NC4 R413
<37> MUTE_LED# 1 2
2 1 1 2
1

R1421 @ 0_0402_5% D
MAX9710ETP_QFN20 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<31,36> EAPD 2

6
11
15
20
21
Place close to JP15
G
Q28 S
3

100P_0402_50V8J
@ RHU002N06_SOT323
1
1

C249
2 2
<36> A_SD 2
G
Q32 S 2 U46A
3

RHU002N06_SOT323 MIC_REF

8
TLV2462_SO8
VDDA_CODEC VDDA_CODEC
3

P
+
1 C982 C276 L58 R211
O 1 J_MIC1
EXT_MICA 1 2 EXT_MICA_1 1 2 1 2 EXT_MICA_2 2 -
1

G
Place close to U14 audio CODEC R426 4.7U_0805_6.3V6K 0.22U_0603_10V7K
HLC0603CSCCR10JT_0603
1 10K_0402_5%

4
R978 2
VDDA_CODEC 47K_0402_5% 100_0402_5% C572

8
68P_0402_50V8J
2

1
1

J_VDDA_CODEC 2
5

P
R995 + C489
O 7
1

100K_0402_5% 2 6 1 2
- G

1
C490 R428 U27B
TLV2462_SO8 R427 100P_0402_50V8J
1 2

<31> PORT_A_SNS Q48 47K_0402_5% JP9 R414

D RHU002N06_SOT323 4.7U_0805_10V4Z 1 MIC1 47K_0402_5%
1 2 1 JJ_MIC_REF 1 2
2

<31> MIC1 1 R1424 0_0402_5%

2 2

2
G MIC2 2 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<31> MIC2 3 3
S 4
3

1
VDDA_CODEC 5 2 1
<31> SENSE_A_A MIC_REF 5 2 J_MIC_REF

100P_0402_50V8J
MIC_SENSE 6 C492 R429 R1423 @ 0_0402_5%
6
1

D R_HP
<31> R_HP 7 7 1
1

VDDA_CODEC

C248
2 <31> L_HP L_HP 8 47K_0402_5%
Q49 G R423 8 4.7U_0805_10V4Z 1
9

2
RHU002N06_SOT323 DLINE_OUT_L 9
S 10
3

<38> DLINE_OUT_L 10
1

100K_0402_5% 2 U46B
<38> DLINE_OUT_R 11 11
R251 VDDA_CODEC 12
2

12

8
TLV2462_SO8
3 <38> DOCK_HPS# 100K_0402_5% ACES_87213-1200 3
5

P
+
1

D R255 C275 L61 R210 J_MIC2

7
2

Q44 DLINE_OUT_L EXT_MICB EXT_MICB_1 1 EXT_MICB_2 O

1 2 1 2 1 2 2 1 2 6 -

G
C527 G 1 1 HLC0603CSCCR10JT_0603 1
S C536 100K_0402_5% C526 0.22U_0603_10V7K 1 10K_0402_5% C470
3

4
0.1U_0603_16V4Z
2 2.2U_0603_6.3V6K @ 1U_0603_10V6K C575 0.1U_0402_16V4Z
2 2 68P_0402_50V8J 2
RHU002N06_SOT323 2

VDDA_CODEC
R261 CHB1608B121_0603
JP24

2
J_R_HP 1 R_C_HP R_CR_HP 1 R_CRL_HP
+

2 1 2 2
C577 150U_D_6.3VM 16_0805_1% L52 5 8 R979
<31> SENSE_A_B
J_DLINE_OUT_R 7 47K_0402_5%
J_DLINE_OUT_L 4

1
D

1
R253 L51 3 Q50 2 MIC_SENSE
J_L_HP L_C_HP L_CR_HP 1 RHU002N06_SOT323
+

1 2 1 2 2 6 G 2
C581 150U_D_6.3VM 16_0805_1% CHB1608B121_0603 L_CRL_HP 2 S

3
1 C984
JP15
Place close to JP24 1
0.1U_0402_16V4Z
1 1 J_MIC_SENSE 5 8
1

C563 C564 SUYIN_010030FR006G101ZL_6P J_VDDA_CODEC R424 7

R445 R446 R418 3.9K_0402_1% 4
470P_0402_50V7K 470P_0402_50V7K 1 2 1 2 EXT_MICB 1 2
U73 1K_0402_1% 1K_0402_1% 2 2 470_0402_5% L46 3
1 6 CHB1608B121_0603 6
2

CH1 CH4 EXT_MICA

1 2 1 2 1 2 2
2 5 +3VS R425 L47 1
Vn Vp 470_0402_5% R421 CHB1608B121_0603 1 1
4 JP27 3.9K_0402_1% C508 C522 SUYIN_010030FR006G101ZL_6P 4
3 CH2 CH3 4

@ S DIO(BR) NUP4301MR6T1 TSOP-6 1 1

2
J_MIC1
Place close to JP24 C487
1 1
C486 470P_0402_50V7K 470P_0402_50V7K
2 J_MIC2 2 2
3 3
JP21
4 4 Place close to U14 10U_0805_10V4Z
2 2
10U_0805_10V4Z
L_SPK+ 1 5 J_MIC_REF JP28
L_SPK- 1 5 J_MIC_SENSE J_R_HP
2 2 6 6 1 1
R_SPK+ 3 2 J_L_HP
R_SPK- 100P_0402_50V8J 4
3
4
ACES_87213-0600 2
3 3
J_DLINE_OUT_L
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 1 1 conn@ 4 4 Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
C506 C514 C507 C518 E&T_3801-04 Place close to JP15 5 5
6
J_DLINE_OUT_R
AMP & Audio Jack
6 J_VDDA_CODEC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100P_0402_50V8J 100P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 2 2 2 ACES_87213-0600 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951
100P_0402_50V8J conn@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 32 of 54
A B C D E
 5 4 3 2 1

Left side USB CONNECTOR 1

Left side USB CONNECTOR 0
USB_VCCA

+5VALW USB_VCCA
U57

1 8 W=80mils JP23 JP25

GND OUT 0_0603_5% R604 0_0603_5% R606
2 IN OUT 7 1 1 1 1

1000P_0402_50V7K
150U_D_6.3VM
D D

0.1U_0402_16V4Z
3 6 1 USB20_N4 1 2USB20_N4_R 2 2 USB20_N5_R 1 2USB20_N5 USB20_N5 <26>
IN OUT <26> USB20_N4 USB20_P4 1 2 2
1 4 EN# OC# 5 1 1 <26> USB20_P4 2USB20_P4_R 3 3 3 3 USB20_P5_R 1 2USB20_P5 USB20_P5 <26>

C567
+

C515

C519
C550 0_0603_5% R605 4 4 0_0603_5% R607
4 4
5 GND GND 5
4.7U_0805_10V4Z G548A2P1U 6 6
2 2 2 2 GND GND
7 GND GND 7
8 GND GND 8

SUYIN_020173MR004S558ZL
SLP_S5 conn@
SUYIN_020173MR004S558ZL
1 2 +5VALW conn@
R163
10K_0402_5%
USB20_P5
USB20_N5
USB20_P4

2
USB20_N4

2
D51
PJDLC05_SOT23~D
D52
PJDLC05_SOT23~D

1
Right side USB CONNECTOR 0

1
+5VALW USB_VCCC

U65
1 8 W=40mils JP26
C GND OUT 0_0603_5% R617 C
2 IN OUT 7 1 1

1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z

3 IN OUT 6 1 <26> USB20_N3 1 2USB20_N3_R 2 2

1 4 EN# OC# 5 1 1 <26> USB20_P3 1 2USB20_P3_R 3 3
C569

+
C517

C558 C521 0_0603_5% R614 4

TPS2061IDGN_MSOP8~N 4
5 GND
4.7U_0805_10V4Z 6
2 2 2 2 GND
7 GND
8 GND
SUYIN_020173MR004S558ZL
SLP_S5 conn@
SLP_S5 <38,39>
1 2 +5VALW
R164
10K_0402_5%

USB20_P3
USB20_N3

2
D61
PJDLC05_SOT23~D

BT Connector

1
JP22
1 +3VAUX_BT
R562
2 USB20_P0_R USB20_P0
3 2 1 0_0402_5% USB20_P0 <26>
USB20_N0_R 2 1 0_0402_5% USB20_N0
B 4 USB20_N0 <26> B
R586
5 BT_LED <35>
R458 1 2 1K_0402_5%
6 R459 1 1K_0402_5% CH_DATA <30>
7 2 CH_CLK <30>
8

2
SMART Card connector +SC_PWR
ACES_87212-0800 D53

@ PACDN042_SOT23~D

1
JP3 1
1 11 SC_FCB C367
1 11 SC_FCB <30>
2 12 SC_CLK
2 12 SC_CLK <30>
3 13 SC_RST 0.1U_0402_16V4Z
3 13 SC_RST <30> 2 +3VALW +3VAUX_BT
4 4 14 14 +SC_PWR
5 15 SC_CD# SC_CD# <30> Q51 SI2301BDS_SOT23
5 15
6 6 16 16

D
7 7 17 17 3 1
8 8 18 18
9 19 SC_DATA SC_DATA <30>
9 19

1
SC_RFU

G
10 20 SC_RFU <30> 1 1 1 1

2
10 20 C306 R518 C546 C545 C549
ACES_85203-1002 4.7U_0805_10V4Z
1U_0603_10V4Z 100K_0402_5% 0.1U_0402_16V4Z
2 2 2 2

2
0.01U_0402_16V7K
C556
R454
<26> BT_OFF 1 2 1 2
47K_0402_5%
A A
0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB & BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 33 of 54
5 4 3 2 1
 A B C D E

1 1
+3VS
RP3
DCD#1 1 8
RI#1 2 7
CTS#1 3 6
DSR#1 4 5
+5VS
4.7K_1206_8P4R_5%

2
IRRX 1 2
R76 D36
1K_0402_5%
CH751H-40_SC76

1
+5VS_PRN

RXD1 <38>
RP51
U8 R64 1K_0402_5% LPD3 1 8
<25,30,35,36> LPC_AD0 LPC_AD0 10 62 RXD1 1 2 LPD2 2 7
LPC_AD1 LAD0 RXD1 TXD1 LPD1
12 63 3 6

SERIAL I/F
<25,30,35,36> LPC_AD1 LAD1 TXD1 TXD1 <38>
<25,30,35,36> LPC_AD2 LPC_AD2 13 64 DSR#1 LPD0 4 5
LAD2 DSR1# DSR#1 <38>
<25,30,35,36> LPC_AD3 LPC_AD3 14 1 RTS#1
LAD3 RTS1# RTS#1 <38>
2 CTS#1 4.7K_1206_8P4R_5%
RP6 CTS1# CTS#1 <38>
<25,30,35,36> LPC_FRAME# LPC_FRAME# 15 3 DTR#1
LFRAME# DTR1# DTR#1 <38>
8 1 SIO_GPIO12 LPC_DRQ#0 16 4 RI#1 RP52
<25> LPC_DRQ#0 LDRQ# RI1# RI#1 <38>

LPC I/F
7 2 SIO_GPIO10 R108 1 2 0_0402_5% 5 DCD#1 LPD7 1 8
<26> NPCI_RST# DCD1# DCD#1 <38>
6 3 SIO_GPIO44 R109 1 2 @ 0_0402_5% SIO_RST# 17 LPD6 2 7
<25,30,35> PLT_RST_B# PCI_RESET#
5 4 SIO_GPIO43 +3VS R99 1 2 10K_0402_5% SIO_PD# 18 37 IRRX LPD5 3 6
LPCPD# IRRX2 IRRX <30>
FIR IRTX2 38 IRTXOUT <30>
LPD4 4 5
2 10K_1206_8P4R_5% PM_CLKRUN# 2
<26,30,35,36> PM_CLKRUN# 19 CLKRUN# IRMODE/IRRX3 39 IRMODE <30>
R120 CLK_PCI_SIO 20 4.7K_1206_8P4R_5%
<15> CLK_PCI_SIO PCI_CLK
1 2 SIO_IRQ SIRQ 21 41 LPTINIT#
R121 10K_0402_5% <26,30,35,36> SIRQ SIO_PME# SER_IRQ INIT# LPTSLCTIN# LPTINIT# <38> RP53
+3VS 1 2 6 IO_PME# SLCTIN# 42 LPTSLCTIN# <38>
1 2 SIO_DPIO45 R67 10K_0402_5% 44 LPD0 LPTACK# 1 8
PD0 LPD0 <38>
10K_0402_5% CLK_14M_SIO 9 46 LPD1 LPTBUSY 2 7
<15> CLK_14M_SIO CLK14 PD1 LPD1 <38>
CLOCK PD2 47 LPD2
LPD2 <38>
LPTPE 3 6
SIO_GPIO40 23 48 LPD3 LPTSLCT 4 5
GPIO40 PD3 LPD3 <38>

PARALLEL I/F
PID0 24 49 LPD4
+3VS GPIO41 PD4 LPD4 <38>
PID1 25 50 LPD5 4.7K_1206_8P4R_5%
GPIO42 PD5 LPD5 <38>
R119 SIO_GPIO43 27 51 LPD6
GPIO43 PD6 LPD6 <38>
CARD_ID# SIO_GPIO44 LPD7 RP54

GPIO
1 2 28 GPIO44 PD7 53 LPD7 <38>
SIO_DPIO45 29 55 LPTSLCT 1 8
GPIO45 SLCT LPTSLCT <38>
10K_0402_5% CARD_ID# 30 56 LPTPE LPTSTB# 2 7
GPIO46 PE LPTPE <38>
SER_SHD 31 57 LPTBUSY LPTAFD# 3 6
<38> SER_SHD GPIO47 BUSY LPTBUSY <38>
SIO_GPIO10 32 58 LPTACK# LPTERR# 4 5
GPIO10 ACK# LPTACK# <38>
SIO_GPIO11 33 59 LPTERR#
SIO_GPIO12 GPIO11/SYSOPT ERROR# LPTAFD# LPTERR# <38> 4.7K_1206_8P4R_5%
34 GPIO12/IO_SMI# ALF# 60 LPTAFD# <38>
SIO_IRQ 35 61 LPTSTB#
GPIO13/IRQIN1 STROBE# LPTSTB# <38>
R68 36 R480
EXPCRD_RST# EXPCRD_RST# GPIO14/IRQIN2 LPTSLCTIN#
1 2 40 GPIO23 1 2
<38> EXPCRD_RST#
10K_0402_5% 8 7 +3VS 4.7K_0402_5%
+3VS VSS VTR R481
22 VSS VCC 11
R77 43 VSS POWER VCC 26 LPTINIT# 1 2
1 2 PID0 52 45
VSS VCC 4.7K_0402_5%
VCC 54 1 1 1 1
10K_0402_5% C84 C88 C76 C57
LPC47N217_STQFP64

R79 Base I/O Address 2 2 2 2

1 2 PID1 0 = 02Eh
3 * 1 = 04Eh 3
10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 4.7U_0805_10V4Z

R80
1 2 SIO_GPIO11

10K_0402_5%

R100
1 2 SIO_GPIO40

10K_0402_5% CLK_PCI_SIO CLK_14M_SIO

1
R96 R81
@ 10_0402_5% @ 10_0402_5%
2

2
1 1
C94 C70
@18P_0402_50V8J @10P_0402_25V8K
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUPER I/O LPC47N217
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 34 of 54
A B C D E
 5 4 3 2 1

BIOS ROM
+3VALW

+3VS
R1287 +3VALW
1 2 SPI_WP#
3.3K_0402_5%
D R1288 U66 D
1
1 2 SPI_HOLD# C989 8 VCC VSS 4 47K
Q75

3
3.3K_0402_5%
0.1U_0402_16V4Z SPI_WP# 3
DTA114YKA_SC59
Mini-PCIE Card LED
2 W
SPI_HOLD# 7 10K 2
HOLD WW_LED# <30>
SPI_CS# 1
<26> SPI_CS# S
SPI_CLK 6 +3VS
<26> SPI_CLK C R1291

1
SPI_SI 5 2 SPI_SO_L 1 2 SPI_SO SPI_SO <26>
<26> SPI_SI D Q 47K

3
47_0402_5%
SST25LF080A_SO8-200mil
R1291 place cloe to U66 10K 2 WL_LED# <30>
Q88
DTA114YKA_SC59 BLUE
+3VS

1
Q79 WL_BLUE_LED# <30,37>
RHU002N06_SOT323
47K

1
D
BT_LED 2
10K <33> BT_LED
2 G
WP_LED# <30>
S

3
2
R505
Q89 100K_0402_5%
DTA114YKA_SC59

1
C C

1
D Q78
WL_LED 2 RHU002N06_SOT323
G
S

3
2
R504
100K_0402_5%

1
TPM1.2
+3VS+3VALW

0.1U_0402_16V4Z
1 1 1 1
C1053 C1054 C1055 C1052
Base I/O Address
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0 = 02Eh +3VS
2 2 2 2 * 1 = 04Eh
0.1U_0402_16V4Z
24
19
10

U69
R1377
VSB
VDD
VDD
VDD

4.7K_0402_5%
LPC_AD0 26 28 LPC_PD#
<25,30,34,36> LPC_AD0 LPC_PD# <26,36>
2

LPC_AD1 LAD0 LPCPD#

<25,30,34,36> LPC_AD1 23 LAD1 TESTB1/BADD 9
LPC_AD2 20 8 R1379 2 1 0_0402_5%
<25,30,34,36> LPC_AD2 LAD2 TEST1
1

LPC_AD3 17 R1378
B <25,30,34,36> LPC_AD3 LAD3 B
14 TPM_XTALO @ 4.7K_0402_5%
XTALO TPM_XTALI 1
XTALI 13 2 TPM_32K_CLK <36>
TPM R101 @ 0_0402_5%
CLK_PCI_TCG 21 SLB 9635 TT 1.1
<15> CLK_PCI_TCG
2

LPC_FRAME# LCLK TPM_GPIO2 PAD T87

<25,30,34,36> LPC_FRAME# 22 LFRAME# GPIO2 2
PLT_RST_B# 16 6 TPM_GPIO
<25,30,34> PLT_RST_B# LRESET# GPIO
SIRQ 27 PAD T62 18P_0402_50V8J
<26,30,34,36> SIRQ SERIRQ
PM_CLKRUN# 15 TPM_XTALI C1057 1 2
<26,30,34,36> PM_CLKRUN# CLKRUN#
+3VS 1 2 7 PP NC 1
1

R1380 3 32.768KHZ_12.5P_Q13MC30610018
@ 4.7K_0402_5% NC R1381
12 1 NC 2
GND
GND
GND
GND

NC IN
1

R1409 4 3
SLB9635TT_TSSOP28 OUT NC
4
11
18
25

0_0402_5% Y8
TPM_XTALO C1056 1 2
2

10M_0402_5%
18P_0402_50V8J

Finger printer +3VS

1
C206

0.1U_0402_16V4Z
2
JP38
0_0402_5% 1
A R1334 USB20_N2_R 1 A
<26> USB20_N2 2 1 2 2
R1335 2 1 USB20_P2_R 3
<26> USB20_P2 3
0_0402_5% 4 4
3

ACES_85205-0400
conn@
D54
@ PACDN042_SOT23~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 35 of 54
5 4 3 2 1
 5 4 3 2 1

+3VL +3VS

1 1 1 1 1 1 1 1 1
C37 C52 C51 C36 C34 C75 C79 C78 C81

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z

2 2 2 2 2 2 2 2 2
+3VL

D BIOS debug port D

RP44
1 8 KSI0 +3VL Place under KB area
KSI3

11
67
81
94

30
38
47
2 7
3 6 KSI2 U47 +3VL

1
4 5 KSI1 KSO[0..13]

VCC1
VCC1
VCC1
VCC1

VCC2
VCC2
VCC2
<37> KSO[0..13]
R30 JP43
10K_1206_8P4R_5% KSO0 17 99 KBC_PWR_ON
KSO0 OUT0 KBC_PWR_ON <45> 1
KSO1 16 100 GREEN_BATLED# 10K_0402_5% VCC1_PWRGD
RP43 KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# <30> 2
15

2
KSI7 KSO3 KSO2 BATSELB_A# D7 EC_GPIO9 3
1 8 14 KSO3 OUT7/SMI# 98 BATSELB_A# <44> 4
2 7 KSI6 KSO4 13 97 KBRST# 1 2 EC_GPIO8
KSI5 KSO5 KSO4 OUT8/KBRST INV_PWM KB_RST# <25> 5
3 6 12 KSO5 OUT9/PWM2 96 INV_PWM <17> 6
4 5 KSI4 KSO6 10 95 FAN_PWM CH751H-40_SC76
KSO7 KSO6 OUT10/PWM0 CHGCTRL FAN_PWM <4> @ ACES_85201-0602
9 KSO7 OUT11/PWM1 93 CHGCTRL <43,44>
10K_1206_8P4R_5% KSO8 7
KSO9 KSO8 FWP# Pin82 250 -- nFWP
6 KSO9 GPIO01 82

Keyboard/Mouse Interface
KSO10 5 62 ON/OFFBTN_KBC# ON/OFFBTN_KBC# <37>
KSO10 GPIO02

General Purpose I/O Interface

KSO11 4 63 LOW_BAT# LOW_BAT# <26>
Pin3 250 : KSO12/OUT8/KBRST KSO12 KSO11 GPIO03 KSO14 +3VL
3 KSO12/GPIO00/KBRST GPIO04/KSO14 64 KSO14 <37>
KSO13 2 66 KSO15 KSO15 <37>
+5VS KSO13/GPIO18 GPIO05/KSO15 THM_MAIN# 1 R600
<37> KSI[0..7] 2
PM_RSMRST# 210K_0402_1%

SMSC_LPC47N250_TQFP-100P
GPIO07/PWM3 68 PM_RSMRST# <26>
R84 KSI0 25 69 EC_GPIO8 ADP_PS1 1 2
TP_CLK KSI1 KSI0 GPIO08/RXD EC_GPIO9 R538 @ 100K_0402_5%
1 2 24 KSI1 GPIO09/TXD 70
KSI2 23 D10 EC_GPIO13 1 R33 2
10K_0402_5% KSI3 KSI2 BATCON 100K_0402_5%
22 KSI3 GPIO11/AB2A_DATA 71 BATCON <44> 2 1 ADP_PRES <28,43,44,45,50>
R85 KSI4 21 72 ADP_PS1
KSI4 GPIO12/AB2A_CLK ADP_PS1 <50>
1 2 TP_DATA KSI5 20 KSI5 GPIO13/AB2B_DATA 73 EC_GPIO13 CH751H-40_SC76
KSI6 19 74 THM_MBAY# 2 R31 1 +3VL
KSI6 GPIO14/AB2B_CLK THM_MBAY# <42>
10K_0402_5% KSI7 18 75 PCI_SERR# 10K_0402_5%
KSI7 GPIO15/FAN_TACH1 PCI_SERR# <24,30>
76 THM_MAIN# D6
C RP5 GPIO16/FAN_TACH2 THM_MAIN# <42> C
77 A20M 1 2
KBD_CLK TP_CLK GPIO17/A20M CH751H-40_SC76 GATEA20 <25> +3VL
1 8 <37> TP_CLK 26 IMCLK
2 7 KBD_DATA TP_DATA 27 78 NUM_LED#
<37> TP_DATA IMDAT GPIO20/PS2CLK NUM_LED# <30,37>
3 6 PS2_CLK KBD_CLK 29 80 SLP_S3# RP1
<38> KBD_CLK KCLK GPIO21/PS2DAT SLP_S3# <26,28,30,31,32,38,39,46,47,48>
4 5 PS2_DATA KBD_DATA 31 1 AB1A_CLK 1 8
<38> KBD_DATA KDAT GPIO24/KSO16
PS2_CLK 32 57 MODE 1 2 0_0402_5% Pin1 250 -- TEST Pin ( NC !! ) AB1A_DATA 2 7
<38> PS2_CLK EMCLK GPIO27 EAPD <31,32> Pin57 250 -- MODE
10K_1206_8P4R_5% PS2_DATA 33 R140 AB1B_CLK 3 6
<38> PS2_DATA EMDAT AB1B_DATA 4 5

Note: R94 must be removed when 86 AB1A_DATA AB1A_DATA <42> 4.7K_1206_8P4R_5%

AB1A_DATA AB1A_CLK
AB1A_CLK 87 AB1A_CLK <42>
R1354 stuff and R87 remove. Access Bus Interface
+3VS PM_CLKRUN# 44 84 AB1B_DATA
<26,30,34,35> PM_CLKRUN# CLKRUN# AB1B_DATA AB1B_DATA <42>
SIRQ 46 85 AB1B_CLK
<26,30,34,35> SIRQ SER_IRQ Power Mgmt/SIRQ AB1B_CLK AB1B_CLK <42>
R94 CLK_PCI_EC 43
<15> CLK_PCI_EC PCI_CLK
1 2 LPCPD# RUNSCI_EC# 59 56 PGM R141 1 2 0_0402_5%
<26> RUNSCI_EC# EC_SCI# PGM Strap/GPIO25 A_SD <32>
R282 C92
10K_0402_5% 83 EA# Pin83 250 -- nEA ( pull up !! )
R1289 LPC_AD3 EA Strap#/GPIO26/KSO17 CLK_14M_KBC Pin56 250 -- PGM CLK_14M_KBC 1
<25,30,34,35> LPC_AD3 40 LAD[3] CLOCK 48 CLK_14M_KBC <15> 2 1 2
1 2 RUNSCI_EC# LPC_AD2 39 58 32K_CLK Pin58 250 -- 32KHz_OUT
<25,30,34,35> LPC_AD2 LAD[2] 32KHZ_OUT/GPIO22
LPC_AD1 37 49 PM_POK Pin49 250 -- Reset Out
<25,30,34,35> LPC_AD1 LAD[1] RESET_OUT#/GPIO06 PM_POK <7,26> 10_0402_5% 10P_0402_25V8K

Bus
LPC
10K_0402_5% LPC_AD0 35 61 PWR_GD
<25,30,34,35> LPC_AD0 LAD[0] PWRGD PWR_GD <21,39,40,49,50> @ @
60 VCC1_PWRGD
VCC1_PWRGD VCC1_PWRGD <40>
LPC_FRAME# 41 50
<25,30,34,35> LPC_FRAME# LFRAME# 24MHZ_OUT/GPIO19/WINDMON Pin50 250 -- 24MHz_Out ADP_ID <50>
PLT_RST# 42
Pin34 250 -- LPCPD# <7,24,25,26,28,30> PLT_RST# LRESET#
34 52 TEST 1 2

Miscellaneous
R87 1 LPCPD#/GPIO23 TEST PIN Pin52 250 -- XOSEL
<26,35> LPC_PD# 2 @ 0_0402_5% LPCPD# R977 300_0402_5% R25
R1354 1 2 @ 0_0402_5% Pin91 250 -- nDMS_LED FWP# 1 2 PM_POK
<50> ADP_EN
CRY1 53 91
XTAL1 DMS_LED#/GPIO10 ADP_PS0 <50>
1 2 CRY2 54 88 AMBER_BATLED# 10K_0402_5%
XTAL2 BAT_LED# AMBER_BATLED# <30>
CLK_PCI_EC 90 STB_LED#
PWR_LED#/8051TX STB_LED# <30,37,38>
R74 51 89 CAPS_LED#
VCC0 FDD_LED#/8051RX CAPS_LED# <30,37>
1

B @ 2M_0402_5% R75 B
AGND

R86 2 1
GND
GND
GND
GND
GND
GND
GND
@ 10_0402_5% 120K_0402_5% +RTCVCC R62 R62 250@ +3VL
KBC1021_TQFP100 MODE 1 2 JP31
2

55

92
79
65
45
36
28
8
1

2 1
C80 Y2 @ 10K_0402_5% VCC1_PWRGD
IN

OUT

R58 2
18P_0402_50V8J 1 1 18P_0402_50V8J +3VL 1 2 100K_0402_5% NUM_LED# 3
R52
@ 10P_0402_50V8J R59 1 2 100K_0402_5% STB_LED# 4
1 C350 C349 PGM R60 100K_0402_5% CAPS_LED#
2 1 1 2 1 2 5
C69 C67
NC

NC

2 2 @ 1K_0402_5% 6
1U_0603_10V4Z 0.1U_0402_16V4Z
2

1 2 R29 Remove from daughter board @ ACES_85201-0602

FWP# 1 2
32.768KHZ_12.5P_Q13MC30610018
@ 1K_0402_5% For KBC debugging used.
1. For normal operation:
+3VL
32K_CLK R91 0_0402_5% J3 R65 Un-install R29,R65
1 2 ADP_EN <50>
PGM 1 2 1 2
R97 1 2 @ 0_0402_5% TPM_32K_CLK <35>
NO SHORT PADS 1K_0402_5%
AGND FILTER FWP#
R28 2. For KBC internal ROM flash:
C58
2 1
@ 1K_0402_5%
Install R29,R65
1 2

0.1U_0402_16V4Z R78
TEST 2 1
A @ 1K_0402_5% A

R27
EA# 2 1
250@ 1021@ 1K_0402_5%

R127 R129
R128 R131
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
R977 R78 LPC47N1021
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R62 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
LA-2951
Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 36 of 54
5 4 3 2 1
 +3VS +5VS

INT_KBD CONN.
220P_0402_50V4Z C749

SWITCH
2 1 STB_LED#
220P_0402_50V4Z C750
2 1 ON/OFF#
JP18 220P_0402_50V4Z C751

BOARD.
14 28 2 1 KSI1 KSO[0..15]
14 28 <36> KSO[0..15]
13 13 27 27
12 26 KSI[0..7]
12 26 <36> KSI[0..7]
11 25 NUM_LED#
11 25 NUM_LED# <30,36>
10 24 CAPS_LED#
10 24 CAPS_LED# <30,36>
9 23 MUTE_LED#
9 23 MUTE_LED# <32>
8 22 WL_BLUE_LED#
8 22 WL_BLUE_LED# <30,35>
7 21 KSO12 +3VALW
7 21 KSI0 JP20 JP6
6 6 20 20
5 19 KSI4 1 KSO15 48 24
5 19 1 LID_SW# <17,26> 48 24
4 18 KSI5 2 KSO10 47 23
4 18 KSI6 2 STB_LED# KSO11 47 23
3 3 17 17 3 3 STB_LED# <30,36,38> 46 46 22 22
2 16 KSI7 8 4 ON/OFF# KSO14 45 21
2 16 GND 4 KSO12 KSO13 45 21
1 1 15 15 9 GND 5 5 44 44 20 20
6 KSI1 KSO12 43 19
ACES_85203-1402 6 KSO3 43 19
7 7 42 42 18 18
KSO6 41 17
ACES_85205-07001 KSO8 41 17
40 40 16 16
KSO7 39 15
39 15
WL,Vol up,Vol down,Mute,Present button KSO4
KSO2
38
37
38
37
14
13
14
13
KSI0 36 12
36 12
On/off ,information button KSO1
KSO5
35
34
35
34
11
10
11
10
KSI3 33 9
KSI2 33 9
32 32 8 8
KSO0 31 7
KSI5 31 7
30 30 6 6

MDC 1.5 Conn.

KSI4 29 5
KSO9 29 5
28 28 4 4
KSI6 27 3
KSI7 27 3
26 26 2 2
KSI1 25 1
+3VS 25 1
conn@
ACES_85203-2402

1
C5

0.1U_0402_16V4Z CP1 CP6

2 KSO9 KSO2
4 5 4 5
JP32 +3VS KSI6 3 6 KSO4 3 6
KSI7 2 7 KSO7 2 7
1 2 KSI1 1 8 KSO8 1 8
AC97_SDOUT_MDC GND1 RES0
<25> AC97_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
5 6 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
R1313 AC97_SYNC_MDC GND2 3.3V
<25> AC97_SYNC_MDC 7 IAC_SYNC GND3 8
<25> AC97_SDIN1 2 1AC97_SDIN1_MDC 9 IAC_SDATA_IN GND4 10 CP3 CP5
33_0402_5% 11 12 AC97_BITCLK_MDC AC97_BITCLK_MDC <25> KSI2 4 5 KSO6 4 5
IAC_RESET# IAC_BITCLK KSO0 KSO3
3 6 3 6
<25> AC97_RST#_MDC AC97_RST#_MDC KSI5 2 7 KSO12 2 7
KSI4 1 8 KSO13 1 8
13
14
15
16
17
18
19
20

100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
TYCO_1-179396-2~D
13
14
15
16
17
18
19
20

CP7 CP2
KSI3 4 5 KSO14 4 5
Connector for MDC Rev1.5 KSO5 3 6 KSO11 3 6
KSO1 2 7 KSO10 2 7
KSI0 1 8 KSO15 1 8

100P_1206_8P4C_50V8 100P_1206_8P4C_50V8

Power button +3VL

+3VL +3VL
1

R536
1

TrackPoint CONN. T/P BOARD.

R22 100K_0402_5%
2

100K_0402_5% U5F ON/OFFBTN_KBC#

14

ON/OFFBTN_KBC# <36>
SN74LVC14APWLE_TSSOP14
2

R26 D
P

ON/OFF# 13 +3VALW +5VS

<38> ON/OFF# I O 12 1 2 2
G R8 JP14 +5VS JP17
G

100K_0402_5% S 1 2 +5VS
1 1
3

C23 C11 100K_0402_5% 1 2 SP_CLK TP_DATA 1

<36> TP_DATA
7

SP_DATA 3 4 TP_CLK 2
5 6 1 <36> TP_CLK 3 1

2
1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# ON/OFFBTN# <26> +5VS C321 C319
2 2 Q70 7 8 4
RHU002N06_SOT323 D42 ACES_87153-0801L D67 0.1U_0402_16V4Z SP_DATA 5 0.1U_0402_16V4Z
CH751H-40_SOD323 2 6 2
SP_CLK 7
8

1
@ PACDN042_SOT23~D ACES_87212-0800

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 37 of 54
 A B C D E

+5VALW

1
DOCK CONN. 184PIN R529

100K_0402_5%
JP29

2
C746 @ 1000P_0402_50V4Z
M_RED 1 2 L10 SLP_S5#_5R DOCK_MOD_RING
C747 @ 1000P_0402_50V4Z KC FBM-L18-453215-900LMA90T_1812 DOCK_MOD_TIP 2
1

1
M_GRN D
1 2 VIN 2 1 DOCKVIN
C748 @ 1000P_0402_50V4Z 1 2 Q65
1 1 <33,39> SLP_S5 1
M_BLU 1 2 C72 C73 G ACES_85205-0200
S RHU002N06_SOT323

3
1000P_0402_50V7K 1000P_0402_50V7K
2 2 SWAP

JP30B
JP30A
<34> LPTACK# LPTACK# 46 128
LPTBUSY 46 128
172 G1 P1 173 DOCKVIN <34> LPTBUSY 47 47 129 129
<34> LPTPE LPTPE 48 130
LPTSLCT 48 130
<34> LPTSLCT 49 49 131 131
<34> LPD7 LPD7 50 132
ON/OFF# DETECT LPD6 50 132
<37> ON/OFF# 1 1 83 83 <34> LPD6 51 51 133 133
2 84 <34> LPD5 LPD5 52 134 KBD_DATA
2 84 52 134 KBD_DATA <36>
MDO2+ 3 85 MDO3+ MDO3+ <29> <34> LPD4 LPD4 53 135 KBD_CLK
<29> MDO2+ 3 85 53 135 KBD_CLK <36>
MDO2- 4 86 MDO3- MDO3- <29> <34> LPD3 LPD3 54 136 CPPE#
<29> MDO2- 4 86 54 136 CPPE# <15,24>
5 87 <34> LPD2 LPD2 55 137 PS2_DATA
5 87 55 137 PS2_DATA <36>
MDO0+ 6 88 MDO1+ MDO1+ <29> <34> LPD1 LPD1 56 138 PS2_CLK
<29> MDO0+ 6 88 56 138 PS2_CLK <36>
MDO0- 7 89 MDO1- MDO1- <29> <34> LPD0 LPD0 57 139 DOCK_HPS#
<29> MDO0- 7 89 57 139 DOCK_HPS# <32>
8 90 <34> LPTSLCTIN# LPTSLCTIN# 58 140
LAN_ACT#_DOCK 8 90 PWR_LED LPTINIT# 58 140 DLINE_IN_L
9 9 91 91 <34> LPTINIT# 59 59 141 141 DLINE_IN_L <31>
LANLINK_STATUS#_DOCK 10 92 1 2 SLP_S5#_5R 60 142 DLINE_IN_R
10 92 60 142 DLINE_IN_R <31>
11 93 R515 1K_0402_5% 61 143
11 93 DVI_CLK 61 143 DLINE_OUT_L
<16> D_VSYNC 12 12 94 94 DVI_CLK <19> 62 62 144 144 DLINE_OUT_L <32>
<16> D_HSYNC 13 95 DVI_DAT DVI_DAT <19> 63 145 DLINE_OUT_R
13 95 63 145 DLINE_OUT_R <32>
<16> D_DDCDATA D_DDCDATA 14 96 64 146
D_DDCCLK 14 96 64 146
<16> D_DDCCLK 15 15 97 97 65 65 147 147
<19> DVI_DETECT DVI_DETECT 16 98 DVI_TX2- 66 148
16 98 DVI_TX2- <19> 66 148
17 99 67 149 PCIE_TXP4 PCIE_TXP4 <26>
M_RED R1404 DOCK_RED 17 99 DVI_TX2+ 67 149
1 2 0_0402_5% 18 18 100 100 DVI_TX2+ <19> 68 68 150 150
M_GRN R1428 1 2 0_0402_5% DOCK_GRN 19 101 69 151 PCIE_TXN4 PCIE_TXN4 <26>
2 M_BLU R1429 DOCK_BLU 19 101 69 151 2
1 2 0_0402_5% 20 20 102 102 70 70 152 152
21 103 DVI_TX1- 71 153
21 103 DVI_TX1- <19> 71 153
<16,19> COMP 22 104 <26> USB20_N6 72 154 PCIE_C_RXP4 1 R1346 2PCIE_RXP4
22 104 72 154 PCIE_RXP4 <26>
<16,19> CRMA 23 105 DVI_TX1+ 73 155 0_0402_5%
23 105 DVI_TX1+ <19> 73 155
<16,19> LUMA 24 106 <26> USB20_P6 74 156 PCIE_C_RXN4 1 R1347 2PCIE_RXN4
24 106 74 156 PCIE_RXN4 <26>
25 107 75 157 0_0402_5%
25 107 DVI_CLK- 75 157
26 26 108 108 DVI_CLK- <19> <26> USB20_N7 76 76 158 158
27 109 77 159 CLK_PCIE_DOCK
<31> LINE_IN_SENSE 27 109 77 159 CLK_PCIE_DOCK <15>
28 110 DVI_CLK+ <26> USB20_P7 78 160
28 110 DVI_CLK+ <19> 78 160
29 111 79 161 CLK_PCIE_DOCK#
<50> ACOCP_EN# 29 111 79 161 CLK_PCIE_DOCK# <15>
30 112 <34> SER_SHD SER_SHD 80 162
30 112 DVI_TX0- EXPCRD_RST# 80 162 PREP#
31 31 113 113 DVI_TX0- <19> <34> EXPCRD_RST# 81 81 163 163 PREP# <26,29,31>
32 114 DETECT 82 164 VA_ON#
32 114 DVI_TX0+ 82 164
33 33 115 115 DVI_TX0+ <19>

1
DCD#1 34 116 176 178 1
<34> DCD#1 34 116 GND GND
RI#1 35 117 DOCK_ADP_SIGNAL 169 180 R66 C59
<34> RI#1 35 117 GND GND
DTR#1 36 118 DOCK_ID 175 182
<34> DTR#1 36 118 DOCK_ID <26> GND GND
CTS#1 37 119 179 174 1K_0402_5% 0.1U_0402_16V4Z
<34> CTS#1 37 119 +3VS GND GND 2
RTS#1 38 120 181 171
<34> RTS#1

2
DSR#1 38 120 GND GND
<34> DSR#1 39 39 121 121 R1387 177 GND GND 170
TXD1 40 122 +5VS
<34> TXD1 40 122 C555
RXD1 41 123 DOCK_ID 1 2
<34> RXD1 41 123

+
42 42 124 124 165 G2 P2 167 1 2
LPTSTB# 43 125 @ 10K_0402_5%
<34> LPTSTB# 43 125 ADP_SIGNAL
LPTAFD# 44 126 @ 22U_1206_10V4Z
<34> LPTAFD# 44 126
LPTERR# 45 127 DOCK_MOD_RING 166 168 DOCK_MOD_TIP
<34> LPTERR# 45 127 R1401 RING TIP

2
DOCK_ADP_SIGNAL 1 2
JAE_SP03-14588-PCL03 JAE_SP03-14588-PCL03
1K_0402_1% D59
@ PACDN042_SOT23~D

3 3

1
V_3P3_LAN LAN_ACT#_DOCK

1
R527 D
2 1 2 Q62
10K_0402_5% G RHU002N06_SOT323
S

3
+3VS +3VS LAN_ACT#
+3VS LAN_ACT# <28,29>
C360 +3VALW
C366 C365
2 1 LANLINK_STATUS#_DOCK
1 2 2 1

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z D
U52 0.1U_0402_16V4Z 2 Q63 R526
U51 U50 G RHU002N06_SOT323
5 VCC
5 VCC 5 S 10K_0402_5%

3
M_BLU VCC LANLINK_STATUS#
<19> M_BLU 1 LANLINK_STATUS# <26,28,29>

2
BLUE A M_GRN M_RED
<16> BLUE 2 B <19> M_GRN 1 A <19> M_RED 1 A
<16> GREEN GREEN 2 <16> RED RED 2 PWR_LED
ISO_PREP# B B
<26> ISO_PREP# 4 OE

1
ISO_PREP# ISO_PREP# D
4 OE 4 OE
3 GND <30,36,37> STB_LED# 2
3 3 G
4 FSA66P5X_SC70-5 GND GND Q59 4
S

3
FSA66P5X_SC70-5 FSA66P5X_SC70-5 RHU002N06_SOT323
<26,28,30,31,32,36,39,46,47,48> SLP_S3#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Docking CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 38 of 54
A B C D E
 A B C D E

+1.8V to +1.8VS Transfer

VRAM
+1.8V VDD_MEM18

U10
8 D S 1
1 1
7 D S 2
1 6 3 +5VALW
C171 D S
5 D G 4 1 1
C160 C170

1
SI4800DY_SO8
2 10U_0805_10V4Z C91
10U_0805_10V4Z R135
2 2
+VCC_CORE 1 2 +VCCP
RUNON 100K_0402_5%

2
0.1U_0402_16V4Z 0.1U_0402_16V4Z

<33,38> SLP_S5 SLP_S5

C184

+VCCP 1 2 +1.5VS

1
D
SLP_S5# 2
0.1U_0402_16V4Z <26,47> SLP_S5#
G
Q22 S
C93

3
RHU002N06_SOT323
+1.5VS 1 2 +1.8V

0.1U_0402_16V4Z

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+3VALW +3VS
+5VALW +5VS B+
2 U13 2
U9 8 1 10U_0805_10V4Z
D S

1
8 1 7 2 +3VL
D S R139 D S
7 D S 2 1 6 D S 3
1 6 3 C127 5 4 1 1
D S D G

1
C86 5 4 1 1 330K_0402_5% C132 C128
D G C71 C77 SI4800DY_SO8 R125

2
SI4800DY_SO8 2 10U_0805_10V4Z
2 10U_0805_10V4Z 10U_0805_10V4Z 2 2 100K_0402_5%
2 2 RUNON

2
RUNON

1
J34 0.1U_0402_16V4Z
0.1U_0402_16V4Z R469 SLP_S3
SHORT PADS
1 2
470_0402_5%

1
D D

2
SLP_S3 2 1 SLP_S3# 2
<26,28,30,31,32,36,38,46,47,48> SLP_S3#
G C120 G
Q18 S Q19 S
3

3
RHU002N06_SOT323 0.01U_0402_25V7Z RHU002N06_SOT323
2

3 3

Discharge circuit PWR_GD <21,36,40,49,50>

+3VS
+0.9V +1.8V VDD_MEM18 +2.5VS +5VS +1.5VS

1
1

1
R134
R188 R1310 R95 R130 R116 R151
470_0402_5%
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
2
1 2

1 2

1 2

1 2

1 2

1 2
1

D D D D D D D
SLP_S5 1 2 2 SLP_S5 2 SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP_S3 2
R1311 @ 0_0402_5% G G G G G G G
S Q90 S Q14 S Q21 S Q17 S Q16 S Q47 S
3

3
SLP_S3 1 2 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
0_0402_5%
R1312 Q27
RHU002N06_SOT323

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 39 of 54
A B C D E
 VDD_MEM18 +3VS +3VS +3VL +3VL
+3VL

1
+3VL
R89 R82 R281 R7

14

14
1K_0402_5% 330_0402_5% 330_0402_5% U5A U5B D8 +3VL 10K_0402_5%

1
R38 CH751H-40_SOD323

P
1

2
1 2 1 2 3 4 1 2 R24
I O 47K_0402_5% I O
VCC1_PWRGD <36>

G
C 100K_0402_5%

14
2 Q10 SN74LVC14APWLE_TSSOP14 1 SN74LVC14APWLE_TSSOP14 U5D

1
B PMST3904_SOT323 C48 D

P
1
C E +3VS 9 8 2

3
Q11 0.1U_0402_16V4Z I O G Q3
2

G
B PMST3904_SOT323 2 S RHU002N06_SOT323
1

3
E C26 SN74LVC14APWLE_TSSOP14
3

7
1
0.1U_0402_16V4Z
+5VS +3VL R47 2

10K_0402_5%
1

2
C25

1
J32
R43 0.1U_0402_16V4Z 1 2 PWR_GD
2 PWR_GD <21,36,39,49,50>
180K_0402_5% SHORT PADS

14
2 U5C

1
D

P
5 I O 6 2
G Q9

G
S RHU002N06_SOT323

3
1

1 SN74LVC14APWLE_TSSOP14

7
R37 C47

560K_0402_5% 0.1U_0402_16V4Z
2
2

+1.5VS +2.5VS +2.5VS +3VL

2

R122 R113 R283

FM1 FM2 FM3 FM4
14

1K_0402_5% 330_0402_5% 330_0402_5% U5E 1 1 1 1

1
D
P
1

11 I O 10 2
G Q2
1

C S RHU002N06_SOT323 CF7 CF8 CF9 CF10 CF11 CF12 CF13 CF14

3

2 Q26 SN74LVC14APWLE_TSSOP14 1 1 1 1 1 1 1 1
7

B
1

C E PMST3904_SOT323
3

<46> VCCP_POK 2 Q15

B
E PMST3904_SOT323 H1 H2 H3 H4 H5 H6 H7 H8 H9
3

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEAHOLEA HOLEA

1
+3VS +3VS
Need be tune to H10 H11 H12 H13 H14
HOLEB HOLEB HOLEB HOLEB HOLEB
1 3msec time delay 1
C991 C992
D60

1
0.1U_0402_16V4Z CH751H-40_SOD323 0.1U_0402_16V4Z
2 2
1 2
5

R123 U62 R1350 U63

P

PWR_GD 1 2 2 4 1 2 2 4 H15 H16 H17

I O I O PGD_IN <49>
0_0402_5% 1 150K_0402_1% 1 HOLEC HOLEC HOLEC
NC NC
G

G
0.47U_0603_10V7K

1
R1402 SN74LVC1G17DBVR_SOT23-5 SN74LVC1G17DBVR_SOT23-5
3

1 2 PGD_IN

1
C990

@ 0_0402_5%
2

R1303 H18 H19 H20 H21 H22 H23 H24 H25

<15,49> CLK_ENABLE# CLK_ENABLE# 1 2 HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED
@ 0_0402_5%

1
H27 H28 H32 H33 H34 H35 H36 H37
HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 40 of 54
 5 4 3 2 1

D D

G965
AC VIN +3VS LDO
Adapter LM358 (2.5V)
VS Thermal
in
Protector

+5VALWP
ACOK SWITCH
MAINPWON VL
+2.5VS 1A
+3VALWP 4A
ENBL2 ENBL1
+5VS
B+ B+ PWR_GD
C MAX8734A C

DC/DC
(3V/5V) VCC SHDN#
+5VALWP 4A
VMB VIN
ISL6260 &ISL6208
VS DC/DC
(CPU_CORE)
+3VLP 0.1A

BQ24703 MAX8743
Charger DC/DC +1.5VSP 4.2A
B+ (1.05V/1.5V) CPU_CORE
B
( 44A) B

SLP_S3#
+1.05V_VCCP 6.4A +5VALWP
ENBL1/ENBL2
BATSELB_A
Battery
Selector
Circuit BATSELB_A# VCC
Battery A Battery B
6 Cell 8 Cell TPS51116
B+ DC/DC +1.8VP 7A
VMB (+1.8VP/+0.9VSP)

SWITCH SWITCH SWITCH Battery

VMB_A VMB_B
Battery
SLP_S5#
+0.9VP 2A
Connector Connector S3/S5
A A B A

BATT
BATT_A Title
POWER BLOCK DIAGRAM
BATT_B
Size Document Number Rev

Date: Friday, April 28, 2006 Sheet 41 of 54

5 4 3 2 1
 A B C D

PCN1 ADP_SIGNAL
9 GND6 SINGAL 5 VIN
8 GND5
1 PL1 1

7 1 FBM-L18-453215-900LMA90T_1812
GND4 PWR1
6 ADPIN 1 2
GND3

100P_0402_50V8J
4 GND2 PWR2 2

1000P_0402_50V7K
3 GND1

1
PC1

100P_0402_50V8J
1

1
PC4
FOX_JPD113E-LB103-7F PC2 PR1
1000P_0402_50V7K

PC3
15K_0402_5%

2
AB/I_A <44>
VMB_A PL2 BATT_A
PCN2
FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_A
SMD EC_SMC_A PR2
SMC 3
2
RES 4 2 1 2

1
5 1M_0402_1%
TS PC5 PC6
6 1000P_0402_50V7K 0.01U_0402_50V4Z

2
GND
1 2 +3VL
TYCO_C-1746706_6P PR10
210K_0402_1%
1

PR3
1K_0402_5%
1

PR4 PR5
100_0402_5% 100_0402_5%
THM_MAIN# <36>
2

EC_SMD_A1 AB1A_DATA <36>

EC_SMC_A1 AB1A_CLK <36>
1

1
220P_0402_25V8K
PC144

PC143 PC145
220P_0402_25V8K 220P_0402_25V8K
2

3 3

VMB_B

PCN3 PL3 BATT_B

FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_B
SMD EC_SMC_B
SMC 3
1

4 AB/I_B 2 PR7 1
B/I TS_B 1K_0402_5% PC8 PC9
TS 5
1 2 1000P_0402_50V7K 0.01U_0402_50V4Z
+3VL
2

2
2

6 PR9
GND PR11 210K_0402_1%
SUYIN_20163S-06G1-K 1K_0402_5%
1
1

PR14 PR15
THM_MBAY# <36>
100_0402_5%
100_0402_5%
2

EC_SMD_B1
AB1B_DATA <36>
4 4

EC_SMC_B1
AB1B_CLK <36>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 42 of 54
A B C D
 A B C D

1 1

VIN P2

BATT
P4 PQ2
PQ3 PQ4 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8
1 8 8 1 2 7
2 7 7 2 3 6
3 6 6 3 5
0.1U_0603_16V7K

PQ5 5 5
B+ P2
47K_0402_5%

DTA144EUA_SC70 PR17

4
1

3 1 0_0402_5%
4

4
1
PC12

PR16 1 2
2

47K

200K_0402_5%

2
0_0402_5%
PR20 PL4
47K

PR19
0.015_2512_1% FBM-L11-322513-151LMAT_1210
2

1 2 1 2
2
PR18
1

47P_0402_50V8J

1
2

ACDRV# CHG_B+
ACN <50>
2
PC13

10U_1206_25V6M

4.7U_1206_25V6K
PR21
1

150K_0402_5% PR22 1 PR23

1
100_0402_1% 0_0402_5%

PC14

PC15
ADP_PRES 2 1
1

1
2

1U_0805_25V4Z
1
1 2

PC17
PD7
2
ADP_EN# <50> PC16 PD5 2

2
2 1 1U_0603_6.3V6M RLZ16B_LL34

2
1 2

3
2
1
PR24 PU2
1SS355_SOD323 1K_0402_1% ACDRV#
SRSET <50> 8 ACN ACDRV# 25
9 ACP VCC 22
26 21 DH_CHG 4 PQ7
ACDET PWM# SI4835BDY_SO8
SRP 16
AC_CHG 2 PR25 1 5 15
1K_0402_1% ENABLE SRN
28 ACSEL BATP 12
PR26 ALARM 19 ALARM BATDRV# 24 BATT
1 2 2 SRSET
191K_0402_1% 3 18 PR28
PL5

5
6
7
8
<36,44> CHGCTRL ACSET VS
+3VL 2 PR27 1 27 ACPRES VHSP 20 0.015_2512_1%
100K_0402_5% 13 LX_CHG 1 2 1 2
BQ24703VREF IBAT

10U_1206_25V6M
133K_0402_1%
1U_0603_6.3V6M

4 VREF BATSET 6
2

100K_0402_1%

4.7U_1206_25V6K
1 8.2UH_MPL73-8R2_4A_20% 1
BATDEP
1

1
PC18

PR29

7 COMP GND 17

1
PGND

3K_0402_1%

3K_0402_1%
PR30

PC19

PC20
10 NC1 NC4 23

1
11 14
2

2
NC2 NC3 2

PR31

PR32
1

4.7U_0805_6.3V6K

PD8
2

29
BQ24703_QFN28 SKS30-04AT_TSMA

2
1

PC22

2
80.6K_0402_1%

PC21
1

1 2
2
1
1U_0603_6.3V6M
PC23

PR33

SE_CHG+
ACDET 0.1U_0402_16V7K
SE_CHG- CV=12.6V(6 CELLS LI-ION)
2

P2
PR34 16.8V(8 CELL LI-ION)
2

+3VL +3VL
150P_0402_50V8J

1 2 PR35
3 150_0402_1%
CC=3A for 2.4AHr 3
1
100K_0603_1%

PC24

330K_0402_5%
BATT CC=3.57A for 2.55AHr
4.7U_0805_10V6K
1 2
1

1
10K_0402_1%

VL
PR36

PR37

PC25
0.1U_0402_10V6K
PC26
2

1
2

AC detector PR39 PR38

Icharger=3A
2

2
8

2.15K_0402_1% PU3A PU4 866_0603_1%

High 11.689V SN74LVC1G17DBVR_SOT23-5
1 2 3 CELLSEL# =0,Vcharger= 12.6V
P

+ BATT
Low 9.879V 1 2 O 4 ADP_PRES <28,36,44,45,50>

12
O I
1

12.4K_0603_1%

2 - NC 1 CELLSEL# =1,Vcharger= 16.8V

G

G
PR40

PR41
1

LM393M_SO8 100K_0603_0.1%
4

+3VL PR42
174K_0603_1%
2

2
1

PR43
2

1
+3VL
4.7K_0402_5%
1

PR46 PR44
1

PR45 1 2 PR47 7.68K_0603_0.5%

2
1

130K_0402_1% 1M_0402_5% 1 2 ALARM <44> PR48

PC27 100K_0402_5% 25.5K_0402_1%

1 2
@0.1U_0402_16V7K
2

2
8

100P_0402_50V8J

PU3B PQ9
2

1
BQ24703VREF PR53 D PQ8
5
P

+
1

D RHU002N06_SOT323
7 AC_CHG <44> 2.8K_0603_0.5% 2 RHU002N06_SOT323
2

O
1
10K_0603_1%

6 2 G
-
1

1
@47K_0402_1%
0.022U_0402_16V7K

PR49 G S
1 2

3
PR51

PC28

LM393M_SO8 100_0402_5% S
4

3
1
PR50

PC29

PR52
VL 10K_0402_1%
2

PR54 PR266
2

4 4

1 2 39.2_0402_1%
1

PQ10 D PQ11 D
2

33K_0402_1% AC_CHG 2 2
G G RHU002N06_SOT323 CELLSEL# <44>
PU5 S S
3

1.24VREF RHU002N06_SOT323
4 REF CATHODE 3

Airline detector NC 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2005/03/10 2006/03/10 Title
High 17.521V 5 1
Issued Date Deciphered Date
Low 16.871V ANODE NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
LMV431ACM5X_SOT23-5 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 43 of 54
A B C D
 A B C D

+3VL

@0.1U_0402_10V6K
1
PC30
1 1

BATT_A

2
5
PU6 PD9
BATT_B PQ12

5
+3VL PU7 1 2

P
INB RHU002N06_SOT323
1 4 1

P
<43> ALARM INB O PR55 PR56
O 4 2 INA 3

G
47K_0402_5%
BATT_IN

S
2 INA 1 2 1 3 1 2

2
PR57
74LVC1G02_04_SOT353 RB715F_SOT323 100_0402_5% 0_0402_5%

0.1U_0603_50V4Z
74LVC1G02_04_SOT353 PD10

3
PQ13
1SS355_SOD323

G
2
RHU002N06_SOT323 PR58
PC31

1
PC32
1.5M_0402_5%

1
S

D
BATSELB_A 1 2 3 1

1
2
1000P_0402_50V7K PQ14 PD11
2

D RHU002N06_SOT323 +3VL
22K_0402_5%

G
2
PR59

2 RLZ6.2C_LL34
G +3VL

2
S
3
1

1
PU8

NC
2 A Y 4
PQ15

G
PC33
1

RHU002N06_SOT323 D SN74LVC1G14DCKR_SC70-5 BATT

3
BATSELB_A# 1 2 2 1
G D
2

22K_0402_5%

1000P_0402_50V7K S PQ16 2 ADP_PRES <28,36,43,45,50>

3

RHU002N06_SOT323 G
PR60

2
S 2
3

1
1

PMBT2222_SOT23
PR61
PQ17
470K_0402_5%

1
RHU002N06_SOT323 D
+3VL +3VL BATT_IN 2

1
C G

2
PQ18
2 S

3
B PR62

10K_0402_5%
E 470K_0402_5%

3
1
PQ19

PR63
PD12

1
RHU002N06_SOT323 D

1
CFET_A 1 2 2
G PR64

2
5

PU9 PU10 S 4.7K_0402_5%

PD13

3
1SS355_SOD323

5
P

NC

PR65

1
BATSELB_A# BATSELB_A PQ20 D
2 4 1 1 2

P
<36> BATSELB_A#

2
A Y IN1
O 4 1 2 2
G

2 G RHU002N06_SOT323
IN2 SKS30-04AT_TSMA

G
SN74LVC1G14DCKR_SC70-5 S
3

3
10K_0402_5%

4
3

1
D
220P_0402_50V7K

SN74AHC1G08DCKR_SC70 PQ23 5 5
BATT_IN 2 3 6 6 3 PR66 BATT_A
1

PC34

G 2 7 7 2 470K_0402_5%
S 1 8 8 1

3
RHU002N06_SOT323 BATT
2

2
PQ21 PQ22
AO4407_SO8 AO4407_SO8
+3VL PQ24 PQ25
3
+3VL AO4407_SO8 AO4407_SO8 3

1
1 8 8 1
5

36,43> CHGCTRL SN74LVC1G17DBVR_SOT23-5 2 7 7 2 PR67

PD14

1
PU11 3 6 6 3 470K_0402_5%
P

PMBT2222_SOT23
0.22U_0402_10V4Z

2 1 2 PR68
I O 4 5 5
2
220K_0402_5%

470K_0402_5%
NC 1

2
2

2
470K_0402_5%

BATT_B

4
1SS355_SOD323
1

470K_0402_5%
PC35

PR70

PR69
3

PR72
PR71 PU12 C
PD15
5

PQ26
10K_0402_1% 2
2

PQ27

1
10K_0402_5%
1 B 1 2
P
1

RHU002N06_SOT323 IN1 E PR73

<43> AC_CHG 4

1
O

1
PR74
BATSELB_A# 2 4.7K_0402_5%
IN2 PD16 SKS30-04AT_TSMA
G
S

3 1
1 2
3

2
+3VL SN74AHC1G08DCKR_SC70
G
2

1 2
ADP_PRES 1SS355_SOD323 PQ29
PR75

1
PQ28 D RHU002N06_SOT323 D
1

1 2 2 2
PR76 G RHU002N06_SOT323 G
+3VL 10K_0402_5% S S
100K_0402_5% 3

3
<50> CFET_B
2

<43> CELLSEL# CELLSEL# CFET_B

RHU002N06_SOT323

PQ30
+3VL +3VL
PQ31
1

1
PQ32 D RHU002N06_SOT323 D
1

I_A# D BATT_IN 2
2
5

PD17 G BATT_IN 2 G
1

CFET_A 2 PU13 S G RHU002N06_SOT323 S

P

3
1

1 2 4 PR264 S
3

CFET_B I O BATCON <36> PR263 330K_0402_5%

3 NC 1
G

4 4
330K_0402_5%
1

100K_0402_5%

RB715F_SOT323 SN74LVC1G17DBVR_SOT23-5
3

2
PR77

CFET_B
2

I_A <50>
<42> AB/I_A PR262
2

PQ75 D PQ76 D
1 2 2 2
G G Security Classification Compal Secret Data Compal Electronics, Inc.
S S Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
3

330K_0402_5% RHU002N06_SOT323 RHU002N06_SOT323

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Battery selector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2005.8.26 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 44 of 54
A B C D
 A B C D E

+3.3V/+5V

B+

1 1
2

PL6
FBM-L18-453215-900LMA90T_1812 PC36 PC37
0.1U_0603_50V4Z 0.1U_0603_50V4Z

2
1 2 BST5B BST3B 1 2
B++
1

PD18
CHP202U_SC70
2200P_0402_50V7K

10U_1206_25V6M VL

1
1 PR78
1

2
PQ34 0_0402_5%
B++
PC38

PC39

1 8 5HG 1 2 DH5 PR79 B++

D2 G2

47_0402_5%
2 7 0_0402_5% PQ35
2

D2 D1/S2/K

1
2

2200P_0402_50V7K
3 G1 D1/S2/K 6 1 D2 G2 8

PR80

4.7U_1206_25V6K
4 5 PR81 PC40 2 7

1
S1/A D1/S2/K 4.7_1206_5% 0.1U_0603_16V7K D2 D1/S2/K
3 6

2
G1 D1/S2/K

1
4 5

1
S1/A D1/S2/K

PC41

PC42
AO4916_SO8

2
1

4.7U_1206_25V6K
LX5 AO4916_SO8

2
PC43

0.1U_0603_50V4Z
VL PR82

2
<50> LX_5V 0_0402_5%
10UH_D104C-919AS-100M_20%

2VREF_1999
1

4.7U_0805_10V4Z
3HG

1
499K_0402_1% 200K_0402_1%

499K_0402_1% 200K_0402_1%
PL7

1U_0805_16V7K
1

2
PC44

PR83

PR84
1

1
BST3A

PC45

PC46
DL5 LX3

2
2 PR85 2
2

2
0_0402_5%

2 1

2 1
18

20

13

17

PR86
BST5A 14

TON

VCC
LD05

V+

1
BST5

PR87
ILIM3 5
16 DL3
DH5

1
+5VALWP

1
15 PL8
LX5 PU14
19 DL5 ILIM5 11 4.7UH_SIQB745-4R7_3A_30%
21 OUT5 MAX1999EEI_QSOP28
9 FB5 BST3 28
10.2K_0402_1%

1 26 DH3

2
N.C. DH3
2

B++ 24
DL3
PR88

6 SHDN# LX3 27
150U_B2_6.3VM

1 4 ON5 OUT3 22
1
47K_0402_5%

2VREF_1999 1 2 3
+ ON3
PC47

PR89 7
1

FB3
PR90

1 2 0_0402_5% 12 2 +3VALWP
@ @ 0_0402_5% SKIP# PGOOD
2 2VREF_19998

0_0402_5% @ 3.57K_0402_1%
PRO#
LDO3
PR91

GND
2

REF
2

2
0_0402_5%

PR93

150U_B2_6.3VM
PR92

PR94
1 2 1
1

0_0402_5%

23

25

10

PC49
+

0.22U_0603_10V7K
PC48
0.1U_0603_25V7K
1

2 1
1
MAINPWON

PC50

2
2

1
PR95 100K_0402_5%

PR96
0_0402_5%

4.7U_0805_10V4Z
VL PR242

+3VLP +3VALWP

1
1

1
3 3

2
PC51
PR97 +3VL

2
499K_0402_1%
2

+3VLP
1

+3VL
PR98 PJP1
100K_0402_5% 2 1
1

PAD-OPEN 2x2m
2

PC52
1

0.1U_0603_16V7K D
2

PQ36 2
RHU002N06_SOT323 G
S RHU002N06_SOT323
3

D PQ37
2
G KBC_PWR_ON <36>
S
3

RHU002N06_SOT323
1

D PQ77
2
G ADP_PRES <28,36,43,44,50>
S
3

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
3.3V / 5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-2541 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 45 of 54
A B C D E
 A B C D

PL9
MAX8743_B+ FBM-L11-322513-151LMAT_1210

10U_1206_25V6M
2 1 B+
1

1
2200P_0402_50V7K
+5VALW

PC53

PC54

2
PR99

2
2 0_0402_5%
1 1

1
1U_0805_50V4Z

2200P_0402_50V7K

4.7U_1206_25V6K
PC56

1
PD19

1
PC55

1
4.7U_1206_16V4Z

1
PR100

2
8
7
6
5

PC57

PC58
20_0603_5%
PQ38 CHP202U_SC70

D
D
D
D

2
AO4422_SO8

2
BST_1.05V_2
BST_1.5V_2 AO4916_SO8

G
S
S
S
1 D2 G2 8
1 2 BST_1.05V_1 2 7

1
2
3
4
PL10 PC59 D2 D1/S2/K
3 G1 D1/S2/K 6

0.1U_0603_50V4Z
3.3UH_MPL73-3R3_6A_20% 0.1U_0603_50V4Z PR101 VCC_MAX8743 4 5
S1/A D1/S2/K

V+ 1U_0805_16V7K
0_0402_5% +1.5VSP
+1.05V_VCCP

1
2 1 2 1 PR102 PC62 PL11
PQ39

PC60

PC61
0_0402_5% 0.1U_0603_50V4Z 3.3UH_SIQB74-3R3RF_4.8A_30%
220U_B2_2.5VM

1 1 2 2 1 1 2

2
8
7
6
5
2.2U_0603_6.3V6K

BST_1.5V_1
1

220U_B2_2.5VM
PC63

PR104

22
1
D
D
D
D

9
PC64

PQ40 DH_1.05V_2 1 2 PU15 0_0402_5%

5.1K_0402_1%

PC66
AO4702_SO8 25 21 1 2 DH_1.5V_2 +

UVP
VCC
2

BST1 VDD

1
2 PR103
1

G
S
S
S
5.1K_0402_1%

PR105
2.2_0402_5% DH_1.05V_1 26 19
DH1 BST2 2
PR106

18 DH_1.5V_1
1
2
3
4
LX_1.05V DH2 LX_1.5V
27 LX1 LX2 17
DL_1.05V 24 20 DL_1.5V

2
DL1 DL2
2
16 2
2

CS2
28 CS1
1 OUT1 OUT2 15
FB2 14
2 FB1 ON2 12
PR109
1

PR110 7 @0_0402_5%
PGOOD

10K_0402_1%
PR107 @0_0402_5% 5 2 1 2 1 SLP_S3#
TON VCCP_POK <40>

PR111
100K_0402_1% SLP_S3# 1 2 11 PR108
ON1 0_0402_5%
ILIM2 13
3

SKIP
GND
OVP
2

REF
ILIM1

2
PR112
MAX8743EEI_QSOP28 PR113 100K_0402_5%

23

10
0_0402_5% 2 1
2 1
2VREF PR115

1
D 47K_0402_5%
2 1

100K_0402_1%
2 2 1 +5VALW

1
PR119 VCC_MAX8743 2 1 PR114 G

PR118
100K_0402_5% @0_0402_5% 0_0402_5% S

3
1
2 1 PR117 PQ41

1
D

0.22U_0603_10V7K
PR116 100K_0402_1% RHU002N06_SOT323

PC69
2 2 1

2
PR122 PR120 G PR121 SLP_S3# <26,28,30,31,32,36,38,39,47,48>

2
1

@0.001U_0402_50V7M
47K_0402_5% 0_0402_5% PQ42 S 0_0402_5%

3
+5VALW 1 2 2 Fine tune power sequenceRHU002N06_SOT323
G

PC70
S
3

PQ43
1

D RHU002N06_SOT323 +3VALW

2
<26,28,30,31,32,36,38,39,47,48> SLP_S3# 1 2 2
3 PR123 G 3

1
@0.001U_0402_50V7M

0_0402_5% S PQ44
3

RHU002N06_SOT323 PJP11
PAD-OPEN 2x2m
1.5VSP/ +1.05V_VCCP/+2.5VALWP
1

PC71

+2.5VSP
2

2
PU26

1
2 VIN VO 3
PC134
10U_1206_6.3V6M 1 4 PR244

2
EN ADJ 13K_0603_1%

1
5 7

2
GND GND PC135
6 8 10U_1206_6.3V6M

2
GND GND

1
PR243
G965-18P1U_SO8
10K_0402_5% PR245
PJP2 PJP3 12K_0402_1%
<26,28,30,31,32,36,38,39,47,48> SLP_S3# 1 2
+1.5VSP 1 2 +1.5VS +5VALWP 1 2 +5VALW

2
(4A,160mils ,Via NO.=8) (4.5A,180mils ,Via NO.= 9)
PAD-OPEN 3x3m
PAD-OPEN 4x4m
PJP5
(7A,280mils ,Via NO.= 14) +3VALWP 1 2 +3VALW
(3A,120mils ,Via NO.= 6)
PAD-OPEN 4x4m
PJP6
PAD-OPEN 4x4m
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.= 12)
4 4

PJP8 PJP9
+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4) +2.5VSP 2 1 +2.5VS (1A,40mils ,Via NO.= 2)
PAD-OPEN 2x2m
PAD-OPEN 3x3m

PJP10
PAD-OPEN 4x4m Security Classification Compal Secret Data Compal Electronics, Inc.
+VDD_COREP 1 2 VDD_CORE (7A,280mils ,Via NO.= 14) Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5VALW/1.5VS/1.05VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 46 of 54
A B C D
 5 4 3 2 1

D D

DDR_B+ PL12
FBM-L11-322513-151LMAT_1210
+1.5VS 2 1 B+

2200P_0402_50V7K
1

1
1

0_1206_5%

PC72
PC73

5
6
7
8
10U_1206_25V6M

PR124

2
PQ45 2

D
D
D
D
AO4422_SO8
PR125 PC74

2
0_0402_5% 0.1U_0603_50V4Z

12
7

G
S
S
S
PU17 BST_1.8V_1
1 2 BST_1.8V_2 1 2
PR126

NC

NC

4
3
2
1
0_0402_5%

10U_0805_10V4Z
1

PC76
PC75 23 22 DH_1.8V_1
1 2 DH_1.8V_2 +1.8V
10U_0805_10V4Z VLDOIN VBST 2.2UH_IHLP-2525CZ-01_8A_+-20%_2525CZ
2

24 21 LX_1.8V 1 2
VTT DRVH
C
+0.9VP PL13 1
C

5
6
7
8
1 VTTGND LL 20
DL_1.8V + PC78

D
D
D
D
PQ46 330U_D2E_2.5VM_R15
1

2 19 AO4702_SO8
PC79 VTTSNS DRVL 2

G
S
S
S
22U_1206_6.3V6M
2

3 18

4
3
2
1
GND PGND

22P_0402_50V8J
PR127
0_0402_5%

0.001U_0402_50V7M

1
20K_0603_1%
1 2 4 MODE CS 16

1
<7,13,14> V_DDR_MCH_REF

PC80
0.033U_0402_16V7K

14K_0402_1%
1

PC83

PR129
PR128
PC81

5 14

2
VTTREF V5FILT

4.7U_0805_10V6K
2

2
1

2
PC82
6 TPS51116RGE_QFN24 13 PR130
COMP PGOOD 3_0402_5%

2
2 1 +5VALWP
8 11 PR131
+5VALW VDDQSNS S5 0_0402_5%

Thermal pad
2 1
SLP_S5# <26,39>
CS_GND
9 10 PR132
VDDQSET S3 @ 0_0402_5%
B

V5IN
B
2 1
PR133 SLP_S4# <26>
0_0402_5%
17

25

15
2 1
SLP_S3# <26,28,30,31,32,36,38,39,46,48>
PR134
2 1
@0_0402_5% SLP_S5# <26,39>

@0.001U_0402_50V7M

@0.001U_0402_50V7M
1

1
PC84

PC85
2 10K_0402_1%
PR135

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V/0.9VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 47 of 54
5 4 3 2 1
 5 4 3 2 1

B+_6269

PL18
D FBM-L11-322513-151LMAT_1210 D

B+ 2 1

10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_50V4Z
+6269_VCC
1

PC89
PC86

PC87
PR136

1
1 2 1 2 PC90

2
2 PR137 0_0402_5% 0.1U_0402_16V7K
10K_0402_5%

+5VS

1
PR138

5
6
7
8
@0_0402_5%

16

15

14

13
PU28 PQ47

D
D
D
D
17 1 PR139 2 AO4422_SO8

PHASE
PGOOD

UG

BOOT
+6269_VCC

2
GND 2.2_0603_5%

G
S
S
S
1 VIN PVCC 12 1 2 PC91
+6269_VCC

4
3
2
1
2.2U_0603_6.3V6K UG

2 11 1.0UH_IHLP-2525CZ-01_11A_+-20%_2525CZ
VCC LG

1
PR140 LX6269 1 2 +VDD_COREP
PC92 0_0402_5%
2.2U_0603_6.3V6K

0.1U_0402_10V7K
1 2 3 10 PL14

2
FCCM PGND

5
6
7
8

220U_B2_2.5VM

220U_B2_2.5VM
1 1 1
PQ48

D
D
D
D
PR249

PC142
+

PC137
+

PC93
C PR141 C
AO4702_SO8
1 2 4 9 1 2
<26,28,30,31,32,36,38,39,46,47> SLP_S3# EN ISEN 11.5K_0402_1% 2

COMP

G
2 2

S
S
S
TEST
0_0402_5%
1

VO
FB

4
3
2
1
PC136
@0.1U_0402_16V7K LG
2

8
ISL6269CRZ-T_QFN16

49.9K_0402_1%
1

1
22P_0402_50V8J
1

1
57.6K_0402_1%
PC95

PR142

PR143
PC96
0.01U_0402_16V7K

2
2

2
1
PC97
6800P_0402_25V7K
2
PR144
1 2

4.12K_0402_1%

+5VALW
B B

1
+5VS
PC139
PCIE_1.2V 1U_0603_6.3V6M

2
PR145 +1.5VS
1

1
1 2
PR246 PR6
100K_0402_1% 1K_0402_1%
49.9K_0402_1%

6
PU27
1

1
5

VCNTL
2

2
PR147 VIN PC138
7 POK
1

PQ49 D 7.15K_0603_1% 10U_1206_6.3V6M

9

2
VIN
2
PR146 G 3
2

VOUT
1

10K_0402_5% PQ66 D
S
3

<19> POW_SW 1 2 2 RHU002N06_SOT323

<26,28,30,31,32,36,38,39,46,47> SLP_S3# 8 EN VOUT 4 PCIE_1.2V
G

GND

1
S 2
3

RHU002N06_SOT323 FB PC141
APL5912-KAC-TRL_SO8 22U_1206_6.3V6M

2
1

1
PR247
1K_0402_1% PC140

2
0.01U_0402_16V7K

2
2005.08.30

POW_SW VDD_CORE

1
High 0.95V PR248
A Low 1V 2K_0402_1% A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VDD_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 48 of 54
5 4 3 2 1
 8 7 6 5 4 3 2 1

+CPU_B+ PL15
FBM-L18-453215-900LMA90T_1812
1 2 B+

68U_25V_M
2200P_0402_50V7K

4.7U_1206_25V6K
0.01U_0402_50V4Z
H 1 H

PC148
10U_1206_25V6M
+
1

1
PC100

PC103
PQ50

PC101

PC102
5
SI7840DP_SO8 2

2
2

+CPU_B+
PR148
+5VS 0_0402_5% 4
2 1

BST_CPU1_2
BST_CPU1_1
2

1U_0603_10V6K
PR149

3
2
1
1
PC104
10_0603_5%

PC105

0.01U_0402_25V7K

2
PU18 0.22U_0603_16V7K
G 5 1 1 2 PL16 G
VCC BOOT
6 8 DH_CPU1 .36UH_MPC1040LR36_ 24A_20%
FCCM UGATE

1
PC106
2 7 LX_CPU1 1 2 +VCC_CORE
PWM PHASE

2
3 4

2
GND LGATE

D 8
D 7
D 6
D 5

8
7
6
5
PR150

FDS6676AS_SO8

FDS6676AS_SO8
ISL6208CRZ-T_QFN8 10_0402_1%

D
D
D
D
+5VS

PQ52

PQ53
PR151 PC107
10K_0402_1% 0.22U_0603_16V7K

1
+3VS

10_0603_5%
1 2 2 1

4 G

G
1 S
2 S
3 S

S
S
S
1
2
3
4

2
PR152
PR153
1 5.11K_0402_1% 2 PR154 1

2
1U_0603_10V6K

@0_0402_5%

1
1

F PR155 F
PC108

1.91K_0603_1% VSUM VO
2

DL_CPU1

1
1 2
PR156 VGATE_INTEL<7,26> +CPU_B+
0_0402_5%
PC109 +5VS
2 1 NTC 19
VGATE
20

18

39

40

2200P_0402_50V7K
0.01U_0402_16V7K ISL6260CRZ-T_QFN40 PR157

4.7U_1206_25V6K
0.01U_0402_50V4Z
0_0402_5% PQ54
VSS

3V3
VDD

VIN

PGOOD
PR158 2 1 SI7840DP_SO8 1

1
PC110
1U_0603_10V6K
0_0402_5%

BST_CPU2_2
BST_CPU2_1

PC111

PC112
2 1 4 PC113
<4> H_PROCHOT# VR_TT#

1
10U_1206_25V6M

PC114
4

2
PR159 1 PWM1 2
2 3 RBIAS PWM1 27
147K_0402_1% PH2

2
E E
2 PR160 1 2 1 NTC 5
4.22K_0603_1% PC115 NTC PC116

3
2
1
2 1 470KB_0402_5%_ERTJ0EV474J 6 23 ISEN1 PU20 0.22U_0603_16V7K
SOFT ISEN1 PL17
5 VCC BOOT 1 1 2
0.015U_0402_16V7K PU19
2 PR1611 28 6 8 DH_CPU2 .36UH_MPC1040LR36_ 24A_20%
<5> CPU_VID0 VID0 FCCM UGATE
<5> CPU_VID1 2 PR162 1 0_0402_5% 29 VID1
0_0402_5% 2 PR163 1 30 26 PWM2 2 7 LX_CPU2 1 2 +VCC_CORE
<5> CPU_VID2 VID2 PWM2 PWM PHASE
<5> CPU_VID3 2 PR164 1 0_0402_5% 31 VID3

2
0_0402_5% 2 PR165 1 32 3 4
<5> CPU_VID4 VID4 GND LGATE

D 8
D 7
D 6
D 5

8
7
6
5
2 PR166 1 0_0402_5% PR167

FDS6676AS_SO8
<5> CPU_VID5 33 VID5
0_0402_5% 2 PR168 1 ISEN2 ISL6208CRZ-T_QFN8

FDS6676AS_SO8
34 22 10_0402_1%

D
D
D
D
<5> CPU_VID6 VID6 ISEN2

PQ56

PQ57
0_0402_5% PR170 PC117
2 PR169 1 37 10K_0402_1% 0.22U_0603_16V7K

1
<4,25> H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1

4 G

G
1 S
2 S
3 S

S
S
S
2 PR171 1 36 41
<7,26> DPRSLPVR DPRSLPVR CS_GND

1
2
3
4

2
2 PR172 1 499_0402_1% 1
D
<5> H_PSI# 0_0402_5% PSI# PR173 D
2 PR174 1 2 24 5.11K_0402_1% 2 PR175 1
<40> PGD_IN 0_0402_5% PGD_IN FCCM
2 PR176 1 38 PR177 @0_0402_5%

1
<15,40> CLK_ENABLE# 0_0402_5% CLK_EN#
2 1 +5VS
<21,36,39,40,50> PWR_GD 2 PR178 1 35 0_0402_5% VSUM VO
0_0402_5% VR_ON
12 25 DL_CPU2
<5> VCCSENSE VSEN PWM3
13 RTN
+VCC_CORE 2 1
PR179 PC118 21
10_0402_1% ISEN3
2 1 11 VDIFF
PR180 PC119
10_0402_1% 1000P_0402_50V7K 2 1
2 1 10 FB
1000P_0402_50V7K PR181
OCSET 7 2 1
9 11.5K_0402_1%
C <5> VSSSENSE COMP C
PR182 PC120 17 VSUM
VSUM
3K_0402_1%

180_0603_1% 1800P_0402_50V7K PR183 8 VW

1
1000P_0402_50V7K

2 1 1 2 2 1
PR185
DROOP

2 PR184 1 0_0402_5%
1.2K_0402_1%
DFB

1
VO

0.22U_0603_16V7K

PC122
4.53K_0402_1%

2
2
PR186

PC123

1 2 2 PR187 1
14

15

16

51K_0603_1%
1

PC124 PC121
2

1 2 0.022U_0402_16V7K
0.1U_0402_16V7K

220P_0402_25V8K PC125 VO
10KB_0603_5%_ERTJ1VR103J

2 1

1000P_0402_50V7K
1
PC126

PR188
2 1
1

B B
@1K_0402_1%

6.98K_0402_1% PR190 PR191

2

PH3

6.19K_0603_1% 1K_0402_1%
PR189

2 1 2 1
2

PC127
2 1

330P_0402_50V7K

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 49 of 54
8 7 6 5 4 3 2 1
 5 4 3 2 1

PQ72 +5VS
+5VS PD20 NDS0610_SOT23
+3VS CH751H-40_SOD323

S
1 2 1 2 1 3

1
+5VS
PR259 PD21
PR193

1
PU22A 1M_0402_1% CH751H-40_SOD323

G
2
8

1U_0805_16V7K
PR194 PR192 1 2

PC128
3 330K_0402_5% PR256 133K_0402_1%

P
D D

2
+ 100K_0402_5% PR257
1 0 2 1
P4

220K_0402_5%
2 10K_0402_5%

2
-
G

220K_0402_5%
PU22B PU21B PU21A 10K_0402_5%
PR197

2
2

0_0402_5%

0_0402_5%
LM358A_SO8 5 3

P
4

2
+ +

1
PR196

PR195
1 2 5 + O 7 O 1

PR251

PR252
6.81K_0402_1% 7 6 2
0 - -

G
1 2 1 2 6 PR208

2
PR199 PR200 - LM393M_SO8 LM393M_SO8 10_0402_5%
1

4
10K_0402_1% 100K_0603_0.5% PR201

2
1
2K_0402_5%
LM358A_SO8 1 2

2
PR202
0_0402_5% 1 2

80.6K_0402_1%
1U_0805_50V4Z

PR203
PQ70
1

PC130

0.027U_0402_16V7K
1 2 604K_0603_1% LX_5V <45>

MMBT3906_SOT23
DTA144EUA_SC70

PR205
2
PC129 VIN
2

1
PQ58
39.2K_0402_1%

PC131
0.22U_0603_16V7K

2
3
7.87K_0402_1%
E
3 1

2
B
2

2
PR206

PR260
PR207 PD28

47K
C
3.9K_0402_5% 1SS355_SOD323

47K
1
PU23

3 2

1 2

1
S PD22
4 3 @CH751H-40_SOD323
REF CATHODE

1
G
2 1 2 PR254
PR211

422_0603_1%
PR210
2 PWR_GD <21,36,39,40,49> 150K_0402_5% PR253
NC

NDS0610_SOT23

1SS355_SOD323
0.1U_0402_16V7K

D 1 2 OCP# <4,26> 210K_0402_1%

1
1

2
PQ73
PC132

5 1 0_0402_5%

2 2
ANODE NC

PD24
C C

2
2

1
LMV431ACM5X_SOT23-5 D

470K_0402_5%
2 PQ60 PD27 ADP_SIGNAL

1
G 1SS355_SOD323 +3VS
RHU002N06_SOT323

PR215
S PR255 PD26

1
1
1

1
PR261 <38> ACOCP_EN# PQ71 D

RHU002N06_SOT323
1 2 1 2

1
PR212 1M_0402_1% 2
0_0402_5% PQ61 G
B+ ADP_PRES
1
<28,36,43,44,45>
C MMBT3904_SOT323 1K_0402_5% 1SS355_SOD323
S

1 2

3
2
2

B I_A D
<44>
PR217 E 2 PQ74
3

47.5K_0402_1% G RHU002N06_SOT323 ADP_PRES <28,36,43,44,45>

1 2 S

3
CFET_B <44>

1
PR265
PQ62 2005.8.24 47K_0402_5%
NDS0610_SOT23
ADP_SIGNAL PD25

2
3900P_0402_50V7K
3.9K_0402_5%
S

3 1 2 1

1
1

PR214
VIN 1SS355_SOD323

PC147
G
2
1

VIN
1

PR223 +3VL 2

1
137K_0402_1% PR224 +3VS
B 22.6K_0402_1% B

1
PC146
2

2
8

PU25A 1U_0603_10V6K PC133

2

1
0.1U_0603_16V7K PR219 +5VS
3
P

PR216

2
+ PR221 1M_0402_5% PR218
O 1
2 10K_0402_5% 2 1 1 2 10K_0402_5%
-
1

PR236 LM393M_SO8 PR220

4

2
470K_0402_5%

8
10K_0402_1% 10K_0402_5% PU24A
+3VS
1 2 3

P
ADP_ID <36> ACN <43> + ADP_PS0 <36>
1
2

PR229 O
2 -

G
1M_0402_5%
1 2 PR222 LM393M_SO8

4
<43> SRSET 71.5K_0402_1% +3VS

2
1

VIN PR238 PR225

2
PR235 1M_0402_5% @100K_0402_5% PR226 +5VS

1
10K_0402_1% VIN 1M_0402_5%
1 2
1

1
1 2
1

PR258 PR228 PR227

2

29.4K_0402_1% PU25B 21K_0603_1% PR232 10K_0402_5%

1

8
5 PR230 21K_0603_1% PU24B
P

2
+ 47K_0402_5%
7 1 2 5

P
2

1 2
O PR231 PR233 +
6 - O 7
1

D 220K_0402_5% 100K_0402_5% C
ADP_EN <36> 6 ADP_PS1 <36>
2

G
47K_0402_5%

2 LM393M_SO8 1 2 2 PQ63 PR234

4

2
1

G B MMBT3904_SOT323 3.48K_0402_1% LM393M_SO8

4
1

D
0_0402_5%

PR237

S PQ65 E
3

A A
1
PR240

@RHU002N06_SOT323 2 PQ64

2
PR241 G RHU002N06_SOT323
1

220K_0402_5%

10K_0402_1% S
2

PD23
2

PR239
2

1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

1SS355_SOD323 Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
ADP_EN# <43> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
2005.8.20 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 50 of 54
5 4 3 2 1
 1 2 3 4 5

06/11/2005 06/24/2005
EE PIR list
Page28: 1.Delete R15 ,due to Internal PD Page19 : Add LVDS L-shape BOM option resistors
2.Delete R69 ,due to Internal PD
06/01/2005 schematics review start : 3. Add U70,U71,R69,R92 R1297 for serial falsh support.
Page10 : Enable TV/ CRT when using 945PM
06/02/2005 Page9 : Enable TV/ CRT when using 945PM
Page38 : Add R58,R59,R60 ,those are removed from daughter board Page19 : Add T8/T9 for GPIO10/14 06/25/2005
Page39 : JP18 pin3 change from ground to BT_LED Page23 : Change L1,L2,L63,L6,L7,L9,L11-16,L65,L66 to FB Page33 : Delete U58, R165,C568,C1,C312,C311 FOR LAYOUT SPACE
Page37 : Remove JP16 & change debug port interface to JP44 Page30 : Disconnect the I2C bus / WL_LED#/WP_LED# on JP46 06/27/2005
1
Page27 : ICH7M pin R7 change to +3VS Page10 : 1. Add R504/R505 for VCC_SYNC Change All 2N7002_SOT23 to RHU002N06_SOT323 to save layout space 1

Page32 : JP44 PLT_RST# change to PLT_RST_B# to reduce the loading 2. Add R490/R491 for VCCTX_LVDS
3. Add R494 for VCCA_CRTDAC 06/28/2005
Page33 : Update audio amp to MAX9710 4. Add R492/R493 for VCCA_LVDS Page40 : Change Q10,Q11,Q15,Q26 from SOT23 to SOT323
5. Add R495 for +3VS_TVBG to save layout space
06/03/2005 Page37 : 1 . Update JP20 to 6 pin connector
Page10 : Add R260 to reduce one 330U cap C666 6. Add R500 for +3VS_TVDACA
7. Add R502 for +1,5VS_TVDAC 2. Update JP20 & JP18 pin assignments to follow Taos
Page25 : 1. R27 change to +3VS 7. Add R499 for +3VS_TVDACB
2..Add R1035 for H_DPSLP# 8. Add R496 for +3VS_TVDACC 06/30/2005
Page28 : Y1 update to smaller package 6x3.5
Page26 : 1.Add T80 for GPIO25 Page09 : 1.Add R460,R461, R550,R552,R553 for CRT discrete/uma option
2. GPIO21 change net name to VGARST# 2. Add R462,R463,R464 for TV discrete/uma option Page25 : Y4 update to smaller package 14M-J
3. Add T88 for GPIO23 Page15 : Y3 update to smaller package 6x3.5
4. Add T89 for GPIO26 06/13/2005
5. GPIO30 change net name to USB_OC#6 07/01/2005
6. GPIO31 change net name to USB_OC#7 Page23 : Add R6 R15,R106,R128,R129 GPIO PD Page23 : Add HW strpping pin on DVPDATA20,21,22,23 for VRAM ID0,1,2,3
7. Add R1036/7 for RESET option Page33 : U57 change to 2A current limit power switch G548
8. Remove the connection of USB_OC#3/4/5 06/14/2005
Page21 : Change L1,L2,L63 to FB
07/04/2005
Page24 : Add ALS_EN on JP35 pin24 for light sensor Page17 : Add R131 for inverter PWM when ATI PWM issue
Page16 : 1. Add C174,C150,C142,C371,C358 for DVI
Page32 : 1.JP13 change to 90 pins connector 2. R103 change to 1% Page19 : 1. Add R49 , R189 for 1.2V voltage divider
2.Add U72 for ESD protection Page35 : U69 pin7 change to PD 2. Add Q12 for M52_therm# & change to GPIO14
2
Page32 : The limitation for 5 pin audio jack can't switch 2

06/04/2005 06/15/2005 headphone/docking line-out ,so add R1420,R1421,C526,R252

Page10 : A. U71 change to U43D (the fourth gate in U43) Page04 : R1265 change to 51_0402_5% & install Delete R256,R255,C536.
B. Add +3VS_TVBG R/C filters & voltage follower D12,D21,R127,R520 Page07 : Install R1344 Page39 : Delete C984~C988
Page34 : audio change-- add R1419 ,R431,R434,R435 for BIASA/B/C
Page28 : Delete U70 ,reserve U71 for 200 mil Page33 : Delete C527
Page35 : Add JP3 for Smart card FFC connector
Page35 : Delete U61 , resevre U66 for 200 mil Page10 : Delete C823 reserved pad
Page18 : 1.R1365 CHANGE TO 2K_0402_1%
2. R1366 change to 562_0402_1% Page29 : Update U7 symbol pinB7/B8/C8 Page25 : Add JP5 slim type ODD connector
3. R1367 change to 1.47K_0402_1% 06/16/2005 07/12/2005
Page31 : JP4 update to RJ45 connector Page36 : Delete R32 ,double PU Page25 : Add C629,C630,C631 for SATA connector
Page15 :Add the connection for UMA VGA clock , & SRC0/2 SWAP Page41 : Delete R180,Q49 ,the same function for +1.8VS Page33 : Swap JP3 samrt card pin assignment for FFC
1.Add R1148/R1149 , R1129/R1132 , R1118/R1121 Page10 : Delete C982 for Lead-free
2.Add R1242/R1248,R1253/R1272 07/14/2005
Page20 : Add C570 for Lead free Page25 : Add R133 100 ohm to avoid RTC short
Page09 : Change 0 ohm resistors before filters ,
and delete the other group of filtes at page 19 Page32 : 1,Delete Q28 . Page15 : 1. clock gen. pin 5 change to connect to +ck_vdd_dp
Page16 : add R671~R678 ,R530,R531 for DVI 2. D49,D50 change to U73 2. C731,C732,C733 change from 0.1u to 0.01u
3. Add C577,C581 for Lead free 3. C361,C364 change from 33p to 27p
Page19 : Swap I2C bus for LVDS/Thermal sensor
Page33 : Add R163,R164,R165 for USB power switch PU
06/07/2005 Page26 : Separate PCIE_WAKE# to NIC/Mini-card PCIE_WAKE# to avoid battery mode can't enter S3 issue
3
Page47 : PQ34 pin5/6/7 change netname to LX_5V Page23 : Delete L65,C270,C269,C271 for M52-T 3

Page38 : Pin96: INVPWM rename to OUT9 & add T90 Page18~23 : ATI VGA controller change to M52T
07/19/2005
Page36 : Delete R500 & rename to EXPCRD_RST# 06/22/2005 Page39 : Add C91,C93,C181 for low speed signal
Page35 : Add JP3 for Smart card FFC connector Page09 : Add R554 , R555 for CRT disable 07/20/2005
Page10 : 1. Add R508,R510 for VCCD_LVDS1/1/2
2. R504,R505 chnage for +2.5VS_GMCH,&delete R490,R491,R492,R493 Page30 : Add R1422 pad for XMIT_OFF
06/08/2005 Page30 : Delete JP48,49 & change screw holes
Page7 : Delete PD resistor R1340~R1343.
Page17 : Update JP35 LVDS connector
06/23/2005
Page16 : Change SDVOB_INT+/- net name to PEG_RXP1/N1
Page26 : A. GPIO28 ==Delete R1321 & A_SD , change to VGA_RST#
B. GPIO21 ==Change to MB_PWR Page10 : 1.R505 / R510 for M52 , R504 / R508 for UMA
C. GPIO19 ==Change to PD 2. R499,R500,R496 connect to +1.5VS for diable CRT

06/09/2005 Page36: Delete R49 & CB_CLK

Page25: JP42 change to wire to board connector
Page17 : Delete Q56 ,R510 ,Caymus support 3V PWM
Page19: 1.Add CRT,TV filters for M52T
Page25 : Update Q92 to AOS4407 2. Add DVI BOM option 0 ohm
Page26 : Delete R252 Page16 : Move 0 ohm to TV-out connector for TV
Page37 : Add PD RP42,R273 Page38 : Move 0 ohm to docking connector for CRT
4
Delete Cardbus 6612 circuit & move to daughter board LS-2953 4

06/10/2005
Page17 : Add R458,R459 for ch_data,ch_clk
Page33 : Add C367 0.1U for +SC_PWR Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 51 of 54
1 2 3 4 5
 1 2 3 4 5

For DB2 Modification 10/07/2005 For PV Modification

Page28 : Install R275,R289；NI R1396,R1398 01/16/2006
08/11/2005 Page28 : Del Q71,R1345；Install R1395,R1384 Page07 : UI R1201,R1204 for SI2 shut down issue
Page31/32 : Update Audio portion for jack sensing NI R1425,R1385 Page15 : Change R1070,R1072,R1075,R1081,R1093,R1095,
Page29 : Add R1040,R871；Del R1404；Reserve Q106
Page35 : Delete LED circuit & connect to LS-2953 directly R1118,R1121,R1257,R1259,R1144,R1145,R1123
Page28 : Add R1091,R1082,R1088,R1085,Q105,R1023,
Page11 : Change R1154 to NI R1024,D63,C1042,U55,R1021,R1076； R1126,R1113,R1111,R1115,R1143,R1249,R1251
Page30 : Add C554 for UIM power Reserve Q103,Q104,R1090, to 24Ω for CLK GEN vendor's recommand.
1
Page25 : Delete JP37 MB2 conector Del R601. Page30 : Change R996 to SM010014500(220Ω impedance) 1

Page15 : Del R1084,R1136 for improve WLAN performance

Page19 : Change C611 to NI ,R662 to 0 ohm for clcok spectrum
Page15 : Add R1136 PD for clk_pcie_m52 ,R1084 change to NI
10/08/2005
Page28 :Install Q103；NI R1091 02/07/2006
Page24 : R1388 change to Install
Page26 : R1364 change to NI
10/13/2005 Page30 : Modify R996 to 1000ohm/100MHz bead
Page24 :Delete BIOS_SEL jump Modify R996's location to L78
Page36 : R1354 change to NI
Page39 :Delete J33 For power noise impact WLAN performance
08/15/2005 10/26/2005 Page30 : Connect R1363.2 to V_3P3_LAN
Page30 : R1418 , R1360 change to NI Page5 :NI R243 INSTALL R1363, UI R1364
Page32 :NI C526
08/19/2005 Page19 :R11 and R13 change to 499 ohm
For support wake on WLAN from S3.
Page15 : Install R1245 and UI R1247
Page35 : Delete FWH , SPI change to +3VALW Page37 :Install CP1~CP6
Page37 : Change Num_LED# and CAPS_LED#
Page36 :Delete R538 10/31/2005 For LED reverse issue
Page10 : Delete L39 Page06 :NI C933；Modify 330U cap from ESR9 to ESR7.
Page25 : Add D15, D16 , R90 , R88 for HDD LED 11/01/2005 02/13/2006
08/20/2005 Page19 :Change R124,R126,R132 and R178 to 150 ohm. Page35 : Del U61. (150mil SPI ROM)
Page30 : Change +3VL / Caps_LED# to Pin45/51
2

Page38 : Delete R551 ,R548,R549,R541 For SI2 Modification 02/14/2006 2

Page26 : Add R1437

Page25 : Add D15,D16,R88,R90 for HDD_LED 12/06/2005 For HALTLED turn on 100ms when power on.
Page30 : Add SW1 C986, R521 , D65,D66 for SIM power off Page06 :Del C938.
Page15 : Add C355,C356,C357,C358,C368,C369,C371,C372
08/24/2005 Page19 :Change R126,R124,R132,R178 to 100ohm
To improve WWAN performance
Page15 : Add C353~C372 for clk cap Page25 :Del C646
08/25/2005 Page26 :Del R1384,R1385,R1425；Connect LP_EN# to GPIO8 02/20/2006
Page31/32 : Add JP16 for audio cable Page30 :NI R1355 , Install D64 Page21 : Add C143,L21.Change C109 and C112 to 1u cap.
Page30 : Internal MIC signal change to JP13 Page34 :Del U45,U48,R1306,R117,R1307,C33,C993,C87 For PCIE_1.2V power noise.
08/26/2005 Page36 :Change RP43,44 to 10K ohm Page23 : Change C195 to 1U cap.
Page37 :exchange netname between JP18's pin 25 and 24 For PCIE_1.2V power noise.
Page32 : Add R427,R429,C492 for J_MIC_REF
12/13/2005 Page32 : Connect JP24 and JP15's 7 and 8 pin to DGND.
08/29/2005 Page15 :Add C740,C741,C744,C745 for EMI request For ESD concern.
Page32 : Add 1423,R1424 for MIC_REF , & MIC_SENSE connection
Page23 : R154 change to NI
12/14/2005
Page26 :Add Q43 to be a HALT LED inverter.
02/23/2006
Page29 : Add C333 for NIC Page33 : Add D51,D52,D61 for ESD issue.
Page37 :Add R1084 and reserve R1094
08/30/2005
12/16/2005
3

Page15 : Add C373 for clk_debug_port Page28 :Del U71,R69,R92,R1297 footprint

03/02/2006 3

Page21 : Change C143,C116 to 22u for PCIE_1.2V noise

Page23 : Add R173 for Therm_SCI# Page30 :NI R1364,Install R1363
Page23 : Change C190 to 22U for PCIE_1.2V noise
Page36 : R538 change to NI Page37 :Add C749,C750,C751
Page21 : Add C140, C172 , C141 , L17 for VDDPLL Page38 :Add C746,C747,C748 and
change R1404,R1428,R1429 to 0603 size 03/08/2006
08/31/2005
Page32 : Delete R1419, R1420
12/21/2005 Page30 : Change R521 to 1K for SW function error
Page37 :Add D67 for EMI request Page32 : Change R1405 and R1406 to 12.1K
Page19 : R189 change to 56_0402_1%
Connect JP20's pin 1 to +3valws directly
09/07/2005 Page38 :Add D59 For MV1 Modification
Page23 : Add R174 for ATI GPIO5
Page15 :Change C361,C364 to 18pF 03/22/2006
10/06/2005 Page36 :Change C350,C349 to 18pF Page19:Change R189 to 75Ω(Improve clock amplitude)
Page24: NI D64 ,install R1355
Page25 :Change C516,C528 to 15pF Page21:Change C103,C104,C105 to 1U, Add C144
Page07: NI R1202,R1203
Page19 :Change C610,C611 to 18pF Improve DVI signal
Page15: Del R1148,R1149,R1129,R1132
Page07: Add R103,R105,R107,R110.
12/22/2005 Page25:Change Y4 to MC-146 (Original is non LF part)
Page06 :Del C934,install C933 Page28:Change R70 to 1.21KΩ
Page10: Del R1337
Page28: NI R1397,U36；Install Q94；Add R1039
12/27/2005
4
Page07 :Install R1201,R1204 4

Page35: Reserve U61

Page15 :Change R1111,R1115,R1075,R1081 to 22 ohm.
Page36: Install R91
Page30: Add R1383；Reserve R1382
10/07/2005 Security Classification Compal Secret Data Compal Electronics, Inc.
Page30: Add R1071,R1073 Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

Page07: NI R1209 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 52 of 54
1 2 3 4 5
 1 2 3 4 5

04/07/2006
Page16 : Change C310,C313,C314 to 18P
For CRT EMI issue
Page19 : Change L23,L24,L25 to 0 ohm；C182,C180,C181 to 12P
Change L18,L19,L20 to 39nH inductor
For CRT EMI issue
1 04/19/2006 1

Page16 : change R542,R543,R544 to 56ohm bead for EMI issue

04/28/2006
Page17 : UnIstall R501, duplicate PD resistor
Page28 : Install R1022 and UI R1021
For clock can't shut down under DC mode

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 53 of 54
1 2 3 4 5
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D

8/26/2005 Add PR2,PR259,PR261(1M ohm),

1 42,44,50 HP To implement 4 cell main battery DB
(DB) Add PQ73,PQ74,PQ75,PQ76(RHU002N06_SOT323)
Add PR260(39.2k)
8/30/2005 Remove PQ49,PQ66
2 48 HP To fix VDD_CORE in 1V. DB
(DB)

Add PC147 3900pF capacitor across PR214

50 10/18/2005
3 HP Changes for OCP circuit Change PR207 from 0 Ohm to 3.9K_5%
(SI)
Change PC131 from 0.22uF to 0.027uF
Change PR203 from 649K to 604K_1%
Change PR221 from 47K to 10K_5%
Add a newPR265 47K_5% resistor in series with PR216-2 SI
Add a new PC146 1uF X7R capacitor from PR216-2 to GND
Change PC133 from 10uF to 0.1uF X7R
C Change PR228 from 10K to 21K_1% C

Change PR234 from 11.5K to 3.48K_1%

Change PR232 from 3.3K to 21K_1%

10/18/2005
4 43 HP sets Max charge current to 3.75A) Change PR29 from 100K to 143K_1% SI
(SI)
12/06/2005
5 50 43 HP Changes for OCP circuit PR225 is open and PR26.2 connects to PQ63.1 SI
(SI2)
12/12/2005
6 50 Compal Correct PR223 value. Correct PR223 from 180K to 137K SI2
(SI2)

12/19/2005
7 47 Compal DRR2 issue Change PC78 from 220u to 330u SI2
(SI2)
Delete PC81,PR127
12/21/2005 OTS#181928
B
8 49 Compal Add PC148(68uF) SI2 B

(SI2) Electrical printed circuit assembly acoustic noise test fail

01/16/2006 Add PC81,PR127
9 47 Compal For 1.8V thermal shut down issue PV
(PV)
10 02/08/2006 OTS#184638
compal
(PV) SVTP_SI1:PC Card Wireless Radio Interference fail on GSM 850 Change PL8,PL11 to shielded inductors PV
and GSM 900 channel.
11 Change PR38 to 866_1% Ohms
43 02/17/2006 This change will slightly increase the battery life
HP Change PR41 to 100K_0.1%
(PV)
Change PR44 to 7.68K_0.1% PV
Change PR53 to 2.80K_0.5%
Add a 39.2_1% resistor in series with PR53.
Connect one end to PR53.2 and the other end to GND.

A A

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
PWR PIR Sheet (1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2541 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 54 of 54
5 4 3 2 1