Winter Semester 2022-2023

VLSI TESTING AND TESTABILITY LAB

Practical Lab Report

Assessment: Scan based ATPG and Fault simulation

using Tessent
(Assessment No.4)
Course Code: MVLD506P
Slot: L31+L32

Submitted by: Hitesh Paliwal

Reg. No: 22MVD0128
Submitted to: Dr. SIVANANTHAM S
Exp 4 Date: 17/05/2023

Scan based ATPG and Fault simulation using Tessent

AIM:
To perform the Scan based ATPG and Fault simulation on given CPU design
(synthesized file) using tessent and analyze the waveforms generated after fault
simulation using questa-sim.

Theoretical part:
A. The transition fault model captures delay defects that cause a slow-to-rise transition or
a slow-to-fall transition at a specific line in the circuit. Under this fault model, it is
assumed that the extra delay caused by a transition fault on a line is large enough so
that the delay of every path passing through this line exceeds the clock period.
 2. Above shows an example of a slow-to-rise transition fault at line c in a 3-input circuit.
Input b and d have constant values. The value of input a change from 0 to 1 at time point
t1, i.e., a rising transition occurs at a, and the transition propagates through the circuit. If
the circuit is fault free, the value of output e is 1 at the required time point t2, where t2-t1
is the clock period. However, due to the slow-to-rise transition fault at line c, the value of
output e remains 0 at t2. Therefore, the circuit cannot operate correctly.

Practical part:

Files required are:

➢ HDL code (.v) file for design of the circuit.

➢ .spf file
➢ Scan insertion HDL code (scaninserted.v)

Commands:
1. Command to convert from .stil format to .do :

stil2mgc -STIL scan1.spf -capture single -dofile stuck_do.do -tpf stuck.proc

2. To invoke Tessent tools:

A. For stuck at faults:

tessent -sh -dofile stuck.do -logfile lab4stuck.log

B. For transition faults:

tessent -sh -dofile transition.do -logfile lab4transition.log

➢ scan1.spf.do file
➢ scan1.spf.proc file
➢ LOG FILES GENERATED
1. stuck.log
2. Transition.log
➢ OUTPUT WAVEFORMS:
1. cpu_serial_pattern_stuck:
➢ si (1-100)
➢ so (1-100)
2. cpu_parallel_pattern_stuck:
➢ si (1-100)
➢ so (1-100)
Conclusion:
1. ATPG patterns has 100% test and 99.9% fault coverage for stuck at faults.

Test Patterns = 480

Simulated Patterns = 542

2. ATPG patterns has 98.59% test and 98.48% fault coverage for transition faults.

Test Patterns = 1227

Simulated Patterns = 1333

3. From above observation, it is clear that transition faults are difficult to detect and
has less coverage than stuck at faults.