Electronics 08 01329

electronics
Review
Review of Multilevel Voltage Source Inverter
Topologies and Analysis of Harmonics Distortions
in FC-MLI
Ronak A. Rana 1 , Sujal A. Patel 1 , Anand Muthusamy 1 , Chee woo Lee 2, * and Hee-Je Kim 2, *
1 School of Electrical Engineering, Pusan National University, Busandaehak-ro 63 beongil 2,
Busan 46241, Korea; ronak.eleindia@gmail.com (R.A.R.); sujalpatel15@gmail.com (S.A.P.);
anand.muthusamy07@gmail.com (A.M.)
2 Department of Electrical Engineering and Electrical Engineering Management, University of technology
Sydney, 15 Broadway Ultimo, Sydney, NSW 2007, Australia
* Correspondence: cwlee1014@pusan.ac.kr (C.w.L.); heeje@pusan.ac.kr (H.-J.K.);
Tel.: +82-51-510-2364 (C.w.L. & H.-J.K.)

Received: 25 September 2019; Accepted: 6 November 2019; Published: 11 November 2019
Abstract: We review the most common topology of multi-level inverters. As is known, the conventional
inverters are utilized to create an alternating current (AC) source from a direct current (DC) source.
The two-level inverter provides various output voltages [(Vdc/2) and (−Vdc/2)] of the load. It is
a successive method, but it makes the harmonic distortion of the output side, Electromagnetic
interference (EMI), and high dv/dt. We solve this problem by constructing the sinusoidal voltage
waveform. This is achieved by a “multilevel inverter” (MLI). The multilevel inverter creates the
output voltage with multiple DC voltages as inputs. Many voltage levels are combined to produce a
smoother waveform. During the last decade, the multilevel inverter has become very popular in
medium and high-power applications with some advantages, such as the reduced power dissipation
of switching elements, low harmonics, and low EMIs. We introduce the information about several
multilevel inverters such as the diode-clamped multilevel inverter (DC-MLI), cascaded H-bridge
multilevel inverter (CHB-MLI), and flying-capacitor multilevel inverter (FC-MLI) with Power systems
CAD (PSCAD) simulation. It is shown that THD is 28.88% in three level FC-MLI while THD is
18.56% in five level topology. Therefore, we can decrease the total harmonic distortion adopting the
higher-level topology.
Keywords: multilevel inverter; diode clamped multilevel inverter; flying capacitor multilevel
inverter; cascade H bridge multilevel inverter; total harmonic distortion; PWM control techniques;
PSCAD/MULTISIM simulation
1. Introduction
Inverters are very useful for various industrial applications. In the last few years,
the voltage-driving method has been adopted. To reduce the semiconductor transient voltage
and current rating, a series and parallel connection method is needed. Moreover, the limited standard
three-phase converter is also adopted up to the maximum allowable voltage of the load. Also, both
the primary and the Pulse width modulation (PWM) switching frequency can be useful. The reduced
switching frequency shows the low disappearance and the higher efficiency. In order to synthesize
the spectrum signals of the harmonics caused by the capacity, the multi-level inverter has received
more attention in recent times. Moreover, a multilevel inverter has a key role in providing improved
operating voltage beyond the voltage limits of conventional semiconductors.
Electronics 2019, 8, 1329; doi:10.3390/electronics8111329 www.mdpi.com/journal/electronics

Electronics 2019, 8, 1329 2 of 37
The following clarification defines the significance of the multilevel converter. The explanation of
a multilevel inverter is: “The multilevel inverter can demonstrate the switching skill very effectively
with different voltage and current levels of its input or output nodes”. It is a practical reply to raise the
Electronics 2019, 8, x FOR PEER REVIEW 2 of 38
power capacity with a comparably low elements load and decreasing the output harmonics.
1.1. The Concept of Multilevel Inverters
The Concept of Multilevel Inverters
Two level inverters are shown in Figure 1. The input voltage of a direct current (DC) is converted
Two level inverters are shown in Figure 1. The input voltage of a direct current (DC) is converted
to the required alternating current (AC) voltage and frequency [1]. When an inverter operates with
to the required alternating current (AC) voltage and frequency [1]. When an inverter operates with Vdc,
Vdc, a two-level inverter can create two different output voltage for a load, Vdc / 2 or (−Vdc) / 2. To
a two-level inverter can create two different output voltage for a load, Vdc/2 or (−Vdc)/2. To generate
generate an AC voltage, both voltages are generally allowable in the PWM. Compared to multilevel
an AC voltage, both voltages are generally allowable in the PWM. Compared to multilevel inverters,
inverters, this two-level method creates harmonic distortion, Electromagnetic interference (EMI), and
this two-level method creates harmonic distortion, Electromagnetic interference (EMI), and huge
huge dv/dt [2]. The idea of a multilevel inverter is not based on the two-voltage level AC.
dv/dt [2]. The idea of a multilevel inverter is not based on the two-voltage level AC. Alternatively,
Alternatively, some voltage levels are connected to get a better waveform and less dv/dt and
some voltage levels are connected to get a better waveform and less dv/dt and harmonic distortion.
harmonic distortion. If the voltage level of the inverter is higher than the waveform, it is much better.
If the voltage level of the inverter is higher than the waveform, it is much better. However, the designs
However, the designs are simple, but increasing voltage levels and more components are needed.
are simple, but increasing voltage levels and more components are needed. The dividing voltage
The dividing voltage and extending its control scheme become more complex in a three-phase setup
and extending its control scheme become more complex in a three-phase setup [3]. Series-connected
[3]. Series-connected multilevel inverters are connected to the capacitor-composing energy tank of
multilevel inverters are connected to the capacitor-composing energy tank of the inverter. That provides
the inverter. That provides many nodes in the inverter connecting to the different phases. The term
many nodes in the inverter connecting to the different phases. The term level does not correspond to
level does not correspond to the voltage level that can be provided by the output inverter. Diodes can
the voltage level that can be provided by the output inverter. Diodes can provide the path of reactive
provide the path of reactive source from the load to the power supply at the current and voltage of
source from the load to the power supply at the current and voltage of Resistance Inductor load (RL)
Resistance Inductor load (RL) load having opposite polarity.
load having opposite polarity.
Figure 1. Two-level inverter.

Figure 1. Two-level inverter.
A multilevel inverter has positive points compared with the two-level inverter using the PWM
method. Also, a multilevel
A multilevel inverter hasinverter
positiveproduces very smallwith
points compared distortions and dv/dt
the two-level in the
inverter output
using side.
the PWM
In addition, it produces a common-mode voltage and operates at a lower switching
method. Also, a multilevel inverter produces very small distortions and dv/dt in the output side. In frequency [2] than
aaddition,
two-stageit inverter.
producesBesides, there are several
a common-mode voltagefeatures of a multilevel
and operates inverter
at a lower that can
switching be summarized
frequency [2] than
as
a the following:
two-stage (1) the Besides,
inverter. multilevelthere
inverter
aredoes not produce
several featureslow of distortion
a multileveloutput voltage,
inverter butcan
that it also
be
decreases the dv/dt stresses. Consequently, problems with electromagnetic
summarized as the following: 1) the multilevel inverter does not produce low distortion outputcompatibility are cleared.
(2) The multi-level
voltage, but it also inverter produces
decreases the adv/dt
lower stresses.
voltage inConsequently,
a common mode; as a result,
problems withtheelectromagnetic
motor attached
load of the multilevel inverter may be decreased. (3) A multilevel inverter
compatibility are cleared. 2) The multi-level inverter produces a lower voltage in a commondraws a small input current
mode;
distortion. (4) To obtain more output voltage levels using fewer switching devices,
as a result, the motor attached load of the multilevel inverter may be decreased. 3) A multilevel many recently
structured multilevel
inverter draws a smallinverters have been
input current presented
distortion. in obtain
4) To this publication
more output [4–16].
voltage levels using fewer
In this paper, various multilevel inverter topologies are
switching devices, many recently structured multilevel inverters have been presented along with their analysis
presented in and
this
comparative assessments. Furthermore, these topologies have been checked with the simulation results
publication [4–16].
usingInPSCAD software.
this paper, various Then a comparison
multilevel inverteroftopologies
different types of multilevel
are presented alonginverter topologies
with their analysisandand
describe PWM control techniques and we can choose one topology for further
comparative assessments. Furthermore, these topologies have been checked with the simulation implementation and
selected from PSCAD
results using the simulation
software.results
Thenderived from the
a comparison of MULTISIM
different typessoftware.
of multilevel inverter topologies
and describe PWM control techniques and we can choose one topology for further implementation
and selected from the simulation results derived from the MULTISIM software.
2. Topologies of Multilevel Inverter
Normally, these inverters can be classified as voltage source or current source inverters as shown
Electronics 2019, 8, 1329 3 of 37
2. Topologies of Multilevel Inverter

Normally, these inverters can be classified as voltage source or current source inverters as shown
in Figure2019,
Electronics 2. 8, x FOR PEER REVIEW 3 of 38
Figure 2. Voltage source or current source inverters.

Figure 2. Voltage source or current source inverters.
Three major multilevel inverter configurations applied in industrial applications and mentioned
Threeliteratures;
in several major multilevel
cascaded inverter configurations
H-bridges applied
inverter with in industrial
separate applications
DC sources, and mentioned
Diode Clamp, and flying
in several used
capacitors literatures; cascaded
virtually H-bridges
in low, medium andinverter with applications
high-power separate DCare sources,
briefly Diode Clamp, and
discussed.
flying capacitors used virtually in low, medium and high-power applications are briefly discussed.
2.1. Diode-Clamped Multilevel Inverter (DC-MLI)
2.1. Diode-Clamped
The multilevelMultilevel
inverter was Inverter (DC-MLI)
invented in 1975, which was a cascade diode inverter. After a few
years,The
it was called the diode-clamped multilevel
multilevel inverter was invented in 1975, inverter
which(DC-MLI) [2]. In diode
was a cascade DC-MLI, voltage
inverter. clamping
After a few
diodes are required to regulate the voltage on the DC bus to reach output
years, it was called the diode-clamped multilevel inverter (DC-MLI) [2]. In DC-MLI, voltage clamping voltage levels; but the
multilevel
diodes areinverter
requiredlevel should be
to regulate theunique
voltage because
on thethe DCneutral
bus topoint
reachisoutput
not available
voltageeven in number
levels; but the
levels [17]. For DC bus with a neutral point and a capacitor, there is a clamping
multilevel inverter level should be unique because the neutral point is not available even in number diode attached to the
number of valve
levels [17]. For DC pairs
bus(m-1),
with awhere
neutral m is the level
point and aofcapacitor,
voltage inthere
the inverter. The explanation
is a clamping diode attached as totowhy
the
the frequency converter is connected to the series with a diode; means
number of valve pairs (m-1), where m is the level of voltage in the inverter. The explanation that all diodes have the same
as to
rated
why thevoltage and may
frequency block aiscorrect
converter voltage
connected level
to the [18]. with a diode; means that all diodes have the
series
sameArated
3-level DC-MLI,
voltage andamayvoltageblockperacapacitor and switch
correct voltage levelis[18].
Vdc/2. The equations are utilized to decide
the number
A 3-level DC-MLI, a voltage per capacitor and switchmisisVdc/2.
of devices forming a given level of a DC-MLI. If the number of levels, are
The equations the number
utilized of to
capacitors on the DC side (C) can be determined through Equation (1).
decide the number of devices forming a given level of a DC-MLI. If m is the number of levels, the The number of switches (S)
per phaseofand
number the clamp
capacitors on diodes
the DC(D) sidecan
(C)becan
determined
be determined through Equations
through (2) and
Equation (1).(3),
Therespectively.
number of
Consequently,
switches (S) per phase and the clamp diodes (D) can be determined through Equationsintermediate
4 switches, 2 diodes, and 2 capacitors are needed as shown in Figure 3a. The (2) and (3),
circuit voltageConsequently,
respectively. is divided into4three phases,
switches, with two
2 diodes, and capacitors C1 and
2 capacitors are C2 whichasare
needed attached
shown in series;
in Figure 3a.
“n”
The intermediate circuit voltage is divided into three phases, with two capacitors C1 and C2voltage
is a neutral point which is the center point of the capacitors. There are 3 levels of output which
Vdc/2, 0, (−Vdc)/2,
are attached for voltage
in series; “n” is alevel
neutralVdc/2, S1 which
point and S2 is arethe
activated, for voltage
center point of the level (−Vdc)/2,
capacitors. ThereS10areand3
S2 0 areofactivated, and for 0 level 0 0 0
levels output voltage Vdc/2, 0, voltage,
(−Vdc)/2,S2 forand S1 are
voltage activated.
level Vdc/2, S1Whenand S2 S2areand S1 are connected,
activated, for voltage
the load is shortened, and the reactive power released.
level (−Vdc)/2, S1' and S2' are activated, and for 0 level voltage, S2 and S1' are activated. When S2'
and S1' are connected, the load is shortened, and the reactive power released.
For the 5-level diode clamped multilevel inverter, m is 5. Following Equations (1), (2) and (3),
therefore, 8 switches, 4 diodes, and 4 capacitors are needed. Figure 3b shows that all diodes are
designed for Vdc / 4, and diodes D1' block 3Vdc/4. Hence, 3 diodes are connected in a series. At 5
voltage levels, Vdc/2, Vdc/4, 0, (−Vdc)/4, (−Vdc)/2 are five states output. To get various output voltage
levels, combinations of switching states are utilized. For Vdc/2, top all switches are activated and, for
Vdc/4, S2, S3, S4, and S1' are activated and a voltage is maintained through a clamping diodes D1
and D1'. For 0 level voltage, S3, S4, S1' and S2' are activated, for a voltage (−Vdc)/4, switch S4, S1', S2',
and S3' are activated and voltage (−Vdc)/2 the bottom all switches are activated and the diodes D2
𝑆 = 2(𝑚 − 1) (2)
𝐷 = (𝑚 − 1)(𝑚 − 2) (3)
There are few advantages of DC-MLI: high efficiency, due to the main switching frequency that
can be used for all devices. Capacitors are pre-charged as a group; all stages have the usual DC bus.
Electronics 2019, 8, 1329 4 of 37
That reduces the capacitance of the inverter. However, there are a few drawbacks of this topology: it
is difficult to flow active power, and controlling is quite difficult for the capacitor voltage balance.
(a)
(b)
Figure 3. (a) Three-level diode-clamped multilevel inverter (DC-MLI); (b) 5-level DC-MLI.
Figure 3. (a) Three-level diode-clamped multilevel inverter (DC-MLI); (b) 5-level DC-MLI.
For the 5-level diode clamped multilevel inverter, m is 5. Following Equations (1), (2) and (3),
2.1.1. 3-Level DC-MLI PSCAD Simulations
therefore, 8 switches, 4 diodes, and 4 capacitors are needed. Figure 3b shows that all diodes are
In Figure
designed 4a, consider
for Vdc/4, and diodes D10 block
the source voltage as +2 Vdc.
3Vdc/4. There
Hence, are total
3 diodes aretwo capacitors
connected in aconnected
series. Atto5
source,
voltagehence
levels,the voltage
Vdc/2, across
Vdc/4, each capacitor
0, (−Vdc)/4, is Vdc.
(−Vdc)/2 As shown
are five in the switching
states output. Tableoutput
To get various 1 the voltage
voltage
levels are available as per the switching sequence.
levels, combinations of switching states are utilized. For Vdc/2, top all switches are activated and,
for Vdc/4, S2, S3, S4, and S10 are activated and a voltage is maintained through a clamping diodes D1
and D10 . For 0 level voltage, S3, S4, S10 and S20 are activated, for a voltage (−Vdc)/4, switch S4, S10 , S20 ,
and S30 are activated and voltage (−Vdc)/2 the bottom all switches are activated and the diodes D2 and
D20 or D3 and D30 are maintaining the voltage.
C = m−1 (1)
S = 2(m − 1) (2)
Electronics 2019, 8, 1329 5 of 37
D = (m − 1)(m − 2) (3)
There are few advantages of DC-MLI: high efficiency, due to the main switching frequency that
can be used+Vdc:
forSwitches S1, S2Capacitors
all devices. are ON. In are
this pre-charged
case, current flows from source
as a group; (charged
all stages capacitors
have the usualC1)DC
to bus.
load through switches S1, S2. 0 voltage: Switches S2 and S3 are ON. Hence no capacitor is
That reduces the capacitance of the inverter. However, there are a few drawbacks of this topology: it isdischarged
through
difficult the active
to flow load. Here the load
power, and iscontrolling
directly connected
is quitetodifficult
ground forat both
the the ends (shorted).
capacitor voltageHence the
balance.
voltage across the load is 0 V. −Vdc: Switches S3 and S4 are ON. In this case, current flows from source
2.1.1. 3-Level capacitors
(charged DC-MLI PSCADC2) to the load through switches S3 and S4.
Simulations
In Figure 4b, a control circuit there is 4 switch signal generated using two comparators. 0–3 V,
In
50 Figure
Hz cycle,4a,a consider
triangularthe source is
waveform voltage
used for +2 Vdc. There
as comparison. are total
A different DCtwo capacitors
signal connected
is used as a base to
source,
forhence the voltage
a comparator. This across each capacitor
will generate is Vdc.
four signals AsS2shown
S1, and in the switching
with different widths. TheTable
other1 two,
the voltage
S3
and S4, are obtained using NOT gate. These
levels are available as per the switching sequence. 4 gate signals are ready to supply to IGBT which are in
the 3-level DC-MLI power circuit, which is illustrated in Figure 4a.
(a)
(b)
Figure 4. Cont.
Electronics 2019, 8, 1329 6 of 37
(c)
Figure 4. (a)4.Power
Figure circuit
(a) Power of of
circuit 3- 3-
level
levelDC-MLI;
DC-MLI; (b) controlcircuit
(b) control circuitofof3-3- level
level DC-MLI;
DC-MLI; (c) phase
(c) phase output
output
voltage waveform
voltage waveformof 3-level DC-MLI.
of 3-level DC-MLI.
+Vdc: Switches S1, S2Table are ON. In this levels

1. 3- Voltage case, ofcurrent
DC-MLIflows from source
and switching states. (charged capacitors C1) to
load through switches S1, S2. 0 voltage: Switches S2 and S3 are ON. Hence no capacitor is discharged
Voltage 𝐒𝟏 𝐒𝟐 𝐒𝟑 𝐒𝟒
through the load. Here the load is directly connected to ground at both the ends (shorted). Hence the
𝑉𝑑𝑐 1 1 0 0
voltage across the load is 0 V. −Vdc:
0 Switches S3 0 and S4 1are ON. In 1 this case,0 current flows from source
(charged capacitors C2) to the−𝑉𝑑𝑐 load through switches0 S30and S4. 1 1
In Figure 4b, a control circuit there is 4 switch signal generated using two comparators. 0–3 V,
50 Hz2.1.2 5-Level
cycle, DC-MLI waveform
a triangular PSCAD Simulations
is used for comparison. A different DC signal is used as a base for
a comparator. This5a,
In Figure will generate
consider the four
source signals S1,asand
voltage S2 There
+Vdc. with different widths.
are total four The other
capacitors two, to
connected S3 and
source,
S4, are henceusing
obtained the voltage acrossThese
NOT gate. each capacitor is +Vdc/4.
4 gate signals As shown
are ready in the switching
to supply Table 2are
to IGBT which thein the
voltage
3-level DC-MLIlevels are available
power circuit,as per the
which is switching
illustrated sequence.
in Figure 4a.
+Vdc/2: Switches S1, S2, S3, S4 are ON. In this case, current flows from source (charged capacitors
Table
C1, C2) to load through 1. 3- Voltage
switches levels
S1, S2, S3, S4. of DC-MLI
+Vdc/4: and switching
Switches states.
S2, S3, S4, and S5 are ON. Here only
capacitor C2 discharges through diode D1 and the switches S2, S3, and S4 to the load. Since only half
Voltage S1 S2 S3 S4
of the capacitor (only C2) discharges, hence total Vdc/4 voltage is available. 0 voltage: Switches S3,
Vdc 1 1 0 0
S4, S5 and S6 are ON. Hence no capacitor
0 is 0discharged
1 through
1 0the load. Here the load is directly
connected to ground at both the ends (shorted). Hence the voltage across the load is 0 V. −Vdc/4:
−Vdc 0 0 1 1
Switches S4, S5, S6, and S7 are ON. Hence the capacitor C3 discharges through the ground–load and
2.1.2.switch
5-Level
S5,DC-MLI
S6, and PSCAD Simulations
S7. As the discharge is in the opposite direction the voltage appeared will be
In Figure−5a,
negative. Vdc/2: Switches
consider theS5, S6, S7 voltage
source and S8 are +Vdc.
asON. Capacitor
ThereC3areand C4 will
total fourdischarge
capacitorsthrough the to
connected
source, hence the voltage across each capacitor is +Vdc/4. As shown in the switching Table 2 the
load in the opposite direction (from the ground to load to switches). Hence total voltage –Vdc/2 will
voltage levels
appear are available
across asFigure.
the load. In per the5bswitching
a control sequence.
circuit there is 8 switch signal generated using four
+Vdc/2: Switches S1, S2, S3, S4 are ON. In this case, current
comparators. 0 – 10 V, 50 Hz cycle, a triangular waveform is usedflows from source
for comparison. And(charged capacitors
different DC
C1, C2) to load through switches S1, S2, S3, S4. +Vdc/4: Switches S2, S3, S4, and S5 are ON. Here only
capacitor C2 discharges through diode D1 and the switches S2, S3, and S4 to the load. Since only half
of the capacitor (only C2) discharges, hence total Vdc/4 voltage is available. 0 voltage: Switches S3,
S4, S5 and S6 are ON. Hence no capacitor is discharged through the load. Here the load is directly
Electronics 2019, 8, 1329 7 of 37
connected to ground at both the ends (shorted). Hence the voltage across the load is 0 V. −Vdc/4:
Switches S4, S5, S6, and S7 are ON. Hence the capacitor C3 discharges through the ground–load
and switch S5, S6, and S7. As the discharge is in the opposite direction the voltage appeared will be
negative. −Vdc/2: Switches S5, S6, S7 and S8 are ON. Capacitor C3 and C4 will discharge through
the load in the opposite direction (from the ground to load to switches). Hence total voltage –Vdc/2
will Electronics
appear across
2019, 8, x the
FOR load. In Figure 5b a control circuit there is 8 switch signal generated
PEER REVIEW using
7 of 38 four
comparators. 0 – 10 V, 50 Hz cycle, a triangular waveform is used for comparison. And different DC
signal
signal is used
is used as a as a base
base for afor a comparator.
comparator. ThisThis
willwill generate
generate fourfour signals
signals S1,S1,
S2,S2,
S3 S3
andand
S4 S4
withwith
different
widths. Other
different four S5
widths. to S8
Other areS5obtained
four using NOT
to S8 are obtained usinggate.
NOT These
gate. 8 gate8signals
These are ready
gate signals to supply
are ready to to
IGBTsupply
whichtoare IGBT which are in the 5-level DC-MLI power circuit, which is shown in Figure 5a.
in the 5-level DC-MLI power circuit, which is shown in Figure 5a.
(a)
(b)
Figure 5. Cont.
Electronics 2019, 8, 1329 8 of 37
(c)
5. (a)5.Power
FigureFigure circuit
(a) Power of 5-level
circuit DC-MLI;
of 5-level DC-MLI;(b)
(b) control circuitofof5-level
control circuit 5-level DC-MLI;
DC-MLI; (c) phase
(c) phase output
output
voltage waveform
voltage of 5-level
waveform DC-MLI.
of 5-level DC-MLI.
Table 2. 5-Voltage
Table 2. 5-Voltagelevels
levelsof
ofDC-MLI andswitching
DC-MLI and switching states.
states.
Voltage 𝐒𝟏
Voltage 𝐒𝟐S1 S2𝐒𝟑 S3 𝐒𝟒S4 𝐒𝟓
S5 S6 𝐒𝟔S7 𝐒𝟕
S8 𝐒𝟖
𝑉𝑑𝑐 1Vdc 1 1 1 0 0 0 0
2 1 1 1 1 0 0 0 0
2 Vdc
𝑉𝑑𝑐 04 1 0 1 1 1 11 11 0 00 00 0
4 0 0 0 1 1 1 1 0 0
0 0−Vdc
4 0 0 0 1 0 1 1 11 1 11 00 0
−𝑉𝑑𝑐 0−Vdc 00 00 0 10 11 1 11 11 0
2
4
−𝑉𝑑𝑐 0 0 0 0 1 1 1 1
2.2. Cascaded H-Bridge
2 Multilevel Inverter (CHB-MLI)
There are various
2.2. Cascaded inverter
H-Bridge topologies
Multilevel based on a series single-phase inverter connected to the
Inverter (CHB-MLI)
individual DC source. If an inverter is implemented in an active transfer of source applications,
There are various inverter topologies based on a series single-phase inverter connected to the
then the sources of each bridge must be separated. Due to this property, it is recommended to use a
individual DC source. If an inverter is implemented in an active transfer of source applications, then
cascaded H-bridge multilevel inverter (CHB-MLI) in fuel cells or photovoltaic (PV) array to reach a
the sources of each bridge must be separated. Due to this property, it is recommended to use a
highercascaded
level [19–21].
H-bridge multilevel inverter (CHB-MLI) in fuel cells or photovoltaic (PV) array to reach a
The resulting
higher phase voltage has been synthesized through increasing the generated voltages
level [19–21].
through different cells.phase
The resulting The voltage
modulehas ofbeen
a bridge is a three-level
synthesized in CHB-MLI,
through increasing and each
the generated module is
voltages
through
appended different
to the cascade.cells.
TheThe module
output of a bridge
voltage for anisn-level
a three-level in multilevel
cascade CHB-MLI, inverter 2n + 1,iswhere
and eachismodule
appended
n is the to DC
source of the cascade. The output
[22]. Switching voltage
angles areforobtained
an n-leveltocascade
reducemultilevel inverter
the overall is 2n + of
distortion 1, where
harmonics.
Maximum output voltage is decided by using Equation. (6) and minimum output voltage is decided
Electronics 2019, 8, 1329 9 of 37
by using Equation (7). The capacitors at the DC side (C) and several switches (S) per phase, calculated
through Equations (4) and (5) respectively.
m−1
C= (4)
2
S = 2(m − 1) (5)
m−1
Maximum output voltage = (Vdc) (6)
2
m−1
Minimum output voltage = (−Vdc) (7)
2
Figure 6a shows 3-level CHB-MLI. Here is a full-bridge that provides 3-levels of output. It is a
simple diagram of 3-level CHB-MLI. This provides 3-levels of output; Vdc, 0 and −Vdc, while battery
voltage is Vdc, where E = Vdc.
As we have already discussed with Equations (4)–(7), for voltage level 3 m = 3, therefore Vdc is a
maximum voltage, and (−Vdc) is minimum output voltage. One DC bus capacitor and four switches
are needed. Generally, to get the output voltage, there are two activating switches. Hence, one pair
of switches gives a positive result and another pair create a negative result. Therefore, to obtain the
output source Vdc, T1, and T2’ are activated, and the output source −Vdc, T2 and T1’ are turned on.
If the current does not pass from the full-bridge then the 0-voltage source is obtained through the
switch T1 and T2 or lower two switches T1’and T2’.
Figure 6b represents 5-level CHB-MLI. One full-bridge module is a three-step cascade multilevel
inverter. Two bridge modules generate five various voltage levels; 2Vdc, Vdc, 0, (−Vdc), and (−2Vdc).
As a Vdc battery voltage with E = Vdc. In 5-level CHB-MLI, we take m = 5. Therefore, following
Equations (4), (5), (6) and (7), 2 capacitors at the DC side, 8 switches are needed. So, the maximum
output voltage is 2Vdc, and a minimum output voltage is −2Vdc.
As discussed in the three-level cascade multilevel inverter, the cross switches are activated,
and upper or lower switches obtain a 0-voltage. Thus, to get the output sources 2Vdc, T11 and T12’
or T21 and T22’ to be activated and the current passing through the capacitor C1 and C2. As with
a negative voltage, the other four cross switches are connected. For output voltage Vdc, the battery
bypassed either top or bottom. Therefore, the current pass throughout C1, T11, a load, T22’, T21’,
and T12’. Besides, for the minimum voltage (−Vdc), the current passes in the contrasting path, and its
passing by C2, T22, load, T11’, T12’ and T21’. For 0 power, there are two probabilities, 1) switches T11,
T12, T21, T22 are activated; 2) switches T11’, T12’, T21’, T22’ are activated. This topology is convenient
especially for photovoltaic generation application, where photovoltaics modules are directly connected
to an individual DC source [23].
The principle advantages of CHB-MLI are a series of H-bridges demonstrating an advanced design,
this will empower the assembling procedure to be rapidly and efficiently, also voltage adjustment is
easy. Although there are few disadvantages of CHB-MLI topology, each H-Bridge needs an isolated
DC source, which limits its use. That has more access to the SDCS, and no ordinary DC-bus [24].
Electronics 2019, 8, 1329 10 of 37
(a)
(b)
Figure 6. (a) Three-level cascaded H-bridge multilevel inverter (CHB-MLI); (b) 5-level CHB-MLI.
Figure 6. (a) Three-level cascaded H-bridge multilevel inverter (CHB-MLI); (b) 5-level CHB-MLI.
2.2.1. Three-Level CHB-MLI PSCAD Simulations
2.2.1. Three-Level CHB-MLI PSCAD Simulations
In Figure 7b, the control circuit has two gate signals S1 and S2. Those are available from the
In Figure
comparator. 7b, thetwo
Another control circuit
has the NOT has two
gate gate
with signals
initial twoS1 and S2.
signals. Those
These aresignals
four available
are from
readythe
to
comparator. Another two has the NOT gate with initial
supply to IGBT which are in the 3-level CHB-MLI power circuit. two signals. These four signals are ready to
supply to IGBT
In Figure 7a,which
all theare inpulses
gate the 3-level CHB-MLI
are applied power
to the circuit.
different IGBT of CHB-MLI. This follows Table 3
In Figure 7a, all the gate pulses are applied to the different
of a sequence of a waveform for gate signals. For Vdc; switched S1 IGBT
andofS4CHB-MLI. ThisHence,
are conduct. follows Table
current
3 of a sequence of a waveform for gate signals. For Vdc; switched S1 and S4 are conduct.
flow from the source, S1, load, S4, and source, for 0Vdc; S3 and S4 are conducted and for −Vdc; S2 and Hence,
current
S3 flow fromtherefore
are conducted, the source, S1, load,
current S4, and
flow from thesource,
source, for S2, 0Vdc; S3 and
load, S3, andsource.
S4 are conducted and for
−Vdc; S2 and S3 are conducted, therefore current flow from the source, S2, load, S3, and source.
Electronics 2019, 8, 1329 11 of 37
Table 3. Voltage levels of 3-level cascade H-bridge multilevel inverter and switching states.
Voltage S1 S2 S3 S4
Vdc 1 0 0 1
0 0 0 1 1
Electronics 2019, 8, x FOR PEER REVIEW −Vdc 0 1 1 0 11 of 38
(a)
(b)
Figure 7. Cont.
Electronics 2019, 8, 1329 12 of 37
(c)
Figure 7. (a) Power circuit of 3- level CHB-MLI; (b) control circuit of 3- level CHB- MLI; (c) phase
Figure 7. (a) Power circuit of 3- level CHB-MLI; (b) control circuit of 3- level CHB- MLI; (c) phase
output voltage waveform of 3-level CHB-MLI.
output voltage waveform of 3-level CHB-MLI.
2.2.2. Five-Level CHB-MLI PSCAD Simulation
Table 3. Voltage levels of 3-level cascade H-bridge multilevel inverter and switching states.
In Figure 8b, the control circuit waveforms are generated by comparison of DC signal (2 V and
4V) with the triangular waveforms𝐒𝟏
Voltage (−10 V to +10𝐒𝟐 V) changing the 𝐒𝟑 values of DC 𝐒𝟒 voltage will change the
𝑉𝑑𝑐 1 0 0
gate pulse widths. Four signals S1, S2, S5, and S6 are available from the comparator. 1 The other four
0 0 0 1 1
signals are obtained using the NOT gate with initial four signals. These 8 gate signals S1, S2, S3, S4, S5,
−𝑉𝑑𝑐 0 1 1 0
S6, S7, and S8 are ready to supply to IGBT which are in the 5-level CHB-MLI power circuit, which is
shown in Figure 8c.
2.2.2. Five-Level CHB-MLI PSCAD Simulation
In Figure 8a, all gate signals are applied to the IGBT of CHB-MLI. The following Table 4 represents
In Figureof8b,
the sequence the control
waveforms forcircuit waveforms
gate signals. Considering for +2 by
are generated Vdccomparison of DC signal
the corresponding (2 Vsuch
switches and
4V) with
as S1, the and
S3, S5, triangular waveforms
S7 are turned (−10 V to +10
ON. Therefore, thereV)ischanging the values
a current path of DC
takes from voltage S1,
Source-1, willLoad,
changeS7,
the gate pulse widths. Four signals S1, S2, S5, and S6 are available from the comparator.
Source-2, S5, S3 and Source-1. As a result, the two sources are added to each other and so the voltage The other
+2
four
Vdcsignals are obtained
is available. usingfor
Similarly, the+Vdc,
NOTthe gate with initial
switches four
S1, S3, S7,signals.
and S8These 8 gateon
are turned signals S1,current
and the S2, S3,
S4, S5, S6, S7, and S8 are ready to supply to IGBT which are in the 5-level CHB-MLI
flows through the Source-1, S1, load, S7, S8, S3 and back to Source-1. For 0 Vdc, switches S3, S4, S7, and power circuit,
which is shown
S8 are turned on.inFor
Figure
−Vdc, 8c.switches S2, S4, S7, S8 are turned on, Current flow through Source-1, S2, S7,
In Figure
S8 Load 8a, all
(the reverse gate signals
direction), aretoapplied
S4, back to −2Vdc:
source-1. the IGBTS2, of
S4, CHB-MLI. The following
S6, S8 are turned ON, current Table 4
flows
represents the sequence of waveforms for gate signals. Considering for +2 Vdc the
through the Source-1, S2, S8, Source-2, S6, Load (the reverse direction), S4 and then back to Source-1. corresponding
switches such as S1, S3, S5, and S7 are turned ON. Therefore, there is a current path takes from Source-
1, S1, Load, S7, Source-2, S5, S3 and Source-1. As a result, the two sources are added to each other
and so the voltage +2 Vdc is available. Similarly, for +Vdc, the switches S1, S3, S7, and S8 are turned
on and the current flows through the Source-1, S1, load, S7, S8, S3 and back to Source-1. For 0 Vdc,
switches S3, S4, S7, and S8 are turned on. For −Vdc, switches S2, S4, S7, S8 are turned on, Current
flow through Source-1, S2, S7, S8 Load (the reverse direction), S4, back to source-1. −2Vdc: S2, S4, S6,
S8 are turned ON, current flows through the Source-1, S2, S8, Source-2, S6, Load (the reverse
direction), S4 and then back to Source-1.
Electronics 2019, 8, 1329 13 of 37
Table 4. Voltage levels of 5-level CHB-MLI and switching states.
Voltage S1 S2 S3 S4 S5 S6 S7 S8
2Vdc 1 0 1 0 1 0 1 0
Vdc 1 0 1 0 0 0 1 1
0 0 0 1 1 0 0 1 1
−Vdc 0 1 0 1 0 0 1 1
−2Vdc
Electronics 2019, 8, x FOR PEER REVIEW 0 1 0 1 0 1 0 1 13 of 38
(a)
(b)
Figure 8. Cont.
Electronics 2019, 8, 1329 14 of 37
(c)
Figure 8. (a)8.Power
Figure circuit
(a) Power ofof
circuit 5-level
5-levelCHB-MLI;
CHB-MLI; (b) controlcircuit
(b) control circuitofof 5-level
5-level CHB-MLI;
CHB-MLI; (c) phase
(c) phase output
output
voltage waveform
voltage of 5-level
waveform CHB-MLI.
of 5-level CHB-MLI.
2.3. Flying-Capacitor Multilevel

Table 4.Inverter (FC-MLI)
Voltage levels of 5-level CHB-MLI and switching states.
Voltage of𝐒𝟏
The same topology the DC-MLI 𝐒𝟐 is a𝐒𝟑 𝐒𝟒
capacitor-clamping 𝐒𝟓 or flying-capacitor
𝐒𝟔 𝐒𝟕 𝐒𝟖multilevel inverter
(FC-MLI) topology 2𝑉𝑑𝑐
in which1 clamping 0 capacitors
1 0 utilized
are 1 to clamp 0 the voltages
1 0
[25]. This topology
is new compared𝑉𝑑𝑐 with other 1 topologies.
0 The1 voltage 0 between 0 the two 0 capacitors
1 1
refers to the output
0 0 0 1 1 0 0 1 1
voltage at the terminal
−𝑉𝑑𝑐
[26].0 The indicated
1 0
voltage1 level in0 the flying-capacitor
0 1
inverter
1
is the same
as like diode-clamped
−2𝑉𝑑𝑐 multilevel
0 inverter
1 0 [27]. Moreover,
1 0 switching
1 pairs
0 may 1 be different and
asymmetrical according to the regulating policy, but the choice of the two pairs leads to the switching
state redundancy, which may utilize to attain the voltage balancing of FC-MLI [2,28,29]. The number
2.3. Flying-Capacitor Multilevel Inverter (FC-MLI)
of output voltage levels is increased through appending some additional switches and a capacitor.
Thefor
Besides this, same topology
FC-MLI of the
(m-1) DC-MLI
number of is a capacitor-clamping
capacitors on a common or flying-capacitor
DC-bus, wheremultilevel inverter
m is the level number
(FC-MLI) topology in which clamping capacitors are utilized to clamp the voltages
of the inverter, and 2(m-1) switch-diode valve pairs are used, and [(m-1) (m-2)/2] clamping capacitors [25]. This topology
is neware
per phase compared with other topologies. The voltage between the two capacitors refers to the output
used [28,30,31].
voltage at the terminal [26]. The indicated voltage level in the flying-capacitor inverter is the same as
The choice of two pairs leads to a surface moving state, which can be used to obtain the FC-MLI
like diode-clamped multilevel inverter [27]. Moreover, switching pairs may be different and
balancing voltage [2,28,29]. In Figure 9a, this indicates 3-level FC-MLI, which has output over a and n
asymmetrical according to the regulating policy, but the choice of the two pairs leads to the switching
points such
state as Vdc/2, 0,
redundancy, (−Vdc)/2.
which For voltage
may utilize to attain Vdc/2, S1 and
the voltage S2 areofactivated,
balancing while (−Vdc)/2,
FC-MLI [2,28–29]. The number S10 and
0
S2 are 0 0 If S1 and S10
of activated and for
output voltage 0 voltage,
levels one pair
is increased activated
through either
appending (S1,additional
some S1 ) pair or (S2, S2and
switches ) pair.
a capacitor.
are activated, thenforC1FC-MLI
is charged, 0
Besides this, (m-1)and its discharge
number when
of capacitors onS2 and S2 are
a common deactivated.
DC-bus, where mAisC1 theis level
balanced
through choosing
number of the the rightand
inverter, combination of level 0 valve
2(m-1) switch-diode switches.
pairs are used, and [(m-1) (m-2)/2] clamping
capacitors
With per phase
5 levels are used
of flying [28,30–31].
capacitor multilevel inverter, the output voltage is more flexible than a
diode clamp inverter. Figure 9b shows a 5-level voltage through the neutral point n, Van is reached
through some switching combustions. For voltage Vdc/2, Switch S1–S4 is activated, voltage level
Vdc/4, there are 3 amalgamations, 1) S1, S2, S3, and S1’ are activated (Vdc/2 of top C40 s and −Vdc/4 of
S2' are activated and for 0 voltage, one pair activated either (S1, S1') pair or (S2, S2') pair. If S1 and S1'
are activated, then C1 is charged, and its discharge when S2 and S2' are deactivated. A C1 is balanced
through choosing the right combination of level 0 switches.
With 5 levels of flying capacitor multilevel inverter, the output voltage is more flexible than a
diode clamp inverter. Figure 9b shows a 5-level voltage through the neutral point n, Van is reached
Electronics 2019, 8, 1329 15 of 37
through some switching combustions. For voltage Vdc/2, Switch S1–S4 is activated, voltage level
Vdc/4, there are 3 amalgamations, 1) S1, S2, S3, and S1' are activated (Vdc/2 of top C4’s and −Vdc/4
ofC1),
C1),2) 2)
S2,S2,
S3,S3,
S4,S4,
andand
S40S4'
areare activated
activated (3Vdc/4
(3Vdc/4 of C3’s
of C3’s and and (−Vdc)
(−Vdc)/2 / 2 of lower
of lower C4), 3)C4), 3) S1,
S1, S3, S4, S3,
andS4,
S30
and
are S3' are activated
activated (Vdc/2 of(Vdc/2
top C4of top
0 , (−3C4’, (−3 Vdc)/4
Vdc)/4 of C3’s ofor C3's or (−Vdc/)/2
(−Vdc/)/2 of C2), of C2),
and and voltage
voltage 0, S3,S4,S1’
0, S3,S4,S1 0 and S20
and
are S2’ are activated.
activated. For voltage
For voltage (−Vdc)/4 (−Vdc)/4
S1, S10 ,S1,
S20S1’,
andS2’S3and
0 areS3’ are activated
activated (Vdc/2(Vdc/2 of top
of top C4’s C4’s
and (−3and (−3
Vdc)/4
Vdc)/4 of C3), and for (−Vdc)/2, activate all lower
of C3), and for (−Vdc)/2, activate all lower switches S1 – S4 .) switches
0 S1'
0 – S4'.)
AAmost
mostessential
essentialsuperiority
superiorityofofFC-MLIFC-MLIisisphasephaseredundancy
redundancyusing usingfor
forbalancing
balancingthe thevoltage
voltage
levels or capacitors, easy to regulate an active and reactive power. In addition,
levels or capacitors, easy to regulate an active and reactive power. In addition, using capacitors means, using capacitors
means, an inverter
an inverter can move canthroughout
move throughout small outages.
small period period outages.
However, However,
there arethere
few are few drawbacks
drawbacks too. It is
too. It is difficult to remark on the voltage level for capacitors, pre-charged every
difficult to remark on the voltage level for capacitors, pre-charged every capacitor is at a similar voltage, capacitor is at a
similar voltage, starting is difficult, and switching usage and productivity are
starting is difficult, and switching usage and productivity are poor for actual power transmission [24].poor for actual power
transmission [24].
(a)
(b)
Figure 9. (a) Three-level flying-capacitor multilevel inverter (FC-MLI); (b) 5-level FC-MLI.
Figure 9. (a) Three-level flying-capacitor multilevel inverter (FC-MLI); (b) 5-level FC-MLI.
In the above description, positive marks of capacitors are in discharge mode and the negative
capacitor marks are in charge mode. With the right choice of capacitor combinations, we can balance
a capacitor charge. As with diode clamping, many bulk capacitors are needed to clamp the voltage.
Specified nominal voltage of the capacitor used as the main power switch.
In the above description, positive marks of capacitors are in discharge mode and the negative
capacitor marks are in charge mode. With the right choice of capacitor combinations, we can balance
Electronics 2019, 8, 1329 16 of 37
a capacitor charge. As with diode clamping, many bulk capacitors are needed to clamp the voltage.
Specified nominal voltage of the capacitor used as the main power switch.
2.3.1. Three-Level FC-MLI PSCAD Simulations
2.3.1. Three-Level FC-MLI PSCAD Simulations
In Figure 10b, the control circuit with two gate signals of g1 and g2 are available. Another two are
In Figure
obtained using10b,the the
NOT control circuit
gate with withtwo
initial twosignals.
gate signals
These offour
g1 and g2 are
signals areavailable.
ready to Another two
give to IGBT
are obtained using the NOT gate with
which are in the 3-level FC-MLI power circuit. initial two signals. These four signals are ready to give to IGBT
which Inare in the
Figure 3-level
10a, FC-MLI
all the power
gate pulses arecircuit.
applied to the different IGBT of FC-MLI following Table 5 of
In Figure
a sequence of a10a, all the gate
waveform pulses
for gate are applied
signals. For Vdc;toswitched
the different
g1 andIGBT of FC-MLI
g4 are conduct.following
For 0Vdc;Table
g1 and 5
of a sequence of a waveform for gate signals.
g3 are conducted and for −Vdc; g3 and g4 are conducted. For Vdc; switched g1 and g4 are conduct. For 0Vdc; g1
and g3 are conducted and for −Vdc; g3 and g4 are conducted.
(a)
(b)
Figure 10. Cont.

Electronics 2019, 8, 1329 17 of 37
(c)
Figure 10.
Figure (a) Power
10. (a) Power circuit
circuit of
of 3-
3- level
level FC-MLI;
FC-MLI; (b)
(b) control
control circuit
circuit of
of 3-
3- level
level FC-MLI;
FC-MLI; (c)
(c) phase
phase output
output
voltage waveform of 3-level FC-MLI.
voltage waveform of 3-level FC-MLI.
Table 5. Voltage levels of 3-level flying-capacitor multilevel inverter and switching states.
Table 5. Voltage levels of 3-level flying-capacitor multilevel inverter and switching states.
Voltage g1 g2 g3 g4
Voltage g1 g2 g3 g4
Vdc 1 1 0 0
𝑉𝑑𝑐 1 0 1
1 0 1
00 0
0 1−Vdc 0 0 0 1 11 0
−𝑉𝑑𝑐 0 0 1 1
2.3.2. Five-Level FC-MLI PSCAD Simulations

2.3.2. Five-Level FC-MLI PSCAD Simulations.
Figure 11b,
Figure 11b, the control circuit
the control circuit waveforms
waveforms are are generated
generated by by comparison
comparison of of the
the DC
DC signal
signal (2(2 V and
V and
44 V) with the sinusoidal waveforms (5 V RMS). Changing the values of
V) with the sinusoidal waveforms (5 V RMS). Changing the values of the DC voltage will change the DC voltage will change the
gategate
the pulse widths.
pulse FourFour
widths. signals g1, g2,
signals g1,g3,
g2,andg3, g4
andareg4available from from
are available the direct comparator.
the direct The other
comparator. The
other four signals are obtained using the NOT with initial four signals. These 8 gate signals aretoready
four signals are obtained using the NOT with initial four signals. These 8 gate signals are ready give
to IGBT
to give towhich
IGBTare in the
which areFC-MLI power circuit.
in the FC-MLI power circuit.
In Figure
In Figure 11a,11a, all
all the
the available
available gate
gate signals
signalsare aregiven
givento toIGBT
IGBTof ofFC-MLI
FC-MLIInverter,
Inverter,following
followingTable
Table6
of the sequence of a waveform for gate signals. Here the total voltage
6 of the sequence of a waveform for gate signals. Here the total voltage is divided into a capacitor is divided into a capacitor
bridge. Each
bridge. Each capacitor
capacitor (C1,(C1, C2,
C2, C3,
C3, and
and C4)
C4) of of the
the first
first line
line gets
gets charged
charged withwith Vdc/4
Vdc/4 voltage. Also,
voltage. Also,
each intermediate capacitor (C1’, C2’, and C3’) gets
each intermediate capacitor (C1’, C2’, and C3’) gets charged by +Vdc/4. charged by +Vdc/4.
+Vdc/2:
+Vdc / 2: Switched
Switched g1, g1, g2,
g2, g3,
g3, and
and g4g4 are
are turned
turned ON.ON. Hence, current flow
Hence, current flow from
from capacitor
capacitor C2, C2, C1,
C1,
g1, g2,
g1, g2, g3,
g3, g4
g4 to
to the
the load.
load. Hence,
Hence, by by two
two capacitor-discharge,
capacitor-discharge,(+Vdc/4 (+Vdc/4+Vdc/4)
+Vdc/4) == +Vdc/2
+Vdc/2 is is available
available atat
load side. +Vdc/4: Similarly, g1, g2, g3, and g5 are turned on. Current flows,
load side. +Vdc/4: Similarly, g1, g2, g3, and g5 are turned on. Current flows, from capacitor C2, C1, from capacitor C2, C1, g1,
g2, g3,
g1, g2, C3’
g3, and
C3’ g5andtog5 thetoload. HenceHence
the load. the voltage across across
the voltage the load is load
the Vdc/4. is In otherIn
Vdc/4. words,
otherC3’ nullifies
words, C3’
the voltage
nullifies thefromvoltageonefrom
of the capacitors
one (C1 or C2)
of the capacitors (C1toor
load
C2)voltage. Hence only
to load voltage. Hencehalfonly
voltage
half (of +Vdc/2)
voltage (of
is available
+Vdc/2) at the load.
is available 0Vdc:
at the load.g1,0Vdc:
g2, g5,g1,g6 are
g2, g5,turned
g6 areon. Similar
turned on.to the previous
Similar operation,
to the previous both C2’
operation,
both C2’ capacitors provide the opposite voltage to C1 and C2. Hence equivalent voltage at the load
is 0, −Vdc/4: g1, g5, g6, g7 are turned on. Current flows through the C2, C1, g1, C2’, C2’, C2’, g5, g6,
Electronics 2019, 8, 1329 18 of 37
capacitors provide the opposite voltage to C1 and C2. Hence equivalent voltage at the load is 0, −Vdc/4:
g1, g5, g6, g7 are
Electronics 2019,turned on. Current
8, x FOR PEER REVIEW flows through the C2, C1, g1, C2’, C2’, C2’, g5, g6,18g7, and load.
of 38
Now here two capacitors charged with +Vdc/4, +Vdc/4, and three capacitors are in opposite direction
g7, and load. Now here two capacitors charged with +Vdc/4, +Vdc/4, and three capacitors are in
and charged by +Vdc/4, +Vdc/4, +Vdc/4 hence the effective voltage at the load is (+2Vdc/4) – (+3Vdc/4)
opposite direction and charged by +Vdc/4, +Vdc/4, +Vdc/4 hence the effective voltage at the load is
= −Vdc/4. −Vdc/2:
(+2Vdc/4) g5, g6, =g7,
– (+3Vdc/4) g8 are
−Vdc/4. turned
−Vdc ON.
/ 2: g5, g6, Current
g7, g8 areflows
turnedfrom C4, C3 flows
ON. Current to load (reverse
from direction)
C4, C3 to
Back to load
C4. (reverse
Hence, the voltage
direction) of two
Back to C4.capacitors
Hence, theisvoltage
available at load
of two side (−Vdc/4
capacitors + (−Vdc/4)
is available = −Vdc/2.
at load side
(−Vdc/4 + (−Vdc/4) = −Vdc / 2.
(a)
(b)
Figure 11. Cont.

Electronics 2019, 8, 1329 19 of 37
(c)
Figure 11. (a) 11.

Figure Power circuit
(a) Power of 5-level
circuit FC-MLI;
of 5-level FC-MLI; (b) controlcircuit
(b) control circuit
of of 5-level
5-level FC-MLI;
FC-MLI; (c) output
(c) phase phase output
voltage voltage
waveform of 5-level
waveform FC-MLI.
of 5-level FC-MLI.
Table 6. Voltage
Table levels
6. Voltage levelsofof5-level FC-MLIand
5-level FC-MLI and switching
switching states.
states.
Voltage Voltage
g1 g2g1 g2g3 g3 g4g4 g5 g6 g6 g7
g5 g7
g8 g8
𝑽𝒅𝒄 1Vdc 1 1 1 0 0 0 0
𝟐 2 1 1 1 1 0 0 0 0
𝑽𝒅𝒄 1Vdc
4 11 11 1 0 0 11 0 0 0 00 0
𝟒 0 1 1 0 0 1 1 0 0
0 1
−Vdc 11 00 0 0 0 11 1 1 1 00 0
−𝑽𝒅𝒄 1 4
−Vdc 0 0 0 1 1 1 0
0 0 0 0 1 1 1 1
𝟒 2
−𝑽𝒅𝒄 0 0 0 0 1 1 1 1
𝟐
3. Performance Evaluations of Different Multilevel Inverters and Characteristics Overview
The3.various
Performance Evaluations
topologies of Different
discussed, Multilevel
described, Inverters and
and analyzed till Characteristics Overview
now are comprehensively compared
in this section
Theonvarious
the basis of different
topologies performance
discussed, described,parameters
and analyzedsuchtillasnow
number capacitors and diodes,
are comprehensively
switches,compared in this
flexibility, section oncapacitor,
balancing the basis ofand
different
cost performance
in Table 7. parameters such as number capacitors
Forand diodes, switches, flexibility, balancing capacitor, and cost in Table 7.
high-voltage applications, for instance high-voltage DC (HVDC), a relatively high voltage
level can be chosen for aTable modular multilevel
7. Comparative inverter
assessment [5,32–53]
of various to inverters.
multilevel the total required current THD,
and dv/dt. For medium- and low-voltage applications, five and three-level inverters for A-NPC [54–58]
and other FC-MLI inverters may be better suited to current specifications. Currently, multilevel
inverters have been suggested in motor drives, flexible AC transmission systems (FACTS) and HVDC.
As per the studies conducted in [2,59–67], the positive points, negative points, methods of modulation,
and application of these inverters are epitomized in Table 8.
Electronics 2019, 8, 1329 20 of 37
Table 7. Comparative assessment of various multilevel inverters.
IT DC-MLI FC-MLI CHB-MLI A-NPC MMC

MS 2(m − 1) 2(m − 1) 2(m − 1) 3(m − 1) 2(m − 1)
MD 2(m − 1) 2(m − 1) 2(m − 1) 3(m − 1) 2(m − 1)
CD (m − 1) (m − 2) - - - -
(m−1)
DBC (m − 1) (m − 1) 2 - -
(m−1)(m−2)
BC - 2 - - -
RD Not Redundant Redundant Redundant Redundant Redundant
F Not√ Flexible Not√
Flexible Flexible
√ Flexible
√ Not√
Flexible
MDV 2 2 Va 2 2 Va 2 2 Va 2 2 Va 2 2 Va
Vdc Vdc Vdc Vdc Vdc
CVR m−1 m−1 m−1 m−1 m−1
ACC Ia Ia Ia Ia Ia
C M M M H H
Note: IT: inverter types, DC-MLI: diode-clamped multilevel inverter, FC-MLI: flying-capacitor multilevel inverter,
CHB-MLI: cascade H-bridge multilevel inverter, A-NPC: active NPC, MMC: modular multilevel converter, MS: main
switches, MD: main diodes, CD: clamping diodes, DBC: DC-bus capacitor, BC: balancing capacitor, RD: redundancy,
F: flexibility, MDV: minimum DC voltage, CVR: component voltage rating, ACC: active component current, C: cost,
H: high, M: medium.
Table 8. Performance summary of multilevel inverter.
R T A D MT AP
[2,59–64] DC-MLI Low cost and fewer Unequal distribution of Pulse width modulation Renewable energy;
components due to a power losses; (PWM) carrier variable speed motor drive;
smaller number of DC-link voltage balance modulation (based static var compensation;
capacitors therefore limits the converter to zero-sequence injection); HVDC/AC transmission
simple structure; three-level topology. Space vector pulse width lines.
equalized blocking modulation (SVPWM)
voltage of power. method (based space
vector selection).
[64–68] FC-MLI Modular structure; The poor dynamic Phase-shifted carrier Renewable energy;
possessing a large response of dc voltage PWM (achieves neutral motor drive;
number of balancing; balancing of flying induction motor control
redundant states; large amounts of flying capacitors). using direct torque control
each branch can be capacitors reduce the circuit;
analyzed system reliability; sinusoidal current rectifiers;
independently. pre-charging capacitors static var generation.
is difficult.
[69–71] CHB-MLI Modular structure is Separate DC sources are Phase-shifted carrier Renewable energy;
easier to analyses; required; PWM (achieves DC power source utilization;
possessing fault isolated transformers equalization of Power factor compensators;
tolerant capability; increase the system power losses). flexible alternating current
same switching volume. transmission system
frequencies for all (FACTS);
the switches. electric vehicle drives.
[32–51,72–76] MMC Modular structure; Low-frequency voltage Nearest-level High-voltage DC (HVDC)
easy to achieve fault oscillation of floating modulation (achieves transmission, A static
tolerant operation. capacitors; equalization of power synchronous compensator
complex data acquisition losses and dc voltage (STATCOM)
and communication for balance).
each power cell.
[54–58] A-NPC Simple structure; Unequal usage of Hybrid phase-shifted Renewable energy
easily extendable to a switches and flying PWM (low frequency for
higher level by capacitors; high voltage switches
stacking flying. requires series switches and high frequency for
to handle high voltage. flying capacitor cells).
Note: R: Reference, T: Topology, A: Advantage, D: Disadvantage, MT: Modulation Technique, AP: Application.
3.1. Choosing Topology

Discussed all multilevel inverters are utilized to generate a smooth waveform, mostly for medium
voltage drives. Out of three FC-MLI [19,77–82] is relatively new compared to DC-MLI and CHB-MLI.
Moreover, FC-MLI has some unique benefits over DC-MLI, including the truancy of clamp diodes and
the ability to adjust the voltage of the flying capacitor by selecting an excess state. Even the voltage level
is higher than 3 [81]. Unlike CHB-MLI, no separate voltage sources are required. Also, there are two
Discussed all multilevel inverters are utilized to generate a smooth waveform, mostly for
Electronics
medium 8, 1329 drives. Out of three FC-MLI [19,77–82] is relatively new compared to DC-MLI and 21 of 37
2019,voltage
CHB-MLI. Moreover, FC-MLI has some unique benefits over DC-MLI, including the truancy of clamp
diodes and the ability to adjust the voltage of the flying capacitor by selecting an excess state. Even
typesthehaving
voltagesome
level deficiencies,
is higher thansuch asUnlike
3 [81]. most DC in CHB-MLI.
CHB-MLI, Losses
no separate are higher
voltage sourcesinarethe DC-MLI. but
required.
FC-MLI has introduced more potential outcomes to regulate the DC-link capacitor’s voltage
Also, there are two types having some deficiencies, such as most DC in CHB-MLI. Losses are higher contrasting
to another multilevel
in the DC-MLI. buttopology
FC-MLI that uses redundant
has introduced switchingoutcomes
more potential arrangements. An FC-MLI
to regulate topology
the DC-link
is designed forvoltage
capacitor’s highercontrasting
voltage and tolower
anothervoltage-distortion
multilevel topology performance. Moreover,switching
that uses redundant in an FC-MLI,
arrangements.
capacitors are usingAn for
FC-MLI topology
clamping is designed
the power over for
thehigher voltage
devices. Also,and lower isvoltage-distortion
FC-MLI appropriate to heavy
load systems. Meanwhile, induction motors are utilizing as a load in many industrialthe
performance. Moreover, in an FC-MLI, capacitors are using for clamping the power over devices. [78].
applications
Also, FC-MLI is appropriate to heavy load systems. Meanwhile, induction motors are utilizing as a
3.2. load in many Simulations
MULTISIM industrial applications
of FC-MLI[78].
3.2.Three-Level
3.2.1. MULTISIM Simulations of FC-MLI Simulations
FC-MLI MULTISIM
In the
3.2.1. above Figure
Three-Level 12a,MULTISIM
FC-MLI the controlSimulations
circuit has a hierarchical block which will be explained in the
next section. Here, the same power circuit is used as the above explained. There are three capacitors.
In the above Figure 12a, the control circuit has a hierarchical block which will be explained in
Among three
the next capacitors,
section. Here, two capacitors
the same power make
circuitthe DC bus
is used andabove
as the remaining capacitor
explained. There acts as a flying
are three
capacitor
capacitors. Among three capacitors, two capacitors make the DC bus and remaining capacitor acts V
which is used for the clamping voltage at different levels. Here we have used 20 as DC as
source power
a flying supply.
capacitor There
which are for
is used four
theMOSFET
clampingswitches
voltage atwhich arelevels.
different triggered by have
Here we the gate
usedpulses
20 V that
generate
DC as from
sourcethe control
power circuit.
supply. ThereFour optocouplers
are four MCT 2Ewhich
MOSFET switches are used for the isolation
are triggered purpose.
by the gate pulses
that generate from the control circuit. Four optocouplers MCT 2E are used for the isolation purpose.
(a)
(b)
Figure (a)(a)Power
12.12.
Figure Powercircuit
circuit of
of 3-Level FC-MLIMULTISIM
3-Level FC-MLI MULTISIM simulations;
simulations; (b) control
(b) control circuitcircuit of 3-level
of 3-level
FC-MLI MULTISIM simulations.
We have generated four gate pulses using the OP-AMPs. In Figure 12b, we have used one OP-
AMP as a ZERO CROSSING DETECTOR and another as a SCHMITT TRIGGER. The output of the
SCHMITT TRIGGER is a square wave but shifted from the output of the ZERO CROSSING
DETECTOR (ZCD). The shifting can vary by varying the POT of 50Kohm. If the shifting is higher
than the output, that has the higher width of zero pulses.
(b)
Electronics 2019, 8, 1329 22 of 37
Figure 12. (a) Power circuit of 3-Level FC-MLI MULTISIM simulations; (b) control circuit of 3-level
We have generated four gate pulses using the OP-AMPs. In Figure 12b, we have used one
We have
OP-AMP generated
as a ZERO four gate
CROSSING pulses using
DETECTOR andthe OP-AMPs.
another In FigureTRIGGER.
as a SCHMITT 12b, we have
Theused oneofOP-
output the
AMP as a ZERO CROSSING DETECTOR and another as a SCHMITT TRIGGER.
SCHMITT TRIGGER is a square wave but shifted from the output of the ZERO CROSSING DETECTOR The output of the
SCHMITT TRIGGER is a square wave but shifted from the output of the ZERO
(ZCD). The shifting can vary by varying the POT of 50Kohm. If the shifting is higher than the output, CROSSING
DETECTOR
that (ZCD).width
has the higher The shifting can vary by varying the POT of 50Kohm. If the shifting is higher
of zero pulses.
than As
thein
output,
Figure 13. we can see the width
that has the higher of zero
all 3 levels of pulses.
output. Here we used 20 V DC as a power source,
As inwe
therefore Figure
have 213. we canlevels
different see the
of all 3 levels
(Vdc/2) =10ofV,output. Here we
and (−Vdc/2) used
= −10 V. 20
ByVchanging
DC as a the
power source,
DC voltage
therefore we have 2 different levels of (Vdc/2) =10 V, and (−Vdc/2) = −10
in the OP-AMP comparator, we can change the width of output zero voltage. This width of zeroV. By changing the DC
voltage in the OP-AMP comparator, we can change
voltage decides the amount of reactive power flow in the system.the width of output zero voltage. This width of
zero voltage decides the amount of reactive power flow in the system.

(a)
(b)
Figure 13. (a) Gate pules of 3-level FC-MLI; (b) phase output voltage waveforms of a 3-level FC-MLI
using MULTISIM.
using MULTISIM.
3.2.2. 5-Level FC-MLI MULTISIM Simulations.

The full set-up is shown in Figure 14a. That is divided into the following two parts. That diagram
is the same as explained above. Here, we have used MOSFET 2N6659 as a switching device. And the
similar three-level optocoupler MCT 2E is used for isolation. We have demonstrated the purely
resistive load for the simplicity. We can change the load as per the relevant applications.
(b)
using MULTISIM.
Electronics 2019, 8, 1329 23 of 37

3.2.2. 5-Level FC-MLI MULTISIM Simulations.
The full set-up is shown in Figure 14a. That is divided into the following two parts. That diagram
3.2.2. 5-Level
is the same as FC-MLI
explained MULTISIM Simulations
above. Here, we have used MOSFET 2N6659 as a switching device. And the
similar
The full set-up is shown in Figure 2E
three-level optocoupler MCT 14a.isThat
usedis for isolation.
divided Wefollowing
into the have demonstrated the purely
two parts. That diagram
resistive load for the simplicity. We can change the load as per the relevant applications.
is the same as explained above. Here, we have used MOSFET 2N6659 as a switching device. And the
Now
similar as the above
three-level explained
optocoupler MCT theory, 4 switches
2E is used get turning
for isolation. on at
We have any time andthe
demonstrated remaining four
purely resistive
switches get turning off at any time what you want. Therefore, each
load for the simplicity. We can change the load as per the relevant applications.switch gets 1/4th voltage of
power supply as a reverse burden.
(a)
(b)
Figure 14. (a).

Figure 14. Power circuit
(a). Power circuit of
of 5-Level
5-LevelFC-MLI
FC-MLIMULTISIM
MULTISIMsimulations;
simulations;(b)
(b)control
controlcircuit
circuitofof5-Level
5-Level
FC-MLI
FC-MLI MULTISIM
MULTISIM simulations.
simulations.
Figure 14b for the control circuit, we have used the two sinusoidal power supplies as the
reference by comparing it with DC power supply. We have four different outputs having four gates
from the required eight pulses. We can obtain the NOT gate combination from the remaining four
pulses. Thus, we can get eight pulses and these pulses are applied to the power circuit through an
optocoupler.
Electronics 2019, 8, 1329 24 of 37
Now as the above explained theory, 4 switches get turning on at any time and remaining four
switches get turning off at any time what you want. Therefore, each switch gets 1/4th voltage of power
supply as a reverse burden.
Figure 14b for the control circuit, we have used the two sinusoidal power supplies as the reference
by comparing it with DC power supply. We have four different outputs having four gates from the
required eight pulses. We can obtain the NOT gate combination from the remaining four pulses. Thus,
we can get eight pulses and these pulses are applied to the power circuit through an optocoupler.
In Figure 15a–c we can see all the 5-levels output and gate pulses. Here we have used 20 V DC.
As a source, we have 4 different levels of (Vdc/2) = 10 V, (Vdc/4) = 5 V, 0 V, (−Vdc/4) = −5 V, (Vdc/2) =
−10 V. By changing the DC. voltage in the OP-AMP comparator; we can change the width of zero for
output
Electronics voltage.
2019, 8, ThisREVIEW
x FOR PEER width of zero voltage decides the amount of reactive power flow in the system.
26 of 38
(a)
Figure 15. Cont.
(b)
Electronics 2019, 8, 1329 25 of 37

(a)
(b)
(c)
Figure 15. (a) S1–S4 gate pules of 5-level FC-MLI; (b) S5-S8 gate pules of 5-level FC-MLI; (c) Phase
Figure 15. (a) S1–S4 gate pules of 5-level FC-MLI; (b) S5-S8 gate pules of 5-level FC-MLI; (c)
output voltage waveforms of a 5-level FC-MLI using MULTISIM.
Phase output voltage waveforms of a 5-level FC-MLI using MULTISIM.
4. Harmonics Analysis of FC-MLI
4. Harmonics Analysis of FC-MLI
4.1. Total Harmonic Distortion (THD)
4.1. Total The
Harmonic
THD isDistortion (THD)
a presenting measurement of harmonic distortion and defined the proportion between
harmonic components and the fundamental frequency of the power. THD is utilized to characterize
The THD is a presenting measurement of harmonic distortion and defined the proportion
the linearity of audio systems and the power quality of electric systems.
between harmonic components and the fundamental frequency of the power. THD is utilized to
characterize the linearity of audio systems and the power quality of electric systems.
If the input signal is sinusoidal, the computation often corresponds to the proportion of the
powers of all the harmonic frequencies beyond the power of the 1st harmonic and the main
frequency.
Electronics 2019, 8, 1329 26 of 37
If the input signal is sinusoidal, the computation often corresponds to the proportion of the powers
of all the harmonic frequencies beyond the power of the 1st harmonic and the main frequency.
P∞ i
P2 + P3 + P4 + · · · + P∞ i=2 P
THD = = (8)
P1 P1
Which can equivalently be written as:
Ptotal − P1
THD = (9)
P1
It is also defined as the amplitude ratio, not the power ratio which results in the determination of
THD given the square root to the above equation.
q
V22 + V32 + V42 + · · · + V∞
2
THD = (10)
V1
4.1.1. Harmonics Analysis of 3-Level FC-MLI

As shown in Figure 16, the analysis can be seen that for lower order mainly 5th and 7th harmonics
are predominant. Here the third harmonic has been reduced very much.
Figure 16.16.
Figure Fourier analysis
Fourier of of
analysis 3-level FC-
3-level MLI.
FC- MLI.
If If
wewechange
change thethe
pulse
pulse width
widthof of
our gate
our pulses
gate pulsesthen thethe
then harmonic
harmonic reduction
reduction can bebe
can changed;
changed;
more
morespecifically, THD
specifically, THD cancan
be be
changed.
changed. Because of changing
Because our our
of changing pulse width,
pulse the starting
width, angleangle
the starting of
output wavewave
of output changes and and
changes thusthus
the the
harmonics alsoalso
harmonics changes. However,
changes. However, if we compare
if we compare this with
this with
conventional
conventional two-level
two-levelinverter then
inverter wewe
then cannot find
cannot any
find harmonics
any harmonics in in
this
thistopology
topology compared
compared with
with
thethe
two-level
two-levelinverter.
inverter.
In Table 9 shows the analysis of THD. The total harmonic distortion shows that how much
In Table 9 shows the analysis of THD. The total harmonic distortion shows that how much
percentage harmonics are present in the waveform or how much the waveform is disturbed from an
percentage harmonics are present in the waveform or how much the waveform is disturbed from an
actual sine wave.
actual sine wave.
Table 9. Total harmonic distortion (THD).
Fourier Analysis for V (25)

DC components 0.142395
No. Harmonics 15
THD 28.8803%
Grid Size 512
Electronics 2019, 8, 1329 27 of 37
Table 9. Total harmonic distortion (THD).

DC Components 0.142395
No. Harmonics 15
Electronics 2019,
THD8, x FOR PEER REVIEW
28.8803% 28 of 38
Grid Size 512
Harmonics
Interpolation Frequency
1 Magnitude Phase Norm. Mag Norm.
Degree Phase
Harmonics
1 Frequency
50 Magnitude
10.7723 Phase
147.086 Norm. Mag1 Norm. Phase0
2 1 10050 10.7723
0.0359127 147.086
−87.093 10.00333381 0 −234.18
3 2 100
150 0.0359127
0.482066 −87.093
−91.605 0.00333381
0.0447506 −234.18−238.69
3 150 0.482066 −91.605 0.0447506 −238.69
4 4 200
200
0.0370429
0.0370429
−90.48
−90.48
0.00343872
0.00343872 −237.57
−237.57
5 5 250
250 2.40309
2.40309 −164.03 0.223081
−164.03 0.223081 −311.11−311.11
6 6 300
300 0.0368095
0.0368095 −93.112 0.00341705
−93.112 0.00341705 −240.2 −240.2
7 7 350
350 1.2825
1.2825 129.104
129.104 0.119056 0.119056 −17.982−17.982
8 8 400
400 0.0367623
0.0367623 −94.406
−94.406 0.00341267 −241.49−241.49
0.00341267
9 450 0.470903 −113.53 0.0437143 −260.61
9 10 450
500 0.470903
0.0369758 −113.53 0.0034325
−96.153 0.0437143 −243.24−260.61
10 11 500
550 0.0369758
1.14951 −96.153 0.106709
178.466 0.0034325 31.3803−243.24
11 12 550
600 1.14951
0.0368479 178.466 0.00342062
−97.806 0.106709 −244.8931.3803
12 13 650
600 0.517375
0.0368479 111.212
−97.806 0.00342062 −35.874−244.89
0.0480284
−99.11
13 14 700
650 0.0369105
0.517375 111.212 0.0480284 −246.21−35.874
0.00342644
15 750 0.454395 −131.73 0.042818 −278.82
14 700 0.0369105 −99.11 0.00342644 −246.21
15 750 0.454395 −131.73 0.042818 −278.82
The following analysis is carried out by the MULTISIM software; here, we have found 15 numbers
The following
of harmonics. analysis isthe
While analyzing; carried out frequency
sampling by the MULTISIM
is taken assoftware;
16 kHz. This here,analysis
we have found
is also 15
carried
numbers of harmonics. While analyzing; the
out with Lagrange’s 1st degree of interpolation. sampling frequency is taken as 16 kHz. This analysis is
alsoThe
carried out with Lagrange’s 1st degree of interpolation.
above tabulated analysis gives us that mainly 5th and 7th harmonics are the predominating
Thea above
and has majortabulated analysis
part in THD gives
normal us that mainly
magnitude. 5th and
A phase 7th harmonics
is measured are thethe
by taking predominating
fundamental
and has a major part in THD normal magnitude. A phase is measured by taking the fundamental 50
50 Hz as a reference.
Hz as a reference.
4.1.2. Harmonics Analysis of 5-Level FC-MLI
4.1.2. Harmonics Analysis of 5-Level FC-MLI.
In Figure 17, the analysis shows that the major 3rd harmonics is predominant but all other has
In Figure
very low 17,Hence,
impact. the analysis shows
here THD that less
is also the major 3rdinharmonics
as given Table 10. is predominant but all other has
very low impact. Hence, here THD is also less as given in Table 10.
Figure 17. Fourier analysis of 5-level FC- MLI.

Figure 17. Fourier analysis of 5-level FC- MLI.
Table 10. Total harmonic distortion.

DC components -0.037107
Electronics 2019, 8, 1329 28 of 37
Table 10. Total harmonic distortion.

DC components −0.037107
No. Harmonics 15
THD 18.5624%
Grid Size 512
Interpolation 1
Degree
Harmonics Frequency Magnitude Phase Norm. Mag Norm. Phase
1 50 11.8044 −0.86678 1 0
2 100 0.00272927 −87.038 0.0002231207 −86.172
3 150 1.82486 −3.0824 0.154591 −2.2156
4 200 0.000617738 −38.435 0.000052331 −37.568
5 250 0.489755 174.772 0.0414891 175.638
6 300 0.00209954 69.2359 0.00017786 70.1027
7 350 0.930224 172.689 0.0788029 173.556
8 400 0.00315766 75.7679 0.000267498 76.6347
9 450 0.561122 170.638 0.0475349 171.505
10 500 0.00256501 79.3973 0.000217292 80.264
11 550 0.114071 168.906 0.00966337 169.773
12 600 0.000955366 95.2264 8.09328 × 10−05 96.0932
13 650 0.00525038 −19.574 0.000444781 −18.707
14 700 0.000845858 −137.32 7.16559 × 10−05 −136.45
15 750 0.195151 164.189 0.016532 165.055
Table 10 shows the analysis of THD. Here, only 3rd harmonic is predominating, and all others are
much lower. Now if we change the width of gate pulses the THD can be further reduced. One thing to
note is that in 3-level the THD was 28.88% while in the 5-level topology the THD is 18.56%. Hence
by increasing the levels of the output, we can reduce the total harmonics distortion. Therefore, if the
number of levels are increased, then THD is decreased.
5. Pulse width modulation (PWM) control techniques

Depending on the control strategy, the most important two types of the PWM modulation
techniques are categorized as open and closed loop. SPMW, PWM space vector, sigma-delta modulation
(SDM) are the part of open-loop PWM methods, and hysteresis, optimized current control; linear
methods are identified by closed-loop current control methods.
5.1. Open-Loop PWM Control Techniques
5.1.1. Sigma Delta PWM (SDM)

The SDM method was first classified by Jager in 1952 as a 1-bit PCM (pulse code modification)
coding method. A 1-bit coding application is created utilizing the integrated feedback block on a pulse
modulator, which is part of the encoding process, as shown in Figure 18a [83]. Sigma delta modulation
originally suggested as a way to encode 1-bit audio and video signals in digital control and modulation
problems. SDM has been classified to avoid a decrease in the power density of the altered signals with
an increase in the sampling frequency. An SDM method was acquired by adding a test and restraint
unit to the main SDM modulator, as shown in Figure 18b.
SDM modified the energy transformation operation utilizing analog to digital converters, which are
widely used in some applications because of the expansion of semiconductor technologies. Using
an inverter with resonant DC-link permits using soft switching applications rather than hard PWM
switching. This type of inverter is mainly known as zero switching losses acquired through switching to
the present time, and this technique can be adjusted according to the SDM. In Figure 18b, the modulator
output signal varies between +Vo, 0 and Vo depending on the sampling period of fs, and the output
Electronics 2019, 8, 1329 29 of 37
signal is compared to the amplitudes of input. The result of the comparison (e) is integrated (E) and
Electronics 2019, 8, xdecide
the quantizer FOR PEER
theREVIEW
output signal across from E. The multilevel SDM creates a multi-bit 30 of 38
data
stream and the output decode creates various output states that might be utilized to regulate the
regulate the activate/deactivate states of multilevel inverter switches. Figure 19 shows a schematic
activate/deactivate
regulate the states of multilevel
activate/deactivate states ofinverter switches.
multilevel Figure
inverter 19 shows
switches. a schematic
Figure diagram of a
diagram of a multilevel inverter regulated by SDM. The interaction between the19 shows
SDM a schematic
modulator and
multilevel
diagram inverter regulated
of aismultilevel by SDM. The interaction between the SDM modulator and the inverter
the inverter controlledinverter regulateddecoding
by a multilevel by SDM.logic
The interaction
block, whichbetween thethe
receives SDMSDMmodulator
signals andand
is controlled
the inverter by a multilevel
is controlled decoding
by a multilevel logic block, which receives the SDM signals and decodes
decoding logic block, which receives the SDM signals and the
decodes the inverter switching signals [84–86].
inverter
decodes switching
the show
invertersignals [84–86].
switching signals [84–86].DC link inverter, SDM might be expanded to regulate
Studies that it designed to regulate
Studies show
Studies show that
that it
it designed
designed to to regulate
regulate DC
DC link
link inverter,
inverter, SDM
SDM might
might bebe expanded
expanded to to regulate
regulate
multilevel inverters via logical interface. For SDM-regulated multilevel inverters, output faults, for
multilevel
multilevel inverters
inverters via
via logical
logical interface.
interface. ForFor SDM-regulated
SDM-regulated multilevel
multilevel inverters,
inverters, output
output faults,
faults, for
instance, unequal voltage distribution and system imbalances, might be decreased to a high
for instance,
instance, unequal
unequal voltage
voltage distribution
distribution and and system
system imbalances,might
imbalances, mightbebedecreased
decreasedtoto aa high
high
switching frequency up to 200 kHz.
switching frequency
switching frequency up up to
to 200
200 kHz.
kHz.
(a)
(a)
(b)
(b)
Figure
Figure 18.
18. Schematic
Schematicdiagram
diagramofofdelta
deltamodulation
modulation(a)
(a)simple
simple delta
delta modulator;
modulator; diagram
diagramof
of delta
delta
Figure 18.
modulation Schematic diagram of delta modulation (a) simple delta modulator; diagram of delta
modulation(b)
(b)sigma-delta
sigma-deltamodulation
modulation(SDM).
(SDM).
modulation (b) sigma-delta modulation (SDM).
Figure19.
Figure SDMcontrol
19.SDM controlofofaamultilevel
multilevelinverter.
inverter.
Figure 19. SDM control of a multilevel inverter.
5.1.2. Sinusoidal PWM (SPWM)
The most widely used method among many PWM techniques is the SPWM out of other power
The most
switching widely
inverters. Inused methodthe
the SPWM, among many of
sine wave PWM techniques
the source is the
voltage SPWM
when out of other
compared power
to a carrier
switching inverters. In the SPWM, the sine wave of the source voltage when compared to a carrier
Electronics 2019, 8, 1329 30 of 37

The most widely used method among many PWM techniques is the SPWM out of other power
Electronics
switching2019, 8, x FOR In
inverters. PEER
theREVIEW 31wave
SPWM, the sine wave of the source voltage when compared to a carrier of 38
of triangular type to produce gate signals for the inverter switch. Energy debauchery can be considered
wave of triangular type to produce gate signals for the inverter switch. Energy debauchery can be
a major problem for high-power applications. A basic SPWM frequency control method has been
considered a major problem for high-power applications. A basic SPWM frequency control method
suggested to reduce the switching losses. SPWM multi-carrier regulate method has also been executed
has been suggested to reduce the switching losses. SPWM multi-carrier regulate method has also
to enhance the performance of operated multilevel inverters and is categorized as per perpendicular
been executed to enhance the performance of operated multilevel inverters and is categorized as per
or horizontal carrier signal adjustment. Perpendicular carrier distribution methods are called phase
perpendicular or horizontal carrier signal adjustment. Perpendicular carrier distribution methods are
dissipation (PD), phase opposition (POD) and alternative phase dissipation (APOD); however, the
called phase dissipation (PD), phase opposition (POD) and alternative phase dissipation (APOD);
horizontal arrangement is called the phase shift control method (PS). Even though PS-PWM is only
however, the horizontal arrangement is called the phase shift control method (PS). Even though PS-
useful for CHB-MLI and FC-MLI, PD-PWM is more useful for DC-MLI [87].
PWM is only useful for CHB-MLI and FC-MLI, PD-PWM is more useful for DC-MLI [87].
From the above discussion, multicarrier SPWM regulates methods is shown in Figure 20a PD,
From the above discussion, multicarrier SPWM regulates methods is shown in Figure 20a PD,
(b) POD, (c) APOD, (d) PS. SPWM is the mainly utilized PWM control technique because of its many
(b) POD, (c) APOD, (d) PS. SPWM is the mainly utilized PWM control technique because of its many
advantages, such as the simple implementation of lower harmonic output signals per other methods
advantages, such as the simple implementation of lower harmonic output signals per other methods
and lower transmission dissipations. In the SPWM, a high-frequency triangular carrier signal is
and lower transmission dissipations. In the SPWM, a high-frequency triangular carrier signal is
analyzed to a low-frequency sine wave signal in an analog or digital device. The frequency of the sine
analyzed to a low-frequency sine wave signal in an analog or digital device. The frequency of the sine
wave modulation signal determines the required frequency of the line voltage at the output of the
wave modulation signal determines the required frequency of the line voltage at the output of the
inverter [88].
inverter [88].
20. Multi-carrier
Figure 20.
Figure Multi-carrier sinusoidal
sinusoidalPWM
PWM(SPWM)
(SPWM)control
controlmethods:
methods:(a)(a)
PD, (b)(b)
PD, POD, (c) (c)
POD, APOD, (d) PS.
APOD, (d)
PS.
5.2. Closed-Loop PWM Control Techniques
Most widely
5.2. Closed-Loop usedControl
PWM applications of PWM converters, like drives of a motor, active filters and many
Techniques
more, need a control form consisting of an inner current feedback loop. A multilevel inverter system
Most widely used applications of PWM converters, like drives of a motor, active filters and many
uses photovoltaic (PV) or wind power sources to combine renewable power sources into the grid.
more, need a control form consisting of an inner current feedback loop. A multilevel inverter system
Several methods have been conducted to reduce harmonics by utilizing current regulate for active
uses photovoltaic (PV) or wind power sources to combine renewable power sources into the grid.
power filter or by connecting a photoelectric and wind generator integrated to grid applications of a
Several methods have been conducted to reduce harmonics by utilizing current regulate for active
multilevel inverter. Current control methods are primarily discussed in terms of hysteresis current
power filter or by connecting a photoelectric and wind generator integrated to grid applications of a
control and line current control [89–92].
multilevel inverter. Current control methods are primarily discussed in terms of hysteresis current
Hysteresis modulation is a current regulate technique in which the load current follows the
control and line current control [89–92].
reference current in the hysteresis band in non-linear load application of multilevel inverter. Figure 21a
Hysteresis modulation is a current regulate technique in which the load current follows the
is a schematic layout of the hysteresis regulation of the H-bridge, and Figure 21b illustrates the
reference current in the hysteresis band in non-linear load application of multilevel inverter. Figure
fundamental law of the hysteresis modulation. The employed controller creates a sinusoidal source
21a is a schematic layout of the hysteresis regulation of the H-bridge, and Figure 21b illustrates the
current that of desired magnitude and also frequency, which is analyzed according to the actual current.
fundamental law of the hysteresis modulation. The employed controller creates a sinusoidal source
If the current surpasses the higher level of the hysteresis band, it must choose the next higher voltage
current that of desired magnitude and also frequency, which is analyzed according to the actual
level to try to force the current error to zero. However, the voltage level of the inverter might be not
current. If the current surpasses the higher level of the hysteresis band, it must choose the next higher
enough to reset the current error to zero, and the inverter must move to the further higher voltage level
voltage level to try to force the current error to zero. However, the voltage level of the inverter might
to obtain the correct voltage level. Consequently, the current returns to the hysteresis band and the
be not enough to reset the current error to zero, and the inverter must move to the further higher
current follow the reference current in the hysteresis band. The three hysteresis controllers correctly
voltage level to obtain the correct voltage level. Consequently, the current returns to the hysteresis
select the voltage level are explained as offset band three-level, double band three-level, and time-based
band and the current follow the reference current in the hysteresis band. The three hysteresis
three-level hysteresis controllers [86,91–94].
controllers correctly select the voltage level are explained as offset band three-level, double band
three-level, and time-based three-level hysteresis controllers [86,91–94].
Considering this to be a different method of multilevel inverter usage, the grid connection to the
inverter must need current regulating. Linear current regulators are categorized as ramp
comparators, stationary vector, and synchronous vector regulator. The ramp regulator uses the
Electronics 2019, 8, 1329 31 of 37
Considering this to be a different method of multilevel inverter usage, the grid connection to the
inverter must need current regulating. Linear current regulators are categorized as ramp comparators,
stationary vector, and synchronous vector regulator. The ramp regulator uses the output ripple and
Electronics
feedback2019, 8, x FOR PEER
to regulate REVIEW
the switching 32 of 38
instantly. In a 3-phase isolated neutral load method, the 3-phase
current must have a zero-sum. Thus, linear compensation and the required two reference voltages of a
method, the 3-phase current must have a zero-sum. Thus, linear compensation and the required two
three-phase inverter can be determined by utilizing 2 to 3 phase AB/ABC conversion blocks as shown
reference voltages of a three-phase inverter can be determined by utilizing 2 to 3 phase AB / ABC
in Figure 22.
conversion blocks as shown in Figure 22.
The main linear current regulator comprises a tracking controller with an equivalent integrator for
The main linear current regulator comprises a tracking controller with an equivalent integrator
photovoltaic converters. Numerous harmonic compensation strategies can be found in the following
for photovoltaic converters. Numerous harmonic compensation strategies can be found in the
articles on re-control and a linear resonant harmonic compensator [86,95–97].
following articles on re-control and a linear resonant harmonic compensator [86,95–97].
(a)
(b)
Figure 21. Hysteresis current control: (a) schematic diagram of a H-bridge cell with hysteresis regulator;
Figure 21. Hysteresis current control: (a) schematic diagram of a H-bridge cell with hysteresis
hysteresis current control (b) hysteresis current band and voltage curves of load feedback.
regulator; hysteresis current control (b) hysteresis current band and voltage curves of load feedback.
Electronics 2019, 8, 1329 32 of 37
Figure 22.
Figure The schematic
22. The schematic plot
plot of
of stationary linear current regulator.
6. Conclusions
6. Conclusion
Many researchers and industries have acquired a multilevel inverter because of the capacities to
Many researchers and industries have acquired a multilevel inverter because of the capacities to
regulate high- and medium-power applications. Also, the sustainable power source of DC needs to be
regulate high- and medium-power applications. Also, the sustainable power source of DC needs to
changed over to AC. We demonstrate three different types of multilevel inverter, such as a cascade
be changed over to AC. We demonstrate three different types of multilevel inverter, such as a cascade
H multilevel inverter, a diode-clamp multilevel inverter, and a flying-capacitor multilevel inverter.
H multilevel inverter, a diode-clamp multilevel inverter, and a flying-capacitor multilevel inverter.
Although all multilevel inverters are utilized to produce smoothing signals, the two types mentioned
Although all multilevel inverters are utilized to produce smoothing signals, the two types mentioned
above have some drawbacks. For example, the individual DC sources are required for each inverter in
above have some drawbacks. For example, the individual DC sources are required for each inverter
CHB-MLI inverter and DC-MLI inverter switching losses are higher. These topologies are modeled in
in CHB-MLI inverter and DC-MLI inverter switching losses are higher. These topologies are modeled
PSCADS SIMULINK. However, a flying-capacitor multilevel inverter has several features to regulate
in PSCADS SIMULINK. However, a flying-capacitor multilevel inverter has several features to
DC link capacitors compared to another multilevel topology using redundant switch configurations.
regulate DC link capacitors compared to another multilevel topology using redundant switch
From the MULTISIM simulation analysis and modeling of a flying-capacitor multilevel inverter in
configurations. From the MULTISIM simulation analysis and modeling of a flying-capacitor
three levels, THD was 28.88% while in the five-level topology the THD was 18.56%. Therefore, we can
multilevel inverter in three levels, THD was 28.88% while in the five-level topology the THD was
decrease the total harmonic distortion adopting the higher-level topology.
18.56%. Therefore, we can decrease the total harmonic distortion adopting the higher-level topology.
Author Contributions: This
Author Contributions: Thispaper
paperwaswasaacollaboration
collaborationeffort
effortamong
amongall
allauthors.
authors. All
All authors
authors conceived
conceived the
the
methodology,
methodology, conducted
conducted the
the experiment
experiment tests,
tests, and
and wrote
wrote the
thepaper.
paper.R.A.R.
R.A.R and
and S.A.P.
S.A.P analyzed,
analyzed, designed
designed and
and
development of the experiment methodologies, A.M. and C.w.L. supported the work to perform in real time and,
development
H.-J.K. verifiedofthe
theoverall
experiment methodologies, A.M. and C.W.L. supported the work to perform in real time
experiment.
and, H.J.K. verified the overall experiment.
Funding: This research was supported by Basic Research Laboratory through the National Research Foundations
Funding:
of This by
Korea funded research was supported
the Ministry by and
of Science, ICT Basic Research
Future Laboratory
Planning through the National Research
(NRF-2015R1A4A1041584).
Foundations of Korea funded by the Ministry of Science, ICT
Conflicts of Interest: The authors declare no conflict of interest. and Future Planning (NRF-2015R1A4A1041584).
Conflicts of Interest: “The authors declare no conflict of interest.”

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Electronics 2019, 8, 1329; doi:10.3390/electronics8111329 www.mdpi.com/journal/electronics

Figure 1. Two-level inverter.

2. Topologies of Multilevel Inverter

2. Topologies of Multilevel Inverter

Figure 2. Voltage source or current source inverters.

+Vdc: Switches S1, S2Table are ON. In this levels

Table 4. Voltage levels of 5-level CHB-MLI and switching states.

2.3. Flying-Capacitor Multilevel

Figure 10. Cont.

2.3.2. Five-Level FC-MLI PSCAD Simulations

Figure 11. Cont.

Figure 11. (a) 11.

Table 7. Comparative assessment of various multilevel inverters.

IT DC-MLI FC-MLI CHB-MLI A-NPC MMC

Table 8. Performance summary of multilevel inverter.

3.1. Choosing Topology

Electronics 2019, 8, x FOR PEER REVIEW 23 of 38

Electronics 2019, 8, x FOR PEER REVIEW 24 of 38

3.2.2. 5-Level FC-MLI MULTISIM Simulations.

Electronics 2019, 8, 1329 23 of 37

Electronics 2019, 8, x FOR PEER REVIEW 25 of 38

Figure 14. (a).

Figure 15. Cont.

Electronics 2019, 8, 1329 25 of 37

Which can equivalently be written as:

4.1.1. Harmonics Analysis of 3-Level FC-MLI

Table 9. Total harmonic distortion (THD).

Fourier Analysis for V (25)

Table 9. Total harmonic distortion (THD).

Fourier Analysis for V (25)

Figure 17. Fourier analysis of 5-level FC- MLI.

Table 10. Total harmonic distortion.

Fourier Analysis for V (47)

Table 10. Total harmonic distortion.

Fourier Analysis for V (47)

5. Pulse width modulation (PWM) control techniques

5.1. Open-Loop PWM Control Techniques

5.1.1. Sigma Delta PWM (SDM)

5.1.2. Sinusoidal PWM (SPWM)

Conflicts of Interest: “The authors declare no conflict of interest.”

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