Electronic Devices Vlsi

ELECTRONICS &
TELECOMMUNICATION ENGINEERING
ELECTRONIC DEVICES & VLSI
Volume - 1 : Study Material with Classroom Practice Questions
Chapter
01. Ans: (a)

1 Basics of Semiconductor
(Solutions for Vol‐1_Classroom Practice Questions)
V
 3800 
1 L
Sol: N D  5  10 22  9
cm 3 5
10  3800 
= 5 ×10 cm–3
13 100  10 1
According to mass action law = 1900 cm/sec
np  n i2
04. Ans: (d)
n n p n  n i2 Sol: For the n-type semiconductor with
N D p n  n i2 (∵nn ≃ND) n = ND and p  n i2 / N D , the hole
n i2 concentration will fall below the intrinsic
pn  value because some of the holes recombine
ND
with electrons.
pn 
1.5 10  10 2
05. Ans: (c)

5 1013
1015
= 4.5 ×106 cm–3 Sol: N A  acceptor / cm 3
1.6
n = 4000 cm2/V-sec
02. Ans: (b) p = 2000 cm2/V-sec
Sol: According to law of mass action n.p  n i2 p = p q p
Where ni = intrinsic carrier concentration. = NAqp (∵ 100% doping efficiency)
ND = doping concentration for a 1015
  1.6  10 19  2000
n- type material. 1.6
Majority carrier concentration = 0.2 mho/cm
n  ND
06. Ans: (d)
n2 Sol: According to mass action law.
p i
np  n i2
ND
n n p n  n i2
1 n p p p  n i2
p
ND
n p N A ≃ n i2
N D p n ≃ n i2
03. Ans: (b)
Sol: V = 5V
L = 100 mm 07. Ans: (a)
n = 3800 cm2/V-sec
Sol: RH = 3.6×10–4 m3/c
p = 1800 cm2/V-sec
Vdn = nE  = 9× 10–3 –m
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Let us consider n-type semiconductor Jdrift = [nn + pp]

1 J ‘’
RH 
nq 
1 Charge concentration
n
qR H
1 11. Ans: (c)

1.6 10  3.6 10  4
19
Sol: Dn = 20 cm2/s
= 1.736 ×1022 m–3 n = 1600 cm2/Vs
D kT
  VT
08. Ans: (b)  q
Sol: At equilibrium 20
No. of e density = No. of hole density  VT   12.5 mV
1600
∵ given e density is n(x1) = 10 n(x2)
 n(x1) is majority 12. Ans: (d)
 n(x2) is minority Sol: Conductivity of a semiconductor,
 P(x2) = 10P(x1)   ( n n  p P ) q
Where, µn → mobility of electrons
09. Ans: (b) µp → mobility of holes
Sol:  p  3  10 3   m n → electron concentration
p = 0.12 m2/V-sec p → hole concentration
VH = 60mV q → electron charge
1
p 
p
13. Ans: (c)
1 Sol: NA = 2.29 × 1016
3  103 
p q p N 
E Fi  E Fp  kT ln A 
1  ni 
p
3  10 1.6  10 19  0.12
3
 2.29  1016 
P = 1.736 × 1016 m–3  0.02586 ln 10 

 1.5 10 
1
RH  = 0.3682 eV
pq
≃ 0.37 eV
1

1.736  10  1.6  10 19
16
= 360 m3/C 14. Ans: (b)

Sol: Given,
10. Ans: (b) 2 wires  W1 & W2
Sol: Jdrift = nnqE + pPqE d2 = 2d1 where d = diameter of wire
Jdrift = [(n.q)n + (p.q)p]E L2 = 4L1 where L = length of wire
:4: Electronic Devices & VLSI
Relation between resistances of 17. Ans: (a)

W1 & W2 Sol: In intrinsic semiconductor,
.L L d No. of e = No. of holes
R  2 r
A r 2
.L 4L L 18. Ans: (a)
R  R 2 Sol: In P-type, as doping increases hole
d 2
d 2
d
 concentration p increases. According to
4
n2
L1 mass action law n p  i  electron
pp
R 1 d12 L1 d 22 L1 2d1 
2
  2  2 concentration decreases.
R 2 L 2 d1 L 2 d1 4L1
2
d2
19. Ans: (b)
R
 1 1  R1 = R2 Sol: In intrinsic semiconductor, electron hole
R2 pairs are generated due to external energy 
true. electron mobility is 2 to 3 times more
15. Ans: (c) than hole mobility  true. Both the
Sol: Hall voltage, VH is inversely proportional to statements are true but statement II is not a
carrier concentration correct explanation of statement I
V P P
 H2  1  1
VH1 P2 2P1 20. Ans: (a)
1 Sol: Both statement (I) and (II) are true and
 VH 2  VH1 statement (II) is the correct explanation of
2
statement (I).
16. Ans: (b)
D kT ..........
Sol:   VT CB CB
 q Eg
0.36  1.38  10 23  300 ..........
D  Eg
1.6  10 19 VB VB
= 9.315×10-3m2/sec n-type P-type
Diffusion length, L = D
 9.315  10 3  340  10 6
= 1.77×10-3m
Chapter
01. Ans: (c)

2 PN Junction Diode
04. Ans: (c)
Sol: p+
VG
VT
VS
VT
N Sol: 1 mA = IGO(e – 1) = ISO(e – 1)
IGO e0.718 /( 20.026 )

= 0.1435 /(10.026 )  4000 = 4  103
ISO e
05. Ans: (c)

Sol: In a PN Junction diode the dynamic
E I I
conductance g m  , gm  C
In P+, ‘+’ indicates heavily region and ‘n’ V VT
indicates lightly doped region. i.e. gm  IC
06. Ans: (d)

02. Ans: (a) Sol: i – v characteristic of the diode
v  0.7
2V0  1 1  i  A , v  0.7 V ….. (1)
Sol: w =
q N  N  500
 D A
From the given circuit, Loop equation :
w2 V0  VR 2 v = 10 – 1000 i, v  0.7 V ….. (2)
=
w1 V0  VR1
1 k
w2 0.8  (7.2) i
= + +
2m 0.8  (1.2) 10 V v
 
w2 = 4 m.
Eliminating ‘v’ from (1) and (2) :

03. Ans: (a)
10  1000 i  0.7 9.3
 AeDP p n 0 AeDn n P 0  i    2i
Sol: I    500 500

 LP Ln  9.3 3.1
3i  , i A  6.2 mA
AeDp p no 500 500
 I
LP
I eD P p no 07. Ans: (b) 20 

A LP Sol: Given,
1.602  10 19 12  1012 V = 0.498 V
 5.5 V 0.498 V
1 10 3 I
VT = 2 mV
= 1.92 mA/cm2
5.5  0.498 The reverse saturation current of Germanium

 I
20 diode is in the order of ‘A’ whereas that for
= 0.2501  250 mA silicon diode is ‘nA’. So, Germanium diode
has a higher reverse saturation current than
08. Ans: (a) silicon diode. Therefore, statement-II is true.
Sol: Given I12  I1  32
Given T1 = 40C T2 =? 12. Ans: (b)
Sol: In all practical cases, the reverse saturation
 T2 T1

I12  I1  2 10  current (I0) increased by 7% per oC rise in
  temperature. I0 approximately doubles for
 T2  T1
 every 10oC temperature rise for both Si and
I1  32  I1  2 10  Ge materials. So, Statement-I is true.
  dV0
T2  T1 In practical cases,  2.5 mV/oC i.e., at
dT
2 5  2 10
room temperature, the p-n junction voltage
T  T1 decreases by about 2.5 mV per oC with rise
 2 5
10 in temperature. So, statement-II is true but
T2  T1 = 50 T2 = 50 +T1 not the correct explanation of statement-I.
T2 = 90C
13. Ans: (c)
09. Ans: (b) Sol:
Sol: For either Si (or) Ge P N
dV – – – – + + + +
 – 2.5 mV/0C – – –
dT – + + + +
To maintain constant current – – – – + + + +
V2  700mV  V = – 2.5  10-3 V Depletion
region
40  20 o C o
C The depletion region of an unbiased pn-
 V2 = 650 mV  660 mV junction contains negative ions in the p-side
and positive ions in the n-side. So, an
10. Ans: (b) unbiased pn-junction develops a built-in
A C  potential at the junction with the n-side
Sol: C = 0 r  = 0 r positive and the p-side negative. Therefore,
d A d
statement-I is true.
11.7  8.85  1012 The pn diode is a passive device. The pn-
=
10  10 6 junction cannot behaves as a battery.
= 10 F Therefore statement-II is false.
11. Ans: (d)

Sol: The cut-in voltage for Germanium diode is
0.3volt whereas the cut-in voltage for silicon
diode is 0.7. So, cut-in voltage for silicon
diode is greater than that for Germanium.
Therefore, statement-I is false.
Chapter
01. Ans: (d)

3 Zener Diode
Given that, Vz = 6V
Sol: Izmin = 5mA
Rs = 200 
Rmin  ILmax
+ IL=50mA 10  6 4
I   80 mA
50 50
30V + I = Izmin + ILmax
RL
10V
− ILmax = 75 mA
−
Vz 6
R L min    80 
I L max 75 10 3
Vs = 30 – 10 = 20V
Vs2 04. Ans: (b)
Power dissipation = Sol: In –ve cycle of i/p diode forward biased, so
Rs
replace by short circuit, so o/p = i/p with
20 2 –12V in o/p only option ‘b’ exists, so using
=
200 method of elimination answer is b.
=2W
05. Ans: (d)
Sol: Given circuit,
02. Ans: (c) R
Sol: Power rating of Zener diode = 5 mW
` I Z VZ  5  10 3 +10V
12V +
3
5  10 5V 100mA to
IZ   1 mA RZ
V0 = 5V
5 500mA
: Current flows through
the circuit is = 1 mA Ze Given, source voltage
10  5 Vs = 12V
RZ   5K
1m ILmin = 100 mA
ILmax = 500 mA
03. Ans: (b) Vz = 5V
Sol: I 50
Iz min = 0A
IZ IL
Vs  Vz
+ R 
I z min  I L max
R
10V
 12  5
R
500mA
7  10 3 08. Ans: (a)

R Sol:
500
 In PN junction diode break down depends
70 on doping. As doping increases
R  R = 14 
5 breakdown voltage decreases.
 In Zener diode breakdown is less than
06. Ans: (c)
6V
Sol: Given circuit,
 It has Negative Temperature coefficient
1K (operate in R. B)
 Avalanche diode breakdown greater than
6.3 6 V.
Vi=13V V0 09. Ans: (b)

6.3 Sol: Both statement (I) and (II) are true but
statement (II) is not a correct explanation of
statement (I) because DC voltage stabilizer
circuit can be implemented by using other
V0 = 0.6 + 6.3 = 6.9 V components like Op-Amp also. There is no
need that only Zener diode to be used.
07. Ans: (a)
Sol: The ideal characteristic of a stabilizer is
constant output voltage with low internal
resistance
Chapter
01. Ans: (a)

4 Special Purpose Diodes
04. Ans: (a)
Sol: Tunnel diode Sol:
It is highly doped S.C (1 : 103) Symbol Circuit Applications
name
It is an abrupt junction (step) with both LED Direct
sides heavily doped made up of Ge (or) Band gap
GaAs
It carries both majority and minority
currents. Tunnel Fast
It can be used as oscillator diode Switching
Operate in Negative Resistance region circuits
Operate as fast switching device Varactor Electronic
diode Tuning
02. Ans: (c)
Sol: The values of voltage (VD) across a tunnel-
diode corresponding to peak and valley 05. Ans: (a)
currents are VP and VV respectively. The Sol: The tunnel diode has a region in its voltage
range of tunnel-diode voltage VD for which current characteristics where the current
the slope of its I-VD characteristics is decreases with increased forward voltage
negative would be VP  VD < VV known as its negative resistance region.
This characteristic makes the tunnel diode
03. Ans: (c) useful in oscillators and as a microwave
Sol: Schottky diode is made of metal and amplifier.
semiconductor to decrease the switching
times, hence it can be used for high
frequency applications.
Chapter
01. Ans: (b)

5 Bipolar Junction Transistor
05. Ans: (a)
Sol:  = /(1+) = 0.9803 Sol: Given  = 0.995, IE = 10mA,
 =  Ico = 0.5mA
ICEO = (1 + ) ICBO
   = 0.9803/0.995
= 0.9852   
I CEO  1  I CBO
 1  
02. Ans: (d) ICEO = (1+199)  0.5  10-6
Sol: IC = 4mA ICEO = 100A
r0  20k
VA 06. Ans: (b)
r0  Sol: ICBO is greater than ICO. Reverse leakage
IC
current double for every Ten degrees rise in
VA temperature.
 20k
IC
VA > 20k × IC 07. Ans: (b)
VA > 20 × 103 × 4 × 10–3 Sol: Given base width WB = 5010–6 cm
VA > 80 Base doping NB = 21016 cm–3
r0= &  = 10–12 F/cm
03. Ans: (d) qN B WB2
Sol: VA = 100 V Vpunch 
2
IC = 1 mA
VCE = 10 V 

1.6  1019  2  1016  50  10 6 2
2  10 12
 V 
ICQ 1  CE  = IC 1.6  2  2500
 VA  Vpunch   103  4V
2
If VA   IC = ICQ
1 08. Ans: (a)
 IC = ICQ =
10
1 Sol:  = 0.98
100 IB = 40 µA
= 0.909 mA ICBO = 1 µA
 0.98
   49
04. Ans: (b) 1   1  0.98
Sol: The phenomenon is known as “Early For a CE active BJT
Effect” in a bipolar transistor refers to a IC =  IB + (1+) ICBO
reduction of the effective base-width caused
= 49 × 40 × 10–6 + 50 × 10–6
by the reverse biasing of the base-collector
junction. = 2.01 mA
: 11 : Electronic Devices & VLSI
09. Ans: (b) 12. Ans: (b)

Sol: ICBO = 0.4 µA Sol:
ICEO = 60 µA Junction Region of
operation
ICEO = (1+) ICBO E-B C-B
I
1    CEO
I CBO F. B F.B Saturation
Region
60 F.B R.B Active Region
 = 150
0.4 R.B F.B Inverse active
 = 150 – 1 Region
= 149 R.B R.B Cut-off Region


1  13. Ans: (c)
149 Sol: High power transistors are made of Si to
 = 0.993
150 withstand high temperature : Silicon is an
indirect band gap material.
10. Ans: (c)
Sol: Variation of base width due to reverse
biased voltage across collector - base
junction is known as “Early Effect”.
E C
p n
n
WB
– +
VEB VCB
+ B –
As VCB increases, effective base width (WB)

decreases
11. Ans: (a)

Sol: Both statement (I) and (II) are true and
statement (II) is the correct explanation of
statement (I)
At very high temperature, extrinsic
semiconductors will behave as intrinsic i.e.,
charge carriers will remains constant.
Chapter
01. Ans: (d)

6 Junction Field Effect Transistor
04. Ans: (d)

Sol: VG  4.2 V to 4.4 V Sol: ID
ID  2.2 mA to 2.6 mA
I D
gm 
VGS
(2.6  2.2)  10 3
 Vds
4.4  4.2
Vp
= 2 m℧ Drain current remains constant at pinch off
region even if the drain voltage increases.
05. Ans: (c)
02. Ans: (c)
Sol: ID Sol: JFET acts as a voltage controlled current
source
IDSS
06. Ans: (a)
Sol: Mobility of electron is higher than mobility
Vgs of hole
Vt Si
Vgs = Vt ID = 0 Electron mobility : 1350 cm 2 / v  s
Hole mobility : 450 cm 2 / v  s
Vgs = 0 ID = IDSS
Ge
03. Ans: (b) Electron mobility : 3600 cm 2 / v  s
Sol: IDmax = IDss = 10 mA Hole mobility : 1800 cm 2 / v  s
VP = –4V : Low leakage current means high input
VGS = –1 V impedance
: Reverse bias increases, channel width
 V 
2 reduces (wedge shaped)
I D  I DSS 1  GS 
 VP  07. Ans: (c)
2 Sol: VP = –8 V
 1 
3
IDSS = 12 mA
 10 10 1  
 4
From the given circuit,
2
3 VG = –5 V
 10 10 3   
4 VS = 0 V
= 5.625 mA VGS = –5 V
VDS at which pinch –off region means (Ri = 0 ; Ro = )

(VDS)min = VGS – VP Gain  B.W is high
= –5 – (–8) FET is voltage controlled current source
= –5 + 8 (Ri =  ; Ro = 0)
=3V
Gain  B.W is low
08. Ans: (d) UJT is a negative resistance device and can
Sol: P. Voltage controlled device –FET (3) be used as an oscillator
Q. Current controlled device –BJT (1) UJT can be used as switch but can’t be
R. Conductivity modulation device-- amplification
IMPATT diode (4) 13. Ans: (a)
S. Negative conductance device -UJT (2) Sol: In FET majority carriers only exist.
In BJT majority & minority carriers exist.
09. Ans: (d)
Sol: IDSS = 12 mA 14. Ans: (a)
VP = –6 V Sol: D
VGS = 0 V
VDS = 7 V G N – channel FET
At VGS = 0V, ID = IDSS S
 2
 Input resistance of FET is of the order of
 V 
= 12mA  I D  I DSS 1  GS   tens (or) hundreds of mega ohms (Ms)
  VP  
  : Vgs is reverse bias.
: In reverse bias very small leakage current
10. Ans: (d) ICO flows through the gate.
Sol:
15. Ans: (c)
Device : Application
Sol: FET’s has high input impedance when
A. Diode Rectifier (3)
compared to BJT. Because of this FET’s are
more suitable at the input stage of milli
B. Transistor Amplifier (1)
voltmeter and CRO’s than BJT’s. Generally
C. Tunnel Oscillator (2)
FET has input impedance in the range of
diode
several M
D. Zener Reference
diode Voltage (4) Statement (II) is false. So, option ‘c’ is
correct
16. Ans: (d)
11. Ans: (a)
Sol: Statement (I) is false, because FET is a
2I 2  25  10 3 voltage control current source.
Sol: g m 0  DSS  =5
Vp 10 Statement (II) is true. Why because
operation of FET does not depends on
minority carrier i.e. FET operation depends
12. Ans: (b) on either electrons or holes as a majority
Sol: BJT is current controlled current source carriers.
Chapter
01. Ans: (a)

7 Optoelectronic Devices
03. Ans: (b)

Sol: Sol: Avalanche photo diodes are preferred over
100 PIN diodes in optical communication
because Avalanche photo diodes are
(APDs), extracted from avalanche gain and
excess noise measurement and higher
+
sensitivity. PIN diodes generate more noise.
–
0.4V
04. Ans: (c)
By KVL, Sol: Photo diode always operates in reverse bias.
0.4 – 100× 1.8 × 10–3–VP = 0 When no light falls on photo diode, Small
amount of reverse saturation current flows
VP = 0.4 – 100 ×1.8 ×10–3 through the device called “dark current”.
= 0.22 V 05. Ans: (a)
VP = rp I Sol: Give,
V Eg = 1.12 eV,; 1 = 1.1 m
rp  P
I 2 = 0.87 m; Eg2 =?
0.22 12400 A 0 1
 Eg   Eg
1.8 10 3  
= 122.22 
E g1 2

02. Ans: (b) E g2 1
Sol: If illumination doubled then current passing 1 1.1
through the photo diode is doubled  E g 2  E g1   1.12 
2 0.87
ID = 21.8 = 3.6mA = 1.416 eV
Voltage across photo diode is 06. Ans: (a)
= 0.4 – 3.610–3 100 Sol: Sensitivity of photo diode depends on light
= 0.4 – 0.36 intensity and depletion region width.
Vp = rpIp
07. Ans: (d)
Vp 24  1.8
rp  Sol: I D  = 0.02707 A = 27.07 mA
Ip 820
0.04
  10 3 08. Ans: (c)
3.6
= 0.01111103 Sol: Photo diode operate in R.B: Photo diode
works on the principle of photo electric
= 11.11 effect.
09. Ans: (b) 13. Ans: (d)

Sol: Voltage across PN junction diode resulting Sol: LED: F.B
in current which in turn produce photons Photo diode: R.B
and light output. This inversion mechanism
also called injection electro luminescence Zener diode: R.B
observed in LED’s. Ordinary diode: F.B
Tunnel diode: F.B
10. Ans: (b) Variable capacitance diode: R.B
Sol:  = 890 Ao Avalanche diode: R.B
1.24  10 6
 m
EG 14. Ans: (c)
Sol: Tunnel diode is always operated in forward
1.24  10 6
 bias and light operated devices are operated
890  10 10 in reverse bias. (Avalanche photo diode).
= 13.93 eV
15. Ans: (b)
11. Ans: (d) Sol: LED’s and LASER’s are used in forward
Sol: Solar cell converts optical (sunlight) energy bias.
into electrical energy. Photo diodes are used in reverse bias.
12. Ans: (b) 16. Ans: (b)

Sol: R = 0.45 A/W Sol: Both statement (I) and (II) are true but
P0 = 50 µW statement (II) is not a correct explanation of
I statement (I).
R P
P0
17. Ans: (a)
IP = R P0 Sol: Both statement (I) and (II) are true and
= 0.45 × 50 statement (II) is the correct explanation of
= 22.5 µA statement (I).
Load current = IP + I0
= 22.5 µA + 1µA
= 23.5 µA
Chapter
01. Ans: (c)

8 MOSFET
= 1011 holes
Sol: VT = 1 0
VDS = 5 – 1 = 4 V
VGS = 3 – 1 = 2 V 05. Ans: (b)
Sol: 1) since it has n-type source & drain, it is
VGS  VT = 2 – 1 = 1 V n-channel MOSFET.
VDS > VGS  VT 2) Drain current flows only when VGS > 2V,
4 > 1  Saturation it implies it has threshold voltage (Vth)
of +2V
 It is enhancement type MOSFET.
02. Ans: (d)
3) VTh = +2V
Sol: In active region (or) saturation region,
W
channel is pinched off. Number of carriers 4) g m   n C ox VGS  VTh ,
present in the channel decreases from source L
end to drain end due to potential increases transconductance depends upon electron
from source to drain. mobility.
03. Ans: (d) 06. Ans: (b)

I D2 K n [VGS 2  VT ]2  A
Sol:  Sol: C sbo  si
I D1 K n [VGS1  VT ]2 d
d = 10 nm
I D2 [1400  400] 2
 si = rsi 0
1 mA [900  400] 2 = 11.7 8.9  1012 F/m
I D 2  4 mA
04. Ans: (d)

Sol: A = 1 sq m = 1012 m2
n+ n+
d = 1 m = 1 106 m
ND = 1019/cm3
ni = 1010
A = (0.21) + (0.21) + (0.21)
No. of holes = concentration  volume
Volume = A  d = 1018 m = 3(0.21) = 0.6  1012 m2
n i2 10 20 11.7  8.9 10 12  0.6  10 12

p   19 C sbo 
n 10 10 10 9
10 holes / cm 3 10  10 6 holes / m 3 Csbo = 6.24  1015
 No. of holes = 101061018  7 fF
: 17 : MOSFET
In practical IC, this cap will provided to si

front and back sides also then area may be C d  C dep A  A
d
A = (0.61012) + (0.21) + (0.21) si
d A
A = 0.68  1012 m2 Cd
11.7  8.9 10 12  0.68  10 12 110 12
C sbo   7fF  (110 4 ) cm  0.857 m
10 10 9 7 12
10
6
07. Ans: (a)
Sol: Lov =  = 20 m 10. Ans: (b)
d = 10 nm, w = 1 m Sol: VTh = 0.5V
VG = 3V
rsi = 11.7, rox = 3.9
0 = 8.9  1012 F/m Pinch-off occurs when
VD = VG – VTh = 3 – 0.5 = 2.5V

Cov = Cox w Lov  ox w L ov
t ox 11. Ans: (a)
rox 0 Sol:
 w L ov
t ox
3.9  8.9  10 12  1  10 6  20  10 9

110 9 M1 M2
15
= 0.69  10 = 0.69 fF  0.7 fF
08. Ans: (a)

Sol: A = 1  104 cm2
20A
si = 1  1012 F/cm
ox = 3.5  1013 F/cm V
C0 = 7 pF 0.5 0.5
 A 2.5V 3V
C 0  C ox A  ox
t ox
ox 3.5 10 13 110 4
t ox  A V  2.5 V  3
C0 7 10 12 20  
0.5 0.5
= 5106 cm = 50 nm
V = 7.75 Volts
09. Ans: (b)
7.75  2.5
C0Cd I D1  10.5A
Sol:  1 pF 0.5
C0  Cd
7.75  3
7 Cd 7 I D2   9.5 A
 1 C d  pF 0.5
Cd  7 6
12. Ans: (b) Only with a positive voltage to the gate an

Sol: The input impedance of insulated gate “Inversion layer” is formed and conduction
MOSFET is very high because of Sio2 layer can take place. So statement-II is true and
and revere bias at gate to source junction correct explanation of statement-I.
(i.e.at input junction)
15. Ans: (b)
Statement (II) also true but not the correct Sol: The drain current (ID) of a MOSFET is
explanation of statement (I) controlled by the gate voltage. Therefore
13. Ans: (d) The input impedance for a MOSFET is very
and the current through the gate terminal (IG)
Sol: Statement (I) is false, for same drain current
is zero. Therefore, MOSFET is an insulated
rating n-channel MOSFET occupies less
gate FET. So statement-II is true but not the
area than p-channel MOSFET why because
correct explanation for statement-I.
electron mobility is higher than hole
mobility
14. Ans: (a)

Sol: An Enhancement type MOSFET can be
operate only in Enhancement mode. For n-
channel EMOSFET, if VGS (positive) > Vth,
than only channel will formed between
source and drain. So, for n-type EMOSFET
only positive voltage can be applied to the
gate with respec to the substrate. Therefore,
Chapter 9 Biasing
04. Ans: (b)
Biasing Sol: AC analysis,
01. Ans: (c) Vin 2M Vgs gmVgs 20K 2K Vout
V  VD 20V  12V
Sol: R D  DD   3.2 K
ID 2.5mA –
In self bias Zi
Z0
VGS = ID RS
2
 V  Zi = 2M, Z0  20K || 2K
I D  I DSS 1  GS 
 Vp 
 20
 Z0  K
 ID  11
VGS  VP 1  

 I DSS 
VGS = 1.06 V 05. Ans: (a)
V 1
R S  GS   400   V 
2
 I D  2 .5 Sol: I D  I DSS 1  GS 
 Vp 
02. Ans: (b) 2
  2
3
Sol: VG = VGS + ID RS  10  10 1   5.625mA
  8 
16  8
ID   4.4 mA
1.8 K KVL at output loop,
16  47
 
 20  2  103 I D  VDS  0
VG   5.45 V
138 
VDS  20  2  103  5.625  10 3 
VG  VGS 5.4  (2V) = 8.75V
RS    1.68K
ID 4.4 m
06. Ans: (b) (By Printing Mistake in Volume-I

03. Ans: (c)
Answer (c) is wrong, Correct answer is (b))
Sol: VDS = VDD  ID(RD + RS)
= 30 V – 4 mA(3.3K + 1.5K) Sol: By observing,
VDS = 10.8 V The circuit is common drain i.e., source

follower circuit.
VCC 02. Ans: (b)

Sol: Av(dB) = 20 log10 Av
Vin VCCS 50 = 20 log10 Av
gm = 0.01S
Rm = 10 m A v 10 (5 / 2 )  316.228
V0
03. Ans: 6.123 106 Hz

100K Sol: Small signal equivalent
1 Cgd
R 0  rd || R s ||
gm
G
= 10 M || 100 K || 100  gmVgs rd RD RL Cds
= 100  S
FREQUENCY ANALYSIS
rd||RD||RL
C1 C2 gmVgs Cds
= 8.33k
01. Ans: (d)
Sol:
RD  1 
P0 = 30W C 2  Cgd 1   ,
 Av 
Av = mid-band,
RL = 5
2
gain = gm(rd||RD||RL) = –16.66
V
P0  0
Req
RL
30  5 = V02
Ceq
V0 = 12.25 V
V0
AV 
Vi  1 
C 2  2pF1   = 2.12 pF
Av (dB) = 20 log10 Av   16.66 
20 = 20 log10 Av 1
fH 
Av = 101 = 10 2C eq R eq
V0
10 Ceq = 1 + 2.12 = 3.12 pF, Req = 8.33k
Vi
V 12.25 fH = 6.123 106 Hz
Vi  0  V  1.225 V
10 10
: 21 : Postal Coaching Solutions
6V
MOSFET BIASING
IDS1
M1
01. Ans: (b) + 5V 5V W
Sol: VT = 0.8   4
 L 1
Kn = 30  106
 W1   W  o Vx
      40 m1 IDS2
 L 1  L  2 M2
VD1  5 W
V0
  1
I D1  I D2  L 2
m2
 4(5  Vx  Vt ) 2  1Vx  Vt 
2
1 W
 n C ox   VGS1  VT  2
2  L 1  VGS1  VG  Vx  5  Vx 
1 W
  n C ox   VGS2  VT
2
  2
 2(5  Vx  Vt )  (Vx  Vt )
 L 2
VGS1  VD1  V0  Vx = 3V
= +5 – V0 04. Ans:  -7 (By Printing Mistake in Volume-I
VGS2  VG1  VS
Answer (7) is wrong, Correct answer is (–7))
= V0 – 0 = V0
 W  W Sol:
  5  V0   0.8    V0  0.8
2 2
L
 1 L
 2 gmVgs rd
V0 = 2.5V rge G Rb//RL
02. Ans: (a)
Rs

Sol:  W  VGS  VT 2 W

   VGS2  VT 
2
 L 1  L 2
1
40 (4.2 – V0)2 = 15(V0 – 0.8)2 rd RD

G gmVgs
V0 = 2.91 V RD//RL
20//20K
03. Ans: (c) Rs = 10K
Sol: From figure IDS1 = IDS2.

 g m rd R D
AV 
1
2
W
 n C 0 x   VGS1  Vt  2 R D  R s  rd  g m rD .R s
 L 1
5  10K 10K

=
1
2
W
 n C 0 x   VGS2  Vt  
2 10K  1K  10K  5mA / V.10K.1K
 L 2  7.042
05. Ans: (d)  V 

2
V2 gmRs I D  I DSS 1  GS 

Sol:  ----- (1)  VP 
Vi 1  g m R s
2
V1  g m R D  1 
3
 ----- (2)  6  10 1  
Vi 1  g m R s RD  3
+ = 10.667 mA
(1)  (2)  V1 From the given circuit
V2 Rs  VS = ID × 0.75 k
 +
V1  R D Vi  RD
2
V2 = 10.667×10–3×0.75×103
 =8V
V2  1 VGSQs = 1 V

V1 2 VG – VS= 1 V
V1 = 2V2 VG = VS + 1
=9V
18R 2
06. Ans: (c) 9
Sol: IDSS = 6 mA R 2  110M
VP = –3 V  R2 = 110 M
VGSQ = 1V
Chapter 10 CMOS & Device Technology
01. Ans: (c) 04. Ans: (b)

Sol: A B  C   DE 1
Sol: n 
2Nf
After option (c) as above answer
1
02. Ans: (a) n 10 8 sec 10 n sec
2  5 10 10 6
Sol: x 1  x 2
03. Ans: (d) Device Technology Key

Sol: Vdd
01. (c) 02. (b) 03. No Answer
04. (b) 05. (a)
OUT
P Q
+VDD
O/P
AND gate

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ELECTRONICS &

01. Ans: (a)

05. Ans: (c)

Let us consider n-type semiconductor Jdrift = [nn + pp]

= 360 m3/C 14. Ans: (b)

Relation between resistances of 17. Ans: (a)

01. Ans: (c)

IGO e0.718 /( 20.026 )

05. Ans: (c)

06. Ans: (d)

Eliminating ‘v’ from (1) and (2) :

5.5  0.498 The reverse saturation current of Germanium

11. Ans: (d)

01. Ans: (d)

7  10 3 08. Ans: (a)

Vi=13V V0 09. Ans: (b)

01. Ans: (a)

01. Ans: (b)

09. Ans: (b) 12. Ans: (b)

As VCB increases, effective base width (WB)

11. Ans: (a)

01. Ans: (d)

04. Ans: (d)

VDS at which pinch –off region means (Ri = 0 ; Ro = )

01. Ans: (a)

03. Ans: (b)

09. Ans: (b) 13. Ans: (d)

12. Ans: (b) 16. Ans: (b)

01. Ans: (c)

03. Ans: (d) 06. Ans: (b)

04. Ans: (d)

n i2 10 20 11.7  8.9 10 12  0.6  10 12

In practical IC, this cap will provided to si

08. Ans: (a)

12. Ans: (b) Only with a positive voltage to the gate an

14. Ans: (a)

06. Ans: (b) (By Printing Mistake in Volume-I

VDS = 10.8 V The circuit is common drain i.e., source

VCC 02. Ans: (b)

03. Ans: 6.123 106 Hz

40 (4.2 – V0)2 = 15(V0 – 0.8)2 rd RD

Sol: From figure IDS1 = IDS2.

05. Ans: (d)  V 

V2 gmRs I D  I DSS 1  GS 

01. Ans: (c) 04. Ans: (b)

03. Ans: (d) Device Technology Key

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