Faculty of Engineering and Technology

Electrical Engineering Department

ELE 215 – Logic Design and

Digital Circuits
Lecture 5 - Combinational Logic
(Part B)
Dr. Nermin Salem
nfawzy@fue.edu.eg
 Course Outline
• Introduction
• Numbering System
• Logic Gates and Gate-Level Minimization
• Boolean Algebra
• K-maps
• Combinational Logic Decoders
Encoders
• Synchronous Sequential Logic
Multiplexers
• Registers and Counters Examples
• Memories and Programmable Logic
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 A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2𝑛 unique
output lines.
Decoder Example: 3 to 8 decoder

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 • Some decoders are constructed with NAND gates.
• A two-to-four-line decoder with an enable input
constructed with NAND gates.
• The circuit operates with complemented outputs and
Decoders a complement enable input. The decoder is enabled
when E is equal to 0 (i.e., active-low enable).

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 w x y z
How to Construct a 4 × 16 Decoder 0 0 0 0

using 3 × 8 Decoders 0
0
0
0
0
1
1
0
0 0 1 1
1st Decoder
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
2nd Decoder
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
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 Common Anode
7 Segment

• 7-segment LED (Light Emitting

Diode) or LCD (Liquid Crystal
Display) type displays letters or even
alpha-numerical characters.
(0 to 9 and A to F)
• Typically, 7-segment display
consist of seven individual
LED’s within single package.

Common Cathode

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 BCD-to-7 Segment Decoder
• This BCD to seven segment decoder has four input lines (A, B, C and
D) and 7 output lines (a, b, c, d, e, f and g), this output is given to
seven segment LED display which displays the decimal number
depending upon inputs.
BCD Input Output to the 7-segment

Display Decoder - BCD to 7 Segment Display Decoder (electronics-tutorials.ws)

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 Implementing Logic Circuits using Decoders
Example 1: Implement the following Boolean functions using
Decoders.
𝑆 𝑥, 𝑦, 𝑧 = ∑(1,2,4,7)
𝐶 𝑥, 𝑦, 𝑧 = ∑(3,5,6,7)
Solution:

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 Encoders
• An encoder is a digital circuit that performs the inverse operation of a
decoder.
• An encoder has 2𝑛 (or fewer) input lines and n output lines.
Example: Octal to binary Encoder.

The encoder can be implemented with three

OR gates.

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 Priority Encoder
• A priority encoder is an encoder circuit that includes the priority function.
• The operation of the priority encoder is such that if two or more inputs are equal to 1 at
the same time, the input having the highest priority will take precedence.
• The truth table of a four-input priority encoder is:

𝐷3 has the highest priority

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 Multiplexers
• A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• Normally, there are 2𝑛 input lines and n selection lines whose bit combinations determine
which input is selected.
• Example: 2 to 1 MUX

S Y
0 𝐼0
1 𝐼1

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 Multiplexers: 4 to 1 MUX

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 Implementing Boolean Functions using MUX
Boolean function with n variables can be implemented with a
multiplexer that has n selection inputs and 2𝑛 data inputs, one for each
minterm.
Boolean function of n variables can be also implemented with a
multiplexer that has n-1 selection inputs and 2𝑛−1 data inputs.
• The first n-1 variables of the function are connected to the selection inputs of
the multiplexer.
• The remaining single variable of the function is used for the data inputs.
• Each data input can be 1, 0, the variable or its complement

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 Implementing Boolean Functions using MUX
Consider the implementation of the Boolean function
F (x, y, z) = (1, 2, 6, 7)
Using 4 to 1 MUX.
Solution:

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 Implementing Boolean Functions using MUX
Consider the implementation of the Boolean function
F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
Using 8 to 1 MUX.
Solution:

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 • Two states are logic 1 and logic 0.
• The third state is high impedance state in which:
• The logic behaves like an open circuit, which means that the output
appears to be disconnected
• The circuit has no logic significance
• The circuit connected to the output of the three-state gate is not
affected by the inputs to the gate
• The most common type of three-state gate is buffer gate.
Three-State • When the control input is equal to 1, the output is equal to the input
• When the control input is equal to 0, the output is disabled, and the
Gates gate goes to a high impedance state, regardless to the input

A multiplexer can be constructed with three-state gates.

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 Multiplexers with three-state gates

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 References
▪ M. Mano and M. Ciletti, Digital Design, with an introduction to the
Verilog HDL. 5th Ed. Pearson, 2013.
▪ John F. Wakerly, Digital Design: Principles and Practices. 4th Ed.
Pearson, 2005.
▪ R. Katz and G. Boriello, Contemporary Logic Design. 2nd Ed. Pearson,
2005.
▪ S. Brown and Z. Vranesic , Fundamentals of Digital Logic with
Verilog Design. 3rd Ed. SEM, 2013.

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 Thank You

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