UR-CST NYARUGENGE CAMPUS

DP: ELECTRICAL AND ELECTRONICS ENG

OP: ELECTRONICS&TELECOM

ACADEMIC YEAR 2017-2018

YEAR 1 ETE

Analog Electronic Circuit I.

GROUP 4:

-SHYOLI IRADUFASHA Theodosie Dalie: 217044131

-MUGOROZI Francois : 218000849

-NIYIBIGIRA Geredi : 218007257

-NGABONZIZA Nestor : 218003836

-MUKAMUHIZI Leontine : 218000594

-MBONIMPA Pacome Simon : 218000124

-MBABAZI Daniel : 218010487

-HIMBAZA Jules Bienvenue : 218009015

-BUKANDA Shukuru : 218002464

-DUSENGIMANA Gadhi : 218012372

-UWAMAHORO Regine Diane :217058671

 ANALOG ASSIGNMENT 2
Q4. The ways to connect voltage between Gate and Source of JFET: the JFET Gate to Source is reverse biased
as shown in figure below

Q10. Data: -VGS(off) = -8V, IDSS = 5Ma

Asked: to plot the transfer curve
Steps: - ID = 0, VGS -8V
- ID = IDSS/4, VGS = 0.5VGS(off) = 0.5(-8) v = -4V
- ID = IDSS/2, VGS = 0.3VGS(off) = 0.3(-8) v = -2.4V
- ID = IDSS(1-(VGS/VGS(off)))2
- For VGS = -1, ID = 5*10-3(1-(-1/-8))2 = 3.8mA
- For VGS = -2, ID = 5*10-3 (1-(-2/-8))2 = 2.8mA
- For VGS = -3, ID =5*10-3 (1-(-3/-8))2 = 1.95mA
- For VGS = -4, ID = 5*10-3 (1-(-4/-8))2 = 1.25mA
- For VGS = -5, ID = 5*10-3 (1-(-5/-8))2 = 0.7mA
- For VGS = -6, ID = 5*10-3 (1-(-6/-8))2 = 0.3mA
- For VGS = -7, ID = 5*10-3 (1-(-7/-8))2 = 0.08mA

VGS ID IDSS VGS(off0

0v 5mA
-1v 3.8mA
-2v 2.8mA
-3v 1.95mA 5mA -8V
-4v 1.25mA
-5v 0.7mA
-6v 0.3mA
-7v 0.08mA
-8v 0mA
Q16.Data: -ID = 12mA, Rs = 100Ω
Asked: VGS (for self-biased n-channel JFET)
Formula: VGS = VG-VS, VG = 0V
VGS = -IDRs = -12mA * 100 Ω = -1.2V

Q22.Data: IDSS = 14mA, VDD = 24V, VGS(off) = -10V

Asked: to set the midpoint bias for JFET
Steps: .ID = IDSS/2 = 14mA/2 = 7mA
. VGS = VGS(off)/3.4 = -10/3.4 = -2.94V
. Rs = |VGS/ID|= |-2.94/7mA = 420 Ω
. VD = VDD/2 = 24V/2 = 12V
.RD = (VDD-VD)/ID = (24-12)V/7mA = 1.7K Ω
.VDS = VD – VS = VDD-ID(RD+RS)
= 24V – 7mA(420 Ω+1.7k Ω)
= 9.16V

Q28.Data: VDS = 0.8V, ID = 0.20Ma for JFET biased in ohmic region

Asked: RDS
Formula: RDS = 1/GDS
GDS = ID/VDS = slope
Solving: RDS = VDS/ID = 0.8V/0.20mA = 4K Ω

Q34. Basic difference between an E-MOSFET and a D-MOSFET

No E-MOSFET D-MOSFET
1 It must be biased with +ve voltage It can operate with both +ve or -ve voltage
2 The bias voltage must be greater than
threshold value
3 Here the channel is to be increased The channel is to be reduced(for ID control)

4 Is normally switched "OFF" Is normally switched "ON"

Q40. Data: VGS(th) = +5v and -5v

Asked: are the MOSFET on or off?

VG = 10M*10V/14.7M
= 6.8V
For VGS>=VGS(th)
6.8v>5v
Then it is ON

VG = 1M*(-25V)/11M = -2.25v
VGS = VG = -2.25V
For VGS >= VGS(th)
-2.25 > -5 (not correct) then it is OFF

Q46. How an excessive collector current can produce a latch-up condition in an IGBT?

We can explain this by considering the equivalent IGBT circuit below

As it is seen IGBT is made of MOSFET at the input Gate and a BJT at the output collector to emitter
The NPNP structure of the IGBT forms a parasitic transistor and an inherent parasitic resistance within the device, as
shown in red color. These parasitic components have no effect during normal operation. However, if the maximum
collector current is exceeded under certain conditions, the parasitic transistor, Qp can turn on. If Qp turns on, it
effectively combines with Q1 to form a parasitic element, as shown in Figure in which a latch up condition can occur. In
latch-up, the device will stay on and cannot be controlled by the gate voltage. Latch-up can be avoided by always
operating within the specified limits of the device.

Q52.

According to the figure above, we make projection to determine the value of sensor voltage for the Ph values:

a) 2, the sensor voltage is -500mv

b) 5, the sensor voltage is -200mv
c) 7, the sensor voltage is 0v
d) 11, the sensor voltage is 400mv

Q58.

Referring to Figure 8–14, determine the maximum power dissipation for a 2N5457 at an ambient temperature of 65oC

From the figure below, we can determine the value of the power that will be dissipated at 65oC with referring to the
power dissipated at 1oC.
It I clear that 2N5457 dissipates 5.0mW/0C

10C 5.0 mW

650C (5.0*10-3*65) w

= 325Mw

The at 650C it will dissipate 325Mw

Q70. Design a MOSFET circuit with zero bias using a 2N3797 that operates from a 9 V dc supply and produces a VDS of
4.5 V. The maximum current drawn from the source is to be 1 mA.

. VDS = 4.5V

. IDSS = 1mA

. RD = (VDS –VDD)/-IDSS = 4.5V/1mA

= 4500Ω = 4.5kΩ

THE CIRCUIT