Professional Documents
Culture Documents
Instructors:
Daniel Holanda Noronha, danielhn@ece.ubc.ca Amin Ghasemazar Mohamed Omran
Cristian Grecu, grecuc@ece.ubc.ca
● Course Overview
○ Motivation
○ Topics
○ Labs/Exam
● Digital systems Course Overview - What is this class about?
○ Overview
● VHDL
○ What is VHDL?
○ Basic concepts and syntax
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Course Overview - What is this class about? Course Overview - What is this class about?
Analog Circuit
This class is about designing digital circuits! Signals can have any value
Digital Circuit
Signals can be either 0 or 1
Introduction 5 6
1971 - Intel 4004 4-bit microprocessor 1977 - Zilog Z80A 8-bit microprocessor
Intel:
80286 - 16 bit data bus, 1982
4 GHz is a very high frequency +
80386 - 32 bit data bus, 1985 Energy is proportional to f² →
80486 - 32 bit data bus, 1989 Energy consumption is very high!
AMD Am5x86 - 1995 Solution: More than one core!
Cyrix Cx5x86 - 1995
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8 processing elements
4 GHz
234,000,000 transistors
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Course Overview - Motivation Course Overview - Motivation
4 cores
2.34 GHz
3,300,000,000 transistors
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● Applications
2016 - Snapdragon 820 mobile
(System on Chip)
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Course Overview - Topics Course Overview - Topics
● Combinational Design
○ Do it all in one clock cycle! ● Who might be interested in this course?
● Sequential design ○ Those of you interested in chip design
○ You can do more if you do things in sequence ○ Those of you interested in control electronics (robots, industrial processes)
■ Ex: Count how many times X was 1 in 10 cycles ○ Those of you interested in communication systems
● Arithmetic circuits ○ Those of you interested in biomedical electronics
○ Adders, multipliers and more ○ Those of you interested in software design (CAD/EDA)
● Datapath design ● Basic prerequisites
○ Path that the input data follows in a processor to become an output ○ Boolean Logic
● Timing strategies ○ Basic Programming
○ Making it run fast and avoiding glitches ○ Interest in Digital Design
● A lot of VHDL
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● Labs ● Labs
○ A significant part of the course is represented by LAB assignments
Preparation Action
○ Use Altera DE0 Board
○ Groups of 2
○ During the lab you will implement your design
○ At the end of the lab the TA will grade your design and your knowledge
○ Total of 4 labs (5th lab is used to repeat something that you didn't like)
○ Need a non-zero grade in at least 2 labs!
○ Read the lab assignment before coming to the lab (time is short)
○ Lab are in MCLD 348/358
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Course Overview - Labs/Exam Course Overview - Labs/Exam
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Digital Systems - Overview
25 Introduction 26
● Combinational Circuits
○ A combinational logic block (CLB) is defined as having its output(s)
0 0 1
depending only of its current inputs at any given time. 1 0 0
○ Can be implemented using logic gates, look-up tables (LUTs), or other 1
1
0
1
0
0
means. 0 1
NOR NAND 1
0
1 0
1
1 1 1 1
0 1 1 0 1
0 1 1
0 0 0
XOR XNOR INVERTER Inputs: X=0 Y=1 Z=1
Output: F = ?
Examples? 0 1 1
1 0 0
1 0
27 0 1 28
Digital Systems - Overview Digital Systems - Overview
● What are the abstraction levels that exist? ● What are the abstraction levels that exist?
■ Behaviour: ■ RTL-level (Register transfer level):
● Description of what the circuit does ● Specify what each functional block will be made of, in terms of
● Ex: You can write a description of the processor without having to multiplexors, ALUs, state machines
design it internally ● Specify connections between components
● You can simulate the processor and confirm that interacts ● How does this help?
correctly with other components (I/O, memory) ○ You get one step closer to the hardware implementation
● You can share the behavioral description with other design teams You can simulate and verify that the design behaves as in
(chipset, compiler) the behavioural specifications (meets your expectations)
● For all these, you do not need to design the processor at ○ Can roughly estimate the size of the design (in terms of
gate/transistor level! #transistors, Si area)
● Problem: Some times might not be possible to convert this to a ○ RTL-level can be synthesized by CAD tools (converted to a
logic circuit (synthesize it) logic circuit)
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Digital Systems - Overview Digital Systems - Overview
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VHDL - What is VHDL?
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● But… why do we really need VHDL? Why can't I just use gates?
○ Answer: Because we need abstraction in order to be productive!
■ The process of finding an efficient set of logic gates to perform a given ● How can we specify a circuit using VHDL?
function is labor intensive and error prone ○ In VHDL, we can specify hardware in two ways:
■ Structurally
■ In the 1990s, designers discovered that they were far more productive ● RTL
if they worked at a higher level of abstraction ● Logic
● Goal: allowing a computer-aided design (CAD) tool to produce ■ Behaviorally
○ Can’t do this with schematics!
the optimized gates from a higher level.
○ More importantly, we can combine structural and behavioural
● Two main languages representations in the same design (and this happens almost all the time)
○ VHDL and Verilog
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VHDL - What is VHDL? VHDL - What is VHDL?
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
● Bigger example: ● Port: Signals that go in and out of the module entity BIG_CIRCUIT is
port ( a, b, c : in STD_LOGIC;
○ Possible port modes: z : out STD_LOGIC);
library ieee; ■ In: you can read from it, but not write end BIG_CIRCUIT;
use ieee.std_logic_1164.all; ■ out: you can write, but you can't read from it
■ Inout: you can both read and write from it
entity BIG_CIRCUIT is ■ Buffer: out that you can read from inside of
port ( a, b, c : in STD_LOGIC; your design
z : out STD_LOGIC); ■ Linkage: used in analog simulation and to
end BIG_CIRCUIT; hook-up power/ground ports (don't worry
about this for this course)
architecture BIG_BEHAV of BIG_CIRCUIT is
begin
z <= (not a and b) or (b and not c);
end BIG_BEHAV; Note: Don't use inout mode all the time. This might be bad for synthesis tool
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
● Using comments
● Architecture:
○ Each entity may have more than one architecture OK code... Great code!
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity MY_ENTITY is
port ( a, b : in STD_LOGIC; entity BIG_CIRCUIT is -- Entity with 3 inputs and 1 output
z : out STD_LOGIC); port ( a, b, c : in STD_LOGIC; entity BIG_CIRCUIT is
end MY_ENTITY; z : out STD_LOGIC); port ( a, b, c : in STD_LOGIC;
end BIG_CIRCUIT; z : out STD_LOGIC);
end BIG_CIRCUIT;
architecture BIG_BEHAV of BIG_CIRCUIT is
architecture ARCH_OR of my_entity is architecture ARCH_AND of MY_ENTITY is begin -- architecture for assignment 4(a)
begin begin z <= (not a and b) or (b and not c); architecture BIG_BEHAV of BIG_CIRCUIT is
z <= a or b; z <= a and b; end BIG_BEHAV; begin
end ARCH_OR; end ARCH_AND; z <= (not a and b) or (b and not c);
end BIG_BEHAV;
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
● Signals: Internal wires that are not inputs or outputs ● Dealing with busses (vectors)
○ VHDL uses STD_LOGIC_VECTOR to indicate busses of STD_LOGIC
○ Little-endian order
library ieee; ■ the least significant bit has the smallest bit number
use ieee.std_logic_1164.all;
■ Ex: STD_LOGIC_VECTOR(3 downto 0) represents a 4-bit bus.
entity MY_ENTITY is ■ The bits, from most significant to least significant, are:
port ( a, b: in STD_LOGIC; ● a(3), a(2), a(1), and a(0)
z: out STD_LOGIC);
end MY_ENTITY; ○ Big-endian order
■ Ex: STD_LOGIC_VECTOR(0 to 3)
architecture MY_ARCH of MY_ENTITY is ■ The bits, from most significant to least significant, are:
signal s1, s2: STD_LOGIC;
begin ● a(0), a(1), a(2), and a(3)
s1<=not a and b;
s2<=not b and a;
z<=s1 or s2;
end MY_ARCH;
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
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VHDL - Basic concepts and syntax VHDL - Basic concepts and syntax
● Dealing with busses (vectors)
● Dealing with busses (vectors)
library ieee;
use ieee.std_logic_1164.all;