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Chapiter II (Memories)

 Combinational logic & sequential logic.

 Memories

Mokrani Hocine
dr.mokrani@gmail.com

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combinational logic
Input exchanges are propagated directly to the outputs.
Combinational logic Propagation

&
Combinational
Sequential logic Inputs
circuit
Output

Outputs

Input events
Time

Important: Wait until the signal is stable

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Examples of combinational circuits Examples of combinational circuits

3 input wires, 8 output possibilities

One output is activated at a time

An input selected as output
8 possible inputs

3 input wires

Multiplexer: selects one of several inputs. Decoder: activate one of several outputs
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Examples of combinational circuits Sequential logic

A logic whose results depend not only on the data
currently being processed, but also on previously
processed data.
Inputs

Results

Propagation

Input s
Operation selection a
Output

Sequential circuit

 Using a memory state st = F (st-1,a)

ALU: Arithmetic and Logic Unit
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Synchronous and asynchronous

Examples of sequential circuits
operation in a sequential circuit
D

Asynchronous mode
Tasks can be performed in two ways. W
Bascule D Q

D= DATA W= WRITE
• Asynchronous mode: • When W = 1 then Q ← D. (This value is stored).
• When W = 0, the bascule remains in the same state and the output is set to
The logic output can change state at any time the last stored value.

when one or more inputs change.

Synchronous Mode
• Synchronous mode:
D
The change of state is controlled by a clock H
Bascule D Q

signal. The information changes with time.

D= DATA H= Clock
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Memories
• Definition
Device for recording, storing and retrieving information.

Memories • Different technologies

Electronics - Magnetics - Optics.
• Different features
• Capacity.
• Access time.
• bandwidth (debit).
• Volatility.

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Comparison of different memory

Memory types
types

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Access method
Locating the different memory types • Sequential access
 To access a piece of information, you have to go through all the
Motherboard information that precedes it.
 Example: magnitic band.

Processor • Direct access

 Each piece of information has its own address, which can be accessed
Main memory
Registres

directly.
Registres

Mass Memory  Example: computer main memory.

• Semi-sequential access
 Intermediary between sequential and direct.
 Example: hard disk: direct cylinder access and sequential sector access
on a cylinder.
• Associative access
 information is identified by its key.
 information is accessed via its key.
15  Example: cache memory. 16

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Registres Register banks

• SRAM memory.
 The information doesn't need to be refreshed.
 Produced by : A register bank of height N and width K is a set of N
Flip-flop (RS or D) that stores information. (4 transistors = 2 NOR gates) . registers of K bit (a memory with N addresses).
• Integrated in the processor core (even in other components).
• A register stores an instruction or information relating to an instruction.
Example:
(Operands required for instruction, Results produced by instruction) A bank of N registers of 3 bit with:
• Very few (generally < 40)  A writing port.
• Very fast (clocked at processor speed).
 Two read ports (when reading, the contents of two
registers are read at the same time).

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Register banks (Example of use) Main memory

Reading operation

• DRAM memory:
– Dynamic: information needs to be periodically refreshed.
– 1 bit = 1 transistor + 1 condensateur.

• The Information is stored as words (memory) of a certain

number of bits (8, 16, 32, 64 bits): the word length is the
memory format.
Write operation

• relatively slow speed (compared to that of the processor).

Example of the use of a register bank

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Memory organization Memory organization

• Memory cell size: K bits = generally, number of bus wires (not always true)

Bus d’adresse
• Number of memory cells: 2ᴺ cell -> N address bus wires.

N bits
• Memory size: 2ᴺ Χ K bits.
Address bus

Mémoire Centrale

R/W
Data bus CS

Bus de données
K bits

12 cells of 8 bits 8 cells of 12 bits 6 cells of 16 bits 21 22

Memory organization Calculation method

Main memory • Memory cell size: K bits = generally, number of bus wires (not always true)
• Number of memory cells: 2ᴺ cell -> N address bus wires.
Cell size= K bits • Memory size: 2ᴺ Χ K bits.
Cell 0
Cell 1
Cell 2
Address busN bits

Cell 3 • Addressing_bit_number = log2 (Memory_cell_number)

Decoder

Cell 4
2N Cells

Cell 2N -3
Cell 2N -2
Cell 2N -1
Memory_Size = K x 2N

Data bus K bits 23 24

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Memory operation
(Read mode) Memory operation
Reading cycle: (Write mode)
 Establishing the address.
Writing cycle:
 Read signal (R/W=0 for example)
 Set address.
 Chip selection (CS=1)
 Chip Selection (CS=1).
 After a certain time, the information appears on the output and
remains there until the end of the cycle.  Set input data.
 Write signal (R/W=1 below).
Cycle time
Address
Address
R/W
R/W
CS
CS
Data
Data
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Access time

Memory performance Access optimization

• Access time • Synchronous memory (synchronized with the bus) : SDRAM.

Time between a read/write request and its completion (t_a).
• Cycle time
Minimum time between two memory accesses (t_c).
t_a < t_c (signal stabilization, synchronization, etc.).
• Bandwidth
Maximum number of bits transmitted per second. For uniform-
time data access.
B = n / t_c. n is the number of bits transferred per cycle.
• For matrix memories, page mode access: load row and
column, then change only the columns for subsequent
accesses (data locality): DRAM FPM.
• For matrix memories, burst access: row and column are
loaded, along with the number of data items to be read;
columns are incremented in memory for subsequent accesses
(data locality): DDR-SDRAM.

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Memory and errors Logical memory

• Information in memory may contain one or more errors • Logical memory is how the processor (or programmer) sees
(due to its physical nature). (physical) memory.

• To detect and correct, control bits are added: • Memory is defined as a set of N consecutive bytes whose first
address is 0 and whose last address is N-1.

 Parity bit: an additional bit to calculate the number of 1's

• Memory addressing in words of : 8 (byte), 16, 32, 64, ... bits.
in the data (Even, Odd).

 ECC memory: (Error correction coding) • A 32-bit word consists of 4 consecutive bytes.
has several additional bits to detect and correct errors.

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Logical memory Logical memory

(data positioning)
For 32-bit data, using an 8-bit cell memory, there are 2 ways of
arranging the bytes that make it up :
 The most significant word is stored first: big-endian
 The most significant word is stored last: little-endian
A memory word can't start anywhere
 16-bit words start at even-numbered addresses.
 32-bit words start at addresses that are multiples of 4.
(Pagination)
logical division of memory into a certain number of blocks, with the
same size.
• An address is coded as a block number.
• A displacement within the block (offset).
• N address bits ⇒ 2ᴺ memory cells.
• B bits (most significant) for the
block number.
• N – B bits (of low significance)
for movement within the
block.
• So we have 2ᴮ blocks each with 2ᴺ-ᴮ
squares.

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Pagination Method for calculating the number of

Main memory

Address bus N bits Cell 0 C0

bits reserved for memory allocation
Cell 1 C1
Cell 2 C2 Page 0 • Memory cell size: K bits = generally, number of bus wires (not always
Cell 3 C3 true)
Cell 4 C0 • Number of memory cells: 2ᴺ cell -> N address bus wires.
0 1 1 1 Cell 5 C1 • Memory size: 2ᴺ Χ K bits.
Page 1
Cell 6 C2
Page 1 Offset 3 Cell 7 C3 • Addressing_bit_number = log2 (Memory_cell_number)
B bits N-B Bits Cell 8 C0
Cell 9 C1
Access to cell 7
C2
Page 2 • Nb_page = Memory_size / Page_size
Cell 10
Cell 11 C3 • Nb_bit_pagination = log2(Nb_page)
Cell 12 C0 • The most significant bits are used to identify the page.
Cell 13 C1 Page 3
Cell 14 C2
Cell 15 C3
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What you still need to know

• How a cache memory works?

• How a MMU works ?

• Memory paging.
• Memory segmentation.
• Pagining memory segment.

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