Design of springs

Microprocessor
Interfacing
02
1. Three devices A, B and C are connected to an Intel (a) Direct transfer of data between memory and
8085 A microprocessor. Device A has the highest accumulator
priority and device C has the lowest priority. The (b) Direct transfer of data between memory and
correct assignment of interrupt inputs is I/O devices without the use of
(a) A uses RST 5.5, B uses RST 6.5 and C uses microprocessor
TRAP [ESE-2003] (c) Transfer of data exclusively within
(b) A uses RST 5.5, B uses RST 6.5 and C uses microprocessor registers
RST 7.5 (d) A fast transfer of data between
(c) A uses RST 7.5, B uses RST 6.5 and C uses microprocessor and I/O devices
RST 5.5 Sol. (b)
(d) A uses TRAP, B uses RST 5.5 and C uses With the help of DMA data transfer is taking place
RST 6.5 between I/O and main memory through memory
Sol. (c) but not using CPU.
Order of priorities for interrupts is
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR. 4. A handshake signal in a data transfer is transmitted
Since the given priority order is A, B, and C so [ESE-2003]
correct option is (c). (a) Along with the data bits
(b) Before the data transfer
2. Which one of the following is NOT a vectored (c) After the data transfer
interrupted? [ESE-2003] (d) Either along with the bits or after the data
(a) TRAP (b) INTR transfer
(c) RST 3 (d) RST 7.5 Sol. (b)
Sol. (b) Handshake signals are always transferred before
INTR is not a vectored interrupt since its address the data transfer.
does not has a fixed address.
While TRAP, RST 7.5, RST 6.5, RST 5.5 are 5. What is the total number of memory locations and
vectored interrupt having predefined addresses. input-output devices that can be addressed with a
processor having 16-bits address bus, using
memory maped I/O ? [ESE-2004]
3. A Direct Memory Access (DMA) transfer implies
[ESE-2003] (a) 64 K memory locations and 256I/O devices
(b) 2561/0 devices and 65279 memory locations

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(c) 64 K memory locations and no 1/O devices 3. For increasing the number of interrupts
(d) 64 K memory locations or input-output 4. Positive edge triggered
devices Codes: A B C D
Sol. (d) (a) 2 4 3 1
(b) 1 4 3 2
In case of memory mapped I/O → I/O devices are (c) 1 3 4 2
treated as memory locations having 16 bit address. (d) 2 3 4 1
So microprocessor having 16 bit address line can Sol. (d)
address 216 memory location and I/O devices. TRAP → is both level triggered as well as edge
16 6 10
2 memory locations = 2 × 2 = 64 K memory triggered
locations. RST 7.5→ is edge triggered
RST 6.5→ level triggered
6. Which one of the following statements is correct? INTR → contains 8-RST as from RST 0.... RST 7
In Intel 8085, the interrupt enable flip-flop is reset so to increase the no. of interrupts
by
TRAP → has highest priority and is non maskable.
[ESE-2004]
(a) DI instructions only
8. The interrupt vector table IVT of 8086 contains
(b) System RESET only
[ESE-2005]
(c) Interrupt acknowledgement only
(a) The contents of CS and IP of the main
(d) Either DI or system RESET or interrupt program address to which the interrupt has
acknowledgement occured.
Sol. (d) (b) The contents of CS and IP of the main
The interrupt enable flip-flop (IE) of the Intel 8085 program address to which the control has to
microprocessor can be reset by recognizing an come back after the service routine.
interrupt, executing the DI (Disable Interrupt) (c) The starting CS and IP values of the interrupt
instruction, or completing a system RESET. service routine.
(d) The starting address of the IVT.
7. Match List-I (Interrupts) with List-II Sol. (c)
(Corresponding Characteristics) and select the
Interrupt vector table contains the beginning code
correct answer using the codes given below:
segment CS and the instruction pointer IP of
[ESE-2004] interrupt service routine.
List-I
A. TRAP 9. Match List-I with List-II and select the correct
B. INTR answer using the codes given below the lists:
C. RST 7.5 [ESE-2005]
D. RST 6.5 List-I
List-II A. Modified during fetch phase
1. Level triggered B. Holds subscripts of arrays
2. Non maskable C. Needed by the DEBUG program

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D. Calculates addresses of data in (b) 3 1 4 2

List-II (c) 2 1 4 3
1. DI (d) 3 4 1 2
2. DS
3. IP datasegment Sol. (d)
4. TRAP is non-maskable
Codes: A B C D INTR is non-vectored
(a) 2 4 1 3 RST 7.5 is edge triggered
(b) 3 1 4 2
(c) 2 1 4 3 RST 5.5 is level triggered.
(d) 3 4 1 2
Sol. (b) 12. Which one of the following is the software
DS → Data segment register → calculate address interrupt of 8085 microprocessor?
of data in data segment. [ESE-2006]
TF → TRAP (single step flag) → Needed by debug (a) RST 7.5 (b) RST 7
program . (c) TRAP (d) INTR
DI→ Holds subscripts of arrays. Sol. (b)
IP→ Modified during fetch phase The Intel 8085 microprocessor's software interrupt
instruction is called TRAP. In order to carry out an
10. Which of the following does NOT take place when interrupt service procedure, it is utilized to start a
8085 processor is reset? [ESE-2005] software interrupt and move control to a certain
(a) 8085 gives reset out signal to reset external memory address.
hardware
(b) 8085 resets program counter to FFFFH 13. The power failure alarm must be connected to
(c) The interrupt system is disabled which one of the following interrupt of 8085 ?
[ESE-2007]
(d) The buses are tristated
(a) RST 7.5 (b) TRAP
Sol. (b)
(c) INTR (d) HOLD
8085 resets program counter to 0000H.
Sol. (b)
TRAP is used for emergency interrupts.
11. Match List-I (Interrupt) with List-II (Property) and
select the correct answer using the code given
below the lists: [ESE-2006] 14. Which one of the following statement
corresponding to execution of SIM instructions is
List-I List-II
not correct?
A. RST 7.5 1. Non-maskable
[ESE-2007]
B. RST 5.5 2. Edge sensitive
(a) It will selectively mark all the interrupts of
C. INTR 3. Level sensitive
8085
D. TRAP 4. Non-vectored
(b) Contents of bit (b7) are copies on SOD pin
Codes: A B C D
only if bit b6 in accumulator is '1'
(a) 2 4 1 3

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Interfacing
(c) RST 7.5 can reset without executing ISR for (a) Both A and R are true and R is the correct
RST 7.5 explanation of A
(d) It can handle interrupts and serial 1/O (b) Both A and R are true but R is NOT the
Sol. (a) correct explanation of A
Selective interrupt mask bit setting in the interrupt (c) A is true but R is false
system control register (ISCR) is possible using the (d) A is false but R is true
SIM (Set Interrupt Mask) instruction. While not all Sol. (a)
8085 interrupts are marked, the programmer can
Assertion (A): is true because analog-to-digital
choose which interrupts to enable or disable.
converters (ADCs) are indeed used to convert
So, statement (a) is not correct. analog signals into digital format so that they can
be processed by a microprocessor or
15. Read the following Assembly Language Program microcontroller.
Segment of 8085 : [ESE-2007] Reason (R): is true because many real-world
El RIM applications, such as temperature sensing, audio
processing, and sensor data acquisition, produce
ANI 80H SIM
signals that are analog in nature, hence
What kind of task is performed by above set of
necessitating the use of ADCs for interfacing with
instructions?
digital systems.
(a) Sends bit out on SOD pin
(b) Accepts bit in from SID pin
17. Which interrupt has the highest priority?
(c) Accepts RST 7.5 interrupt
[ESE-2007]
(d) Resets RST 7.5 interrupt
(a) RST 7.5 (b) RST 7
Sol. (d)
(c) RST 6.5 (d) INTR
RIM: This instruction loads the interrupt status
Sol. (d)
data into the accumulator by reading it from the
TRAP has the highest priority.
interrupt system.
ANI 80H: This instruction masks all bits except bit
7 by executing a logical AND operation between 18. The contents of memory location 4FFFH are
the accumulator and the immediate data 80H. 11011011. The memory word could not be
interpreted as which one of the following?
SIM: This command saves the information in the
accumulator back into the control word of the [ESE-2007]
interrupt system. This essentially clears the RST (a) 2's complement number
7.5 interrupt enabling bit and resets the RST 7.5 (b) 1's complement number
interrupt because bit 7 was masked (set to 0).
(c) Octal number
(d) BCD number
16. Assertion (A): Analog to digital converters are
Sol. (d)
used to interface microprocessor to analog signals.
BCD can't be more than 9 as a single bit.
Reason (R): Many applications in real world
produce signal analog in nature. [ESE-2007]

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19. What is the number of machine cycles in the

instruction LDA 2000H that consists of thirteen 22. When TRAP interrupt is triggered in an intel 8085
states? [ESE-2008] A, the program control is transferred to which one
(a) 2 (b) 3 of the following? [ESE-2008]
(c) 4 (d) 5 (a) 0020H (b) 0024H
Sol. (c) (c) 0028H (d) 002CH
Four Machine Cycles – 1 for Opcode fetch, 2 for Sol. (b)
Mem Read to read address 2000H, 1 for Mem Read For calculating the address of TRAP we treat it as
to fetch data at 2000H. RST 4.5 (only for address calculation) so address
= (8 × 4.5)10 = (36)10 = (24)H
20. An intel 8085A microprocessor is operated at a
frequency of 2MHz. If the instruction
23. An output device is interfaced with an 8085
LXIH,EOOOH that takes ten ' T ' states, is
microprocessor as memory-mapped 1/0. The
executed, then what is the instruction cycle time?
address of the device is 1000H. In order to output
[ESE-2008]
data from the accumulator to the device, what will
(a) 10μs (b) 5μs be the sequence of instructions? [ESE-2009]
(c) 4μs (d) 2.5μs (a) LXIH1 1000H
Sol. (b) (b) LXIH, 1000H MOV A, M MOV M, A
(c) LHLD 1000H
One T-state (d) LHLD 1000H MOV A, M MOV M, A
So instruction cycle =10 T states Sol. (b)
=10 × 0.5 μ sec = 5 μ sec LXI H, 1000H load the address of device in HL
pair

21. Three devices P,Q and R have to be connected to HL = (1000)_H

an 8085 microprocessor. Device P has the highest MOV M, A → Content of Accumulator are copied
priority and device R has the lowest priority. In this to the location whose address is given by content of
context, which of the following is the correct HL pair i.e. device address.
assignment of interrupt inputs? [ESE-2008]
(a) P uses TRAP, Q uses RST 5.5 and R uses 24. For 16 bit address-bus, if an 8 K RAM chip is
RST 6.5 selected when A13, A14 and A15 address bits are all
(b) Puses RST 5.5, Quses RST 6.5 and Ruses one, then what is the range of the memory address?
RST 7.5 [ESE-2009]
(c) Puses RST 7.5, Q uses RST 6.5 and R uses (a) EOOOH-EFFFH (b) EOOOH-FFFFH
RST 5.5 (c) FOOOH-FFFFH (d) FOOOH - FEEEH
(d) P uses RST 5.5, Q uses RST 6.5 and R uses Sol. (b)
TRAP For 8K RAM, 8 × 1K = 2 3 × 210 i.e., 13 bits (A0 to
Sol. (c) A12) out of 16 to represent RAM and left 3 (A 13 to
As per order of priority as shown below: A15) for chip select lines.
RST 7.5 > RST 6.5 > RST 5.5

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Interfacing
25. To address the memory 14 bits are used. Then what (d) A as input or output port
is the address of the last memory location? Sol. (d)
[ESE-2009] Any port can be used as an input or output port.
(a) 16382 (b) 16383
(c) 16384 (d) 16385 29. On receiving an interrupt the CPU of an 8085
Sol. (b) microprocessor [ESE-2010]
(a) Completes the current instruction and then
A15 A15 A13 A12 A11 A10 A9 A8 goes to the interrupt service routing.
0 0 1 1 1 1 1 1 (b) Branches off to the interrupt service routing
A7 A6 A5 A4 A3 A2 A1 A0 immediately.
1 1 1 1 1 1 1 1
(c) Hands over control of address bus and data
≡ (3FFF)HEX = (16383)DEC
bus to the interrupting device.
26. Handshaking mode of data transfer is [ESE-2010]
(d) Goes to HALT state for pre-determined
(a) Synchronous data transfer period.
(b) Asynchronous data transfer Sol. (a)
(c) Interrupt driven data transfer An 8085 microprocessor's CPU completes the
(d) Level mode of DMA data transfer execution of the current instruction upon receiving
Sol. (b) an interrupt, saves the address of the subsequent
The handshaking mode of data transfer is typically instruction on the stack, and then branches off to
associated with asynchronous data transfer. the interrupt servicing function. By doing this, it is
ensured that the CPU can continue executing the
program after handling the interrupt and doesn't
27. Assertion (A) : An I/O device connected to lose its place in the main flow.
microprocessor in 1/O mapped 1/O mode has an 8
bit port address. [ESE-2010]
30. In 8085 microprocessor, the order of priority for
Reason (R) : Microprocessor based system design
hardware interrupts, are [ESE-2010]
uses concept of zero paging
(a) INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
(a) Both A and R are true and R is the correct
explanation of A (b) TRAP, RST 7.5, RST 6.5, RST 5.5, INTR

(b) Both A and R are true but R is NOT the (c) TRAP, INTR, RST 5.5, RST 6.5, RST 7.5
correct explanation of A (d) INTR, RST 5.5, RST 6.5, RST 7.5, TRAP
(c) A is true but R is false Sol. (b)
(d) A is false but R is true The order of interrupt priority is
Sol. () TRAP, RST 7.5, RST 6.5, RST 5.5, INTR

28. In mode. '0' (Zero) operation of 8255, the ports can 31. Assertion (A) : SIM instruction cannot be used to
be used as port: [ESE-2010] disable or change priority of INTR pin. [ESE-2010]
(a) A as input port only Reason (R) : INTR is a pseudo-vectored interrupt
(b) B as output port only PIN.

(c) A as output port only

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(a) Both A and R are true and R is the correct address in the range
explanation of A [ESE-2011]
(b) Both A and R are true but R is NOT the A15
correct explanation of A A14
A13 CS
(c) A is true but R is false A12
(d) A is false but R is true A11

Sol. () (a) 7800H-7FFFH (b) 1000H-1EFFH

(c) 8000H-8FFFH (d) 8800H-8FFFH
32. Which value a program counter will have when non Sol. (d)
maskable interrupt of 8085 microprocessor is
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
[ESE-2011]
1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 = 8800H
(a) 0004H (b) 0014H
to 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 = (FFF)H
(c) 0024H (d) 0034H
Sol. (c) = 0 for chip select:
Non-maskable interrupt is TRAP which A15 = 1
corresponds to address 0024H. A44 = 0
A13 = 0} fix
33. Assertion (A): Instruction SIM is necessary to A12 = 0
implement the interrupts INTR. [ESE-2011] A11 = 1
Reason (R): INTR requires external hardware for
implementation.
35. Which one of the following statements is not
(a) Both A and R are true and R is the correct correct? [ESE-2011]
explanation of A
(a) CMP A is a single byte instruction and CMA
(b) Both A and R are true but R is NOT the is not an instruction.
correct explanation of A
(b) The instruction SUB A sets the zero flag.
(c) A is true but R is false
(c) Bus is a group of wires.
(d) A is false but R is true
(d) Instructions INR does not affect carry flag.
Sol. (d)
Sol. (a)
R is correct as INTR requires external hardware for
CMP A is single byte instruction is correct.
implementation.
CMA is a instruction used to complement the
A is incorrect as SIM is necessary to implement
accumulator. So (a) is wrong.
RST 7.5 RST 6.5 RST 5.5 not INTR.

36. To execute the following instructions [ESE-2011]

34. The logic circuit used to generate the active low
(i) LDA 2100H
chip select signal by an Intel 8085 (ii) LXIH, 2100H
microprocessor to address to address a peripheral is by an Intel 8085 microprocessor the numbers of
shown in figure. The peripheral will respond to memory cycles required are
(a) 2 for (i) and 2 for (ii)

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Interfacing
(b) 4 for (i) and 2 for (ii) 39. In a microprocessor based system, DMA facility is
(c) 3 for (i) and 3 for (ii) required to increase the speed of the data transfer
between the [ESE-2013]
(d) 4 for (i) and 3 for (ii)
(a) microprocessor and the 1/0 memory
Sol. (d)
(b) microprocessor and 1/O devices
LDA 2100H→4 memory cycles → fetch +3 read.
(c) memory and the 1/O devices
LXI H, 2100H →3 memory cycles → fetch +2
read. (d) memory and register
Sol. (c)
37. According to Flynn's classification, which Because without DMA microprocessor requires
architecture is of only theoretical interest and no instruction for every byte of data transfer.
practical system has been developed based on it? 40. I/O mapped system identify their input/output
[ESE-2013] devices by giving them an [ESE-2013]
(a) Single Instruction Single Data (SISD) (a) 8 bit port number
(b) Single Instruction Multiplied Data (SIMD) (b) 16 bit port number
(c) Multiple Instruction Single Data (MISD) (c) 8 bit buffer number
(d) Multiple Instruction Multiple Data (MIMD) (d) 16 bit buffer number
Sol. () Sol. (a)
In I/O mapped I/O devices are identified with 8-bit
38. Cycle-stealing mode of DMA operation involves port address.
[ESE-2013]
(a) DMC controller takes over the address, data 41. A microprocessor based safety control system
and control buses while a block of data is installed in a nuclear power plant must be stress
transferred between memory and an I/O tested under which of the following conditions?
device. [ESE-2013]
(b) while the μP is executing a program an 1. Ageing due to radiation
interface circuit takes over control of the 2. Thermal stresses
address, data and control buses when not in
3. Seismic vibration
use by the μP.
4. Inadequate nuclear reactor coolant
(c) data transfer takes place between the 1/O
(a) 1 and 2 only (b) 2 and 4 only
device and memory during every alternate
clock cycle. (c) 1,2 and 3 only (d) 1, 2, 3 and 4
(d) the DMA controller waits for the μP to Sol. ()
finishexecution of the program and then
takes over the buses. 42. In a 5 × 7 dot matrix format [ESE-2014]
Sol. (a) (a) 64 bits are required to store 64 alphanumeric
In cycle steel/short burst mode block of data is characters.
transferred between I/O and memory. (b) 560 bits are required to store 64
alphanumeric characters.

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(c) 1120 bits are required to store 64

alphanumeric characters. 46. Three devices A,B and C have to be connected to
(d) 2240 bits are required to store 64 an 8085 microprocessor. Device A has highest
alphanumeric characters. priority and device C has the lowest priority. In this
Sol. (d) context, which of the following is correct
assignment of interrupt inputs?
5 columns and 7 rows so, 5 × 7 → 35 dots
[ESE-2014]
Each dot requires 64 characters this means, 64 ×
(a) A uses TRAP, B uses RST 5.5 and C uses
35→2240 bits are required
RST 6.5
(b) A uses RST 7.5, Buses RST 6.5 and C uses
43. In order to generate continuous square wave using
RST 5.5
8254 timer, it must be programmed in [ESE-2014]
(c) A uses RST 5.5, Buses RST 6.5 and C uses
(a) mode 0 (b) mode 1
RST 7.5
(c) mode 2 (d) mode 3
(d) A uses RST 5.5, Buses RST 6.5 and Cuses
Sol. () TRAP
Sol. (b)
44. Direct Memory Access channel (DMA) facilitates Priority order is TRAP (RST - 4.5), RST 7.5, RST
data to move in and out of the system [ESE-2014] 6.5, RST 5.5.
(a) on first-come first-serve basis
(b) with equal time delay 47. Statement (I): The main difference between a
(c) without a sub-routine microprocessor and a micro-controller is that the
(d) without programe intervention former does not have any on chip memory.
Sol. (d) Statement (II): A microprocessor does not need
memory to run programmes. [ESE-2015]
In DMA data transfer scheme, data are directly
transferred from an 1/O device. For DMA data (a) Both Statement (I) and Statement (II) are
transfer, the data and address buses come under the individually true and Statement (II) is the
control of the peripheral device which wants DMA correct explanation of Statement (I).
data transfer, and this process is done with out (b) Both Statement (I) and Statement (II) are
program intervention. individually true but Statement (II) is not the
correct explanation of Statement (I)
45. A device or a peripheral equipment which is not in (c) Statement (I) is true but Statement (II) is
direct communication with CPU of a computer is false.
called [ESE-2014] (d) Statement (I) is false but Statement (II) is
(a) off line device (b) on line device true.
(c) active device (d) slow device Sol. (c)
Sol. (a) Statement-Il is wrong, microprocessor need
memory to run programmes but the memory used
OFF line devices do not require the support of CPU
by microprocessor is provided externally.
directly.
Example: photocopy machine. This device can
work independently.

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48. Which one of the following is used for serial I/O 3. HLT 4. CLI
transfer in 8085 based system? [ESE-2015] Which of the above are machine control
(a) 8251 (b) 8255 instructions?
(c) 8259 (d) 8279 (a) 1 and 4 (b) 1 and 3
Sol. (a) (c) 2 and 3 (d) 2 and 4
8251→ USRAT (Universal Synchronous Sol. (b)
Asynchronous Receiver and Transmitter). HLT & LOCK are for internal machine control
operations of NP.
49. To interface a slow memory, wait states are added HLT ⇒ To stop NP execution of program
by [ESE-2015] LOCK ⇒ Related to 8086 , instruction with lock
(a) extending the time of the chip select logic prefix is executed first.
(b) causing READY signal to go low
(c) causing READY signal to go high 53. The port C of 8255 can be configured to work in
(d) by increasing the clock frequency [ESE-2016]
Sol. (b) (a) mode 0, mode 1, mode 2 and BSR
Wait states are added by causing ready signal to go (b) mode 0, mode 1 and mode 2
low. It is an input signal to microprocessor. (c) mode 2 and BSR
(d) BSR mode only
50. In 8085 microprocessor with memory mapped I/O, Sol. (a)
which one of the following is correct? [ESE-2015] Only port C can be used in BSR mode i.e., bit set
(a) I/O devices have 16 bit addresses reset in mode 0 as i/p or o/p mode, in mode 1 and
(b) I/O devices are accessed during IN and OUT mode 2 for control signals.
instructions
(c) There can be a maximum of 256 input and 54. Consider the following statements: [ESE-2016]
256 output devices 1. Semiconductor memories are organized as
(d) Logic operations cannot be performed linear array of memory locations.
Sol. (a) 2. To address a memory location out of N
Memory mapped I/O address is of 16 -bits. memory locations, at least log N bits of
address are required.
3. 8086 can address 1048576 addresses.
51. The DMA transfer technique where one word data
is transferred at a time is called [ESE-2015] 4. Memory for an 8086 is set up as two banks
to make it possible to read or write a word
(a) Cycle-stealing (b) Memory stealing
will one machine cycle.
(c) Hand shaking (d) Interleaving
Which of the above statements are correct?
Sol. (d)
(a) 1, 2 and 3 only (b) 1, 2 and 4 only
1 byte word is transferred for an instruction.
(c) 3 and 4 only (d) 1, 2, 3 and 4
Sol. (d)
52. Consider the following instructions: [ESE-2016]
All are true.
1. LOCK 2. STD

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In 8086 two banks are used as data bus is 16 -bits I and II both are true and I is correct explanation as
wide i.e., each bank contains one byte. in DMA data takes place between μP memory at
faster rate without intervention of CPU/μP.
55. Statement (I): READY is an output signal used to
synchronize slower peripheral. [ESE-2016] 57. In microprocessor interface, the concept of
Statement (II): HOLD is activated by an external detecting some error condition such as 'no match
signal. found' is
[ESE-2019]
(a) Both Statement (I) and Statement (II) are
individually true and Statement (II) is the (a) Syntax error (b) Semantic error
correct explanation of Statement (I). (c) Logical error (d) Error trapping
(b) Both Statement (I) and Statement (II) are Sol. ()
individually true but Statement (II) is not the
correct explanation of Statement (I)
58. The maximum number of input or output devices
(c) Statement (I) is true but Statement (II) is that can be connected to 8085 microprocessor are
false. [ESE-2019]
(d) Statement (I) is false but Statement (II) is (a) 8 (b) 16
true.
(c) 40 (d) 256
Sol. (d)
Sol. (d)
I. False as READY is input signal to μP.
t In the instruction IN 8-bit port address and OUT
II. Hold is activated by DMA controller. ∴ 8-bit port address.
True.
I/O has 8-bit value so therefore 2^8→256 devices
can be connected.
56. Statement (I): The direct memory access or DMA
mode of data transfer is the fastest among all the
59. Which one of the following is the correct
modes of data transfer. [ESE-2016]
combination of registers in DMA controller?
Statement (II): In DMA mode the device directly
[ESE-2020]
transfers data to/from memory without interference
(a) Data register, Stack pointer and Data counter
from CPU.
(b) Data register, Address register and Data
(a) Both Statement (I) and Statement (II) are
counter
individually true and Statement (II) is the
correct explanation of Statement (I). (c) Data register, Stack pointer and Address
register
(b) Both Statement (I) and Statement (II) are
individually true but Statement (II) is not the (d) Data register, Program counter and Data
correct explanation of Statement (I) counter
(c) Statement (I) is true but Statement (II) is Sol. (b)
false. Address register to store source address, count
(d) Statement (I) is false but Statement (II) is register → to hold count of no. of bytes Data
true. registers → To hold data from memory or I/O
while transferring.
Sol. (a)

GATE WALLAH ELECTRONICS ENGINEERING for ESE 1.11

Microprocessor
Interfacing
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1.12 GATE WALLAH ELECTRICAL ENGINEERING for ESE

 Microprocessor

Answer Key

1. (c) 16. (a) 31. () 46. (b)

2. (b) 17. (a) 32. (c) 47. (c)
3. (b) 18. (d) 33. (d) 48. (a)
4. (b) 19. (c) 34. (d) 49. (b)
5. (d) 20. (b) 35. (a) 50. (a)
6. (d) 21. (c) 36. (d) 51. (d)
7. (d) 22. (b) 37. () 52. (b)
8. (c) 23. (b) 38. (a) 53. (a)
9. (b) 24. (b) 39. (c) 54. (d)
10. (b) 25. (b) 40. (a) 55. (d)
11. (d) 26. (b) 41. () 56. (a)
12. (b) 27. () 42. (d) 57. ()
13. (b) 28. (d) 43. () 58. (d)
14. (a) 29. (a) 44. (d) 59. (b)
15. (d) 30. (b) 45. (a)
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GATE WALLAH ELECTRONICS ENGINEERING for ESE 1.13