Design of springs

Introduction to 8085 and its

Functional Organization
01
1. The length of a bus cycle in 8086/8088 is four other purposes, such as power supply, clock input,
clock cycles, T1, T2, T3, T4 and an indeterminate and other input pins.
number of wait state clock cycles denoted by Tw Hence, the correct option is (b).
The wait states are always inserted between
[ESE-2001]
4. The program counter in a 8085 micro-processor is a
(a) T1 and T2 (b) T2 and T3
16 -bit register, because [ESE-2003]
(c) T3 and T4 (d) T4 and T1
(a) It counts 16 bits at time
Sol. (c)
(b) There are 16 address lines
The ready signal corresponds to wait states, which
(c) It facilitates the user storing 16-bit data
are always accessible between T3 and T4.
temporarily
Hence, the correct option is (c).
(d) It has to fetch two 8-bit data at a time
Sol. (b)
2. Which one of the following circuits transmits two
In a 8085 microprocessor Program Counter (PC)
messages simultaneously in one direction?
register stores the address of the next instruction to
[ESE-2001] be executed, since address bus in 8085 is 16 bit, the
(a) Duplex (b) Diplex PC register is of 16 bits.
(c) Simplex (d) Quadruplex Hence, the correct option is (b).
Sol. (b)
A Diplex circuit allows transmission of two 5. A microprocessor is ALU [ESE-2003]
independent signals simultaneously over a single (a) and control unit on a single chip
station.
(b) and memory on a single chip
Hence, the correct option is (b).
(c) register unit and I/O device on a single chip
(d) register unit and control unit on a single chip
3. The number of output pins of a 8085
Sol. (d)
microprocessor are
A microprocessor is a programmable device and
[ESE-2002]
contains ALU, control unit and register unit.
(a) 40 (b) 27
Hence, the correct option is (d).
(c) 21 (d) 19
Sol. (b)
6. In Intel 8085 A microprocessor ALE signal is made
The 8085 microprocessor comprises 40 pins in
high to [ESE-2003]
total, of which 27 are used for output and 13 for

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 Microprocessors

(a) Enable the data bus to be used as low order

address bus 9. Match List-I with List-II and select the correct
(b) To latch data D0 – D7 from data bus answer using the codes given below the lists:
(c) To disable data bus List-I
(d) To achieve all the functions listed above A. Monitor program
Sol. (a) B. Assembler
ALE when set high it allows data bus to be used as C. Mnemonic
low order address bus. D. Program counter
Hence, the correct option is (a). List-II
1. Used to indicate memory location
7. Output of the assembler in machine codes is 2. A combination of letters, symbols and
referred to as numerals
[ESE-2003]
3. A program that translates symbolic
(a) Object program instructions into binary equivalent
(b) Source program 4. An operating system
(c) Macroinstruction Codes : [ESE-2004]
(d) Symbolic addressing A B C D
Sol. (a) (a) 4 3 2 1
The term "Object program" refers to the machine (b) 4 3 1 2
code output produced by the assembler, which is
(c) 3 4 1 2
made up of machine language instructions that are
(d) 3 4 2 1
derived from the source code.
Sol. (a)
Hence, the correct option is (a).
Assembler: a program that translates symbolic code
into binary code that translates source code into
8. Which one of the following statements for Intel
object code.
8085 is correct? [ESE-2004]
A mnemonic system consists of a mix of numerals
(a) Program counter (PC) specifies the address
and letters.
of the instruction last executed
Program counter → Indicates where the next
(b) PC specifies the address of the instruction
instruction to be executed is stored in memory.
being executed
An operating system is an observer program.
(c) PC specifies the address of the instruction to
Hence, the correct option is (a).
be executed
(d) PC specifies the number of instructions
executed so far 10. A good assembly language programmer should use
general purpose registers rather than memory in
Sol. (c)
maximum possible ways for data processing. This
In a 8085 microprocessor Program Counter (PC)
is because :
register stores the address of the next instruction to
(a) Data processing with registers is easier than
be executed.
with memory.
Hence, the correct option is (c).

1.2 GATE WALLAH ELECTRICAL ENGINEERING for ESE

 Introduction to 8085 and its Functional
Organization
(b) Data processing with memory requires more Sol. (c)
instructions in the program than that with 8086 has 20 address lines so it can address
registers.
= 220 memory locations
(c) Of limited set of instructions for data
= 210  210
processing with memory.
=1K1K
(d) Data processing with registers takes fewer
cycles than that with memory. [ESE-2005] = 1 M memory location
Sol. (d) so total memory it can address is 1 M byte.
Registers allow for faster data transfer than 8086 has thirteen 16 bit registers.
memory does. Data transfer often occurs during 8086 has 9 flags as CF, PF, AF, ZF, SF, TF, IF,
opcode fetch, requiring additional memory read or DF, OF.
write cycles. Hence, the correct option is (c).
Hence, the correct option is (d).
13. Processor status word of 8085 microprocessor has
11. Which of the following is not correct? five flags. Which are these five flags? [ESE-2006]
(a) Bus is a group of wires. (a) S, Z, AC, P, CY (b) S, OV, AC, P, CY
(b) Bootstrap is a technique or device for (c) S, Z, OV, P, CY (d) S, Z, AC, P, OV
loading first instruction. Sol. (a)
(c) An instruction is a set of bits that defines a 8085's flag register is as
computer operation.
S Z X AC X P X CY
(d) An interrupt signal is required at the start of
every program. [ESE-2005] The status flags are S, Z, AC, P, CY
Sol. (d) Hence, the correct option is (a).
An interrupt signal is only required at start for sub
routine programs, and not every program. 14. What are the sets of commands in a program which
Hence, the correct option is (d). are not translated into machine instructions during
assembly process, called? [ESE-2007]

12. Consider the following statements: (a) Mnemonics (b) Directives

1. A total of about one million bytes can be (c) Identifiers (d) Operands
directly addressed by the 8086 Sol. (b)
microprocessor Directives are instructions or commands in
2. 8086 has thirteen 16 -bit registers assembly language that provide guidance to the
3. 8086 has eight flags assembler about how to process the source code.

4. Compared to 8086, the 80286 provides a Hence, the correct option is (b).
higher degree of memory protection.
Which one of the statements given above are 15. The cycle required to fetch and execute an
correct? [ESE-2005] instruction in a 8085 microprocessor is which one
(a) 2, 3 and 4 (b) 1, 3 and 4 of the following? [ESE-2007]

(c) 1, 2 and 4 (d) 1, 2 and 3 (a) Clock cycle (b) Memory cycle

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 Microprocessors

(c) Machine cycle (d) Instruction cycle (c) To slow down a fast peripheral device so as
Sol. (d) to communicate at the microprocessor's
device.
The cycle required to fetch and execute an
instruction in an 8085 microprocessor is commonly (d) None of the above
known as the "Instruction cycle." Sol. (b)
Hence, the correct option is (d). READY signal is used for slow responding
peripherals to communicate with microprocessor.
16. In an Intel 8085 A, which is always the first Hence, the correct option is (b).
machine cycle of an instruction?
[ESE-2008] 19. Assertion (A) : Monostable multivibrators (IC
(a) An op-code fetch cycle 74121) are used in a microprocessor based system
(b) A memory read cycle for frequency measurement.
(c) A memory write cycle Reason (R) : Microprocessor counts the number of
interrupt signals/second or within a specified
(d) An I/O read cycle
interval through ISR. [ESE-2009]
Sol. (a)
(a) Both A and R are true and R is the correct
The opcode fetch cycle is always the initial
explanation of A
machine cycle of an instruction in the Intel 8085 A
(b) Both A and R are true but R is NOT the
microprocessor. The microprocessor retrieves the
correct explanation of A
instruction's opcode (operation code) from memory
during this cycle. (c) A is true but R is false
Hence, the correct option is (a). (d) A is false but R is true
Sol. (a)
17. Both the ALU and control section of CPU employ Both are correct. IC74121 is used for frequency
which special purpose storage locations? measurement in microprocessor based system. How
it measures the frequency by counting number of
[ESE-2008]
interrupt signal generated within one second or
(a) Buffers (b) Decoders
subjected interval of time through ISR.
(c) Accumulators (d) Registers
Hence, the correct option is (a).
Sol. (c)
Accumulators are used for many purposes like it is
20. Consider the following :
used in all logical and arithmetical operations.
1. Sign flag 2. Trap flag
Hence, the correct option is (c).
3. Parity flag 4. Auxiliary carry
flag
18. In an Intel 8085 A microprocessor, why is READY
Which of the above flags is/are present in 8085
signal used? [ESE-2008]
microprocessor? [ESE-2009]
(a) To indicate to user that the micro-processor
(a) 1 only (b) 1 and 2
is working and is ready for use.
(c) 2 and 3 (d) 1, 3 and 4
(b) To provide proper WAIT states when the
Sol. (d)
microprocessor is communicating with a
slow peripheral device.

1.4 GATE WALLAH ELECTRICAL ENGINEERING for ESE

 Introduction to 8085 and its Functional
Organization
The flags present in 8085 microprocessor are Sign Sol. (b)
flag, parity flag and auxiliary carry flag. Both assertion and reason are true, but reason is not
Hence, the correct option is (d). correct explanation of assertion. Address bus
carries address from the CPU to memory and I/O
devices, its unidirectional. Data bus is bidirectional,
21. Consider the following statements:
it carries both from memory to CPU and from the
In 8085 microprocessor, data-bus and address bus
CPU to memory.
are multiplexed in order to [ESE-2009]
Hence, the correct option is (b).
1. Increase the speed of microprocessor.
2. Reduce the number of pins.
24. Assertion (A) : The frequency of 8085 system is
3. Connect more peripheral chips.
1/2 of the crystal frequency.
Which of these statements is/are correct?
Reason (R) : Microprocessor (8085) requires a two
(a) 1 only (b) 2 only phase clock. [ESE-2010]
(c) 2 and 3 (d) 1, 2 and 3 (a) Both A and R are true and R is the correct
Sol. (b) explanation of A
To reduce the number of pins, the 8085 lower order (b) Both A and R are true but R is NOT the
address bus and data bus are multiplexed. correct explanation of A
Demultiplexing is accomplished via the ALE pin, (c) A is true but R is false
which is used when 1 lower order byte is used as an
(d) A is false but R is true
address and when 0 is used as data.
Sol. (b)
Hence, the correct option is (b).
The frequency of the 8085 system is indeed
typically half of the crystal frequency because the
22. The field, which is never present in an assembly 8085 microprocessor uses a basic clocking
language statement, is [ESE-2010] mechanism that requires two clock cycles for each
(a) Opcode (b) Operand instruction cycle.
(c) Continue (d) Comment The 8085 microprocessor requires a two-phase
Sol. (c) clock, which means the clock signal oscillates
between two complementary phases, to properly
In an assembly language statement, “Continue”
synchronize the internal operations.
field is not present.
Both the statements are true but Reason does not
Hence, the correct option is (c).
directly explains Assertion.
Hence, the correct option is (b).
23. Assertion (A) : Address bus is unidirectional.
Reason (R) : Data bus is bidirectional. [ESE-2010]
25. ALU (Arithmetic Logic Unit) of an 8085
(a) Both A and R are true and R is the correct
microprocessor consists of [ESE-2011]
explanation of A
(a) Accumulator, temporary register, arithmetic
(b) Both A and R are true but R is NOT the
and logic circuits
correct explanation of A
(b) Accumulator, arithmetic, logic circuits and
(c) A is true but R is false
five flags
(d) A is false but R is true
(c) Accumulator, arithmetic and logic circuits

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 Microprocessors

(d) Accumulator, temporary register, arithmetic, (a) A memory read cycle

logic circuits and five flags (b) A fetch cycle
Sol. (b) (c) An 1/0 read cycle
ALU consists of Accumulator, temporary resisters, (d) A memory write cycle
logic circuits and five flags.
Sol. (b)
Hence, the correct option is (b).
Opcode fetch cycle is the first machine cycle of any
instruction.
26. Which components are NOT found on chip in a Hence, the correct option is (b).
microprocessor but may be found on chip in a
microcontroller? [ESE-2011]
29. The output data lines of microprocessors and
(a) SRAM and USART
memories are usually tristated because [ESE-2011]
(b) EPROM and PORTS
(a) More than one device can transmit
(c) EPROM, USART and PORTS information over the data bus by enabling
(d) SRAM, EPROM and PORTS only one device at a time.
Sol. (c) (b) More than one device can transmit over the
Microcontrollers have on-chip EPROM, USART, data bus at the same time.
and ports, whereas microprocessors do not. (c) The data lines can be multiplexed for both
Hence, the correct option is (c). input and output.
(d) It increases the speed of data transfer over
the data bus.
27. For the purpose of data processing an efficient
assembly language programmer makes use of the Sol. (a)
general purpose registers rather than memory. The The output data lines of microprocessors and
reason is [ESE-2011] memories are typically tristate because more than
(a) the set of instructions for data processing one device can transmit information over the data
with memory is limited. bus by enabling only one device at a time.
(b) data processing becomes easier when register Hence, the correct option is (a).
are used.
(c) more memory related instructions are 30. The correct sequence of steps in the instruction
required in the program for data processing. cycle of a basic computer is
(d) data processing with registers takes fewer [ESE-2012]
cycles than that with memory. (a) Fetch, Execute, Decode and Read effective
Sol. (d) address.
Because processing data through registers requires (b) Read effective address, Decode, Fetch and
less cycles than processing data through memory, it Execute.
is faster than processing data through memory. (c) Fetch, Decode, Read effective address and
Hence, the correct option is (d). Execute.
(d) Fetch, Read effective address, Decode and
Execute.
28. The first machine cycle of an instruction is always
Sol. (c)
[ESE-2011]

1.6 GATE WALLAH ELECTRICAL ENGINEERING for ESE

 Introduction to 8085 and its Functional
Organization
An instruction cycle is the amount of time needed Sol. (b)
to finish one instruction. In this cycle, an Mnemonics in assembly language represent
instruction is fetched, decoded, read at its effective specific instructions or operations that the CPU will
location, and then executed. execute. They serve as a human-readable shorthand
Hence, the correct option is (c). for the machine language instructions understood
by the processor.
31. Following is a 16-bit register for 8085 Example – In (MVI A, 25) , MVI is mnemonic.
microprocessor: [ESE-2012] Hence, the correct option is (b).
(a) Stack pointer (b) Accumulator
(c) Register B (d) Register C 34. While using a frequency counter for measuring
Sol. (a) frequency, two modes of measurement are possible.
For 8085 microprocessor, stack pointer is 16 -bit 1. Period mode 2. Frequency mode
register. There is a 'cross-over frequency' below which the
Hence, the correct option is (a). period mode is preferred. Assuming the crystal
oscillator frequency to be 4 MHz the cross-over
frequency is given by [ESE-2013]
32. The register which holds the information about the
(a) 8 MHz (b) 2 MHz
nature of results of arithmetic of logic operations is
called as [ESE-2012] (c) 2 kHz (d) 1 kHz
(a) Accumulator Sol. (b)
(b) Condition code register Crystal Frequency = 4 MHz
(c) Flag register
(d) Process status registers Cross frequency
Sol. (c) Hence, the correct option is (b).
A component of the arithmetic/logic unit (ALU) is
the accumulator. This register is used to carry out 35. In a 8085 microprocessor system with memory
logical and arithmetic operations as well as store 8- mapped I/O, which of the following is true?
bit data. An operation's outcome is kept in the
[ESE-2013]
accumulator, and flags are used to identify the type
(a) Devices have 8-bit address line
of outcome.
(b) Devices are accessed using IN and OUT
Hence, the correct option is (c).
instructions
(c) There can be maximum of 256 input devices
33. When referring to instruction words, a mnemonic is
and 256 output devices
[ESE-2012]
(d) Arithmetic and logic operations can be
(a) a short abbreviation for the operand address directly performed with the I/O data
(b) a short abbreviation for the operation to be Sol. (d)
performed.
Memory-mapped I/O is an approach that treats I/O
(c) a short abbreviation for the data word stored devices like memory locations. This indicates that
at the operand address. the same instructions (IN and OUT) used to access
(d) Shorthand for machine language. memory locations are also utilized to access I/O

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 Microprocessors

devices. The memory address space includes the [ESE-2014]

addresses used to reach these devices. Thus, it is (a) DMA bus (b) Memory bus
accurate to say that IN and OUT commands are
(c) Address bus (d) Control bus
used to access devices.
Sol. (b)
Hence, the correct option is (d).
Data bus is responsible for data transfer between
the CPU and main memory, ti is also called
36. Consider the following statements: memory bus.
Arithmetic Logic Unit (ALU) [ESE-2013] Hence, the correct option is (b).
1. Performs arithmetic operations.
2. Performs comparisons. 39. The operations executed by two or more control
3. Communicates with I/O devices. units are referred as [ESE-2014]
4. Keeps watch on the system. (a) Micro-operations
Which of these statements are correct? (b) Macro-operations
(a) 1, 2, 3 and 4 (b) 1, 2 and 3 only (c) Multi-operations
(c) 1 and 2 only (d) 3 and 4 only (d) Bi control-operations
Sol. (c) Sol. (c)
ALU performs only arithmetic and logical The operations executed by two or more control
operations. units are referred as multioperation.
Hence, the correct option is (c). Hence, the correct option is (c).

37. Ready pin of microprocessor is used [ESE-2014] 40. Consider the following registers:
(a) to indicate that microprocessor is ready to 1. Accumulator and flag register
receive inputs 2. B and C registers
(b) to indicate that microprocessor is ready to 3. D and E registers
receive outputs
4. H and L registers
(c) to introduce wait state
Which of these 8 bit registers of 8085 P can be
(d) to provide direct memory access paired together to make a 16 bit register?
Sol. (c) [ESE-2014]
A microprocessor's Ready pin is an input signal (a) 1, 3 and 4 (b) 2, 3 and 4
that's frequently utilized to introduce wait states. A
(c) 1, 2 and 3 (d) 1, 2 and 4
wait state is a cycle in which the CPU stops
working to wait for external devices-usually Sol. (b)
memory or I/O devices-to finish their tasks. 8085 offers B – C, D – E and H – L as register pairs
Hence, the correct option is (c). which can be used to handle 16-bit data.
Hence, the correct option is (b).

38. A bus connected between the CPU and the main

memory that permits transfer of information 41. The first microprocessor to include virtual memory
between main memory and the CPU is known as in the Intel microprocessor family is [ESE-2014]

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 Introduction to 8085 and its Functional
Organization
(a) 80286 (b) 80386 Hence, the correct option is (c).
(c) 80486 (d) Pentium
Sol. (a) 43. Statement (I) : Ready signal of microprocessor is
An extremely powerful 16-bit microprocessor is the used to detect whether a peripheral is ready for the
Intel 80286. It can manage memory, protect data transfer or not.
memory at four different levels, and handle virtual Statement (II) : In the microprocessor during data
memory and operating systems. transfer operations, the wait states are added by
Hence, the correct option is (a). forcing the ready signal low. [ESE-2015]
Codes :
42. Statement (I) : Segment Override Prefix (SOP) is (a) Both Statement (I) and Statement (II) are
used when a default offset register is not used with individually true and Statement (II) is the
its default base segment register but with a different correct explanation of Statement (I).
base register. (b) Both Statement (I) and Statement (II) are
Statement (II) : The offset registers IP and SP can individually true but Statement (II) is not the
never be associated with any other segment correct explanation of Statement (I).
registers apart from their respective default (c) Statement (I) is true but Statement (II) is
segments. false.
Codes : [ESE-2014] (d) Statement (I) is false but Statement (II) is
(a) Both Statement (I) and Statement (II) are true.
individually true and Statement (II) is the Sol. (c)
correct explanation of Statement (I). It is true that a microprocessor's Ready signal is
(b) Both Statement (I) and Statement (II) are used to determine if a peripheral device is prepared
individually true but Statement (II) is not the to receive data. The peripheral is prepared to send
correct explanation of Statement (I). or receive data when the Ready signal is indicated.
(c) Statement (I) is true but Statement (II) is Statement I is True.
false.
(d) Statement (I) is false but Statement (II) is .
true.
Sol. 44. Program counter in a digital computer [ESE-2015]
(a) counts the numbers of programs run in the
machine
(b) counts the number of times a subroutine is
called
(c) counts the number of times the loops are
executed
(d) points the memory address of the current or
Segment override allows the offset registers IP
the next instruction to be executed
(Instruction Pointer) and SP (Stack Pointer) to be
linked to distinct segment registers. So, statement II Sol. (d)
is False.

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 Microprocessors

Program Counter points to the address of next

instruction which is to be executed. 48. The relation among IC (Instruction Cycle), FC
Hence, the correct option is (d). (Fetch Cycle) and EC (Execute Cycle) is
[ESE-2015]
45. During which T-state, contents of OP code from (a) IC = FC – EC (b) IC = FC + EC
memory are loaded into IR (Instruction Register)? (c) IC = FC + 2EC (d) EC = IC + FC
[ESE-2015] Sol. (b)
(a) T1 OP code Fetch (b) T2 OP code Fetch Instruction cycle is combination of fetch cycle and
(c) T3 OP code Fetch (d) T4 OP code Fetch execute cycle.
Sol. (b) Hence, the correct option is (b).
The contents of the opcode from memory are
normally loaded into the Instruction Register (IR) 49. Each instruction in an assembly language program
during the second machine cycle (T2) or the second has the following fields
T-state of the instruction execution fetch cycle.
1. Label field 2. Mnemonic field
Hence, the correct option is (b).
3. Operand field 4. Comment field
What is the correct sequence of these fields?
46. Assuming LSB is at position 0 and MSB at position
[ESE-2015]
7, which bit positions are not used (undefined) in
(a) 1, 2, 3 and 4 (b) 2, 1, 4 and 3
Flag Register of an 8085 microprocessor?
(c) 1, 3, 2 and 4 (d) 2, 4, 1 and 3
[ESE-2015]
Sol. (c)
(a) 1, 3, 5 (b) 2, 3, 5
The correct sequence of fields for each instruction
(c) 1, 2, 5 (d) 1, 3, 4
in an assembly language program is typically:
Sol. (a)
1. Label field (if present)
Flag register of 8085 microprocessor is
2. Mnemonic field
S Z X AC X P X C 3. Operand field (if present)
7 6 5 4 3 2 1 0 4. Comment field (if present)
Hence, the correct option is (c).
Positions 1,3,5 are not used for flag.
Hence, the correct option is (a).
50. What is the assembler directive statement used to
reserve an array of 100 words in memory and
47. At the beginning of a fetch cycle, the contents of initialize all 100 words with 0000 and give it a
the program counter are [ESE-2015] name STORAGE? [ESE-2016]
(a) incremented by one (a) STORAGE DW 100
(b) transferred to address bus (b) STORAGE DW 100 DUP (0)
(c) transferred to memory address register (c) STORAGE DW 100 DUP (?)
(d) transferred to memory data register (d) STORAGE DB 100
Sol. (b) Sol. (b)

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 Introduction to 8085 and its Functional
Organization
Words so DW  Define words i.e., 2 bytes of (b) higher address bus
memory locations are reserved. (c) data bus
But for array STORAGE DW 100 DUP (0) (d) lower as well as higher order address bus
DUP (0)  Means 100 words space is reserved Sol. (d)
with data in location initialized as 0000 H. In IN and OUT instructions, as I/O has 8 bit
Hence, the correct option is (b). address in last machine cycle address is placed on
A15 – A8 (AD7 – AD0).
51. Consider the symbol shown below. Hence, the correct option is (d).

54. Statement (I) : Registers are used for storage of

What function does the above symbol represent in a small data in the microprocessor.
program flow chart? [ESE-2016] Statement (II) : All registers are accessible to the
(a) A process user through instructions. [ESE-2020]

(b) Decision making (a) Both Statement (I) and Statement (II) are
individually true and Statement (II) is the
(c) A subroutine
correct explanation of Statement (I)
(d) Continuation
(b) Both Statement (I) and Statement (II) are
Sol. (c) individually true; but Statement (II) is not the
 Symbol for subroutine. correct explanation of Statement (I)
(c) Statement (I) is true; but Statement (II) is
false
Hence, the correct option is (c).
(d) Statement (I) is false; but Statement (II) is
true
52. When a peripheral is connected to the
Sol. (c)
microprocessor in input/output mode, the data
transfer takes place between [ESE-2016] Registers are used for storage of small data in the
microprocessor, however not all registers are
(a) any register and I/O device
accessible by the programmer/user.
(b) memory and I/O device
Hence, the correct option is (c).
(c) accumulator and I/O device
(d) HL register and I/O device
55. Which one of the following is used for recognizing
Sol. (c) the magnetic encoding numbers printed at the
The data transmission usually occurs between the bottom of a cheque? [ESE-2023]
accumulator and the I/O device when a peripheral (a) Optical Mark Recognition
is connected to the CPU in input/output mode.
(b) Magnetic Ink Character Recognition
Hence, the correct option is (c).
(c) Barcode Reader
(d) Optical Character Recognition
53. While execution of I/O instruction takes place, the
Sol. (b)
8-bit address of the port is placed on [ESE-2016]
The magnetic encoding numbers printed at the
(a) lower address bus
bottom of a cheque are typically recognized using

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 Microprocessors

(b) Magnetic Ink Character Recognition (MICR)  AND logic can be implemented for bytes/
technology. words as it is a bit-wise operation.
Hence, the correct option is (b).  to a peripheral device, or vice-versa.
Hence, the correct option is (c).
56. According to the description of the AND
instruction of 8086 microprocessor, what are the
essential conditions to be satisfied while executing
it?
1. The source can be a register or a memory
location.
2. The destination can be a register or a
memory location.
3. The source and destination must both be
bytes or be words.
4. The source and the destination cannot both
be memory locations in an instruction.
[ESE-2023]
(a) 1 and 2 only (b) 1 and 4 only
(c) 1, 2, 3 and 4 (d) 1, 2 and 3
Sol. (c)
8086 is a 16 -bit microprocessor :
 AND instructions can work with source as a
Register/Memory and destination can also be
Register/Memory but both operands can't be
memory.
 AND can also be with immediate data.

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