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ENGINEERING
Switches
31st March 2023
• Switches
• The CMOS Transistor
• Building Circuits Using Gates
• Class Exercises
• Gates vs. switches
• Conclusion
4.5 A
4.5 A
between two points (volts, V) – +
9V
– Analogous to water pressure
• Resistance: Tendency of wire to resist
2 ohms
current flow (ohms, )
– Analogous to water pipe diameter 9V
0V
• Current: Flow of charged particles (amps, A)
– Analogous to water flow 4.5 A
• V = I * R (Ohm’s Law) a
– 9 V = I * 2 ohms
– I = 4.5 A If a 9V potential difference is applied
across a 2 ohm resistor, then 4.5 A of
current will flow.
quarter
(to see the relative size)
Showed application 1 0 0
x y
Digital design x
0
1 1
• Implement Boolean operators using
transistors 1.8 V
Next slides show how
“1”
these circuits work.
– Call those implementations logic gates. 1.2 V Note: The above OR/AND
– Lets us build circuits by doing math - 0.6 V implementations are
inefficient; we’ll show why,
“0”
- powerful concept 0V and show better ones,
later.
1 and 0 each actually corresponds to
a voltage range
– Turn on lamp (F=1) when motion sensed (a=1) and no light (b=0)
– F = a AND NOT(b)
– Build using logic gates, AND and NOT, as shown
– In that case, a first digital circuit is built.
Seatbelt
• Timing diagram illustrates circuit Inputs
behavior k
1
– We set inputs to any values 0
1
– Output set according to circuit s a
0
Outputs
1
w
0
time
Switches 31st March 2023 31
Exs. 2: Seat belt warning light extensions
• Only illuminate warning light if
k Belt W a rn
0 BeltWarn
s
k w
w
0
k s
1 Seatbelt a
Circuit
– Makes intuitive sense
a • Occupied if all doors
Circuit are locked
S a S
b b
c
c
p 1 ns
1 ns
1 ns 1 ns a
w
s 1 ns 1+1+1+1+1 = 5 ns
1 ns
1 ns 1 ns 1+0.5+1+1+1+1+1 = 6.5 ns
0.5 ns
t 1 ns 1+1+1 = 3 ns
Critical path delay = 6.5 ns
Hence, circuit’s delay is 6.5 ns
• Wires also have delay
• Assume gates and wires have delays as shown
• Path delay – time for input to affect output
• Critical path – path with longest path delay
• Circuit delay – delay of critical path
pMOS
1 0
IC gate
(a)