Teaching ESD Chap3

Electronic System Design Finite State Machine
Finite State Machine
1. Review on counter design

2. State Diagrams for FSM
3. Moore & Mealy Models
4. State Minimization
5. Examples
6. HDL for FSM
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Sequential Logic Implementation

• Models for representing sequential circuits
– Finite-state machines (Moore and Mealy)
– Representation of memory (states)
– Changes in state (transitions)
• Design procedure
– State diagrams
– State transition table
– Next state functions
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2 – STATE DIAGRAM FOR FSM
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Finite State Machines

• Sequential circuits
– primitive sequential elements
– combinational logic
– finite-state machines (Moore and Mealy)
• Basic sequential circuits revisited
– shift registers
– counters
• Design procedure
– state diagrams
– state transition table
– next state functions
• Hardware description languages
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Abstraction of state elements

1. Divide circuit
– combinational logic and state
2. Feedback loops
– Localize
– Break cycles Inputs Outputs
3. storage elements Combinational
Logic
– sequential logic
State Inputs State Outputs
Storage Elements
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Forms of sequential logic

1. Asynchronous sequential logic
– state changes occur whenever state inputs change
– elements may be simple wires or delay elements
2. Synchronous sequential logic

– state changes occur in lock step across all storage elements
– using a periodic waveform - the clock
Clock
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FSM Representations
1. States
– determined by possible values in sequential storage elements
2. Transitions
– change of state
3. Clock
– controls when state can change by controlling storage elements
4. Sequential logic
– sequences through a series of states
– based on sequence of values on input signals
– clock period defines elements of sequence
001 010 111
In = 1 In = 0
In = 0
100 110
In = 1
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Can any sequential system be

represented with a state diagram?
OUT1 OUT2 OUT3
• Shift register
– input value shown
IN D Q D Q D Q
on transition arcs
– output values shown CLK
within state node
1
100 110
1 0 1 1
1
0 000 1 010 101 0 111 1
0
0 0 1 0
001 011
0
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1- DESIGN A COUNTER
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Counters are simple finite state

machines
• Counters
– proceed through well-defined sequence of states in response to
enable
• Many types of counters: binary, BCD, Gray-code
– 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
– 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
001 010 011
000 3-bit up-counter 100
111 110 101
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How do we turn a state diagram

into logic?
• Counter
– 3 flip-flops to hold state
– logic to compute next state
– clock signal controls when flip-flop memory can change
• wait long enough for combinational logic to compute new value
• don't wait too long as that is low performance
OUT1 OUT2 OUT3
D Q D Q D Q
CLK
"1"
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FSM design procedure

• Start with counters
– simple because output is just state
– simple because no choice of next state based on input
• State diagram to state transition table
– tabular form of state diagram
– like a truth-table
• State encoding
– decide on representation of states
– for counters it is simple: just its value
• Implementation
– flip-flop for each state bit
– combinational logic based on encoding
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FSM design procedure: state

diagram to encoded state transition
table – counter case 1
• Tabular form of state diagram
• Like a truth-table (specify output for all input combinations)
• Encoding of states: easy for counters – just use value
010 011
present state next state
001
0 000 001 1
1 001 010 2
000 3-bit up-counter 100 2 010 011 3
3 011 100 4
111 110 101 4 100 101 5
5 101 110 6
6 110 111 7
7 111 000 0
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Implementation
• D flip-flop for each state bit
Verilog notation to show
• Combinational logic based on encoding function represents an
input to D-FF
C3 C2 C1 N3 N2 N1
0 0 0 0 0 1
0 0 1 0 1 0 N1 <= C1’
0 1 0 0 1 1 N2 <= C1C2’ + C1’C2
0 1 1 1 0 0 <= C1 xor C2
N3 <= C1C2C3’ + C1’C3 + C2’C3
1 0 0 1 0 1 <= (C1C2)C3’ + (C1’ + C2’)C3
1 0 1 1 1 0 <= (C1C2)C3’ + (C1C2)’C3
1 1 0 1 1 1 <= (C1C2) xor C3
1 1 1 0 0 0
N3 C3 N2 C3 N1 C3
0 0 1 1 0 1 1 0 1 1 1 1
C1 0 1 0 1 C1 1 0 0 1 C1 0 0 0 0
C2 C2 C2
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Back to the shift register -

counter case 2
• Input determines next state
In C1 C2 C3 N1 N2 N3
0 0 0 0 0 0 0 1
100 110
0 0 0 1 0 0 0
0 0 1 0 0 0 1 1 0 1 1
1
0 0 1 1 0 0 1
0 000 1 010 101 0 111 1
0 1 0 0 0 1 0
0 1 0 1 0 1 0 0 1 0
0 0
0 1 1 0 0 1 1
0 1 1 1 0 1 1 001 011
0
1 0 0 0 1 0 0
1 0 0 1 1 0 0 N1 <= In
1 0 1 0 1 0 1 N2 <= C1
1 0 1 1 1 0 1 N3 <= C2 OUT1 OUT2 OUT3
1 1 0 0 1 1 0
1 1 0 1 1 1 0
1 1 1 0 1 1 1 IN D Q D Q D Q
1 1 1 1 1 1 1
CLK
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More complex counter example -

counter case 3
• Complex counter
– repeats 5 states in sequence
– not a binary number representation
• Step 1: derive the state transition diagram
– count sequence: 000, 010, 011, 101, 110
• Step 2: derive the state transition table from the state transition
diagram
Present State Next State
000 110 C B A C+ B+ A+
0 0 0 0 1 0
0 0 1 – – –
0 1 0 0 1 1
010 101 0 1 1 1 0 1
1 0 0 – – –
1 0 1 1 1 0
011 1 1 0 0 0 0
1 1 1 – – –
note the don't care conditions that arise from the unused state codes
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More complex counter example

(cont’d)
• Step 3: K-maps for next state functions
C+ C B+ C A+ C
0 0 0 X 1 1 0 X 0 1 0 X
A X 1 X 1 A X 0 X 1 A X 1 X 0
B B B
C+ <= A
B+ <= B’ + A’C’
A+ <= BC’
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Self-starting counters (cont’d) –

counter case 3a
• Re-deriving state transition table from don't care assignment
C+ C B+ C A+ C
0 0 0 0 1 1 0 1 0 1 0 0
A 1 1 1 1 A 1 0 0 1 A 0 1 0 0
B B B
Present State Next State 111 001

C B A C+ B+ A+
0 0 0 0 1 0
0 0 1 1 1 0 000 110
0 1 0 0 1 1 100
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 1 1 0 010 101
1 1 0 0 0 0
1 1 1 1 0 0
011
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Self-starting counters
• Start-up states
– at power-up, counter may be in an unused or invalid state
– designer must guarantee that it (eventually) enters a valid state
• Self-starting solution
– design counter so that invalid states eventually transition to a valid
state
– may limit exploitation of don't cares
111 111 implementation 001
001 on previous slide
000 110 000 110

100 100
010 101 010 101
011 011
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Activity
• 2-bit up-down counter (2 inputs)
– direction: D = 0 for up, D = 1 for down
– count: C = 0 for hold, C = 1 for count
S1 S0 C D N1 N0
0 0 0 0 0 0
C=0 C=0
0 0 0 1 0 0
D=X C=1 D=X 0 0 1 0 0 1
D=0 0 0 1 1 1 1
0 1 0 0 0 1
00 11 0 1 0 1 0 1
C=1 C=1 0 1 1 0 1 0
C=1 0 1 1 1 0 0
D=0 D=1 D=0 1 0 0 0 1 0
1 0 0 1 1 0
01 10 1 0 1 0 1 1
C=1 1 0 1 1 0 1
C=0 D=0 C=0 1 1 0 0 1 1
D=X D=X
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 1 1 0
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Activity (cont’d)
S1
0 0 1 1 N1 = C’S1
S1 S0 C D N1 N0 0 0 1 1 + CDS0’S1’ + CDS0S1
D + CD’S0S1’ + CD’S0’S1
0 0 0 0 0 0
C 1 0 1 0 = C’S1
0 0 0 1 0 0
0 0 1 0 0 1 0 1 0 1 + C(D’(S1  S0) + D(S1  S0))
0 0 1 1 1 1 S0
S1
0 1 0 0 0 1
0 1 0 1 0 1 0 1 1 0
N0 = CS0’ + C’S0
0 1 1 0 1 0 0 1 1 0
0 1 1 1 0 0 D
1 0 0 0 1 0 C 1 0 0 1
1 0 0 1 1 0 1 0 0 1
1 0 1 0 1 1 S0
1 0 1 1 0 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 1 1 0
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Counter/shift-register model
• Values stored in registers represent the state of the circuit
• Combinational logic computes:
– next state
• function of current state and inputs
– outputs
• values of flip-flops
next state
Inputs Next State
logic
Current State
Outputs
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General state machine model

• Values stored in registers represent the state of the circuit
• Combinational logic computes:
– next state
• function of current state and inputs
– outputs
• function of current state and inputs (Mealy machine)
• function of current state only (Moore machine)
output Outputs
logic
Inputs
next state Next State
logic
Current State
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State machine model (cont’d)

• States: S1, S2, ..., Sk
• Inputs: I1, I2, ..., Im
• Outputs: O1, O2, ..., On
• Transition function: Fs(Si, Ij)
• Output function: Fo(Si) or Fo(Si, Ij)
output Outputs
logic
Inputs
next state Next State
logic
Current State
Next State
State
Clock 0 1 2 3 4 5
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3 - MOORE & MEALY MACHINES
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Mealy vs Moore Machines

• Mealy machines tend to have less states
– different outputs on arcs (n2) rather than states (n)
• Moore machines are safer to use
– outputs change at clock edge (always one cycle later)
– in Mealy machines, input change can cause output change as soon as
logic is done – a big problem when two machines are interconnected –
asynchronous feedback may occur if one isn’t careful
• Mealy machines react faster to inputs
– react in same cycle – don't need to wait for clock
– in Moore machines, more logic may be necessary to decode state into
outputs – more gate delays after clock edge
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Comparison of Mealy and Moore

machines (cont’d)
• Moore inputs
combinational
logic for
next state logic for
reg outputs
outputs
state feedback
• Mealy inputs
logic for
outputs
outputs
combinational
logic for reg
next state
state feedback
• Synchronous Mealy
logic for
inputs outputs
outputs
combinational
logic for reg
next state
state feedback
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Outputs for a Moore machine

• Output is only function of state
– specify in state bubble in state diagram
– example: sequence detector for 01 or 10
current next
reset input state state output
0
1 – – A
1 0 0 A B 0
B/0 D/1
0 1 A C 0
0 0 0 B B 0
0
reset 0 1 B D 0
A/0 1 0
0 0 C E 0
1 0 1 C C 0
1
0 0 D E 1
C/0 E/1 0 1 D C 1
0
0 0 E B 1
1 0 1 E D 1
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Outputs for a Mealy machine

• Output is function of state and inputs
– specify output on transition arc between states
– example: sequence detector for 01 or 10
0/0 current next

reset input state state output
B 1 – – A 0
0 0 A B 0
0/0
0 1 A C 0
reset/0 0 0 B B 0
A 0/1 1/1
0 1 B C 1
0 0 C B 1
1/0
0 1 C C 0
C
1/0
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Registered Mealy machine (really

Moore)
• Synchronous (or registered) Mealy machine
– registered state AND outputs
– avoids ‘glitchy’ outputs
– easy to implement in PLDs
• Moore machine with no output decoding
– outputs computed on transition to next state rather than after
entering
– view outputs as expanded state vector
output Outputs
logic
Inputs
next state
logic
Current State
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Activity
A 3-bit sequence detector will detect 111 and 001. All the input and
output will be reset after each sequence had been detected. An
example of input/output sequence that satisfies the conditions of the
network specifications is as follows;
x=011 111 010 100 001 011
z=000 001 000 000 001 000
Draw the state transition diagram of the system using Mealy machine
method.
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Example: Ant Brain (Ward, MIT)

• Sensors:
– L and R antennae, 1 if in touching wall
• Actuators:
– F - forward step, TL/TR - turn
left/right slightly
• Goal:
– find way out of maze
• Strategy:
– keep the wall on the right
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Ant Behavior
A: Following wall, touching B: Following wall, not touching
Go forward, turning Go forward, turning right
left slightly slightly
D: Hit wall again

C: Break in wall Back to state A
Go forward, turning
right slightly
E: Wall in front F: ...we are here, same as

Turn left until... state B
G: Turn left until...

LOST: Forward until we
touch something
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Designing an Ant Brain

• State Diagram
L+R L’ R
LOST L+R E/G L A

(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’
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Synthesizing the Ant Brain Circuit

• Encode States Using a Set of State Variables
– Arbitrary choice - may affect cost, speed
• Use Transition Truth Table
– Define next state function for each state variable
– Define output function for each output
• Implement next state and output functions using combinational
logic
– 2-level logic (ROM/PLA/PAL)
– Multi-level logic
– Next state and output functions can be optimized together
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Transition Truth Table

• Using symbolic states
and outputs
L+R L’ R
LOST L+R E/G L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
state L R next state outputs
LOST 0 0 LOST F B C
(TR, F) (TR, F) R’
LOST – 1 E/G F R’
LOST 1 – E/G F
A 0 0 B TL, F
A 0 1 A TL, F
A 1 – E/G TL, F
B – 0 C TR, F
B – 1 A TR, F
... ... ... ... ...
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Synthesis
• 5 states : at least 3 state variables required (X, Y, Z)
– State assignment (in this case, arbitrarily chosen)
LOST - 000
E/G - 001
A - 010
B - 011
state L R next state outputs C - 100
it now remains
X,Y,Z X', Y', Z' F TR TL to synthesize
000 0 0 000 1 0 0 these 6 functions
000 0 1 001 1 0 0
... ... ... ... ...
010 0 0 011 1 0 1
010 0 1 010 1 0 1
010 1 0 001 1 0 1
010 1 1 001 1 0 1
011 0 0 100 1 1 0
011 0 1 010 1 1 0
... ... ... ... ...
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Synthesis of Next State and Output

Functions
state inputs next state outputs
X,Y,Z L R X+,Y+,Z+ F TR TL
000 0 0 000 1 0 0
000 - 1 001 1 0 0
000 1 - 001 1 0 0
001 0 0 011 0 0 1
001 - 1 010 0 0 1 e.g.
001 1 - 010 0 0 1
TR = X + Y Z
010 0 0 011 1 0 1
010 0 1 010 1 0 1 X+ = X R’ + Y Z R’ = R’ TR
010 1 - 001 1 0 1
011 - 0 100 1 1 0
011 - 1 010 1 1 0
100 - 0 100 1 1 0
100 - 1 010 1 1 0
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Circuit Implementation
• Outputs are a function of the current state only - Moore machine
output F
TR
logic
TL
L next state Next State
R logic
X+ Y+ Z+
Current State
X Y Z
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Don’t Cares in FSM Synthesis

• What happens to the "unused" states (101, 110, 111)?
• Exploited as don't cares to minimize the logic
– If states can't happen, then don't care what the functions do
– if states do happen, we may be in trouble
L’ R’
L+R L’ R
000 L+R 001 L 010
(F) (TL) (TL, F)
101
L’ R’ R
R
L’ R’
011 100
110 (TR, F) (TR, F) R’
R’
111
Ant is in deep trouble
if it gets in this state
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State Minimization
• Fewer states may mean fewer state variables
• High-level synthesis may generate many redundant states
• Two state are equivalent if they are impossible to distinguish from
the outputs of the FSM, i. e., for any input sequence the outputs are
the same
• Two conditions for two states to be equivalent:

– 1) Output must be the same in both states
– 2) Must transition to equivalent states for all input combinations
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Ant Brain Revisited

• Any equivalent states?
L+R L’ R
LOST L+R E/G L A

(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’
Nurul Hazlina 42
New Improved Brain

• Merge equivalent B and C states
• Behavior is exactly the same as the 5-state brain
• We now need only 2 state variables rather than 3
L+R L’ R
LOST L+R E/G L A

(F) (TL) (TL, F)
L’ R’ L’ R’ R
L’ R’
B/C
R’
(TR, F)
Nurul Hazlina 43
New Brain Implementation
state inputs next state outputs

X+ X Y+ X
X,Y L R X',Y' F TR TL
0 1 1 1 0 1 1 1
00 0 0 00 1 0 0
0 0 1 1 1 0 0 0
00 - 1 01 1 0 0 R R
0 0 1 0 1 0 0 1
00 1 - 01 1 0 0 L L
0 0 1 0 1 0 1 1
01 0 0 11 0 0 1 Y Y
01 - 1 01 0 0 1
01 1 - 01 0 0 1
X X X
10 0 0 11 1 0 1 F TR TL
1 0 1 1 0 0 1 0 0 1 0 1
10 0 1 10 1 0 1
1 0 1 1 0 0 1 0 0 1 0 1
10 1 - 01 1 0 1 R R R
1 0 1 1 0 0 1 0 0 1 0 1
11 - 0 11 1 1 0 L L L
1 0 1 1 0 0 1 0 0 1 0 1
11 - 1 10 1 1 0
Y Y Y
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Example: Vending Machine

• Release item after 15 cents are deposited
• Single coin slot for dimes, nickels
• No change
Reset
N
Vending Open
Coin Machine Release
Sensor FSM Mechanism
D
Clock
Nurul Hazlina 45
Example: Vending Machine (cont’d)

• Suitable Abstract Representation
– Tabulate typical input sequences: Reset
• 3 nickels
• nickel, dime S0
• dime, nickel N D
• two dimes
– Draw state diagram: S1 S2
• Inputs: N, D, reset N D N D
• Output: open chute S4 S5 S6
S3
– Assumptions: [open] [open] [open]
• Assume N and D asserted N

for one cycle
S7
• Each state has a self loop [open]
for N = D = 0 (no coin)
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• Minimize number of states - reuse states whenever possible
Reset present inputs next output

state D N state open
0¢ 0 0 0¢ 0
0 1 5¢ 0
0¢ 1 0 10¢ 0
1 1 – –
N 5¢ 0 0 5¢ 0
0 1 10¢ 0
5¢ D 1 0 15¢ 0
1 1 – –
N 10¢ 0 0 10¢ 0
0 1 15¢ 0
D 10¢ 1 0 15¢ 0
1 1 – –
N+D 15¢ – – 15¢ 1
15¢ symbolic state table

[open]
Nurul Hazlina 47

• Uniquely Encode States
present state inputs next state output

Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 – – –
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 – – –
1 1 – – 1 1 1
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• Mapping to Logic Q1 Q1 Q1
D1 D0 Open
0 0 1 1 0 1 1 0 0 0 1 0
0 1 1 1 1 0 1 1 0 0 1 0
N N N
X X X X X X X X X X X X
D D D
1 1 1 1 0 1 1 1 0 0 1 0
Q0 Q0 Q0
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
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• One-hot Encoding
present state inputs next state output

Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open
0 0 0 1 0 0 0 0 0 1 0 D0 = Q0 D’ N’
0 1 0 0 1 0 0
1 0 0 1 0 0 0
1 1 - - - - - D1 = Q0 N + Q1 D’ N’
0 0 1 0 0 0 0 0 1 0 0
0 1 0 1 0 0 0 D2 = Q0 D + Q1 N + Q2 D’ N’
1 0 1 0 0 0 0
1 1 - - - - -
0 1 0 0 0 0 0 1 0 0 0 D3 = Q1 D + Q2 D + Q2 N + Q3
0 1 1 0 0 0 0
1 0 1 0 0 0 0 OPEN = Q3
1 1 - - - - -
1 0 0 0 - - 1 0 0 0 1
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Equivalent Mealy and Moore State

Diagrams
• Moore machine Mealy machine
outputs associated with
– outputs associated with state
transitions
Reset N’ D’ + Reset Reset/0 (N’ D’ + Reset)/0
0¢
N’ D’ 0¢ N’ D’/0
[0]
N N/0
D 5¢ D/0
N’ D’ 5¢ N’ D’/0
[0]
N N/0
10¢
D N’ D’ D/1 10¢ N’ D’/0
[0]
N+D N+D/1
15¢
Reset’ 15¢ Reset’/1
[1]
Nurul Hazlina 51
Example: Traffic Light Controller

• A busy highway is intersected by a little used farmroad
• Detectors C sense the presence of cars waiting on the farmroad
– with no car on farmroad, light remain green in highway direction
– if vehicle on farmroad, highway lights go from Green to Yellow to Red,
allowing the farmroad lights to become green
– these stay green only as long as a farmroad car is detected but never
longer than a set interval
– when these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green
– even if farmroad vehicles are waiting, highway gets at least a set
interval as green
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• Assume you have an interval timer that generates:
– a short time pulse (TS) and
– a long time pulse (TL),
– in response to a set (ST) signal.
– TS is to be used for timing yellow lights and TL for green lights
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(cont’)
• Highway/farm road intersection
farm road
car sensors
highway
Nurul Hazlina 54

(cont’)
• Tabulation of Inputs and Outputs
inputs description outputs description
reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights
C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights
TS short time interval expired ST start timing a short or long interval
TL long time interval expired
• Tabulation of unique states – some light configurations imply

others
state description
S0 highway green (farm road red)
S1 highway yellow (farm road red)
S2 farm road green (highway red)
S3 farm road yellow (highway red)
Nurul Hazlina 55

(cont’)
• State Diagram
(TL•C)' Reset
S0
TL•C / ST TS / ST
S0: HG
S1: HY TS' S1 S3 TS'
S2: FG
S3: FY TS / ST TL+C' / ST
S2
(TL+C')'
Nurul Hazlina 56

(cont’)
• Generate state table with symbolic states
output encoding – similar problem
• Consider state assignments to state assignment
(Green = 00, Yellow = 01, Red = 10)
Inputs Present State Next State Outputs

C TL TS ST H F
0 – – HG HG 0 Green Red
– 0 – HG HG 0 Green Red
1 1 – HG HY 1 Green Red
– – 0 HY HY 0 Yellow Red
– – 1 HY FG 1 Yellow Red
1 0 – FG FG 0 Red Green
0 – – FG FY 1 Red Green
– 1 – FG FY 1 Red Green
– – 0 FY FY 0 Red Yellow
– – 1 FY HG 1 Red Yellow
SA1: HG = 00 HY = 01 FG = 11 FY = 10
SA2: HG = 00 HY = 10 FG = 01 FY = 11
SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot)
Nurul Hazlina 57
Logic for Different State

Assignments
• SA1
NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0
NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0
ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0

H1 = PS1 H0 = PS1'•PS0
F1 = PS1' F0 = PS1•PS0'
• SA2
NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0
NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0
ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1

H1 = PS0 H0 = PS1•PS0'
F1 = PS0' F0 = PS1•PS0
• SA3
NS3 = C'•PS2 + TL•PS2 + TS'•PS3 NS2 = TS•PS1 + C•TL'•PS2
NS1 = C•TL•PS0 + TS'•PS1 NS0 = C'•PS0 + TL'•PS0 + TS•PS3
ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3

H1 = PS3 + PS2 H0 = PS1
F1 = PS1 + PS0 F0 = PS3
Nurul Hazlina 58
Vending Machine Example

(PLD mapping)
D0 = reset'(Q0'N + Q0N' + Q1N + Q1D)
D1 = reset'(Q1 + D + Q0N) CLK
OPEN = Q1Q0
Q0
DQ
Seq
N
Q1
DQ
Seq
D
Open
DQ
Com
Reset
Nurul Hazlina 59
Vending Machine (cont’d)

• OPEN = Q1Q0 creates a combinational delay after Q1 and Q0
change
• This can be corrected by retiming, i.e., move flip-flops and logic
through each other to improve delay
• OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
• Implementation now looks like a synchronous Mealy machine
– Common for programmable devices to have FF at end of logic
Nurul Hazlina 60
Vending Machine (Retimed PLD

Mapping)
OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
CLK
Q0
DQ
Seq
N
Q1
DQ
Seq
D
OPEN Open
DQ
Seq
Reset
Nurul Hazlina 61
STATE MINIMIZATION
Nurul Hazlina 62
Finite State Machine Optimization

• Should look over this one
• Make sure you know the motivation for this
– State Minimization
• Try to merge state with same behavior so total # of states are less
– State Encoding
• Less combinational logic involved in implementing if correct state
encoding is chosen.
• Less Flip flops used if a more dense encoding is used.
– # of flip flop could range from log2(n) to n
• Make sure you know the algorithm for both
Nurul Hazlina 63
Finite State Machine Optimization

• State Minimization
– Fewer states require fewer state bits
– Fewer bits require fewer logic equations
• Encodings: State, Inputs, Outputs
– State encoding with fewer bits has fewer equations to implement
• However, each may be more complex
– State encoding with more bits (e.g., one-hot) has simpler equations
• Complexity directly related to complexity of state diagram
– Input/output encoding may or may not be under designer control
Nurul Hazlina 64
Algorithmic Approach to State

Minimization
• Goal – identify and combine states that have equivalent behavior
• Equivalent States:
– Same output
– For all input combinations, states transition to same or equivalent
states
• Algorithm Sketch
– 1. Place all states in one set
– 2. Initially partition set based on output behavior
– 3. Successively partition resulting subsets based on next state
transitions
– 4. Repeat (3) until no further partitioning is required
• states left in the same set are equivalent
– Polynomial time procedure
Nurul Hazlina 65
State Minimization
2 Methods:
1. Row Matching
2. Implication Chart
NurulHazlina/BEE2243/FSM
Nurul Hazlina 66
Implication Chart Method

• Sequence detector for 010 or 110
Input Next State Output

Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
S0
0/0 1/0
S1 S2
0/0 1/0 0/0 1/0
S3 S4 S5 S6
1/0 1/0 1/0 1/0
0/0 0/1 0/0 0/1
Nurul Hazlina 67
S0
S1
S2
S3
S4
S5
S6
S0 S1 S2 S3 S4 S5 S6
Figure 1 : Chart with entry of every pairs of states
Nurul Hazlina 68
S0
S1
S2
S3
S4
S5
S6
S0 S1 S2 S3 S4 S5 S6
Nurul Hazlina 69

IMPLIED
S0 STATE
PAIRS
S1 S1-S3
S2-S4
S1-S5 S3-S5
S2-S6 S4-S6
S2
S1-S0 S3-S0 S5-S0
S3 S2-S0 S4-S0 S6-S0
S4
X X X X
S5
S1-S0
S2-S0
S3-S0
S4-S0
S5-S0
S6-S0
S0-S0
S0-S0 X
S6
X X X X S0-S0
S0-S0
X
S0 S1 S2 S3 S4 S5 S6
S0, S1, S2, S3, S5sameNurulHazlina/BEE2243/FSM
output (group1)
S4, S6  same output (group2) any combination across g1 and g2 indicate by X
Nurul Hazlina 70
Implied State Pairs

G1
S0 G2
S1
S4
S2
S6
S3
S5
S0, S1, S2, S3, S5same output (group1)

S4, S6  same output (group2) any combination across g1 and g2 indicate by X
Nurul Hazlina 71
Implied State Pairs

Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
Nurul Hazlina 72
Rechecked Implied State Pairs

S0
S1 X
X S3-S5
S2 S4-S6
S3 X X X
S4 X X X X
S5
X X X S0-S0
S0-S0
X
S6 X X X X S0-S0
S0-S0
X
S0 S1 S2 S3 S4 S5 S6
IF square Si and Sj contains the ISP Sm-Sn and square Sm,Sn contains an X, then
Mark
Nurul Si,Sj with an X as well.
Hazlina 73

Reset S0 S1' S1' 0 0

0+1 S1' S3' S4' 0 0
X0 S3' S0 S0 0 0
X1 S4' S0 S0 1 0
Simplified Table
S0
X/0
S1’
0/0 1/0
S3’ S4’
X/0 0/1 1/0
Nurul Hazlina 74
Another Example
0
A B
0 1
[0] [0]
0
1 1
C
G 0 [0]
[0] 1
0 0
0
1 D
F [1]
E
[0] [0] 1
1
Nurul Hazlina 75
Continue
Present Next state output
state 0 1
Divide into 2 groups;
A B C 0
A,B,C,E,F,G and D based on
Output value
B A C 0
C D C 0
D D E 1
E A F 0
F B G 0
G A E 0
Nurul Hazlina 76
State Minimization Example

• Sequence Detector for 010 or 110

Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
S0
0/0 1/0
S1 S2
0/0 1/0 0/0 1/0
S3 S4 S5 S6
1/0 1/0 1/0 1/0
0/0 0/1 0/0 0/1
Nurul Hazlina 77
Method of Successive Partitions

Row Matching
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
( S0 S1 S2 S3 S4 S5 S6 )
S1 is equivalent to S2
( S0 S1 S2 S3 S5 ) ( S4 S6 )
S3 is equivalent to S5
( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) S4 is equivalent to S6
( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )
Nurul Hazlina 78
Minimized FSM
• State minimized sequence detector for 010 or 110
Reset S0 S1' S1' 0 0

0+1 S1' S3' S4' 0 0
X0 S3' S0 S0 0 0
X1 S4' S0 S0 1 0
S0
X/0
S1’
0/0 1/0
S3’ S4’
X/0 0/1 1/0
Nurul Hazlina 79
Implication Chart
Nurul Hazlina 80
More Complex State Minimization

• Multiple input example
inputs here
00 10
S0 00 S1
[1] [0]
01 present next state output
10 11 state 00 01 10 11
11
00 01 S0 S0 S1 S2 S3 1
00 01 S1 S0 S3 S1 S4 0
S2 S3 S2 S1 S3 S2 S4 1
[1] 01 [0] S3 S1 S0 S4 S5 0
10
10 11 11 S4 S0 S1 S2 S5 1
01
S5 S1 S4 S0 S5 0
10 10
00 S4 11 S5 00
[1] [0]
symbolic state
01 transition table
11
Nurul Hazlina 81
Minimized FSM
• Implication Chart Method
– Cross out incompatible states based on outputs
– Then cross out more cells if indexed chart entries are already crossed
out
S1 present next state output

state 00 01 10 11
S0-S1
S0' S0' S1 S2 S3' 1
S1 S0' S3' S1 S3' 0
S2 S1-S3
S2-S2 S2 S1 S3' S2 S0' 1
S3-S4 S3' S1 S0' S0' S3' 0
S0-S1
S3 S3-S0
S1-S4
S4-S5 minimized state table
S0-S0 S1-S0 (S0==S4) (S3==S5)
S4 S1-S1 S3-S1
S2-S2 S2-S2
S3-S5 S4-S5
S0-S1 S1-S1
S5 S3-S4 S0-S4
S1-S0 S4-S0
S4-S5 S5-S5
S0 S1 S2 S3 S4
Nurul Hazlina 82
Minimizing Incompletely Specified

FSMs
• Equivalence of states is transitive when machine is fully specified
• But its not transitive when don't cares are present
e.g., state output
S0 –0 S1 is compatible with both S0 and S2
S1 1– but S0 and S2 are incompatible
S2 –1
• No polynomial time algorithm exists for determining best grouping

of states into equivalent sets that will yield the smallest number of
final states
Nurul Hazlina 83
Minimizing States May Not Yield

Best Circuit
• Example: edge detector - outputs 1 when last two input changes
from 0 to 1
X Q1 Q0 Q1+ Q0+
X’ 0 0 0 0 0
0 0 1 0 0
00 X’
0 1 1 0 0
[0]
1 0 0 0 1
01 1 0 1 1 1
X’ X [1] 1 1 1 1 1
– 1 0 0 0
11 X
[0]
Q1+ = X (Q1 xor Q0)
X
Q0+ = X Q1’ Q0’
Nurul Hazlina 84
Another Implementation of Edge

Detector
• "Ad hoc" solution - not minimal but cheap and fast
X’
00
X’ [0] X
X
10 01
[0] [1]
X’
X’ 11 X
[0]
Nurul Hazlina 85
Sequential Logic Implementation

Summary
– Abstraction of sequential elements
– Finite state machines and their state diagrams
– Inputs/outputs
– Mealy, Moore, and synchronous Mealy machines
• Finite state machine design procedure
– Deriving state diagram
– Deriving state transition table
– Determining next state and output functions
– Implementing combinational logic
• Implementation of sequential logic
– State minimization
– State assignment
– Support in programmable logic devices
Nurul Hazlina 86
Finite State Machine Concept

FSMs are the decision making logic of digital designs
Partitioning designs into datapath and control elements
When inputs are sampled and outputs asserted
Basic Design Approach: 4-step Design Process
Implementation Examples and Case Studies
Finite-string pattern recognizer – mini project a
Traffic light controller – mini project b
Door combination lock – mini project c
SEQUENTIAL LOGIC EXAMPLES
Nurul Hazlina 87
General FSM Design Procedure

1. Determine inputs and outputs
2. Determine possible states of machine
– State minimization
3. Encode states and outputs into a binary code
– State assignment or state encoding
– Output encoding
– Possibly input encoding (if under our control)
4. Realize logic to implement functions for states and outputs
– Combinational logic implementation and optimization
– Choices in steps 2 and 3 have large effect on resulting logic
Nurul Hazlina 88
Finite String Pattern Recognizer

(Step 1)
• Finite String Pattern Recognizer MINI PROJECT 3a
– One input (X) and one output (Z)
– Output is asserted whenever the input sequence …010… has been
observed, as long as the sequence 100 has never been seen
• Step 1: Understanding the Problem Statement

– Sample input/output behavior:
X: 0 0 1 0 1 0 1 0 0 1 0 …
Z: 0 0 0 1 0 1 0 1 0 0 0 …
X: 1 1 0 1 1 0 1 0 0 1 0 …
Z: 0 0 0 0 0 0 0 1 0 0 0 …
Nurul Hazlina 89

(Step 2)
• Step 2: Draw State Diagram
– For the strings that must be recognized, i.e., 010 and 100
– Moore implementation
reset S0
[0]
0 1
S1 S4
[0] [0]
1 0
S2 S5
[0] [0]
0 0
S3 S6 0 or 1
[1] [0]
Nurul Hazlina 90

(Step 2, cont’d)
• Exit conditions from state S3: have recognized …010
– If next input is 0 then have …0100 = ...100 (state S6)
– If next input is 1 then have …0101 = …01 (state S2)
reset S0
[0]
Exit conditions from S1: 0 1
recognizes strings of form …0 0 S1 S4 1
[0] ...0 ...1 [0]
(no 1 seen);
loop back to S1 if input is 0 1 0
S2 S5
Exit conditions from S4: ...01 [0] [0]
recognizes strings of form …1 0 1 0
(no 0 seen);
loop back to S4 if input is 1 S3 S6 0 or 1
...010 [1] ...100 [0]
Nurul Hazlina 91

(Step 2, cont’d)
• S2 and S5 still have incomplete transitions
– S2 = …01; If next input is 1,
then string could be prefix of (01)1(00)
S4 handles just this case
– S5 = …10; If next input is 1, reset S0
then string could be prefix of (10)1(0) [0]
S2 handles just this case 0 1
0 S1 S4 1
• Reuse states as much as possible [0] ...0 ...1 [0]
– Look for same meaning 1 0
1
– State minimization leads to
S2 1 S5
smaller number of bits to
...01 [0] [0]...10
represent states
0 1 0
• Once all states have complete
set of transitions we have S3 S6 0 or 1
...010 [1] ...100 [0]
final state diagram
Nurul Hazlina 92

• Review of Process
– Understanding problem
• Write down sample inputs and outputs to understand specification
– Derive a state diagram
• Write down sequences of states and transitions for sequences to be
recognized
– Minimize number of states
• Add missing transitions; reuse states as much as possible
– State assignment or encoding
• Encode states with unique patterns
– Simulate realization
• Verify I/O behavior of your state diagram to ensure it matches
specification
Nurul Hazlina 93
Traffic Light Controller as Two

Communicating FSMs MINI PROJECT 3b
• Without Separate Timer
– S0 would require 7 states TS'
– S1 would require 3 states S1 S1a

– S2 would require 7 states TS/ST
S1b
– S3 would require 3 states
– S1 and S3 have simple transformation S1c
–/ST
– S0 and S2 would require many more arcs
• C could change in any of seven states
• By Factoring Out Timer
traffic light
– Greatly reduce number of states controller
• 4 instead of 20
ST
– Counter only requires seven or eight states TS TL
• 12 total instead of 20 timer
Nurul Hazlina 94
Communicating Finite State

Machines
• One machine's output is another machine's input
X
CLK
FSM 1 FSM 2
Y FSM1 A A B
Y==0 X==0 FSM2 C D D

Y==0 X==0
A C Y
[1] [0]
Y==1 X==1
B D machines advance in lock step

[0] [1] initial inputs/outputs: X = 0, Y = 0
X==0
X==1
Nurul Hazlina 95
Datapath and Control

• Digital hardware systems = data-path + control
– Datapath: registers, counters, combinational functional units (e.g.,
ALU), communication (e.g., busses)
– Control: FSM generating sequences of control signals that instructs
datapath what to do next
"puppeteer who pulls the strings"

control
status control
info and state signal
inputs outputs
data-path
"puppet"
Nurul Hazlina 96
Digital Combinational Lock

MINI PROJECT 3c
• Door Combination Lock:
– Punch in 3 values in sequence and the door opens; if there is an error
the lock must be reset; once the door opens the lock must be reset
– Inputs: sequence of input values, reset

– Outputs: door open/close
– Memory: must remember combination or always have it available
– Open questions: how do you set the internal combination?

• Stored in registers (how loaded?)
• Hardwired via switches set by user
Nurul Hazlina 97
Determining Details of the

Specification
• How many bits per input value?
• How many values in sequence?
• How do we know a new input value is entered?
• What are the states and state transitions of the system?
new value reset
clock
open/closed
Nurul Hazlina 98
Digital Combination Lock State

Diagram
• States: 5 states
– Represent point in execution of machine
– Each state has outputs
• Transitions: 6 from state to state, 5 self transitions, 1 global
– Changes of state occur when clock says its ok
– Based on value of inputs
• Inputs: reset, new, results of comparisons ERR
• Output: open/closed closed
C1!=value
C2!=value C3!=value
& new
& new & new
S1 S2 S3 OPEN
reset closed closed closed open
C1==value C2==value C3==value
& new & new & new
not new not new not new

Nurul Hazlina 99
Datapath and Control Structure

• Datapath
– Storage registers for combination values
– Multiplexer
– Comparator
• Control
– Finite-state machine controller
– Control for data-path (which value to compare)
C1 C2 C3 new reset
4 4 4 mux
multiplexer
control
4 controller
value comparator
clock
4 equal
Nurul Hazlina open/closed 100

State Table for Combination Lock

• Finite-State Machine
– Refine state diagram to take internal structure into account
– State table ready for encoding
next
reset new equal state state mux open/closed
1 – – – S1 C1 closed
0 0 – S1 S1 C1 closed
0 1 0 S1 ERR – closed
0 1 1 S1 S2 C2 closed
...
0 1 1 S3 OPEN – open
...
Nurul Hazlina 101

Encodings for Combination Lock

• Encode state table
– State can be: S1, S2, S3, OPEN, or ERR
• Needs at least 3 bits to encode: 000, 001, 010, 011, 100
• And as many as 5: 00001, 00010, 00100, 01000, 10000
• Choose 4 bits: 0001, 0010, 0100, 1000, 0000
– Output mux can be: C1, C2, or C3 new reset
• Needs 2 to 3 bits to encode mux
control
• Choose 3 bits: 001, 010, 100 controller
clock
– Output open/closed can be: open or closed equal
• Needs 1 or 2 bits to encode
open/closed
• Choose 1 bit: 1, 0
next
reset new equal state state mux open/closed
1 – – – 0001 001 0
0 0 – 0001 0001 001 0 mux is identical to last 3 bits of state
0 1 0 0001 0000 – 0 open/closed is identical to first bit of state
0 1 1 0001 0010 010 0 therefore, we do not even need to implement
... FFs to hold state, just use outputs
0 1 1 0100 1000 – 1
Nurul...Hazlina 102
Datapath Implementation for

Combination Lock
• Multiplexer
– Easy to implement as combinational logic when few inputs
– Logic can easily get too big for most PLDs
value C1i C2i C3i
mux
control
C1 C2 C3
4 4 4 mux
control
multiplexer
4
value comparator
4 equal
equal
Nurul Hazlina 103
Datapath Implementation (cont’d)

• Tri-State Logic
– Utilize a third output state: “no connection” or “float”
– Connect outputs together as long as only one is “enabled”
– Open-collector gates can value C1i C2i C3i
only output 0, not 1
mux
• Can be used to implement control
logical AND with only wires
+ oc
C1 C2 C3
4 4 4 mux
control tri-state driver
multiplexer
4 (can disconnect
equal from output)
value comparator
4 equal open-collector connection
(zero whenever one connection is zero,
one otherwise – wired AND)
Nurul Hazlina 104
Digital Combination Lock (New

Datapath)
• Decrease number of inputs
• Remove 3 code digits as inputs
– Use code registers
– Make them loadable from value
– Need 3 load signal inputs (net gain in input (4*3)–3=9)
• Could be done with 2 signals and decoder
(ld1, ld2, ld3, load none) ld1 ld2 ld3
C1 C2 C3
4 4 4 mux
multiplexer
control
4
value comparator
4 equal
CS 150 - Fall 2000 - Introduction - 105
Nurul Hazlina 105
Section Summary
• FSM Design
– Understanding the problem
– Generating state diagram
– Implementation using synthesis tools
– Iteration on design/specification to improve qualities of mapping
– Communicating state machines
• Four case studies
– Understand I/O behavior
– Draw diagrams
– Enumerate states for the "goal"
– Expand with error conditions
– Reuse states whenever possible
Nurul Hazlina 106

FSM AND HDL
Nurul Hazlina 107

Hardware Description Languages

and Sequential Logic
• Flip-flops
– representation of clocks - timing of state changes
– asynchronous vs. synchronous
• FSMs
– structural view (FFs separate from combinational logic)
– behavioral view (synthesis of sequencers – not in this course)
• Data-paths = data computation (e.g., ALUs, comparators) +
registers
– use of arithmetic/logical operators
– control of storage elements
Nurul Hazlina 108

Example: reduce-1-string-by-1
• Remove one 1 from every string of 1s on the input
Moore Mealy
zero
[0] 0/0
zero
1 0 [0]
0 one1 0/0 1/0
[0]
one1
0 1 [0]
1 1/1
two1s
[1]
Nurul Hazlina 109

Verilog FSM - Reduce 1s example

• Moore machine state assignment
(easy to change,
module reduce (clk, reset, in, out); if in one place)
input clk, reset, in;
output out;
parameter zero = 2’b00;

parameter one1 = 2’b01;
parameter two1s = 2’b10; zero
[0]
reg out;
reg [2:1] state; // state variables 1 0
reg [2:1] next_state;
0 one1
always @(posedge clk) [0]
if (reset) state = zero;
else state = next_state; 0 1
1
two1s
[1]
Nurul Hazlina 110

Moore Verilog FSM (cont’d)

always @(in or state)
crucial to include
case (state) all signals that are
zero:
// last input was a zero
input to state determination
begin
if (in) next_state = one1;
else next_state = zero;
end
one1: note that output
// we've seen one 1 depends only on state
begin
if (in) next_state = two1s;
else next_state = zero;
end
two1s: always @(state)
// we've seen at least 2 ones case (state)
begin zero: out = 0;
if (in) next_state = two1s; one1: out = 0;
else next_state = zero; two1s: out = 1;
end endcase
endcase
endmodule
Nurul Hazlina 111

Mealy Verilog FSM

module reduce (clk, reset, in, out);
output out;
reg out;
reg state; // state variables
reg next_state;
always @(posedge clk)

else state = next_state;
0/0
always @(in or state) zero
case (state) [0]
zero: // last input was a zero
begin 0/0 1/0
out = 0;
if (in) next_state = one; one1
else next_state = zero; [0]
end 1/1
one: // we've seen one 1
if (in) begin
next_state = one; out = 1;
end else begin
next_state = zero; out = 0;
end
endcase
endmodule
Nurul Hazlina 112

Synchronous Mealy Machine

module reduce (clk, reset, in, out);
output out;
reg out;
reg state; // state variables
always @(posedge clk)

else
case (state)
zero: // last input was a zero
begin
out = 0;
if (in) state = one;
else state = zero;
end
one: // we've seen one 1
if (in) begin
state = one; out = 1;
end else begin
state = zero; out = 0;
end
endcase
endmodule
Nurul Hazlina 113

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Electronic System Design Finite State Machine

Finite State Machine

1. Review on counter design

Sequential Logic Implementation

2 – STATE DIAGRAM FOR FSM

Finite State Machines

Abstraction of state elements

State Inputs State Outputs

Forms of sequential logic

2. Synchronous sequential logic

Can any sequential system be

0 000 1 010 101 0 111 1

Counters are simple finite state

001 010 011

000 3-bit up-counter 100

111 110 101

How do we turn a state diagram

FSM design procedure

FSM design procedure: state

Back to the shift register -

More complex counter example -

More complex counter example

Self-starting counters (cont’d) –

Present State Next State 111 001

000 110 000 110

010 101 010 101

General state machine model

State machine model (cont’d)

3 - MOORE & MEALY MACHINES

Mealy vs Moore Machines

Comparison of Mealy and Moore

Outputs for a Moore machine

Outputs for a Mealy machine

0/0 current next

Registered Mealy machine (really

Example: Ant Brain (Ward, MIT)

D: Hit wall again

E: Wall in front F: ...we are here, same as

G: Turn left until...

Designing an Ant Brain

LOST L+R E/G L A

Synthesizing the Ant Brain Circuit

Transition Truth Table

Synthesis of Next State and Output

Don’t Cares in FSM Synthesis

• Two conditions for two states to be equivalent:

Ant Brain Revisited

LOST L+R E/G L A

New Improved Brain

LOST L+R E/G L A

New Brain Implementation

state inputs next state outputs

Example: Vending Machine

Example: Vending Machine (cont’d)

• Assume N and D asserted N

Example: Vending Machine (cont’d)

Reset present inputs next output

15¢ symbolic state table

Example: Vending Machine (cont’d)

present state inputs next state output

Example: Vending Machine (cont’d)

Example: Vending Machine (cont’d)

present state inputs next state output