Digital Logic Microprocessor Design With Interfacing 2Nd Edition Enoch O Hwang Full Chapter

Digital Logic & Microprocessor Design
With Interfacing, 2nd Edition Enoch O.

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Digital Logic and
Microprocessor Design
with Interfacing
Digital Logic and
with Interfacing
2nd Edition
Enoch O. Hwang
La Sierra University
Riverside, California, USA
Digital Logic and Microprocessor Design with © 2018, 2006 Cengage Learning®
Interfacing, Second Edition
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To my wife Windy,
the love of my life,
for her endless love and support.
CONTENTS
Preface................................................................................................................................... xv
About the Author................................................................................................................... xxi
CHAPTER 1
Introduction to Microprocessor Design 1
1.1 Overview of Microprocessor Design ................................................................................ 3
1.2 Design Abstraction Levels............................................................................................... 6
1.3 Examples of a 2-to-1 Multiplexer.................................................................................... 7
1.3.1 Behavioral Level ................................................................................................. 7
1.3.2 Gate Level........................................................................................................... 9
1.3.3 Transistor Level ................................................................................................ 11
1.4 Introduction to Hardware Description Language ........................................................... 11
1.5 Synthesis ...................................................................................................................... 15
1.6 Going Forward.............................................................................................................. 16
1.7 Problems ...................................................................................................................... 17
CHAPTER 2
Fundamentals of Digital Circuits 18
2.1 Binary Numbers............................................................................................................ 19
2.1.1 Counting in Binary ........................................................................................... 20
2.1.2 Converting between Binary and Decimal .......................................................... 20
2.1.3 Octal and Hexadecimal Notations .................................................................... 23
2.1.4 Binary Number Arithmetic ............................................................................... 25
2.2 Negative Numbers ........................................................................................................ 27
2.2.1 Two’s Complement Representation ................................................................... 27
2.2.2 Sign Extension .................................................................................................. 29
2.2.3 Signed Number Arithmetic ............................................................................... 30
2.3 Binary Switch ............................................................................................................... 32
2.4 Basic Logic Operators and Logic Expressions............................................................... 33
2.5 Logic Gates .................................................................................................................. 35
2.6 Truth Tables ................................................................................................................. 36
2.7 Boolean Algebra and Boolean Equations ....................................................................... 38
2.7.1 Boolean Algebra ............................................................................................... 38
2.7.2 Duality Principle............................................................................................... 41
2.7.3 Boolean Functions and Their Inverses .............................................................. 41
vii
viii Contents
2.8 Minterms and Maxterms .............................................................................................. 46

2.8.1 Minterms .......................................................................................................... 46
2.8.2 Maxterms ......................................................................................................... 49
2.9 Canonical, Standard, and Non-Standard Forms ............................................................ 52
2.10 Digital Circuits............................................................................................................. 53
2.11 Designing a Car Security System .................................................................................. 54
2.12 Verilog and VHDL Code for Digital Circuits ................................................................ 57
2.12.1 Verilog Code for a Boolean Function................................................................ 57
2.12.2 VHDL Code for a Boolean Function................................................................ 58
2.13 Problems ...................................................................................................................... 59
CHAPTER 3
Combinational Circuits 65
3.1 Analysis of Combinational Circuits............................................................................... 66
3.1.1 Using a Truth Table .......................................................................................... 67
3.1.2 Using a Boolean Function ................................................................................ 70
3.2 Synthesis of Combinational Circuits ............................................................................. 72
3.2.1 Using Only NAND Gates ................................................................................. 75
3.3 Minimization of Combinational Circuits ....................................................................... 76
3.3.1 Boolean Algebra ............................................................................................... 77
3.3.2 Karnaugh Maps................................................................................................ 78
3.3.3 Don’t-Cares ...................................................................................................... 85
3.3.4 Tabulation Method ........................................................................................... 86
3.4 Timing Hazards and Glitches........................................................................................ 89
3.4.1 Using Glitches .................................................................................................. 91
3.5 BCD to 7-Segment Decoder.......................................................................................... 92
3.6 Verilog and VHDL Code for Combinational Circuits .................................................... 95
3.6.1 Structural Verilog Code .................................................................................... 95
3.6.2 Structural VHDL Code .................................................................................... 97
3.6.3 Dataflow Verilog Code.....................................................................................101
3.6.4 Dataflow VHDL Code.....................................................................................102
3.6.5 Behavioral Verilog Code ..................................................................................103
3.6.6 Behavioral VHDL Code ..................................................................................104
3.7 Problems .....................................................................................................................106
CHAPTER 4
Standard Combinational Components 112
4.1 Signal Naming Conventions .........................................................................................113
4.2 Multiplexer..................................................................................................................114
4.3 Adder ..........................................................................................................................117
4.3.1 Full Adder .......................................................................................................117
4.3.2 Ripple-Carry Adder.........................................................................................118
4.3.3 Carry-Lookahead Adder .................................................................................120
Contents ix
4.4 Subtractor ...................................................................................................................123

4.5 Adder-Subtractor Combination ....................................................................................125
4.6 Arithmetic Logic Unit..................................................................................................129
4.7 Decoder.......................................................................................................................137
4.8 Tri-State Buffer...........................................................................................................140
4.9 Comparator .................................................................................................................142
4.10 Shifter .........................................................................................................................146
4.11 Multiplier ....................................................................................................................149
4.12 Problems .....................................................................................................................151
CHAPTER 5
Sequential Circuits 157
5.1 Bistable Element..........................................................................................................159
5.2 SR Latch.....................................................................................................................160
5.3 Car Security System—Version 2 ..................................................................................163
5.4 SR Latch with Enable..................................................................................................164
5.5 D Latch .......................................................................................................................164
5.6 D Latch with Enable ....................................................................................................166
5.7 Verilog and VHDL Code for Memory Elements ...........................................................166
5.7.1 VHDL Code for a D Latch with Enable ..........................................................168
5.7.2 Verilog Code for a D Latch with Enable ..........................................................169
5.8 Clock...........................................................................................................................169
5.9 D Flip-Flop..................................................................................................................171
5.9.1 Alternative Smaller Circuit ..............................................................................175
5.10 D Flip-Flop with Enable...............................................................................................176
5.10.1 Asynchronous Inputs.......................................................................................177
5.11 Description of a Flip-Flop............................................................................................180
5.11.1 Characteristic Table .........................................................................................180
5.11.2 Characteristic Equation ...................................................................................180
5.11.3 State Diagram ..................................................................................................180
5.12 Register .......................................................................................................................181
5.13 Register File ................................................................................................................182
5.14 Memories ....................................................................................................................188
5.14.1 ROM................................................................................................................190
5.14.2 RAM ...............................................................................................................192
5.15 Shift Registers .............................................................................................................197
5.15.1 Serial-to-Parallel Shift Register ........................................................................199
5.15.2 Serial-to-Parallel and Parallel-to-Serial Shift Register......................................200
5.15.3 Linear Feedback Shift Register ........................................................................202
5.16 Counters......................................................................................................................205
5.16.1 Binary Up Counter ..........................................................................................205
5.16.2 Binary Up Counter with Parallel Load ............................................................207
x Contents
5.17 Timing Issues...............................................................................................................210

5.18 Problems .....................................................................................................................211
CHAPTER 6
Finite-State Machines 215
6.1 Finite-State Machine Models.......................................................................................217
6.2 State Diagrams............................................................................................................221
6.3 Analysis of Finite-State Machines ...............................................................................224
6.3.1 Next-State Equations .......................................................................................225
6.3.2 Next-State Table ..............................................................................................226
6.3.3 Output Equations ............................................................................................228
6.3.4 Output Table....................................................................................................228
6.3.5 State Diagram ..................................................................................................229
6.3.6 Example...........................................................................................................230
6.4 Synthesis of Finite-State Machines ..............................................................................234
6.4.1 State Diagram ..................................................................................................235
6.4.2 Next-State Table ..............................................................................................236
6.4.3 Next-State Equations .......................................................................................237
6.4.4 Output Table and Output Equations................................................................237
6.4.5 FSM Circuit.....................................................................................................238
6.5 Optimizations for FSMs ..............................................................................................239
6.5.1 State Reduction................................................................................................239
6.5.2 State Encoding.................................................................................................240
6.5.3 Unused States ..................................................................................................243
6.6 FSM Construction Examples.......................................................................................243
6.6.1 Car Security System—Version 3.......................................................................243
6.6.2 Modulo-6 Up-Counter.....................................................................................245
6.6.3 One-Shot Circuit..............................................................................................249
6.6.4 Simple Microprocessor Control Unit ...............................................................251
6.6.5 Elevator Controller Using a Moore FSM ........................................................254
6.6.6 Elevator Controller Using a Mealy FSM .........................................................258
6.7 Verilog and VHDL Code for FSM Circuits ..................................................................261
6.7.1 Behavioral Verilog Code for a Moore FSM......................................................261
6.7.2 Behavioral Verilog Code for a Mealy FSM ......................................................265
6.7.3 Behavioral VHDL Code for a Moore FSM......................................................266
6.7.4 Behavioral VHDL Code for a Mealy FSM ......................................................269
6.8 Problems .....................................................................................................................270
CHAPTER 7
Dedicated Microprocessors 283
7.1 Need for a Datapath ....................................................................................................286
7.2 Constructing the Datapath...........................................................................................287
7.2.1 Selecting Registers ...........................................................................................293
7.2.2 Selecting Functional Units...............................................................................294
Contents xi
7.2.3 Data Transfer Methods....................................................................................295

7.2.4 Generating Status Signals ................................................................................297
7.3 Constructing the Control Unit......................................................................................302
7.3.1 Deriving the Control Signals............................................................................303
7.3.2 Deriving the State Diagram .............................................................................305
7.3.3 Timing Issues ...................................................................................................312
7.3.4 Deriving the FSM Circuit ................................................................................315
7.4 Constructing the Complete Microprocessor ..................................................................320
7.5 Dedicated Microprocessor Construction Examples.......................................................323
7.5.1 Greatest Common Divisor ...............................................................................323
7.5.2 High-Low Number Guessing Game.................................................................330
7.5.3 Traffic Light Controller....................................................................................337
7.6 Verilog and VHDL Code for Dedicated Microprocessors..............................................341
7.6.1 FSM1D Model ...............................................................................................342
7.6.2 FSMD Model ..................................................................................................351
7.6.3 Algorithmic Model ..........................................................................................354
7.7 Problems .....................................................................................................................356
CHAPTER 8
General-Purpose Microprocessors 363
8.1 Overview of the CPU Design .......................................................................................364
8.2 The EC-1 General-Purpose Microprocessor .................................................................366
8.2.1 Instruction Set .................................................................................................366
8.2.2 Datapath..........................................................................................................367
8.2.3 Control Unit ....................................................................................................369
8.2.4 Complete Circuit..............................................................................................373
8.2.5 Sample Program...............................................................................................373
8.2.6 Simulation........................................................................................................375
8.2.7 Hardware Implementation ...............................................................................375
8.3 The EC-2 General-Purpose Microprocessor .................................................................376
8.3.1 Instruction Set .................................................................................................376
8.3.2 Datapath..........................................................................................................377
8.3.3 Control Unit ....................................................................................................379
8.3.4 Complete Circuit..............................................................................................384
8.3.5 Sample Program...............................................................................................384
8.3.6 Hardware Implementation ...............................................................................387
8.4 Extending the EC-2 Instruction Set..............................................................................388
8.5 Using and Interfacing the EC-2....................................................................................391
8.6 Pipelining ....................................................................................................................395
8.6.1 Basic Pipelined Processor.................................................................................395
8.6.2 Pipeline Hazards ..............................................................................................397
8.7 Verilog and VHDL Code for General-Purpose Microprocessors ...................................399
8.7.1 FSM1D Model ...............................................................................................399
8.7.2 FSMD Model ..................................................................................................405
8.8 Problems .....................................................................................................................411
xii Contents
CHAPTER 9
Interfacing Microprocessors 415
9.1 Multiplexing 7-Segment LED Display .........................................................................416
9.1.1 Theory of Operation........................................................................................416
9.1.2 Controller Design ............................................................................................417
9.2 Issues with Interfacing Switches ...................................................................................420
9.3 3 3 4 Keypad Controller ..............................................................................................427
9.4 PS2 Keyboard and Mouse............................................................................................431
9.4.1 Theory of Operation—PS2 Keyboard .............................................................431
9.4.2 Controller Design—PS2 Keyboard ..................................................................432
9.4.3 Theory of Operation—PS2 Mouse ..................................................................436
9.4.4 Controller Design—PS2 Mouse .......................................................................438
9.5 RS-232 Controller for Bluetooth Communication .........................................................444
9.5.1 Theory of Operation—RS-232 ........................................................................445
9.5.2 Controller Design—RS-232 .............................................................................446
9.5.3 Implementation................................................................................................449
9.6 Liquid-Crystal Display Controller................................................................................450
9.7 VGA Monitor Controller .............................................................................................457
9.7.3 Implementation................................................................................................466
9.8 A/D Controller for Temperature Sensor........................................................................467
9.8.3 Implementation................................................................................................474
9.9 I2C Bus Controller for Real-Time Clock.......................................................................475
9.9.3 Implementation................................................................................................483
9.10 Problems .....................................................................................................................484
APPENDIX A
Xilinx Development Tutorial 486
A.1 Starting ISE ................................................................................................................486
A.1.1 Creating a New Project ....................................................................................486
A.1.2 Specifying the FPGA .......................................................................................489
Contents xiii
A.2 Creating a New Schematic Source File.........................................................................492

A.2.1 Drawing Your Schematic Circuit......................................................................493
A.2.2 Creating and Using a Schematic Symbol..........................................................495
A.2.3 Editing a Schematic Symbol ............................................................................497
A.2.4 Using a Schematic Symbol in Another Project.................................................500
A.3 Creating a New Verilog or VHDL Source File..............................................................500
A.4 Setting the Top-Level Module Design File ....................................................................500
A.5 Mapping the I/O Signals..............................................................................................500
A.5.1 Using PlanAhead for Mapping the Pins...........................................................501
A.5.2 Faster Alternative Method for Mapping the Pins.............................................503
A.6 Synthesis and Implementation......................................................................................503
A.7 Programming the Circuit to the FPGA.........................................................................505
A.8 Problems .....................................................................................................................509
APPENDIX B
Altera Development Tutorial 512
B.1 Starting Quartus .........................................................................................................512
B.1.1 Creating a New Project ....................................................................................512
B.1.2 Specifying the FPGA .......................................................................................514
B.2 Using the Graphic Editor .............................................................................................516
B.2.1 Starting the Graphic Editor .............................................................................516
B.2.2 Drawing Tools..................................................................................................516
B.2.3 Inserting Logic Symbols ..................................................................................517
B.2.4 Selecting, Moving, Copying, and Deleting Logic Symbols...............................518
B.2.5 Making and Naming Connections ...................................................................519
B.2.6 Selecting, Moving, and Deleting Connection Lines..........................................521
B.3 Managing Files in a Project .........................................................................................521
B.3.1 Design Files in a Project...................................................................................522
B.3.2 Creating a New Verilog or VHDL Source File .................................................522
B.3.3 Opening a Design File......................................................................................522
B.3.4 Adding Design Files to a Project......................................................................523
B.3.5 Deleting Design Files from a Project................................................................523
B.3.6 Setting the Top-Level Entity Design File .........................................................523
B.3.7 Saving the Project.............................................................................................523
B.4 Analysis and Synthesis.................................................................................................523
B.5 Creating and Using a Logic Symbol .............................................................................524
B.6 Mapping the I/O Signals..............................................................................................525
B.6.1 Faster Alternative Method for Mapping the Pins.............................................527
B.7 Fitting the Netlist and Pins to the FPGA......................................................................527
B.8 Programming the Circuit to the FPGA.........................................................................528
B.9 Problems .....................................................................................................................529
xiv Contents
APPENDIX C
Verilog Summary 533
C.1 Basic Language Elements ............................................................................................533
C.1.1 Keywords.........................................................................................................533
C.1.2 Comments........................................................................................................534
C.1.3 Identifiers.........................................................................................................534
C.1.4 Signals .............................................................................................................534
C.1.5 Numbers and Strings .......................................................................................534
C.1.6 Constants.........................................................................................................535
C.1.7 Data Types.......................................................................................................536
C.1.8 Data Operators ................................................................................................536
C.1.9 Module ............................................................................................................537
C.1.10 Module Parameter ...........................................................................................539
C.2 Behavioral Model ........................................................................................................540
C.2.1 Assignment ......................................................................................................540
C.2.2 initial................................................................................................................541
C.2.3 always ..............................................................................................................542
C.2.4 Event Control ..................................................................................................542
C.2.5 begin-end .........................................................................................................544
C.2.6 if-then-else .......................................................................................................545
C.2.7 case, casex, casez ..............................................................................................545
C.2.8 for ....................................................................................................................546
C.2.9 while ................................................................................................................547
C.2.10 function..........................................................................................................547
C.2.11 Behavioral Model Example ............................................................................548
C.3 Dataflow Model...........................................................................................................548
C.3.1 Continuous Assignment...................................................................................549
C.3.2 Conditional Assignment ..................................................................................549
C.3.3 Dataflow Model Example................................................................................550
C.4 Structural Model .........................................................................................................550
C.4.1 Built-in Gates...................................................................................................550
C.4.2 User-Defined Module ......................................................................................551
C.4.3 Structural Model Example...............................................................................552
APPENDIX D
VHDL Summary 553
D.1 Basic Language Elements ............................................................................................553
D.1.1 Keywords.........................................................................................................553
D.1.2 Comments........................................................................................................554
D.1.3 Identifiers.........................................................................................................554
D.1.4 Data Objects ....................................................................................................554
D.1.5 Data Types.......................................................................................................554
D.1.6 Data Operators ................................................................................................557
D.1.7 ENTITY ..........................................................................................................558
Contents xv
D.1.8 ARCHITECTURE..........................................................................................559
D.1.9 GENERIC.......................................................................................................560
D.1.10 PACKAGE ....................................................................................................562
D.2 Behavioral Model—Sequential Statements...................................................................564
D.2.1 PROCESS........................................................................................................564
D.2.2 Sequential Signal Assignment ..........................................................................564
D.2.3 Variable Assignment ........................................................................................565
D.2.4 WAIT...............................................................................................................565
D.2.5 IF-THEN-ELSE..............................................................................................565
D.2.6 CASE...............................................................................................................566
D.2.7 NULL..............................................................................................................566
D.2.8 FOR ................................................................................................................567
D.2.9 WHILE............................................................................................................567
D.2.10 LOOP ............................................................................................................567
D.2.11 EXIT .............................................................................................................567
D.2.12 NEXT............................................................................................................567
D.2.13 FUNCTION..................................................................................................568
D.2.14 PROCEDURE ..............................................................................................569
D.2.15 Behavioral Model Example............................................................................570
D.3 Dataflow Model—Concurrent Statements....................................................................570
D.3.1 Concurrent Signal Assignment ........................................................................570
D.3.2 Conditional Signal Assignment........................................................................571
D.3.3 Selected Signal Assignment..............................................................................571
D.3.4 Dataflow Model Example................................................................................572
D.4 Structural Model—Concurrent Statements ..................................................................573
D.4.1 COMPONENT Declaration ............................................................................573
D.4.2 PORT MAP .....................................................................................................574
D.4.3 OPEN ..............................................................................................................574
D.4.4 GENERATE ...................................................................................................575
D.4.5 Structural Model Example...............................................................................575
D.5 Conversion Routines.....................................................................................................576
D.5.1 CONV_INTEGER( )......................................................................................576
D.5.2 CONV_STD_LOGIC_VECTOR( , )...............................................................577
Index .....................................................................................................................................578
P R E FA C E
This book is about the digital logic design of microprocessors, and is intended to
provide both an understanding of the basic principles of digital logic design, and how
these fundamental principles are applied in the building of complex microproces-
sor circuits using current technologies. Although the basic principles of digital logic
design have not changed, the design process and the implementation of the circuits
have. With the advances in fully integrated modern hardware computer-aided design
(CAD) tools for logic synthesis, simulation, and the implementation of digital circuits
in field-programmable gate arrays (FPGAs), it is now possible to design and imple-
ment complex digital circuits very easily and quickly
quickly.
Many excellent books on digital logic design have followed the traditional approach
of introducing the basic principles and theories of digital logic design and the building
of separate standard combinational and sequential components. However, students
are left to wonder about the purpose of these individual components and how they
are used in the building of more complex digital circuits, such as microcontrollers
and microprocessors that are used in controlling real-world electronic devices. The
primary goal of this book is to fill in this gap by going beyond the logic principles and
the building of basic standard components. The book discusses in detail how the basic
components are combined together to form datapaths, how control units are designed,
and how these two main components (datapath and control unit) are connected
together to produce actual dedicated custom microprocessors and general-purpose
microprocessors. The book ends with an entire chapter containing many examples on
how microprocessors are interfaced with real-world devices.
Many texts on digital logic design and implementation techniques mainly focus on
the logic gate level. At this low level, it is difficult to discuss larger and more complex
circuits that are beyond the standard combinational and sequential circuits. However,
with the introduction of the register-transfer technique for designing datapaths and
the concept of a finite-state machine for control units, we can easily design a dedicated
microprocessor for any arbitrary algorithm and then implement it on a FPGA chip
to execute that algorithm. The book uses an easy-to-understand ground-up approach
with complete circuit diagrams, and both Verilog and VHDL codes, starting with the
building of basic digital components. These components are then used in the build-
ing of more complex components, and finally the building of the complete dedicated
microprocessor circuit. The construction of a general-purpose microprocessor then
comes naturally as a generalization of a dedicated microprocessor. At the end, stu-
dents will have a complete understanding of how to design, construct, and implement
fully working custom microprocessors.
xvii
xviii PReFACe
Design of Circuits using Verilog and VHDL

Although this book provides coverage on both Verilog and VHDL for all of the
circuits, this information can be omitted entirely while gaining an understanding of
digital circuits and their design. For an introductory course in digital logic design,
learning the basic principles is more important than learning how to use a hardware
description language (HDL). In fact, instructors may find that students can get lost
in learning the principles while trying to learn the language at the same time. With
this in mind, the Verilog and VHDL code in the text is totally independent of the
presentation of each topic and may be skipped without any loss of continuity
continuity.
On the other hand, by studying the HDL codes, the student can not only learn
the use of a hardware description language but also learn how digital circuits can be
designed automatically using a synthesizer. This book provides an introduction to
both Verilog and VHDL and uses the “learn-by-examples” approach. In writing either
Verilog or VHDL code at the dataflow and behavioral levels, the student will see the
power and usefulness of a state-of-the-art hardware CAD synthesis tool.
New to This Edition

In this newly revised second edition, a new chapter on interfacing microprocessors
with external devices has been added. Just knowing how to design and implement a
microprocessor is not sufficient. The main purpose and usage of a microprocessor is
to control external devices. This entire chapter contains many real-world examples on
interfacing microprocessors with external devices. Students can use these examples to
help them in doing their final projects.
Throughout the book, many new examples have been added and old examples
updated. This new edition also covers the usage of both Verilog and VHDL, the two
industry standard hardware description languages for describing digital circuits. All
circuit examples, in addition to having schematic diagrams, also include codes written
in both VHDL and Verilog.
In addition to the Altera FPGA development software, a new section in the
Appendix is added for using the Xilinx FPGA development software. Using either
the Altera or the Xilinx FPGA development software and their respective FPGA
hardware development boards, students can actually implement these microprocessor
circuits and see them execute, both in software simulation and in hardware. The book
contains many interesting examples with complete schematic diagrams and Verilog
and VHDL codes for implementing them in hardware. With the hands-on exercises,
students will learn not only the principles of digital logic design but, also in practice,
how circuits are implemented using current technologies.
To actually see your own microprocessor come to life in real hardware and being
able to control real-world external devices is an exciting experience. Hopefully, this
will help students to not only remember what they have learned but will also get them
interested in the world of microprocessor controllers and digital circuit design.
PReFACe xix
Using This Book

This book can be used in either an introductory or a more advanced course in digital
logic design. For an introductory course with no previous background in digital logic,
Chapters 1 and 2 are intended to provide the fundamental basic concepts in digital
logic design, while Chapters 3 and 4 cover the design of combinational circuits and
standard combinational components. Chapter 5 on the design of sequential circuits
can be introduced and lightly covered.
An advanced digital logic design course will start with sequential circuits in
Chapter 5, and the design of finite-state machines in Chapter 6. Chapters 7 and 8
cover the design of datapaths and control units, and the building of dedicated and
general-purpose microprocessors. Finally, Chapter 9 concludes with the interfacing of
microprocessors with the external world.
It is strongly recommended that a lab component be fully integrated with the lecture.
With an integrated lab, students can have a hands-on learning experience alongside the
theoretical concepts that they have learned in class. In fact, many teachers find that too
often not enough hours are given to the lab. As we probably know, it is often easier to
understand the theory, but to actually implement a circuit and to get it to work requires
much more detail and time. Ready-to-use labs that complement the lecture are available
for download from the teachers’ resource website at https://login.cengage.com.
Chapter 1—Introduction to Microprocessor Design gives an overview of the var-
ious components of a microprocessor circuit and the different abstraction levels in
which digital circuits can be designed.
Chapter 2—Fundamentals of Digital Circuits provides the basic principles and
theories for designing digital logic circuits by introducing binary numbers, the use of
truth tables, Boolean algebra, and how the theories get translated into logic gates and
circuit diagrams. Also a brief introduction to Verilog and VHDL is given.
Chapter 3—Combinational Circuits shows how combinational circuits are ana-
lyzed, synthesized, and optimized.
Chapter 4—Standard Combinational Components discusses the standard combi-
national components that are used as building blocks for larger digital circuits. These
components include the adder, subtractor, arithmetic logic unit, decoder, multiplexer,
tri-state buffer, comparator, shifter, and multiplier. In a hierarchical design, these com-
ponents will be used in the building of the datapath used in the microprocessor.
Chapter 5—Sequential Circuits introduces latches and flip-flops as basic storage
elements and then continues with larger storage components such as registers, register
files, and memories. Special sequential components such as shift registers and counters
are also covered.
Chapter 6—Finite-State Machines shows how finite-state machines are analyzed,
synthesized, and optimized.
Chapter 7—Dedicated Microprocessors first introduces the need for a datapath,
and then explains how a control unit, in the form of a finite-state machine, is used to
xx PReFACe
control the datapath. The chapter expands further showing how dedicated micropro-
cessors are constructed by connecting the datapath and the control unit together as
one coherent circuit.
Chapter 8—General-Purpose Microprocessors continues on from Chapter 7 to
suggest that a general-purpose microprocessor is really a dedicated microprocessor
that is dedicated to only read, decode, and execute instructions. The chapter discusses
the complete design and construction of two simple general-purpose microprocessors
with their own custom instruction set, and how programs written in machine language
are executed on them. The highlight of this chapter and this book is that these two
fully-working general-purpose microprocessors can be implemented in hardware and
have programs executed by them.
Chapter 9—Interfacing Microprocessors provides several complete examples on
how to interface microprocessors with real-world external devices. Examples include
interfacing with a real-time clock IC using the I2C protocol, Bluetooth communication
using RS-232, and drawing graphics on a VGA monitor.
The Appendixes provide tutorials on using both the Altera and Xilinx software
development tools, and summaries on the Verilog and VHDL hardware description
languages.
Supplements
Resources for the book can be found at https://login.cengage.com/. The instructor site
is password protected and requires a verified instructor login to access the site.
Student Resources
● Chapter on Implementation Technologies
● Labs for each chapter
● All of the example codes from the book in VHDL and Verilog
● Altera FPGA development software download
● Xilinx FPGA development software download
Instructor Resources
● Chapter on Implementation Technologies
● Labs for each chapter
● PowerPoint lecture slides
● Solutions to problems at the end of each chapter
● All of the example codes from the book in VHDL and Verilog
● Altera FPGA development software download
● Xilinx FPGA development software download
PReFACe xxi
Acknowledgments
I want to thank Professor Zhiguo Shi, Ph.D., and many of his graduate students from
Zhejiang University, Hangzhou, China, for translating this book into Chinese. In the
process, we have become lasting friends.
I also want to thank the following reviewers for their constructive feedback:
Christopher Doss, North Carolina A&T State University
Eric Durant, Milwaukee School of Engineering
Rajiv JJ. Kapadia, Minnesota State University, Mankato
Emma Regentova, University of Nevada, Las Vegas
Darrin Rothe, Milwaukee School of Engineering
I wish to acknowledge and thank the Global Engineering team at Cengage Learn-
ing for their dedication to this new book:
Timothy Anderson, Product Director; Ashley Kaupert, Associate Media Content
Developer; Kim Kusnerak, Senior Content Project Manager; Kristin Stine, Mar-
keting Manager; Elizabeth Brown, Learning Solutions Specialist; and Alexander
Sham, Product Assistant. They have skillfully guided every aspect of this text’s
development and production to successful completion.
I also want to thank the College of Information Science and Electronic Engineer-
ing at Zhejiang University for inviting me as a visiting professor to teach their Digital
Systems Design course (in English) using the contents of this book. During this time, I
was able to gather many valuable ideas and feedbacks from the bright and enthusiastic
students on how to make the book better. As a result, numerous changes have been
made. This book truly is field-tested.
I also want to thank my school, La Sierra University in sunny California, for giv-
ing me the time off to be at Zhejiang University and to work on this book. It would
have been extremely difficult without this extra time.
Finally, I want to thank my wife, Windy, for her support and giving me the time
to focus and to finish this book.
Enoch O. Hwang, Ph.D.

Riverside, California
ABOUT THE AUTHOR
Enoch Hwang has a Ph.D. in Computer Science from the University

of California, Riverside. He is currently a professor of computer sci-
ence at La Sierra University in Southern California teaching digital
logic and microprocessor design. In 2015, he was invited as a visit-
ing professor to Zhejiang University in Hangzhou, China, where he
taught their Digital Systems Design course. Many new ideas from
that class have been incorporated into this edition of the book.
Even from his childhood days, he has been fascinated with elec-
tronic circuits. In one of his first experiments, he attempted to connect
a microphone to the speaker inside a portable radio through the ear-
phone plug. Instead of hearing sound from the microphone through
the speaker, smoke was seen coming out of the radio. Thus ended that
experiment and his family’s only radio. He now continues his interest
in digital circuits with research in embedded microprocessor systems,
controller automation, power optimization, and robotics.
xxiii
CHAPTER 1
Introduction to
Control Data
Inputs Microprocessor Inputs
'0'
Control Unit 8 Datapath
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Logic Register Signals ff
Register
Status 8
Signals
Control Data
Outputs Outputs
2 CHAPTER 1 IntroductIon to MIcroprocessor desIgn
Electronic devices are an integral part of our lives. Every day and everywhere we
see and use electronic devices, from cellular telephones to electronic billboards, cars,
toys, TVs, elevators, musical greeting cards, personal computers, traffic lights, and
many more. Inside each and every one of them, there is a microprocessor that controls
their operations. Microprocessors are at the heart of all of these “smart” devices.
Their smartness is a direct result of the work of the microprocessor, without which
none of these electronic devices would be able to operate as they do.
There are generally two types of microprocessors: general-purpose microprocessors
and dedicated microprocessors. General-purpose microprocessors, such as the Intel
Core™ i7 CPU shown in Figure 1.1(a) can perform different tasks under the control
of different software programs. General-purpose microprocessors typically are much
more powerful in terms of processing power and speed. However, they usually require
external components for their memory and supporting input/output (I/O) peripherals.
They are used in all personal computers.
Dedicated microprocessors, also known as microcontrollers or application-specific
integrated circuits (ASICs), on the other hand, are designed to perform just one specific
task. For example, inside your cell phone is a dedicated microcontroller that does noth-
ing else but control its entire operation. Microcontrollers therefore are usually not as
powerful (because they do not need to perform so many tasks) as a microprocessor and
are much smaller in size. However, they usually will have the memory and supporting
I/O peripherals included inside the chip, hence the entire system can be on a single chip.
For example, the Atmel ATtiny13A microcontroller shown in Figure 1.1(b) has built-in
flash memory, electrically erasable programmable read-only memory (EEPROM), static
random-access memory (SRAM), general-purpose I/Os, timers, serial interface, and ana-
log-to-digital converters (ADC). Dedicated microcontrollers are used in almost all smart
electronic devices. Although the small dedicated microcontrollers are not as powerful
and are slower in speed as compared to general-purpose microprocessors, they are being
sold much more and are used in a lot more places than general-purpose microprocessors.
© Oleksiy Maksymenko Photography /
Dmitry S. Gordienko /
Alamy Stock Photo
Shutterstock.com
(a) (b)
FIGURE 1.1 Microprocessors: (a) General-purpose Intel Core™ i7 CPU; (b) Dedicated
Atmel ATtiny13A microcontroller.
1.1 overvIew of MIcroprocessor desIgn 3
In this book, I will show you in detail how to design, implement, and interface a
microprocessor. At the end, you will be able to design your own custom microproces-
sor and use it to control your own electronic device. I will use a hands-on approach to
guide you step-by-step through the entire design process with complete circuits that
you actually can implement in hardware. The exciting part is that at the end, you can
actually, very easily and inexpensively, implement your own custom microprocessor in
a real integrated circuit (IC) and see that it really can execute software programs, make
lights flash, or do whatever you have designed it to do.
We will start with the fundamentals of digital logic circuit design in Chapter 2, which
will provide you with a good foundation and basic building blocks for creating larger and
more complex digital circuits. Chapters 3 and 4 will discuss the design of simple digital
circuits and common circuits that are used as building blocks for larger circuits. Chapter
5 talks about the design of memory circuits. Typically, an introduction to digital logic
design course will cover the materials from Chapters 1 to 5 only. Moving on to more
advanced digital logic design, Chapter 6 talks about control unit circuits. Chapter 7 talks
about the datapath and how to connect it with the control unit to produce a dedicated
microcontroller. Chapter 8 extends the dedicated microcontroller from Chapter 7 to
produce a general-purpose microprocessor. Finally, Chapter 9 concludes with examples
of how to interface these microprocessors and microcontrollers in the real world.
1.1 Overview of Microprocessor Design

The microprocessor or microcontroller is an electronic digital logic circuit that is imple-
mented inside an IC chip. Any digital electronic circuit at the lowest physical level
understands only whether there is electricity or no electricity, which is typically rep-
resented by the use of a 1 or a 0. The question is how do we design a microprocessor
so that it can understand the 1s and 0s, and then do something meaningful with that
understanding? To design a microprocessor is to design its logic circuit to do whatever
it is intended to do. To implement the microprocessor is to put the logic circuit of the
microprocessor onto an IC chip.
Previously, making an IC chip with any circuit was a long and expensive pro-
cess. With the advance of large-capacity field-programmable gate array (FPGA) chips,
digital circuits of almost any size can be implemented in a chip easily and quickly.
Moreover, because FPGA chips are erasable, you can use the same FPGA chip over and
over again to implement different circuits. If you put an adder circuit in the FPGA chip,
that chip will be an adder, and if you put a traffic light controller circuit in the FPGA
chip, that chip will be a traffic light controller. So implementing any digital circuit in a
FPGA chip is quite simple. The challenge now is how to design the circuit; how do we
design the adder circuit or the traffic light controller circuit?
A block diagram of a microprocessor circuit is shown in Figure 1.2. As you can
see, it is divided into two main parts: the control unit and the datapath. The datap-
ath is responsible for the execution of all of the microprocessor’s data operations,
such as the addition of two numbers inside the arithmetic logic unit (ALU). The dat-
apath also includes registers for the temporary storage of data and comparators for
testing data values. These and many other functional units are connected together
Control Data
Inputs Inputs
'0'
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Register
Status 8
Signals
Control Data
Outputs Outputs
FIGURE 1.2 Internal parts of a microprocessor.
with multiplexers and data signal lines. The data signal lines are for transferring data
between two functional units. Sometimes, several data signal lines are grouped together
to form a bus. The width of the bus (i.e., the number of data signal lines in the group) is
annotated next to the bus line. In the figure, the bus lines are thicker and are 8-bit wide.
Multiplexers, also known as MUXs, are for selecting data from two or more sources to
go to one destination. In the figure, a 2-to-1 multiplexer is used to select between the
input data and the constant “0” to go to the left operand of the ALU. The output of the
ALU is connected to the input of the register. The output of the register is connected
to three different destinations: (1) the right operand of the ALU; (2) an OR gate used
as a comparator for the test “not equal to 0”; and (3) a tri-state buffer, which is used to
control the output of the data from the register.
Even though the datapath is capable of performing all of the microprocessor’s data
operations, it cannot, however, do it on its own. In order for the datapath to execute the
operations automatically and correctly, a control unit is required. The control unit, also
known as the controller, controls all of the operations of the datapath and therefore,
the operations of the entire microprocessor. The control unit is also called a finite-state
machine (FSM) because it is a machine that executes by going from one state to another,
and there are only a finite number of states for the machine to go to. The control unit is
made up of three parts: (1) the next-state logic; (2) the state memory; and (3) the output
logic. The purpose of the state memory is to remember the current state that the FSM
is in. The next-state logic is the circuit that determines what the machine’s next state
should be. The output logic is the circuit that generates the actual control signals for
controlling the datapath and/or external devices.
Every digital logic circuit, regardless of whether it is part of the control unit or
the datapath, is categorized as either a combinational circuit or a sequential circuit.
1.1 overvIew of MIcroprocessor desIgn 5
A combinational circuit is one where the output of the circuit is dependent only on the
current inputs to the circuit, and therefore has no memory about what has happened
before. For example, an adder is a combinational circuit because it will produce a sum
when given any two input numbers.
A sequential circuit, on the other hand, is dependent not only on the current inputs,
but also on all of the previous inputs. In other words, a sequential circuit has to remem-
ber its past history. For example, a register is a sequential circuit because it can remember
a value indefinitely. Because sequential circuits are dependent on the history, they must
contain memory elements to remember that history. Combinational circuits, on the other
hand, do not need to remember the history, and so they do not have memory elements.
An analogy of the difference between a combinational circuit and a sequential cir-
cuit is the combination lock that we are familiar with. There are actually two different
types of combination locks as shown in Figure 1.3. For the lock in Figure 1.3(a), you
just turn the three number dials in any order you like to the correct number and the lock
will open. For the lock in Figure 1.3(b), you also have three numbers that you need to
turn to, but you need to turn to these three numbers in the correct sequence. If you turn
to these three numbers in the wrong sequence the lock will not open even if you have
the numbers correct. The lock in Figure 1.3(a) is like a combinational circuit where the
order in which the inputs are entered into the circuit does not matter, whereas, a sequen-
tial circuit is like the lock in Figure 1.3(b) where the sequence of the inputs does matter.
Examples of combinational circuits inside the microprocessor include the ALU,
multiplexers, tri-state buffers, and comparators in the datapath, and the next-state logic
and output logic circuits in the control unit. Examples of sequential circuits include
the register for the state memory in the control unit and the registers in the datapath.
Nattawat Kaewjirasit / Shutterstock.com
Cloud7Days / Shutterstock.com
(a) (b)
FIGURE 1.3 Two types of combination locks: (a) the order in which you enter the
numbers does not matter; (b) the order in which you enter the numbers does matter.
All digital logic circuits, whether they are combinational or sequential, are made up of
the three basic logic gates: AND, OR, and NOT gates. From these three basic gates, the most
powerful computer can be made. Furthermore, these basic gates are built using transis-
tors—the fundamental building blocks for all digital logic circuits. Transistors are simply
electronic binary switches that can be turned on and off. The 1s and 0s that we, as com-
puter scientists, often talk about are used to represent the on and off states of a transistor.
To summarize, transistors, as the lowest-level building blocks, are used to build
the basic logic gates. Logic gates are connected together to form either combinational
circuits or sequential circuits. The difference between these two types of circuits is only
in the way the logic gates are connected together. Certain combinational circuits and
sequential circuits are used as standard building blocks for larger circuits and so are
kept in standard libraries. These standard combinational and sequential components
are connected together to form either the datapath or the control unit. Finally, com-
bining the datapath and the control unit together will produce the circuit for either a
dedicated or a general-purpose microprocessor.
1.2 Design Abstraction Levels

Digital circuits can be designed at any one of several abstraction levels. When designing
a circuit at the transistor level, which is the lowest level, you are dealing with discrete
transistors and connecting them together to form the circuit. The next level up in the
abstraction is the gate level. At this level, you are working with logic gates to build the
circuit. In using logic gates, a designer usually creates standard combinational and
sequential components for building larger circuits. In this way, a very large circuit, such
as a microprocessor, can be built in a hierarchical fashion. Design methodologies have
shown that solving a problem hierarchically is always easier than trying to solve the
entire problem as a whole from the ground up. These combinational and sequential
components are used at the register-transfer level to build the datapath and the control
unit in the microprocessor. At the register-transfer level, we are concerned with how the
data is transferred between the various registers and functional units to realize or solve
the problem at hand. Finally, at the highest level, called the behavioral level, we can
describe the behavior or operation of the circuit using a high-level hardware description
language, and we can use a synthesizer, which is equivalent to a compiler, to automati-
cally generate the logic circuit for it. Designing at this level does not require knowledge
of the underlying logic gates and circuits because the synthesizer will automatically
create the logic circuit for you. This is very similar to writing a computer program
using a high-level programming language, and then using the compiler to automatically
translate the program into machine language that the computer can execute.
An important point to realize is that there are many different ways to create
the same functional circuit. Although they are all functionally equivalent, they are
different in other respects, such as the actual circuit (how the transistors or gates
are connected together), size (how big the circuit is or how many transistors or gates
it uses), speed (how long it takes for the output result to be valid), cost (how much
it costs to manufacture), and power usage (how much power it uses). Hence, when
designing a circuit, in addition to being functionally correct, we also should consider
1.3 exaMples of a 2-to-1 MultIplexer 7
the economic versus performance tradeoffs. In this book, we will focus mainly on how
to design a functionally correct circuit with some discussion about how to optimize
the circuit size.
1.3 Examples of a 2-to-1 Multiplexer

As an introduction example, let us look at the design of the 2-to-1 multiplexer from
different abstraction levels. At this point, don’t worry too much if you don’t understand
the details of how all of these circuits are built. This example is intended just to give
you an idea of what the circuit looks like at the different abstraction levels. We will get
to the details in the rest of the book.
The multiplexer is a component that is used a lot in the datapath. An analogy for
the operation of the 2-to-1 multiplexer is similar in principle to a railroad switch in
which two railroad tracks are to be merged onto one track. The switch controls which
one of the two trains on the two separate tracks will move onto the one track. Similarly,
the 2-to-1 multiplexer has two data inputs, d1 and d0, and a select input, s. The select
input determines which data from the two data inputs will pass to the output, y.
Figure 1.4 shows the graphical symbol, also referred to as the logic symbol, for the
2-to-1 multiplexer. From looking at the logic symbol, you can tell how many signal lines
the 2-to-1 multiplexer has, and the name or function designated for each line. For the
2-to-1 multiplexer, there are two data input signals, d1 and d0, a select input signal, s,
and an output signal, y.
d1 d0
1.3.1 Behavioral Level

s 1 0
We can describe the operation of the 2-to-1 multiplexer simply
(using the same names as in the logic symbol) by saying that
y
if s 5 0 then d0 passes to y,
FIGURE 1.4 Logic
otherwise symbol for the
2-to-1 multiplexer.
d1 passes to y
Or more precisely, the value that is at d0 passes to y if s 5 0, and the value that is
at d1 passes to y if s 5 1.
We use a hardware description language (HDL), which is quite similar to many
high-level computer programming languages, to describe the circuit at the behavioral
level. When describing a circuit at this level, you would write basically the same thing
as in the description, except that you have to use the correct syntax required by the
hardware description language. Figure 1.5 shows the description of the 2-to-1 multi-
plexer using the hardware description language called Verilog, and Figure 1.6 shows
the description of the same 2-to-1 multiplexer using another hardware description
language called VHDL, which stands for VHSIC Hardware Description Language
(VHSIC, in turn, stands for Very High Speed Integrated Circuit). Verilog and VHDL
are two standard hardware description languages used for digital logic design.
module multiplexer (
input s,
input d0,
input d1,
output reg y
);
always @ (s or d0 or d1) begin
if (s == 0) begin
y = d0;
end else begin
y = d1;
end
end
endmodule
FIGURE 1.5 Behavioral Verilog code for a 2-to-1 multiplexer.
In the Verilog code shown in Figure 1.5, the declaration of the component begins
with the keyword module followed by the name of the component, which in the exam-
ple, is the user identifier multiplexer. All of the words used in Verilog are case sen-
sitive. The input and output interface signals are listed next using the keywords input
and output. For ease of reference, the user-defined names used for these signals match
those shown earlier in the logic symbol. The always block is followed by its sensitivity
list of signals inside the parentheses. The always block is executed each and every time
when any one of the signals in the sensitivity list changes value. The statements inside
the always block (bracketed by the begin and end keywords) are executed sequen-
tially. In the example, there is only one if-then-else statement inside the block.
Like any if statement in other programming languages, the assignment statement y
= d0 is executed when the condition “s equals to 0” is true, otherwise the assignment
statement y = d1 is executed. For the two assignment statements, the value for the
expression on the right side of the equal sign is assigned to the signal on the left side
of the equal sign. Notice that the output signal y on the left side of the equal sign is
declared as a reg because assignment statements inside the always block cannot
drive a wire data type, but can only drive a register or an integer data type. Finally,
the module is terminated with the keyword endmodule. A summary of the Verilog
language can be found in Appendix C.
In the VHDL code shown in Figure 1.6, the LIBRARY and USE statements are simi-
lar to the “#include” and “using namespace” preprocessor commands in C11. None
of the words used in VHDL is case sensitive, however, in the examples, the keywords
are shown in upper case. The IEEE library contains the definition for the STD_LOGIC
type used in the declaration of signals. The ENTITY section declares the interface for
the circuit by specifying the input and output signals of the circuit. In this example,
there are three input signals of type STD_LOGIC and one output signal also of type
STD_LOGIC. Again, the names used for these signals match those shown earlier in the
logic symbol. The ARCHITECTURE section defines the actual operation of the circuit.
1.3 exaMples of a 2-to-1 MultIplexer 9
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY multiplexer IS PORT (
s, d0, d1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Behavioral OF multiplexer IS
BEGIN
PROCESS(s, d0, d1)
BEGIN
IF (s = '0') THEN
y <= d0;
ELSE
y <= d1;
END IF;
END PROCESS;
END Behavioral;
FIGURE 1.6 Behavioral VHDL code for a 2-to-1 multiplexer.
The ARCHITECTURE keyword is followed by a user identifier name and the entity that
it is for. The PROCESS block with its sensitivity list is like the always block in Verilog.
The operation of the multiplexer is defined in the conditional IF-THEN-ELSE statement.
The two signal assignment statements, which use the symbol ,5 to denote the signal
assignment, in conjunction with the IF-THEN-ELSE statement, says that the signal y gets
the value of d0 if s is equal to 0; otherwise, y gets the value of d1. The PROCESS block is
terminated by the END PROCESS statement, and the ARCHITECTURE block is terminated by
the END keyword followed by the name of this architecture. A summary of the VHDL
language can be found in Appendix D.
Having written the behavioral code, either in Verilog or VHDL, we will use a syn-
thesizer to automatically construct the netlist (which is the circuit connections) that
will operate according to the description of the code. As you can see, when designing
circuits at the behavioral level, we do not need to know what logic gates are needed or
how they are connected together. We only need to know their interface and functional
operation, and then describe it using an HDL.
1.3.2 Gate Level

At the gate level, you can draw a schematic diagram or circuit diagram, which shows
how the logic gates are connected together. Two different schematic diagrams of a
2-to-1 multiplexer circuit are shown in Figures 1.7(a) and (b). In Figure 1.7(a), the
circuit uses three NOT gates ( ), four 3-input AND gates ( ), and one 4-input OR gate
( ). In Figure 1.7(b), only one NOT gate, two 2-input AND gates, and one 2-input OR
gate are needed. Although one circuit is larger (in terms of the number of gates needed)
than the other, both of these circuits realize the same 2-to-1 multiplexer function.
Therefore, when we want to actually implement a 2-to-1 multiplexer circuit, we will
want to use the second, smaller circuit rather than the first.
s d1 d0
d0
y s y
d1
(a) (b)
FIGURE 1.7 Gate level circuit diagram for the 2-to-1 multiplexer: (a) circuit using
eight gates; (b) circuit using four gates.
At the gate level, you also can describe the 2-to-1 multiplexer using a truth table or
with a Boolean equation as shown in Figures 1.8(a) and (b), respectively. For the truth
table, we list all possible combinations of the binary values for the three inputs, s, d0,
and d1, and then determine what the output value y should be based on the functional
description of the circuit. We see that for the first four rows of the table when s 5 0,
y has the same values as d0; whereas, in the last four rows when s 5 1, y has the same
values as d1.
The Boolean equation in Figure 1.8(b) can be derived from either the schematic
diagram or the truth table. The first equality in Figure 1.8(b) matches the truth table
in Figure 1.8(a) and also the schematic diagram in Figure 1.7(a). The second equality
in Figure 1.8(b) matches the schematic diagram in Figure 1.7(b). To derive the first
equality equation from the truth table, we look at all of the rows where the output y is
a 1. Each of these rows results in a term in the equation. For each term, the variable is
primed 1 r 2 when the value of the variable is a 0, and unprimed when the value of the
variable is a 1. For example, the first term s rd1rd0 in the equation is obtained from the
first row in the truth table where y is a 1, since s is a 0, d1 is a 0 and d0 is a 1.
s d1 d0 y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
y 5 s rd1rd0 1 s rd1d0 1 sd1d0r 1 sd1d0
1 1 1 1 5 s rd0 1 sd1
(a) (b)
FIGURE 1.8 Gate level description of the 2-to-1 multiplexer: (a) using a truth table;
(b) using a Boolean equation.
1.4 IntroductIon to Hardware descrIptIon language 11
d0
Vcc
s y
d1
FIGURE 1.9 Transistor circuit for the 2-to-1 multiplexer.
1.3.3 Transistor Level

The 2-to-1 multiplexer circuit at the transistor level is shown in Figure 1.9. It contains
six transistors, three of which are P-type metal-oxide semiconductor (PMOS) transis-
tors ( ), and three are N-type metal-oxide semiconductor (NMOS) transistors ( ).
The pair of transistors on the left forms a NOT gate for the signal s, while the two pairs
of transistors on the right form two transmission gates. The transmission gate allows
or disallows the data signal d0 or d1 to pass through, depending on the control signal s.
The top transmission gate is turned on when s is a 0, and the bottom transmission gate
is turned on when s is a 1. Hence, when s is 0, the value at d0 is passed to y, and when
s is 1, the value at d1 is passed to y.
A more detailed discussion about how to design digital circuits at the transistor
level can be found in the online chapter on Implementation Technologies.
1.4 Introduction to Hardware Description Language

The popularity of using hardware description languages (HDL) to design digital cir-
cuits began in the mid-1990s when commercial synthesis tools became available. Two
popular HDLs used by many engineers today are VHDL and Verilog. VHDL was
sponsored and developed jointly by the U.S. Department of Defense and the Institute
of Electrical and Electronic Engineers (IEEE) in the mid-1980s. It was standardized by
the IEEE in 1987 (VHDL-87), and later extended in 1993 (VHDL-93). Verilog, on the
other hand, was first introduced in 1984, and again later in 1988, as a proprietary hard-
ware description language by two companies: Synopsys and Cadence Design Systems.
Both Verilog and VHDL, in many respects, are similar to a regular computer
programming language, such as C. For example, it has constructs for variable assign-
ments, conditional statements, loops, and functions (just to name a few). In a computer
programming language, a compiler is used to translate the high-level source code to
machine code. In HDL, however, a synthesizer is used to translate the source code
to a description of the actual hardware circuit that implements the code. From this
description, which we call a netlist, the actual, physical digital device that realizes the
source code can be made automatically. Accurate functional and timing simulation of
the code is also possible in order to test the correctness of the circuit.
We saw in the previous section how we used Verilog and VHDL to describe the
2-to-1 multiplexer at the behavioral level. HDL also can be used to describe a circuit at
other levels. Figure 1.10 shows the VHDL code for the multiplexer written at the data-
flow level. The main difference between the behavioral VHDL code shown in Figure 1.6
and the dataflow VHDL code is that, in the behavioral code, there is a PROCESS block
statement; whereas, in the dataflow code, there is no PROCESS statement. Statements
within a PROCESS block are executed sequentially as in a computer program, while state-
ments outside a PROCESS block (including the PROCESS block itself) are executed concur-
rently or in parallel. The signal assignment statement, using the symbol <=, is derived
directly from the Boolean equation for the multiplexer, as shown in Figure 1.8(b), using
the built-in VHDL operators: AND, OR, and NOT.
The corresponding Verilog version of the 2-to-1 multiplexer written at the dataflow
level is shown in Figure 1.11. For Verilog, the assign keyword is used for the signal
assignment, and the symbols &, 0 , and , are used for the logical operators AND, OR,
and NOT, respectively.
In addition to the behavioral and dataflow levels, we also can write HDL code at
the structural level. Figure 1.13 shows the Verilog code for the multiplexer written at
the structural level and Figure 1.14 shows the VHDL code. The code is based on the
circuit shown in Figure 1.7(b) and duplicated here in Figure 1.12.
LIBRARY IEEE;
ENTITY multiplexer IS PORT(
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Dataflow OF multiplexer IS
BEGIN
y <= ((NOT s) AND d0) OR (s AND d1);
END Dataflow;
FIGURE 1.10 Dataflow level VHDL description of the 2-to-1 multiplexer.
input s, d0, d1,
output y
);
assign y = ((~s) & d0) | (s & d1);
endmodule
FIGURE 1.11 Dataflow level Verilog description of the 2-to-1 multiplexer.
1.4 IntroductIon to Hardware descrIptIon language 13
d0 snd0
U2
U1
sn
s U4 y
U3
d1 sd1
FIGURE 1.12 2-to-1 multiplexer circuit.
input s, d0, d1,
output y
);
wire sn,snd0,sd1;
// first parameter is the output;
// remaining parameters are the inputs
not U1(sn,s);
and U2(snd0,sn,d0);
and U3(sd1,s,d1);
or U4(y,snd0,sd1);
endmodule
FIGURE 1.13 Structural Verilog code for the 2-to-1 multiplexer.
----------------- NOT gate -----------------------

LIBRARY IEEE;
ENTITY notgate IS PORT(
i: IN STD_LOGIC;
o: OUT STD_LOGIC);
END notgate;
ARCHITECTURE Dataflow OF notgate IS
BEGIN
o <= NOT i;
END Dataflow;
----------------- 2-input AND gate ---------------
LIBRARY IEEE;
ENTITY and2gate IS PORT(
i1, i2: IN STD_LOGIC;
o: OUT STD_LOGIC);
END and2gate;
FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.

(continued on next page)
ARCHITECTURE Dataflow OF and2gate IS

BEGIN
o <= i1 AND i2;
END Dataflow;
----------------- 2-input OR gate ----------------
LIBRARY IEEE;
ENTITY or2gate IS PORT(
o: OUT STD_LOGIC);
END or2gate;
ARCHITECTURE Dataflow OF or2gate IS
BEGIN
o <= i1 OR i2;
END Dataflow;
----------------- 2-to-1 multiplexer ------------
LIBRARY IEEE;
ENTITY multiplexer IS PORT(
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Structural OF multiplexer IS
COMPONENT notgate PORT(
i: IN STD_LOGIC;
o: OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2gate PORT(
o: OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2gate PORT(
o: OUT STD_LOGIC);
END COMPONENT;
SIGNAL sn, snd0, sd1: STD_LOGIC;
BEGIN
U1: notgate PORT MAP(s, sn);
U2: and2gate PORT MAP(d0, sn, snd0);
U3: and2gate PORT MAP(d1, s, sd1);
U4: or2gate PORT MAP(snd0, sd1, y);
END Structural;
FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.
In the structural Verilog code shown in Figure 1.13, the keywords (not, and, or) for
the various gates are used. The first parameter for these gate statements is the output from
the gate. The remaining parameters in the statements are the inputs to the gate. The wire
1.5 sYntHesIs 15
keyword defines user identifiers using the wire data type for connecting the gates together
based on the schematic diagram. For example, looking at the schematic diagram, the NOT
gate labeled U1 has s as the input and sn as the output. Hence in the corresponding code,
we have the statement not U1(sn, s). The user-identifier name U1 in the statement
is optional, and is added only for easy identification of the gate in the circuit.
The structural VHDL code shown in Figure 1.14 looks more complicated than
the Verilog code, but it actually does the same thing. The three different gates (notgate,
and2gate, and or2gate) used in the circuit are declared and defined first using the ENTITY
and ARCHITECTURE statements, respectively. After this, the multiplexer is declared (also
with the ENTITY statement). The actual, structural definition of the multiplexer is in the
ARCHITECTURE section for multiplexer. First of all, the COMPONENT statements specify
what components are used in the circuit. The SIGNAL statement declares the three inter-
nal signals (sn, snd0, and sd1) that will be used in the connection of the circuit. Finally,
the PORT MAP statements declare the instances of the gates used in the circuit and specify
how they are connected using the external and internal signals. So if you ignore all of
the preliminary declaration stuff, the last few statements in the VHDL code matches
the statements in the Verilog code.
The focus of this book is not to teach the details of how to write Verilog or VHDL
codes. Because these two hardware description languages are quite similar to high-level
computer languages such as C, which you already should be familiar with, we will take the
approach of learning by examples. Throughout the book, there are Verilog and VHDL
codes for all of the circuits discussed, and in the appendix there is a syntax summary of the
two languages for your reference. By looking at the examples and the summary references,
you should be able to write codes using these languages to describe your digital circuits.
1.5 Synthesis
Given a gate-level circuit diagram, such as the one shown in Figure 1.7, you actually
can get some discrete logic gates and manually connect them together with wires on
a breadboard. Traditionally, this is how electronic engineers actually designed and
implemented digital logic circuits. However, this is not how electronic engineers design
circuits anymore. They write programs, such as the one in Figure 1.6, just like what
computer programmers do. The question is how does the program that describes the
operation of the circuit actually get converted to the physical circuit?
The problem here is similar to translating a computer program written in a high-
level language to machine language for a particular computer to execute. For a computer
program, we use a compiler to do the translation. For translating a digital logic circuit,
we use a synthesizer. Instead of using a high-level computer language to describe a
computer program, we use a hardware description language (HDL) to describe the oper-
ations of a digital logic circuit. Writing a description of a digital logic circuit is similar to
writing a computer program except that a different language is used. A synthesizer then
is used to translate the HDL program into the circuit netlist. A netlist is a description of
how a circuit actually is realized or connected using basic gates. This translation process
from an HDL description of a circuit to its netlist is referred to as synthesis.
The netlist from the output of the synthesizer can be used directly to implement
the actual circuit in a FPGA IC chip. With this final step, the creation of a digital
circuit that is implemented fully in an IC chip can be done easily. The appendices
give a tutorial of the complete process: from writing the Verilog or VHDL code to
synthesizing the circuit and uploading the netlist to a FPGA chip using an FPGA
development board.
1.6 Going Forward

We will now embark upon a journey that will take you from a simple transistor to the
construction of a microprocessor. Figure 1.2 will serve as our guide and map. If you
get lost on the way, and do not know where a particular component fits in the overall
picture, just refer to this map. At the end, you will be able to design your own custom
microprocessor. The exciting part is that this is not just talk and theories. You will be
able to implement and try out all of the circuits on a real FPGA chip. You will be able
to make lights flash, motors run, and execute your own software program on your own
custom microprocessor.
Figure 1.15 is an actual picture of the circuitry inside an Intel Pentium 4 CPU.
When you reach the end of this book, you still may not be able to design the cir-
cuit for the P4 because of lack of resources, but you certainly will know how it is
designed, because you actually will have designed and implemented a real working
microprocessor yourself.
Getty Images / Handout
FIGURE 1.15 The internal circuitry of the Intel Pentium 4 CPU.
1.7 probleMs 17
1.7 PROBLEMS
1.1. Find out the approximate number of general-purpose microprocessors
sold in your country in the most recent year versus the number of dedi-
cated microprocessors sold.
1.2. Compile a list of devices controlled by a microprocessor that you use
during one regular day.
1.3. Describe what your regular daily routine would be like if no electrical
power (including battery power) were available.
1.4. What are the inputs and outputs for the following systems?
a) Traffic light
b) Heart pacemaker
c) Microwave oven
d) Musical greeting card
e) Hard disk drive (not the entire personal computer)
1.5. The speed of a microprocessor is often measured by its clock frequency.
What is the clock frequency of the fastest general-purpose microprocessor
available today?
1.6. Compare some typical clock speeds between general-purpose micropro-
cessors and dedicated microprocessors.
1.7. Summarize the mainstream generations of the Intel general-purpose
microprocessors used in personal computers, starting with the 8086 CPU.
List the year introduced, the clock speed, and the number of transistors in
each.
1.8. The first-generation PC uses the Intel 8088 with approximately 29,000
transistors. Approximately how many transistors are in the Intel Core
i7 (Quad) CPU? Approximately how many transistors are in the Xilinx
Virtex-7 FPGA? Approximately how many transistors are in the Altera
Stratix V FPGA?
1.9. Using Figure 1.11 as a template, write the dataflow Verilog code for the
2-to-1 multiplexer circuit shown in Figure 1.7(a).
1.10. Using Figure 1.13 as a template, write the structural Verilog code for the
1.11. Using Figure 1.10 as a template, write the dataflow VHDL code for the
1.12. Using Figure 1.14 as a template, write the structural VHDL code for the
1.13. Do the Xilinx ISE tutorial in Appendix A.
1.14. Do the Altera Quartus tutorial in Appendix B.
CHAPTER 2
Fundamentals of Digital Circuits
Control Data
Inputs Microprocessor Inputs
'0'
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Register
Status 8
Signals
Control Data
Outputs Outputs
18
2.1 BInARY nUMBeRs 19
Our world is an analog world. Measurements that we make of the physical objects
around us are never in discrete units, but rather in a continuous range. We talk about
physical constants such as 2.718281828. . . or 3.141592. . . . To build analog devices
that can process these values accurately is next to impossible. Even building a simple
analog radio requires very accurate adjustments of frequencies, voltages, and currents
at each part of the circuit. If we were to use voltages to represent the constant 3.14, we
would have to build a component that will give us exactly 3.14 volts every time. This is
again impossible because the manufacturing process is imperfect, and each component
produced will be slightly different from the others. Even if the manufacturing process
could be made as perfect as we can get, we still would not be able to get 3.14 volts from
this component every time we use it. The reason is that the physical elements used in
producing the component behave differently in different environments, such as tem-
perature, pressure, and gravitational force, just to name a few. Therefore, even if the
manufacturing process is perfect, using this component in different environments will
not give us exactly 3.14 volts every time.
To make things simpler, we work with a digital abstraction of our analog world.
Instead of working with an infinite continuous range of values, we use just two values,
1 and 0, to represent the two states, on and off, in a digital electronic circuit. It cer-
tainly is much easier to control and work with two values rather than an infinite range
of values. We call these two values binary values because there are only two of them.
A single 0 or a single 1 is a binary digit or bit for short (where “bi” comes from the first
two letters of the word “binary,” and “t” comes from the last letter of the word “digit”).
This sounds great, but we have to remember that the underlying building block for our
digital circuits is still based on an analog world.
This chapter provides the theoretical foundations for building digital logic circuits
using logic gates, the basic building blocks for all digital circuits. We start with an intro-
duction on working with binary numbers and performing simple arithmetic in binary.
We then will introduce the basic logic gates for building digital circuits. Next, we cover
the basic theory of Boolean algebra, Boolean functions, and how to use and manipulate
them. Many students may find these theories to be boring and difficult to understand,
but let me encourage you to grind through it patiently. The good news is that I will
try to keep them as short and simple as possible. You also will find that many of the
Boolean theorems are very familiar, because they are similar to the algebra theorems
that you already learned in your high school math class. Finally, we conclude with an
example of building a simple digital circuit.
2.1 Binary Numbers

Because digital circuits deal with binary values, we will begin with an introduction to
binary numbers. A bit, having a value of either 0 or 1, can represent only two things
or two pieces of information. It is, therefore, necessary to group together many bits to
represent more pieces of information. A string of n bits can represent 2n different pieces
of information. For example, a string of two bits can represent four different things
20 CHAPTER 2 FUnDAMentALs oF DIGItAL CIRCUIts
using the four unique combinations: 00, 01, 10, and 11. By using different encoding
techniques, a group of bits can be used to represent different information, such as a
number, a letter of the alphabet, a character symbol, or a command for the micropro-
cessor to execute.
Instead of working with the more familiar decimal numbers that consist of decimal
digits, we work with binary numbers, which consist of a string of bits. However, the
use of binary numbers is just a convenient form of representation for a string of bits,
because we can just as well use octal, decimal, or hexadecimal numbers to represent
this group of bits. In fact, you will find that hexadecimal numbers often are used as a
shorthand notation for binary numbers.
2.1.1 Counting in Binary

The decimal number system that we all are familiar with is a positional system. In
other words, the value of the digit is dependent on the position of the digit within the
number. For example, in the decimal number 48, the decimal digit 4 has a greater value
than the decimal digit 8 because it is in the tens position, whereas the digit 8 is in the
unit position.
The binary number system is also a positional system, with the only difference
between the two systems being that the binary system is a base-2 system, using only two
digits, 0 and 1, instead of a base-10 system, using ten digits, 0 to 9. So for the binary
number 101, the leftmost 1 has a larger value than the rightmost 1.
Counting in binary is just like counting in decimal. When we count in decimal, we
count from 0 to 9. After reaching 9 (the last digit) we go back to 0, and have a carry of
a 1 by incrementing the next digit to the left by 1, giving us 10. Doing the same thing in
binary, we count from 0 to 1 (which is the last digit in the binary system). After reach-
ing 1, we go back to 0, and increment the next bit to the left by 1, giving us 10. Although
we use the number 10 in both systems, they are different because one is in base ten and
the other is in base two, and so they have different values. To avoid confusion, we will
use a subscript to denote what base the number is in, for example, 102 is the number
10 in base 2, and 1010 is the same number, but in base 10. Continuing with the count in
binary, the next few numbers in sequence are 11, 100, 101, 110, 111, and 1000.
The binary numbers from 0 to 15 (decimal) are shown in Figure 2.1. The range
from 0 to 15 has 16 different combinations. We need a 4-bit binary number (i.e., a string
of four bits) to represent this range because 24 5 16. The count from 0 to 15 in binary
is shown in the second column. The corresponding octal (base 8) and hexadecimal
(base 16) numbers also are shown in the figure. We will discuss them further in later
sections.
2.1.2 Converting between Binary and Decimal

The decimal value of a binary number can be found just like that for a decimal number,
except that we raise the base number 2 to a power rather than the base number 10 to
a power. The rightmost digit or bit is raised to the power 0, the next digit or bit to the
left is raised to the power 1, then the next one to the power 2, and so on. For example,
the value for the decimal number 658 is
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influence had been most potent in his life, and he at once replied,
“Mother’s.” In his personal appearance he strongly resembled her. If
one could have wished for any change in his character, it might have
been that he should have had in it just a little bit more of the ideality
of his father, and just a little bit less of the intense realism of his
mother. Some of his mother’s most evident characteristics were in a
measure traceable as an inheritance from her father, William Diven;
for example, the place to which she assigned education among the
values of life. He was a man of considerable literary attainments, for
his day, and for one residing out in the country; so that when in later
years he came to make his home with the Mateers he brought with
him a collection of standard books, thus furnishing additional and
substantial reading for the family. Even Shakspere and Burns were
among the authors, though they were not placed where the children
could have access to them, and were made familiar to them only by
the grandfather’s quotation of choice passages. When his daughter
was a little girl, so intense was his desire that she should have as
good an education as practicable, that if the weather was too
inclement for her to walk to the schoolhouse he used to carry her on
his back. It was her lifelong regret that her education was so
defective; and it is said that after she was seventy years of age, once
she dreamed that she was sent to school at Mount Holyoke, and she
awoke in tears to find that she was white-haired, and that it was only
a dream. Although it involved the sacrifice of her own strength and
ease, she never faltered in her determination that her children should
have the educational advantages to which she had aspired, but
never attained; and in what they reached in this direction she had a
rich satisfaction. Toward every other object which she conceived to
be good and true, and to be within the scope of her life, she set
herself with like persistence, and strength, and willingness for self-
sacrifice. Her piety was deep, thorough and all-controlling; but with
her it was a principle rather than a sentiment. Its chief aim was the
promotion of the glory of the infinitely holy God, though as she
neared the visible presence of her Saviour, this softened somewhat
into a conscious love and faith toward him. She survived her
husband twenty-one years, and died at the advanced age of
seventy-nine. When the tidings of this came to her children in China,
their chief lament was, “How we shall miss her prayers!”
When Calvin was about five years old, his parents bought a farm
twelve miles north of Gettysburg, near what is now York Springs, in
Adams County. It is some twenty miles from the place of his birth,
and beyond the limits of the Cumberland valley. Even now it is a
comparatively out-of-the-way spot, reached only by a long drive from
the nearest railway station; then it was so secluded that the Mateers
called the house into which they removed the “Hermitage.” Here the
family continued to reside until about the time of Calvin’s graduation
from college. Then a second and much longer move was made, to
Mercer County, in western Pennsylvania. Still later, a third migration
brought them to Illinois. It is to the home in Adams County that
Calvin refers in the line quoted at the head of this chapter, as the
place where “were all the fond recollections and associations” of his
youth.
The farm was not very large, and the soil was only moderately
productive, notwithstanding the labor and skill that the Mateers put
upon it. In picking off the broken slate stones which were turned up
thick by the plow, the children by hard experience were trained in
patient industry as to small details. At least the two elder frequently
beguiled the tedium of this task “by reciting portions of the
Westminster Catechism and long passages of Scripture.” Another
really tedious occupation, which, however, was converted into a sort
of late autumn feast of ingathering, was shared by the whole family,
but was especially appreciated by the children. This was the nut
harvest of the “shellbark” hickory trees of the forest. As many as fifty
or more bushels were gathered in a season; the sale of these
afforded a handsome supplement to the income of the household.
Along the side of the farm flows a beautiful stream, still bearing its
Indian name of Bermudgeon, and in front of the house is a smaller
creek; and in these Calvin fished and set traps for the muskrats, and
experimented with little waterwheels, and learned to swim. Up on an
elevation still stand the old house and barn, both constructed of the
red brick once so largely used in the eastern section of
Pennsylvania. Both of these are still in use. Though showing signs of
age and lack of care, they are witnesses that for those days the
Mateers were quite up to the better standard of living customary
among their neighbors. “This growing family,” says Mrs. Kirkwood
(Jennie), “was a hive of industry, making most of the implements
used both indoors and out, and accomplishing many tasks long since
relegated to the factory and the shop. Necessity was with them the
mother not only of invention, but of execution as well. All were up
early in the morning eating breakfast by candlelight even in summer,
and ready before the sun had risen for a day’s work that continued
long after twilight had fallen.” In the barn they not only housed their
horses and cattle and the field products, but also manufactured most
of the implements for their agricultural work. Here Calvin first had his
mechanical gifts called into exercise, sometimes on sleds and
wagons and farm tools, and sometimes on traps and other articles of
youthful sport.
In this home family worship was held twice each day,—in the
morning often before the day had fully dawned, and in the evening
when the twilight was vanishing into night. In this service usually
there were not only the reading of Scripture and the offering of
prayer, but also the singing of praise, the fine musical voice of the
father and his ability to lead in the tunes making this all the more
effective. Of course, on the Sabbath the entire family, young and old,
so far as practicable, attended services when held in the
Presbyterian church not far away. But that was not all of the religious
observances. The Sabbath was sacredly kept, after the old-
fashioned manner of putting away the avoidable work of the week,
and of giving exceptional attention to sacred things. Mrs. Kirkwood,
who was near enough in age to be the “chum” of Calvin, writes:
“Among the many living pictures which memory holds of those years,
there is one of a large, airy, farmhouse kitchen, on a Sabbath
afternoon. The table, with one leaf raised to afford space for ‘Scott’
and ‘Henry’ stands between two doors that look out upon tree-
shaded, flower-filled yards. There sits the mother, with open books
spread all about her, studying the Bible lesson for herself and for her
children. Both parents and children attended a pastor’s class in
which the old Sunday School Union Question Book was used. In this
many references were given which the children were required to
commit. Older people read them from their Bibles, but these children
memorized them. Some of the longer ones could never be repeated
in after times without awakening associations of the muscularizing
mental tussles of those early days.” It was a part of the religious
training of each child in that household, just as soon as able to read,
to commit to memory the Westminster Shorter Catechism,—not so
as to blunder through the answers in some sort of fashion, but so as
to recite them all, no matter how long or difficult, without mistaking so
much as an article or a preposition.
Stories are handed down concerning the boy Calvin at home,
some of which foreshadow characteristics of his later years. One of
these must suffice here. The “Hermitage,” when the Mateers came
into it, was popularly believed to be haunted by a former occupant
whose grave was in an old deserted Episcopal churchyard about a
mile away. The grave was sunken, and it was asserted that it would
not remain filled. It was also rumored that in the gloomy woods by
which the place was surrounded a headless man had been seen
wandering at night. Nevertheless the Mateer children often went up
there on a Sabbath afternoon, and entered the never-closed door, to
view the Bible and books and desk, which were left just as they had
been when services long before had ceased to be held; or wandered
about the graves, picking the moss from the inscriptions on the
headstones, in order to see who could find the oldest. It was a place
that, of course, was much avoided at night; for had not restless white
forms been seen moving about among these burial places of the
dead? The boy Calvin had been in the habit of running by it in the
late evening with fast-beating heart. One dark night he went and
climbed up on the graveyard fence, resolved to sit in that supremely
desolate and uncanny spot till he had mastered the superstitious fear
associated with it. The owls hooted, and other night sounds were
intensified by the loneliness, but he successfully passed his chosen
ordeal, and won a victory worth the effort. In a youthful way he was
disciplining himself for more difficult ordeals in China.
II
THE MAKING OF THE MAN
“It has been said, and with truth, that when one has finished his course in
an ordinary college, he knows just enough to be sensible of his own
ignorance.”—letter to his mother, January 15, 1857.
The letter from which the sentence at the head of this chapter is
taken was written a week after Mateer had reached his twenty-first
year and when he was almost half advanced in his senior year in
college. Later in the letter he says: “Improvement and advancement
need not, and should not, stop with a college life. We should be
advancing in knowledge so long as we live.” With this understanding
we may somewhat arbitrarily set his graduation from college as
terminating the period of his life covered by what I have designated
as “the making of the man.”
Back of all else lay his native endowments of body and of mind.
Physically he was exceptionally free from both inherited and
acquired weaknesses. In a letter which he wrote to his near relatives
in this country on the occasion of his seventieth birthday, he said, “I
have not only lived, but I have enjoyed an exceptional measure of
health.” At no period was he laid aside by protracted sickness. At the
same time, this must not be understood to signify that he had one of
those iron constitutions that seem to be capable of enduring without
harm every sort of exposure except such as in its nature must be
mortal. In that part of his Journal covering portions of his college and
seminary work he often tells of a lassitude for which he blames
himself as morally at fault, but in which a physician would have seen
symptoms of a low bodily tone. Bad food, lack of exercise and ill
treatment on the voyage which first brought him to China left him
with a temporary attack of dyspepsia. Occasionally he had
dysentery, and once he had erysipelas. At no time did he regard
himself as so rugged in constitution that he did not need to provide
himself with proper clothing and shelter, so far as practicable.
Nevertheless it was because of the sound physique inherited from
his parents, and fostered by his country life during early youth, that
without any serious breaking down of health or strength he was able
to endure the privations and the toils and cares of his forty-five years
in China.
As to his native mental endowments, no one would have been
more ready than he to deny that he was a “genius,” if by this is
meant that he had an ability offhand to do important things for the
accomplishment of which others require study and effort. If, as to
this, any exception ought to be made in his favor, it would be
concerning some of the applied sciences and machinery, and
possibly mathematics. He certainly had an extraordinary aptitude
especially as to the former of these. While he himself regarded his
work in the Mandarin as perhaps the greatest of his achievements,
he had no such talent for the mastery of foreign languages that he
did not need time and toil and patience to learn them. In college his
best standing was not in Latin or Greek. In China other missionaries
have been able to preach in the native tongue after as short a period
of preparation; and the perfect command of the language which he
attained came only after years of ceaseless toil.
Such were his native physical and mental endowments: a good,
sound, though not unusually rugged, bodily constitution; and an
intellect vigorous in all of its faculties, which was in degree not so
superior as to set him on a pedestal by himself, yet was very
considerably above the average even of college students.
Concerning the qualities of his heart and of his will it is best to wait
and speak later in this volume.
In the making of a man native endowments are only the material
out of which and on which to build. Beyond these, what we become
depends on our opportunities and the use to which we put them. The
atmosphere of the old home had much to do with the unfolding of the
subsequent life and character of Mateer. Some of his leading
qualities were there grown into his being.
Other powerful influences also had a large share in his
development. About three quarters of a mile from the “Hermitage”
stood a township schoolhouse, a small brick building, “guiltless alike
of paint or comfort,” most primitive in its furnishing, and open for
instruction only five or six months each year, and this in the winter.
The pressure of work in the house and on the farm never was
allowed to interrupt the attendance of the Mateer children at this little
center of learning for the neighborhood. Of course, the teachers
usually were qualified only to conduct the pupils over the elementary
branches, and no provision was made in the curriculum for anything
beyond these. But it so happened that for two winters Calvin had as
his schoolmaster there James Duffield, who is described by one of
his pupils still living as “a genius in his profession, much in advance
of his times, and quite superior to those who preceded and to those
who came after him. In appearance Duffield was awkward and shy.
His large hands and feet were ever in his way, except when before a
class; then he was suddenly at ease, absorbed in the work of
teaching, alert, full of vitality, with an enthusiasm for mastery, and an
intellectual power that made every subject alive with interest, leaving
his impress upon each one of his pupils.” Algebra was not
recognized as falling within the legitimate instruction, and no
suspicion that any boy or girl was studying it entered the minds of
the plain farmers who constituted the official visitors. One day a
friend of the teacher, a scholarly man, came in at the time when the
examinations were proceeding, and the teacher sprang a surprise by
asking this friend whether he would like to see one of his pupils solve
a problem in algebra. He had discerned the mathematical bent of the
lad, Calvin Mateer, and out of school hours and just for the
satisfaction of it he had privately been giving the boy lessons in that
study. When an affirmative response was made by the stranger,
Calvin went to the blackboard and soon covered half of it with a
solution of an algebraic problem. Surprised and delighted, the
stranger tested the lad with problem after problem, some of them the
hardest in the text-book in use, only to find him able to solve them. It
would have been difficult to discover which of the three principal
parties to the examination, the visitor, the teacher, or the pupil, was
most gratified by the outcome. There can be no question that this
country school-teacher had much to do with awakening the
mathematical capabilities and perhaps others of the intellectual gifts
which characterized that lad in manhood and throughout life.
When Calvin was in his seventeenth year, he started in his pursuit
of higher education, entering a small academy at Hunterstown, eight
miles from the “Hermitage.” In this step he had the stimulating
encouragement of his mother, whose quenchless passion for
education has already been described. His father probably would at
that time have preferred that he should remain at home and help on
the farm; and occasionally, for some years, the question whether he
ought not to have fallen in with the paternal wish caused him serious
thought. As it was, he came home from the academy in the spring,
and in the autumn and also at harvest, to assist in the work.
The first term he began Latin, and the second term Greek, and he
kept his mathematics well in hand, thus distinctly setting his face
toward college. But his pecuniary means were narrow, and in the
winter of 1853-54 he had to turn aside to teach a country school
some three miles from his home. In a brief biographical sketch
which, by request of his college classmates, he furnished for the
fortieth anniversary of their graduation he says: “This was a hard
experience. I was not yet eighteen and looked much younger. Many
of the scholars were young men and women, older than I, and there
was a deal of rowdyism in the district. I held my own, however, and
finished with credit, and grew in experience more than in any other
period of my life.”
When the school closed he returned to the academy, which by that
time had passed into the hands of S. B. Mercer, in whom he found a
teacher of exceptional ability, both as to scholarship and as to the
stimulation of his students to do and to be the best that was possible
to them. In the spring of 1855 Mr. Mercer left the Hunterstown
Academy, and went to Merrittstown, Fayette County, Pennsylvania,
where he took charge of the Dunlaps Creek Academy. Calvin,
influenced by his attachment to his teacher, and also by his intention
to enter Jefferson College, situated in a neighboring county, went
with him. Here he made his home, with other students, in the house
occupied by the Mercers. For teaching two classes, one in geometry
and one in Greek, he received his tuition. For the ostensible reason
that he had come so far to enter the academy he was charged a
reduced price for his board. All the way down to the completion of his
course in the theological seminary he managed to live upon the
means furnished in part from home, and substantially supplemented
by his own labors; but he had to practice rigid economy. It was while
at Merrittstown that he made a public profession of religion. This was
only a few months before he entered college. He found in Dr.
Samuel Wilson, the pastor of the Presbyterian church, a preacher
and a man who won his admiration and esteem, and who so
encouraged and directed him that he took this step.
In the autumn of 1855 he entered the junior class of Jefferson
College, at Canonsburg, Pennsylvania. In those days it was
customary for students to be admitted further advanced as to
enrollment than at present. I had myself preceded Mateer one year,
entering as a sophomore in the same class into which he first came
as a junior. One reason for this state of things was that the
requirements were considerably lower than they now are; and they
were often laxly enforced. Then, because the range of studies
required was very limited in kind, consisting until the junior year
almost exclusively of Latin, Greek and mathematics, it was possible
for the preparatory schools to carry the work of their students well up
into the curriculum of the college. Mateer had the advantage,
besides, of such an excellent instructor as Professor Mercer, and of
experience in teaching. He says: “I was poorly prepared for this
class, but managed to squeeze in. The professor of Latin wanted me
to make up some work which I had not done; but I demurred, and I
recollect saying to him, ‘If after a term you still think I ought to make
it up, I will do it, or fall back to the sophomore class.’ I never heard of
it afterwards. I was very green and bashful when I went to college,
an unsophisticated farmer’s boy from a little country academy. I
knew little or nothing of the ways of the world.”
As his classmate in college, and otherwise closely associated with
him as a fellow-student, I knew him well. I remember still with a good
deal of distinctness his appearance; he was rather tall, light-haired,
with a clear and intelligent countenance, and a general physique that
indicated thorough soundness of body, though not excessively
developed in any member. When I last saw him at Los Angeles a few
years ago, I could perceive no great change in his looks, except
such as is inevitable from the flight of years, and from his large and
varied experience of life. It seems to me that it ought to be easy for
any of his acquaintances of later years to form for themselves a
picture of him in his young manhood at the college and at the
theological seminary. So far as I can now recall, he came to college
unheralded as to what might be expected of him there. He did not
thrust himself forward; but it was not long until by his work and his
thorough manliness, it became evident that in him the class had
received an addition that was sure to count heavily in all that was of
importance to a student. I do not think that he joined any of the
Greek letter secret societies, though these were at the height of their
prosperity there at that time. In the literary societies he discharged
well and faithfully his duties, but he did not stand out very
conspicuously in the exercises required of the members. In those
days there was plenty of “college politics,” sometimes very petty, and
sometimes not very creditable, though not wholly without profit as a
preparation for the “rough-and-tumble” of life in after years, but in
this Mateer did not take much part. Most of us were still immature
enough to indulge in pranks that afforded us fun, but which were
more an expression of our immaturity than we then imagined; and
Mateer participated in one of these in connection with the Frémont-
Buchanan campaign in 1856. A great Republican meeting was held
at Canonsburg, and some of us students appeared in the procession
as a burlesque company of Kansas “border ruffians.” We were a
sadly disgraceful-looking set. Of one thing I am sure, that while
Mateer gave himself constantly to his duties and refrained from most
of the silly things of college life, he was not by any of us looked upon
as a “stick.” He commanded our respect.
The faculty was small and the equipment of the college meager.
The attendance was nearly three hundred. As to attainments, we
were a mixed multitude. To instruct all of these there were—for both
regular and required work—only six men, including one for the
preparatory department. What could these few do to meet the needs
of this miscellaneous crowd? They did their best, and it was possible
for any of us, especially for the brighter student, to get a great deal of
valuable education even under these conditions. Mateer in later
years acknowledges his indebtedness to all of the faculty, but
particularly to Dr. A. B. Brown, who was our president up to the latter
part of our senior year; to Dr. Alden, who succeeded him; and to
Professor Fraser, who held the chair of mathematics. Dr. Brown was
much admired by the students for his rhetorical ability in the pulpit
and out of it. Dr. Alden was quite in contrast to his predecessor as to
many things. He had long been a teacher, and was clear and
concise in his intellectual efforts. Mateer said, late in life, that from
his drill in moral science he “got more good than from any other one
branch in the course.” Professor Fraser was a brilliant, all-round
scholar of the best type then prevalent, and had the enthusiastic
admiration even of those students who were little able to appreciate
his teaching. In the physical sciences the course was necessarily still
limited and somewhat elementary. His classmates remember the
evident mastery which Mateer had of all that was attempted by
instruction or by experimentation in that department. It was not
possible to get much of what is called “culture” out of the curriculum,
and that through no fault of the faculty; yet for the stimulation of the
intellectual powers and the unfolding of character there was an
opportunity such as may be seriously lacking in the conditions of
college instruction in recent years.
These were the palmy days of Jefferson College. She drew to
herself students not only from Pennsylvania and the contiguous
states, but also from the more distant regions of the west and the
south. We were dumped down there, a heterogeneous lot of young
fellows, and outside of the classroom we were left for the most part
to care for ourselves. We had no luxuries and we were short of
comforts. We got enough to eat, of a very plain sort, and we got it
cheap. We were wholly unacquainted with athletics and other
intercollegiate goings and comings which now loom up so
conspicuously in college life; but we had, with rare exceptions, come
from the country and the small towns, intent on obtaining an
education which would help us to make the most of ourselves in after
years. As to this, Mateer was a thoroughly representative student.
He could not then foresee his future career, but he was sure that in it
he dared not hope for success unless he made thoroughly good use
of his present, passing opportunities. He was evidently a man who
was there for a purpose.
The class of 1857 has always been proud of itself, and not without
reason. Fifty-eight of us received our diplomas on commencement.
Among them were such leaders in the church as George P. Hays,
David C. Marquis and Samuel J. Niccolls, all of whom have been
Moderators of the General Assembly of the Presbyterian Church. In
the law, S. C. T. Dodd, for many years the principal solicitor of the
Standard Oil Company, stands out most conspicuously. Three of our
number have served for longer or shorter periods as college
presidents. Of Doctors of Divinity we have a long list, and also a
goodly number of Doctors of Law; and others, though they have
received less recognition for their work, have in our judgment
escaped only because the world does not always know the worth of
quiet lives. To spend years in the associations of such a class in
college is itself an efficient means of education. It is a high tribute to
the ability and the diligence of Mateer that, although he was with us
only two years, he divided the first honor. The sharer with him in this
distinction was the youngest member of the class, but a man who, in
addition to unusual capacity, also had enjoyed the best preparation
for college then available. On the part of Mateer, it was not what is
known as genius that won the honor; it was a combination of solid
intellectual capacity, with hard, constant work. The faculty assigned
him the valedictory, the highest distinction at graduation, but on his
own solicitation, this was given to the other first honor man.
In a letter sent by him from Wei Hsien, China, September 4, 1907,
in answer to a message addressed to him by the little remnant of his
classmates who assembled at Canonsburg a couple of months
earlier, to celebrate the fiftieth anniversary of their graduation, he
said:
It was with very peculiar feelings of pleasure mingled with

sadness that I read what was done by you at your meeting.
The distance that separated me from you all adds a peculiar
emphasis to my feelings, suggestive of loneliness. I have
never been homesick in China. I would not be elsewhere than
where I am, nor doing any other work than what I am doing.
Yet when I read over the account of that meeting in
Canonsburg my feelings were such as I have rarely had
before. Separated by half the circumference of the globe for
full forty-four years, yet in the retrospect the friendship formed
in these years of fellowship in study seems to grow fresher
and stronger as our numbers grow less. A busy life gives little
time for retrospection, yet I often think of college days and
college friends. Very few things in my early life have
preserved their impression so well. I can still repeat the roll of
our class, and I remember well how we sat in that old
recitation room of Professor Jones [physics and chemistry]. I
am in the second half of my seventy-second year, strong and
well. China has agreed with me. I have spent my life
itinerating, teaching and translating, with chief strength on
teaching. But with us all who are left, the meridian of life is
past, and the evening draws on. Yet a few of us have still
some work to do. Let us strive to do it well, and add what we
can to the aggregate achievement of the class’s life work—a
record of which I trust none of us may be ashamed.
In the unanticipated privilege of writing this book I am trying to

fulfill that wish of our revered classmate.
III
FINDING HIS LIFE WORK
“From my youth I had the missionary work before me as a dim vision. A

half-formed resolution was all the while in my mind, though I spoke of
it to no one. But for this it is questionable whether I would have given
up teaching to go to the Seminary. After long consideration and many
prayers I offered myself to the Board, and was accepted.”—
autobiographical sketch for college class anniversary, 1897.
In the four sentences at the head of this chapter we have a

condensed outline of the process by which Calvin Mateer came to be
a foreign missionary. In his case it did not, as in the antecedent
experience of most other clergymen who have given themselves to
this work, start with an attraction first toward the ministry, and then
toward the missionary service; but just the reverse. In order to
understand this we need to go back again to “the old home,” and
especially to his mother. We are fortunate here in having the veil of
the past lifted by Mrs. Kirkwood, as one outside of the family could
not do, or, even if he could, would hesitate to do.
Long before her marriage, when indeed but a young girl,

Mary Nelson Diven [Calvin’s mother] heard an appeal for the
Sandwich Islands made by the elder Dr. Forbes, one of the
early missionaries of the American Board, to those islands.
He asked for a box of supplies. There was not much
missionary interest in the little church of Dillsburg, York
County, Pennsylvania, of which she was a member; for the
Presbyterian Board of Foreign Missions had not been
organized, and the American Board had not attained its
majority. Her pastor sympathized with the newly awakened
zeal and interest of his young parishioner, when she proposed
to canvass the congregation in response to Dr. Forbes’s
appeal. The box was secured and sent. This was the seed
that germinated in her heart so early and bore fruit through
the whole of her long life.
When in her nineteenth year she was married to John
Mateer, hers was a marriage in the Lord; and together she
and her husband consecrated their children in their infancy to
his service. This consecration was not a form; they were laid
upon the altar and never taken back. Through all the self-
denying struggles to secure their education, one aim was
steadily kept in view, that of fitting them either to carry the
gospel to some heathen land, or to do the Lord’s work in their
own land.
In addition to the foreign missionary periodicals, a number
of biographies of foreign missionaries were secured and were
read by all the family. Not only did this mother try to awaken in
her children an interest in missions through missionary
literature, but she devised means to strengthen and make
permanent this interest, to furnish channels through which
these feelings and impulses might flow toward practical
results. One of these was a missionary mite box which she
fashioned with her own hands, away back in the early forties,
before the mite boxes had been scattered broadcast in the
land. Quaint indeed it was, this plain little wooden box,
covered with small-figured wall paper. Placed upon the parlor
mantel, it soon became the shrine of the children’s devotion.
No labor or self-denial on their part was considered too great
to secure pennies for “the missionary box.” Few pennies were
spent for self-indulgence after that box was put in place, and
overflowing was the delight when some unwonted good
fortune made it possible to drop in silver coins—“six-and-a-
fourth bits,” or “eleven-penny bits.” Most of the offerings were
secured by such self-denials as foregoing coffee, sugar, or
butter. There was not at that time much opportunity for
country children to earn even pennies. The “red-letter” day of
all the year was when the box was opened and the pennies
were counted.
This earnest-hearted mother had counted the cost of what
she was doing in thus educating her children into the
missionary spirit. When her first-born turned his face toward
the heathen world, there was no drawing back—freely she
gave him to the work. As one after another of her children
offered themselves to the Foreign Board, she rejoiced in the
honor God had put upon her, never shrinking from the heart
strain the separation from her children must bring. She only
made them more special objects of prayer, thus transmuting
her personal care-taking to faith. She lived to see four of her
children in China.
This explains how it came about that this elder son, from youth,
had before him the missionary work as “a dim vision,” and that “a
half-formed resolution” to take it up was all the while in his mind.
When he graduated from college, he had made no decision as to
his life work. During the years preceding he at no time put aside the
claims of missions, and consequently of the ministry, upon him, and
in various ways he showed his interest in that line of Christian
service. As he saw the situation the choice seemed mainly to lie
between this on the one hand, and teaching on the other. Before he
graduated he had the offer of a place in the corps of instructors for
the Lawrenceville (New Jersey) school, since grown into such
magnitude and esteem as a boys’ preparatory institution; but the
conditions were not such that he felt justified in accepting.
Unfortunately, there is a blank in his Journal for the period between
March 4, 1857, some six months before he received his diploma at
Jefferson, and October 24, 1859, when he had already been a good
while in the theological seminary; and to supply it scarcely any of his
letters are available. In the autobiographical sketch already noticed
he says:
From college I went to take charge of the academy at

Beaver, Pennsylvania. I found it run down almost to nothing,
so that the first term (half year) it hardly paid me my board. I
was on my mettle, however, and determined not to fail. I
taught and lectured and advertised, making friends as fast as
I could. I found the school with about twenty boys, all day
scholars; I left it at the end of the third term with ninety, of
whom thirty were boarders. I could easily have gone on and
made money, but I felt that I was called to preach the gospel,
and so, I sold out my school and went to Allegheny [Western
Theological Seminary], entering when the first year was half
over.
One of his pupils at Beaver was J. R. Miller, D.D., a distinguished

minister of the gospel in Philadelphia; and very widely known
especially as the author of solid but popular religious books. Writing
of his experience at the Beaver Academy, he says:
When I first entered, the principal was Mr. Mateer. The first
night I was there, my room was not ready, and I slept with him
in his room. I can never forget the words of encouragement
and cheer he spoke that night, to a homesick boy, away for
almost the first time from his father and mother.... My contact
with him came just at the time when my whole life was in such
plastic form that influence of whatever character became
permanent. He was an excellent teacher. His personal
influence over me was very great. I suppose that when the
records are all known, it will be seen that no other man did so
much for the shaping of my life as he did.
While at Beaver he at last decided that he was called of God to

study for the ministry, but called not by any extraordinary external
sign or inward experience. It was a sense of duty that determined
him, and although he obeyed willingly, yet it was not without a
struggle. He had a consciousness of ability to succeed as a teacher
or in other vocations; and he was by no means without ambition to
make his mark in the world. Because he was convinced by long and
careful and prayerful consideration that he ought to become a
minister he put aside all the other pursuits that might have opened to
him. Not long after he entered the seminary he wrote to his mother:
“You truly characterize the work for which I am now preparing as a
great and glorious one. I have long looked forward to it, though
scarcely daring to think it my duty to engage in it. After much
pondering in my own mind, and prayer for direction I have thought it
my duty to preach.”
On account of teaching, as already related, he did not enter the
theological seminary until more than a year after I did, so that I was
not his classmate there. He came some months late in the school
year, and had at first much back work to make up; but he soon
showed that he ranked among the very best students. His
classmate, Rev. John H. Sherrard, of Pittsburg, writes:
One thing I do well remember about Mateer: his mental

superiority impressed everyone, as also his deep spirituality.
In some respects, indeed most, he stood head and shoulders
above his fellows around him.
Another classmate, Rev. Dr. William Gaston, of Cleveland, says:
We regarded him as one of our most level-headed men; our

peer in all points; not good merely in one point, but most
thorough in all branches of study. He was cheerful and yet not
flippant, and with a tinge of the most serious. He was
optimistic, dwelling much on God’s great love.... He was not
only a year in advance of most of us in graduating from
college, but I think that we, as students, felt that though we
were classmates in the seminary, he was in advance of us in
other things. Life seemed more serious to him. I doubt if any
one of us felt the responsibility of life as much as he did. I
doubt if anyone worked as hard as he.
The Western Theological Seminary, during the period of Mateer’s

attendance, was at the high-water mark of prosperity. The general
catalogue shows an enrollment of sixty-one men in his class; the
total in all classes hovered about one hundred and fifty. In the faculty
there were only four members, and, estimated by the specializations
common in our theological schools to-day, they could not adequately
do all their work; and this was the more true of them, because all
save one of them eked out his scanty salary by taking charge of a
city church. But they did better than might now be thought possible;
and especially was this practicable because of the limited curriculum
then prescribed, and followed by all students. Dr. David Elliott was
still at work, though beyond the age when he was at his best.
Samuel J. Wilson was just starting in his brilliant though brief career,
and commanded a peculiar attachment from his pupils. Dr. Jacobus
was widely known and appreciated for his popular commentaries.
However, the member of the faculty who left the deepest impress on
Mateer was Dr. William S. Plumer. Nor in this was his case
exceptional. We all knew that Dr. Plumer was not in the very first
rank of theologians. We often missed in his lectures the marks of
very broad and deep scholarship. But as a teacher he nevertheless
made upon our minds an impression that was so great and lasting
that in all our subsequent lives we have continued to rejoice in
having been under his training. Best of all was his general influence
on the students. We doubt whether in the theological seminaries of
the Presbyterian Church of the United States it has ever been
equaled, except by Archibald Alexander of Princeton. The dominant
element of that influence was a magnificent personality saturated
with the warmest and most tender piety, having its source in love for
the living, personal Saviour. For Dr. Plumer, Mateer had then a very
high degree of reverent affection, and he never lost it.
Spiritually, the condition of the seminary while Mateer was there
was away above the ordinary. In the winter of 1857-58 a great revival
had swept over the United States, and across the Atlantic. In no
place was it more in evidence than in the theological schools; it
quickened immensely the spiritual life of the majority of the students.
One of its fruits there was the awakening of a far more intense
interest in foreign missions. I can still recall the satisfaction which
some of us who in the seminary were turning our faces toward the
unevangelized nations had in the information that this strong man
who stood in the very first rank as to character and scholarship had
decided to offer himself to the Board of Foreign Missions for such
service as they might select for him. It was a fitting consummation of
his college and seminary life.
Yet it was only slowly, even in the seminary, and after much
searching of his own heart and much wrestling in prayer, that he
came to this decision. Outside of himself there was a good deal that
tended to impel him toward it. The faculty, and especially Dr. Plumer,
did all they could wisely to press on the students the call of the
unevangelized nations for the gospel. Representatives of this cause
—missionaries and secretaries—visited the seminary, where there
were, at that time, more than an ordinary number of young men who
had caught the missionary spirit. In college, Mateer, without seeking
to isolate himself from others, had come into real intimacy with
scarcely any of his fellow-students. He says in the autobiographical
sketch, “I minded my own business, making comparatively few
friends outside of my own class, largely because I was too bashful to
push my way.” In the seminary he, while still rather reserved, came
nearer to some of his fellow-theologues; and especially to one,
Dwight B. Hervey, who shared with him the struggle over duty as to a
field of service. They seem to have been much in conference on that
subject.
On the 21st of January, 1860, he presented himself before the
Presbytery of Ohio, to which the churches of Pittsburg belonged,
passed examination in his college studies, and was received under
the care of that body; but he had not then made up his mind to be a
missionary. On the 12th of April of the same year he went before the
Presbytery of Butler, at Butler, Pennsylvania (having at his own
request been transferred to the care of that organization, because
his parents’ home was now within its bounds), and was licensed to
preach. Yet still he had not decided to be a missionary. He was
powerfully drawn toward that work, and vacillation at no time in his
life was a characteristic; there simply was as yet no need that he
should finally make up his mind, and he wished to avoid any
premature committal of himself, which later he might regret, or which
he might feel bound to recall.
The summer of 1860 he spent in preaching here and there about
Pittsburg, several months being given to the Plains and Fairmount

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Digital Logic & Microprocessor Design

With Interfacing, 2nd Edition Enoch O.

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2.8 Minterms and Maxterms .............................................................................................. 46

4.4 Subtractor ...................................................................................................................123

5.17 Timing Issues...............................................................................................................210

7.2.3 Data Transfer Methods....................................................................................295

A.2 Creating a New Schematic Source File.........................................................................492

Design of Circuits using Verilog and VHDL

New to This Edition

Using This Book

Enoch O. Hwang, Ph.D.

Enoch Hwang has a Ph.D. in Computer Science from the University

1.1 Overview of Microprocessor Design

FIGURE 1.2 Internal parts of a microprocessor.

1.2 Design Abstraction Levels

1.3 Examples of a 2-to-1 Multiplexer

1.3.1 Behavioral Level

FIGURE 1.5 Behavioral Verilog code for a 2-to-1 multiplexer.

1.3.2 Gate Level

FIGURE 1.9 Transistor circuit for the 2-to-1 multiplexer.

1.3.3 Transistor Level

1.4 Introduction to Hardware Description Language

FIGURE 1.10 Dataflow level VHDL description of the 2-to-1 multiplexer.

FIGURE 1.11 Dataflow level Verilog description of the 2-to-1 multiplexer.

FIGURE 1.12 2-to-1 multiplexer circuit.

FIGURE 1.13 Structural Verilog code for the 2-to-1 multiplexer.

----------------- NOT gate -----------------------

FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.

ARCHITECTURE Dataflow OF and2gate IS

1.6 Going Forward

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FIGURE 1.15 The internal circuitry of the Intel Pentium 4 CPU.

Fundamentals of Digital Circuits

2.1 Binary Numbers

2.1.1 Counting in Binary

2.1.2 Converting between Binary and Decimal

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