METAL-OXIDE-

SEMICONDUCTOR
(MOS CAPACITOR)

Reference:
u Streetman Ch. 6.1 ~ 6.4
u Chenming Hu Ch. 5

Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 METAL-OXIDE-
SEMICONDUCTOR
(MOS CAPACITOR)

Reference:
u Streetman Ch. 6.1 ~ 6.4
u Chenming Hu Ch. 5

Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 METAL-OXIDE-
SEMICONDUCTOR
(MOS CAPACITOR)

Reference:
u Streetman Ch. 6.1 ~ 6.4
u Chenming Hu Ch. 5

Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Equilibrium no fermilevel. no carriers

M
HO
- &Padd : - -

Si changeable
>
-

P-Si
&

electrons
n N-type MOS capacitor negative elections
only surface
contain
,

Ø Semiconductor: p-type substrate for carrier inversion (becoming electrons)

Ø Work function: !"! (metal) is less than !"" (semiconductor, = !$ + ('# −
'$ )) generally
n Before M-O-S contact
Ø vacuum levels of three different regions are the same
Ø Fermi levels might not be the same for all three before they touch

189 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Equilibrium
At touch & After touch Et

fixe

4
./
③
Hide
x
3i

· &
&
3. 15
-
#
(Ec-Ef) ↓
e 45

(Ef-Ev) Y psy
④
- >

Depletion region
↓
holes I
holes # constr =-

V linear depletion region

n Fermi level re-arrangement
Ø Electrons in metal have higher energy, transferring to p-Si until '! = '"
Ø Surface depletion in p-Si due to accepting electrons (losing holes)
n Band offset unchanged only Psi Vox change .

Ø M-O: 4.1 – 0.95 = 3.05 eV; O-S = 4.05 – 0.95 = 3.1 eV fixed
n Ec – Ef can be calculated by doping level and vacuum level continuous
n Vacuum level must be continuous (otherwise, ' = −*+ → ∞, not allowed)
190 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 m ED
* /It *E2 E T ED

7
=
E
& = 0 (in oxide >
Equilibrium vs. Flatband
&
.

H
·
· Om + Ps
* Es
(Ulinear)Equilibrium Flat-band
n Flat-band (FB) voltage (!!" )
"# = $
· need to balance "# = "$% Ø Defined as the external voltage to
#E 7
eliminate the potential drop in
* semiconductor (or you can say to
Vox
eliminate the
MK VFB
q: 3 9
.
= Us + Vox depletion/accumulation)
Vs
Ø +$- = work function difference
E
ma

between metal and Si = φm – φs.

Yv
G = 12
W Ø If there exists charges in oxide,
3
+$- = 51 − 52 − %& (X)
4%&
D+ &
IPMF
=

↓ => Vth
n Potential drop (+%&%'( ) in oxide (+&) ) and Si (+*+ ) at equilibrium (i.e. +, = 0, but not
necessary flat band unless +$- = 0):
Ø +*+ :
 By expressing W (depletion width) as a function of +*+ E -DV =

‚ Then / +*+ = !0. 1 & T ** *TAl

/
ƒ Based on Gauss’ Law, the electric field at Si/SiO2 interface: '*+ +*+ = 0
& Fa !"
0!"
Ø Vox: at Si/SiO2 interface, 2*+ '*+ = 2&) '&) , '&) (+*+ ) = '
0#$ *+
and +&) +*+ = '&) ×4&)
Ø +%&%'( (+*+ ) = +$- = +*+ + +&) : a function of +*+ , which can be solved by working on
1(+*+ ) first Us Pm-4s Vox(Vsi)
191 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Accumulation, Depletion, Inversion
majority carrier
D Metal ## &
n At Vg < 0 (> 0) for p-Si (n-
↑ Si), the holes (electron)s
are piled up at Si
P of (interface) since the Efs at
surface is closer to Ev (Ec)
k -G compared to bulk
n Here we assume VFB = 0
(i.e. Efm = Efs at Vg = 0)
4M 4s
-
= O
D-type (FA)

VVth
VVth

↓t
Deplete Eff
htt
Ov ↓
& vt hity :
e hole
n At Vg > 0 (< 0) for p-Si (n-Si), the holes
surface
(electrons) are depleted up at Si (interface) n As Vg increases further, Efs cross Ei
since the Efs at surface is closer to Ev (Ec) such that the opposite charges exist
compared to bulk at the surface called weak inversion
n There exist fixed ionized acceptors (donors) n As the inverted charge density is
for p-Si (n-Si). equal to the bulk doping density,
192 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li strong inversion occurs e surface ↑ bulk
=
.
 NMO ↳ DMOS
Accumulation, Depletion, Inversion
Si Si

Vg = 0
& &

Vgco REMG
Vg >O

Of by

e deplete .

Vg7O VgcO
I

* M
e /44
A

193 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

hole **** B
 Surface Potential Ps =
Usi
n Band bending at Si/SiO2
Ø due to charge transfer from
Fermi level imbalance
n Bending potential "(>):
Ø downwards: positive
Ø upwards: negative
Ø surface potential:
"" = " > = 0 = +*+
z
reference level
n +, − +$- = +&) + +*+ (= 6" )
Ø The deviation from flat-band is the sum of
band bending in oxide (+&) ) and Si (+*+ ).
Ø The surface bending at Si will pull down the
oxide CB the same amount due to the fixed
CB barrier height
n +$- = "! − "" or −!+$- = '$! − '$"
Ø If '$! > '$" , +$- < 0; '$! < '$" , +$- > 0; '$! = '$" , +$- = 0
W
= qNa
n How to solve +, − +$- = +&) + +*+ (= 6" )
Ø Check the procedure in slide #270
/567 = !0' 1 = 22*+ !0' 6" = 22*+ !0' +*+ Vg El P Vi
|/567 | 22*+ <0' +*+ 22*+ <0' +*+ band bending
+&) = = , +, − +$- = + +*+
;&) ;&) ;&)
194 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li TAG I Vox
 V94 7 F Vox Usi
E high metal gate
Accumulation
,

* K

#IA KEND
c +

↑
-

n !( − !!" = !&' + !)* = (+ < 0 ⟹ (+ < 0

N %!&' n Ev gets closer to EF at the surface: more
holes at the surface called “Accumulation”
!" ($)
N n Hole concentration , - = ., % - &'
& Ø At bulk - → ∞ or - ≫ 2, , - = .,
Vg < O - Ø At - → 0,
./ (123) ./(
- -
, - = 0 = ., % = ., % > ., 56 56
accumu late
Hole accumulation at the Si/SiO2 interface
majority
n Capacitance: P
Choles) !" ($)
-
Ø 4788 = ∫ %., % &' 6- (unit: Coulomn/area)
9)**
-O : CoV Ø 7&' = − and !&' = 7&' 8&' =
.

:+,

=
9)** 9)**
−
- 8
:+, &'
=−
0
;+,
= Cox

since 7&' = 9:;<8 due to NO charges in oxide

(9)**<9-. )
Ø General form: !&' = − ;+,

195 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Accumulation
I

I
I

P& P bulk
Vg >O
surface

# n Accumulation is like a capacitor by applying

negative voltage on metal to induce positive
holes in semiconductor
eB
Debye n In semiconductors, 4 kinds of charges:
-
+

Length Ø Mobile: electrons and holes

t
W
-

Ø Immobile: ionized acceptor and donors

Ø In p-Si, holes and acceptors (negative)
present, so only holes attracted by
negative gate voltage

196 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Vg # EY Veh Depletion Majority Carrier,

n Important parameters:
Ø B(=) is defined as the potential
change in Si, which is a function of
x
Ø %B! = 7* − 7! in deep bulk Si

n Based on Gauss’ Law

Carriers (mobile) Impurity

(immobile)
6= ( 67 >
6= =
= −
6=
= −
?)* &
, = − ; = + .>
<
= −
&
.7
-
(=) D

Ø In p-Si bulk substrate of uniform doping (x → ∞) and charge #

neutrality condition
.>< = − .7- (=) = −.7- (=)
O
jo
, = − ; = + .>< = − .7- (=) ≡ 0
; =
*
, = − ; = − .7- = ≡ 0 → −.7- = = −, = + ; = = −,3 +
,3
(

197 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Depletion
Bulk

Ef Ei -
I
6 ? = 6+ ? − 6+ ? → ∞ 6- ? = 68 ? − 6+ ? → ∞
qPB
9[;'<;" ) ] 9[;(<; ) ] 9;( <9; )
@ ? = A+ ! >? = A+ ! >? = A+ ! >? ! >? O

<9; ) <9; )
= @@! >? = 0' ! >? Bulk
9[;" ) <;'] 9[; ) <;(] <9;( 9; )
A ? = A+ ! >? = A+ ! >? = A+ ! >? ! >?
9; ) A+A 9; ) A+A 9; )
= A@! >? = ! >? = ! >?
@@ 0'
no

Ø Substitute the above equations of p(x) and n(x) into the

equation based on Gauss’ Law
W v
6= ( 67 >
= =− =− , = − ; = + .>< = − .7- (=) d
6= 6= ?)*
> -?@ ' ;*= ?@ ' ;*=
=− . % 56 − % 56 − .7 +
?)* 7 .7 .7
=
> -?@ ' ;* ?@ '
=− .7 % 56 − 1 − % 56 − 1
?)* .7

198 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

I
 Depletion ↓
(dxS BA6
B? A
=−
< <9; )
0 ! >? − 1 −
2*+ '
5;
A+A 9; )
0'
! >? − 1 #dy

·
Ø Multiply on both sides and integrate from
5)
5;
the bulk (ψ = 0 and
5)
= 0) to the surface, I PB
we have
01
02 "# "# ' 1 671 ,4: 71
! " = − ! )5 * 89 − 1 − * 89 − 1 "#
/ "$ "$ (34 / )5

B6 A
2DE0' <9; <6 A+A 9; <6
v
- |'|A = = ! >? + − 1 + A ! >? − −1
B? 2*+ DE 0' DE
Ø At x = 0 (surface), ψ= ψs and ' = Es. The total charge density (in 2D) is
(
<9; <6 A+A 9; <6
/ ? = 0 = /%&%'( = 2*+ '" = − 22*+ DE0' ! >? + − 1 + A ! >? − −1
DE 0' DE
ü 2 exponential terms: accumulation (negative biased for p-Si case) and
inversion (positive biased for p-Si case)
9; VCO = RES/hole
ü Depletion term: V > 0 = b23)e-
>? accumulation
ü Equilibrium dopant term: 1
199 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 PB Depletion
inversion n Accumulation (ψs < 0): D
Ø 1st and 5th terms
Ø Since Na >> ni, 4th ~ 6th can be ignored
D Ø 1st term >> 2nd and 3rd terms
* n Depletion (ψs > 0 and Ef still below Ei):
Ø 2nd and 4th terms &
Ø Since ψs > 0, 1st term becomes small.
Veh Ø At very small ψs, 5th term < 2nd term
② (due to Na >> ni), only 2nd term
dominate called weak inversion
⑳ n Inversion (ψs > 0 and Ef above Ei)
Ø As ψs increases, 2nd and 4th term
increases.
Ø With Ef slightly above Ei, the surface is
&
inverted, but Qtotal (inverted electron
concentration) << Na (p-type bulk
FB doping), i.e. weak inversion, still 2nd
term dominates. &
/01 +, /.4 01 +,
|")*)+, | = 2%-. &'(+ ) 23 + − 1 + 4 ) 23 − −1 Ø With ψs increases to make Qtotal =
&' (+ &' Na, strong inversion occurs and 4th
1 2 3 4 5 6 term dominates.
>? B5
Ø 6" ≡ 26- = 2 GA *
N

p surface 6 C"

200
= bulkn
Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li PBE * PB
>
Strong Inversion
 X = 0 = 4 4s=
Depletion
X = W= 4 =
0 no
bending
56
n Surface potential B.C.: 2(" > ( > ?
A
B6 2DE0' <9; <6 A+A 9; <6
= ! >? + − 1 + A ! >? − −1
B? 2*+ DE 0' DE

B6 2DE0' <9; <6 A+A 9; <6

=− ! >? + − 1 + A ! >? − −1
B? 2*+ DE 0' DE
Depletion
2DE0' <6 2<0' 6
=− =−
2*+ DE 2*+
A
; )
B6 2<0' <0'
H = −H B? → 6 = 6" 1 − ?
;6 6 @ 2*+ 22*+ 6"
? A ? A
→ 6 = 6" 1 − = 6" 1−
22*+ 6" 1
<0'
n Depletion
charges:
22*+ 6"
/567 = −<0' 1 = −<0' = − IJDE KLFM2
<0'
201 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Depletion
Depletion
n In depletion region, 7A is away from 7! ,
W
leading to hole depletion, but , > ; if 7! −
7A < 7; − 7!
n Thus, positive charges at Metals (electrons,

I
mobile) and negative charges at
Semiconductor (ionized acceptors, immobile)

- (4>.D < 0)
4+BC 4>.D %.7 2 2?)* >.7 !)*
!&' = − =− = =
F&' F&' F&' F&'
We EVsi
eNa ⟹ !)* =
%.7 2 =
=> Vsix Vox
2?)*
Wasi
!( − !!" = !&' + !)* W2 Usi
(X)
⟹ !( = !!" + !&' +
-
!)*T
%.7 2 %.7 2 = solve W
= !!" + +
F&' 2?)*
202 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Inversion
P < Na P = Na

n> P
n Inversion ≡ at Si/SiO2 interface, 7! ≥ 7* or
to be precisely:
E ('23)-E; E -E< ('→G)
- * 56 - ; 56
; ≥ , ⟹ .8 % ≥ .A %

n In this case, the material becomes more

like a “n-type” by electrons instead of
acceptors for charge balance

n Strong inversion ≡ at Si/SiO2 interface,

;+ = ; = = 0 = ,(= → ∞) bulk
HI .7
,

(+ ≡ 2(" = 2 J;
% ;*
.
2?)* (+ 4?)* (" 4?)* HIJ; ;7
*
2H7' = = =
>.7 >.7 > = .7

Na >
-

4B + ↓s >
-
Wmax
203 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Inversion
n Inverted electrons:
Ø Reside in the channel with a distance
to the surface within 5 nm. With a
higher surface potential (by increasing
W Vg), the electrons are even closer to
the surface.
Ø It is actually a 2D electrons and by
considering quantum mechanics, the
&
inversion
peak of electron density is 1 ~ 2 nm
↑ away from the surface.
E
Depletion
- B6 2DE0' <9; <6 A+A 9; <6
=− ! >? + − 1 + A ! >? − −1
Depletion B? 2*+ DE 0' DE
charge inversion
2DE0' <6 A+A 9;
=− + ! >?
2*+ DE 0'A
dominant Numerically solving ((=)
From oxide To Si A+A 9; )H@ A+A 9;6
A ?=0 = ! >? = ! >?
0' 0'
: Decay A+A 9;6
/+CG = − 22*+ DE ! >? = − IJDE NOP(Q)
204 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li 0'
 Inversion Cox
Vgxo n Electrons close to Si/SiO2 interface, where

↓ are they from? In p-Si, majority carriers are

holes, how can so much electrons appear?

↓ n As strong inversion (!" ≡ 2!- )

Co Ø more positive $, will induce electrons at the

surface since % & = 0 =
B5
C"7
)
89 $:;
<=
No
Ø So ∆$, will NOT drop across semiconductor
for $*+ , but on $&) only on surface
Ø acceptors are “screened” by those inverted
#B = Deplete
+
electrons, so +(= +!') ) if with more ∆$,
inversion Ø C for acceptors = I#$ I>?@
-(Udep + Qinv)
I#$ JI>?@ Vox =

Cox
t Ø C for electrons = .&)
COXT -inv Vg
=

Ø /+CG !" ≡ 2!- = −.&) $, − $%

↓ ⟹ $, = $$- + $&) + $*+ = $$- + $&) + 2!-

a = $$- + 2!- −
/>?@ J/"AB
I#$
= $% −
Vg-Vt
/"AB
I#$
/>?@
⟹ $% = $$- + 2!- −
-

I#$
(/567 < 0) Define
205 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li Usi Vox -
 Inversion ③

#I

*
strong in version I = R
7 = −M!
2 =R

-
2x(-e)
(F /))
7 = −%!

F /III Eox Esi

I solve

Pover
Cox = Esi
.

67 L
EF =
6= ?+
· GA

N
E 39
=
.

-
#
·
E =
QA

13 F
206 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Vg-VFB =
Usi +Vox

D Edepletion TE F deplete ,

# inversion * *T EH
As = Di + &d I total
Ef Ei =

& Vg47lK . 4 = 243 =

&
surface P bending
②

.
&

-
ex
inversion
Us = PB = Na -
CTT 24B

20B =
strong inversion -mD A
&
207 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Threshold Voltage
Vg > O

n Threshold voltage (Vth) is defined as the gate voltage which

can induce strong inversion: Vox -Odep EsqNaVsi 2

Vg VFB O O = =
=

!( − !!" = !&' + !)* = (+ COX

Cox
9=!> =:-. ?I)J-.
General form → !( − !!" = − ;+,
+ !)* =
;+,
+ !)* P .
20
=:-. ?I)=@?
→ !( − !!" = + 2(" Vsi =
24B
;+,
MN@A OPB MQC
→ !( = "KL = "$% + RDE
+ OP%

208 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Threshold Voltage
OQST RSU OP%
VFB !( = "KL = "$% + + OP%

-
TVW
↓ Vox
Usi

Pm Os-

-Si

C
interface
charge

·
*
-)
E
I

&

209 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Threshold Voltage: Channel Potential
Inversion Depletion
↑
+ + f D
&
- --

deplete e

&

e(Vc-VB)

n For real MOS applications such as MOSFET, there exists pn

junction such as p (sub)/n (drain or source). Usually, the drain
and substrate may not be grounded (i.e. certain bias in between),
leading to non-equilibrium.

210 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 Threshold Voltage: Channel Potential
channel bulk
n VSi: !)* = 2(" + (!8 − !" )

n Vox: Usi
4>.D 2?)* >.7 (2(" + !8 − !" )
!&' = =
F&' F&'

n Vth:
↑ ExtL
!( − !" ;:U ≠ 0 − !!" = !)* + !&'
u

2?)* >.7 (2(" + !8 − !" )

→ !( − !" − !!" = 2(" + !8 − !" +
F&'
VB EE = F
OQST RSU (OP% + "Z − "% )
→ !( = !XY = "$% + OP% + "Z +
TVW

n Qinv: = −F&' (!( − !XY ) E

Vox
211 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li bending
 C-V Measurements
Basic Derivation Stimulus Capacitance Equation
Equation
Capacitance is
Step Voltage calculated from the
dQ ì0 (t < 0 ) ΔQ measured charge
=C V =í C =
dV îΔV (t ³ 0 ) ΔV and amplitude of
applied step voltage.

Q = CV Capacitance is

&
Ramp Voltage calculated from
dQ dV I I
= I =C V = At C = = the measured
dV A
dt dt dt current and ramp
Quasi-static ↑ rate of applied
ramp voltage.
exp
-

Ec Capacitance is
AC Voltage impedence jwG calculated from the
measured impedance
1 -j æ 1 ö 1
C= = = - Imç ÷=- and frequency of
j wZ wZ è wZ ø w Im(Z ) applied AC signal.

Most widely-used method I

by
capacitance meter Ac signal
212 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 C-V Characteristics
(inversions
Total C
C Cox frequency
.

=
low
&
Is 0 283 Ps
↓
=
=

Cox ↑ = deplete
+ inversion-

: already
C
inversion

Wmax
if Vg < 0
, O

this
hole"45p 44 ,

Esit . Csit =

frequency
si

=> Ctotal &

20B n
Cox

! ! ! ()23 (depletion)
= + %&' "23 =
"-.-/0 ".1 "23 (*4
Ci :
Cox Wmax
Cox P Csi
Cdmin = Csi P
213 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Charges vs. Voltages
< O Q colomb
/
:

-Q = C .
OV area

(t) Cox ( > -

Fl

Cox

& 7
& &

strong inversion

de Vgs
③ ↓ -

Oxide

e -

Cox

DQ = C -
OV

↓ + (+ 3
214 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li c -) (-)
 D Accumulation C-V
-?@(
W4)* W 2?)* HI.7 % 56
F)* = =
W(+ W(+
Osi
-?@ −>
= 2?)* HI.7 % 56 | |
2HI
Vox
> >
= 4)* = F&' (!( − !!" − (+ )
2HI 2HI
& Why ? L *B, we sion
in .
Osi =
Cox Vox
·

1 1 1
= +
FX&X7[ F&' &F)*
1 1
= +
F&' F&' (!( − !!" − (+ ) >
&

·
2HI
1 2HI
= 1+
F&' >(!( − !!" − (+ )

e"dB ~ Cox ,
as
VgO
215 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Flat-Band Capacitance
Ci
n From slide #288, the charge can be approximated at flat-band
56
( K ≪ 1):
78 <9;6 <6" A+A 9;6 <6"
|/*+,%&%'( | = 22*+ DE0' ! >? +
DE
− 1 + A ! >? −
0' DE
−1 ↓ P-ts
A
too small
<6"
≈ 22*+ DE0'
///1−
<6"
DE
+ DE
2
+
<6"
DE
−1 = 6"
2*+ 0' < A
DE
= 6" ;"+

Ps & VFB
↑
Taylor Expansion ,

n Total capacitance Ctotal:

1 1 1 1 1
= + = + ③

FX&X7[ F&' F)* F&' ?)* .7 > =

HI
?)* HI
1 .7 > = 1 Y>.C\.
= + = +
F&' ?)* F&' ?)*

216 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

 &
Depletion C-V &
4 VFB
=
=> No depletion region
Ps 43
=
= surface Us =
Ps
LYs 24B
=
= Surfas US =
bulk P
O

n -9 is zero at .:; and close to

when at 201 zero in accumulation
= Vz n No depletion in accumulation
X since majority holes are
attracted, but NOT depleted

O
n -9 increases from 0 to 2-; as
.< increases from .:;
V n As -9 reaches 2-; , surface is
Wamax & 4s
2920B= strongly “inverted” to electron
qNa populated from majority holes
4s 201
=
n .< at that point is threshold volt.
Was .=
n -9 does not increase much
further beyond 2-;
n 0 ∝ -9 in depletion
n 0 → 0>?@ at .< ≥ .= (just like
as -9 → 2-; )
217 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Depletion C-V
n From slide #291:
Vox
4>.D
!( − !!" = + !)*
F&'
2?)* >.7 (+
= + (+
F&'
and

-F)* =
W4>.D
W(+
=
2?)* >.7
(+
-

1 1 1 TVW Cox Csi

= + → FX&X7[ =
FX&X7[ F&' F)*
OTMVW ("# − "$% ) Cox + Csi
Z+
* Metal = OK ** QST RSU

Ø Total capacitance Ctotal decreases due to reduced CSi until

inversion formed, leading to the screening of the depleted
charged and bouncing-back total capacitance, i.e. Ctotal is large
because inversion layer formed.
218 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Inversion C-V
carriers EGY =
n Three possible measured CV
GCox L
curves for inversion
Ø Low-Frequency (LF)

e
Ø High-Frequency (HF)
Ø Deep-Depletion (DD)
·
VT

20B

n Low-Frequency: HF
Ø Inverted charges are Majority
minority carriers, so it (EN))
takes time for them to be DD
collected X
P sub + NMOs
D Ø If the measurement is under LF, the carriers can grasp the speed
and be populated, leading to increased capacitance.
Ø However, as the channel is inverted, there are still some charged
depleted at the same time, the effective capacitance is still low.
Ø Until the strong inversion occurs, most carriers are populated at the
surface to make the effective Si capacitance as infinity (thickness is
so thin ~ 1 nm), thus the effective C is Cox.
219 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li Cmin-
> Wamax-
>
 &
Inversion C-V: HF
hole frequency E F = IthE
DC AL (V)
.
n High-Frequency:
Ø Even with a DC bias which
creates the inverted
MF charges at the surface, if
AC signal is too fast, the
DC(V) AC(X) inversion layer cantcatch
.

the speed, so the effective

capacitance stays constant.
Ø Where are the increased
DC(X) charges going? They are
going to the depletion edge.

Ø The effective capacitance .7

is 1 1 1 8&' 2H7' 8&' 4HIJ; ;* Cin
= + = + = +
FX&X7[ F&' F)* ?&' ?)* ?&' ?)* > = .7
1 is =
201 =

2In
T

FX&X7[ =

asi4s
.7
4HIJ; Wmax
8&' ;*
-

+ q Na
?&' ?)* > = .7
220 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 ③
Inversion C-V: Deep Depletion (DD)
n Deep Depletion:
Ø If DC bias changed too fast, the
inversion layer cannot be
formed anyway.
Ø Thus, with Vg still applied
(increased), more negative
charges must be induced by
depleting the p-Si substrate
further, which is called deep
depletion.
. I hole
↑ sub (majority) >
-

e(minority deplete .

Ø Since Wd (depletion width) can be increased without pinning at Wmax by

forming inversion layer, the effective (total) Ctotal can be reduced further
since CSi is decreasing with Vg.

T
7

1 1 1 5A@ 0E 1
= + = + → 4=A=?B =
4=A=?B 4A@ 4CD 6A@ 6CD 5A@ 0E
~ +
6A@ 6CD

221 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li WY - Csit = Ototal ↑
 Inversion C-V strong E = -hole
pairs

e
LE
-
X

ht
:.
Tat7 * 7
HE
Tr
=> .
C

DD

n What is (b)?
As AC frequency is between HF and LF, the inversion charges could catch
up the signals, leading to partial inversion layer formed, leading to Ctotal
between CLF and CHF
n Why (d) goes to (c)? WY => EX = avalaunch break down
Similar to pn junction, as Vg keep increasing, creating larger depletion E-field
and leading to impact ionization, beyond the scope of this course.
222 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Q
Effects of Cox
CV
=

(x) A F
Oxide b
-

Depletion Inversion

If
, CoxA- ,

KV .

~ Uth

& bandbending bEV

Depletion .
>
=
Cox thi CoxP Ctotal e ,

n For thinner oxide, the slope of 79 vs. Vg increases due to the

larger Cox, usually called better electrostatic control.
n For thinner oxide, Cox is larger, which will make the depletion
C dip deeper. Think resistor. If you have a larger resistor
parallel to the same small resistor, which one will be affected
stronger? K IE
DMK Ci
CONF * .

223 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li

=> EB
 Effects of Cox and Csi
Wit Csit Stotal +

n Doping level increases, the depletion width is reduced.

n For the same oxide thickness (Cox fixed), as the doping level
increases, CSi increases, leading to a higher Ctotal.

224
E coxtCoxtesi
Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
<to a e
 Defects in Oxide
n 4 Major types of defect charges: *
 Interface trapped charges (fixed) D

S
‚ Fixed oxide charges
ƒ Oxide trapped charges
(fixed)
(fixed)
&

D
„ Mobile ionic charges (mobile)
n The effects of interface trapped and fixed oxide
charges (1 and 2)
 Interacting with charges near Si surface (either
inverted charges or depleted charges), leading
to the distribution of charge and surface
potential
‚ Additional C (capacitance) induced due to the
resulting changes of trapped charge density with
the change of surface potential
ƒ Serve as recombination-generation centers or
V assisted band-to-band tunneling process,
leading to leakage current through oxide
n The effect of mobile ionic charges :
 Unstable operation due to the shift of Vt
Om
225 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Interface Charges
n Since Si lattice stops at the surface or
interface of SiO2/Si, there exists
localized states within bandgap, which
traps electrons or holes in these states.
n As the surface potential changes with
Vg, the distance of Fermi level relative
to the surface state changes so the
carrier occupancy varies, leading to an
extra capacitance component.

*n Via trapping, electron number can be reduced so the conduction current

is reduced.
n Via recombination or generation, a surface state can capture an electron
and a hole or emit an electron and a hole, both of which would generate
the current.
n Depends on the surface condition such as orientation. It can be reduced
by annealing in a hydrogen or forming (hydrogen + nitrogen) gas.
n Generally, Dit < 1011 cm-2 is requird because the density of inverted
surface charges (mobile) is on the order of 1011 ~ 1012 cm-2.
226 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Fixed and Mobile Charges
n Oxide fixed charges could change the threshold
voltage. Usually they are positively charged in SiO2.
This is mainly due to the excess Si atoms in SiO2
matrix, leading to net positive charges.
n Mobile charges:
1. Contributed from Na or K ions during
processing.
2. Na+ and K+ are very mobile and can be
moving from M side to S side in a MOS
structure particularly in elevated temperatures.
3. As Na+ or K+ is very close to the surface, it can repel holes and
attract electrons, which leads to a unwanted channel between
n+source/n+drain and current conduction.
4. Na+ and K+ could also behave as scattering sites to reduce the
carrier mobility. T
5. Care must (and can) be taken to reduce those ions such as
deionized (DI) water, developer without less Na+ and in a less metal
environment. Most of the developing solution contains NaOH. MF-
series developer (such as MF-319) means metal-free.
227 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li
 Band-to-Band Tunneling (BTBT)

&

228 Solid State Electronics (2023 Fall) by Prof. Jiun-Yun Li