Lecture 27 – High Speed Op Amps (6/25/14) Page 27-1

LECTURE 27 – HIGH SPEED OP AMPS

LECTURE ORGANIZATION
Outline
• Extending the GB of conventional op amps
• Cascade Amplifiers
- Voltage amplifiers
- Voltage amplifiers using current feedback
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 370-386

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-2

INCREASING THE GB OF OP AMPS

What is the Influence of GB on the Frequency Response?
The unity-gainbandwidth represents a limit in the trade-off between closed loop voltage
gain and the closed-loop -3dB frequency.
Example of a gain of -10 voltage amplifier:

What defines the GB?

We know that
gm
GB = C
where gm is the transconductance that converts the input voltage to current and C is the
capacitor that causes the dominant pole.
This relationship assumes that all higher-order poles are greater than GB.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-3

What is the Limit of GB? jw

jGB’
The following illustrates what happens
when the next higher pole is not greater Dominant jGB
High Order Pole
than GB: Poles
a
-wA GB

For a two-stage op amp, the poles and zeros are:

-gm1
1.) Dominant pole p1 =
Av(0)Cc 150504-01

-gm6
2.) Output pole p2 = C
L
-gm3
3.) Mirror pole p3 = C +C
gs3 gs4
and z3 = 2p3
-1
4.) Nulling pole p4 =
RzCI
-1
5.) Nulling zero z1 =
RzCc-(Cc/gm6)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-4

Higher-Order Poles
For reasonable phase margin, the smallest higher-order pole should be 2-3 times larger
than GB if all other higher-order poles are larger than 10GB.
Av(0) dB
Larger non- Smallest non- Dominant
dominant poles dominant pole pole

-10GB -GB
10GB
0dB
GB GB log10w
Av(0)
060709-01

If the higher-order poles are not greater than 10GB, then the distance from GB to the
smallest non-dominant pole should be increased for reasonable phase margin.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-5

Increasing the GB of a Two-Stage Op Amp

1.) Use the nulling zero to cancel the closest pole beyond the dominant pole.
2.) The maximum GB would be equal to the magnitude of the second closest pole
beyond the dominant pole.
3.) Adjust the dominant pole so that 2.2GB  (second closest pole beyond the dominant
pole)
Illustration which assumes that p2 is the next closest pole beyond the dominant pole:

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-6

Example 27-1 - Increasing the GB of the Op Amp Designed in Ex. 23-1

Use the two-stage op amp designed in Examples 23-1 and 23-2 and apply the above
approach to increase the gainbandwidth VDD = 2.5V
M3 M4 M6
as much as possible. Use the capacitor 15µm 15µm 85µm
0.5µm 0.5µm 0.5µm
values in the table shown along with Cox Cc =3pF
vout
= 6fF/µm2. 30µA M1
1.5µm 1.5µm
M2
Rz = 4.56kW CL =
-
0.5µm 0.5µm 95µA 10pF
Solution vin
+
1.) First find the values of p2, p3, and p4. 30µA
3µm 10µm
0.5µm 3µm 0.5µm
a.) From Ex. 23-2, we see that M8 M5 0.5µm M7
p2 = -95x106 rads/sec. 140709-01

b.) p3 was found in Ex. 23-1 as Type P-Channel N-Channel Units

CGSO 220 10-12 220  10-12 F/m
p3 = -1.25x109 rads/sec. (also CGDO 220  10-12 220  10-12 F/m
there is a zero at -2.5x109 CGBO 700  10-12 700  10-12 F/m
rads/sec.) CJ F/m2
560  10-6 770  10-6
CJSW 350  10-12 380  10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-7

Example 27-1 - Continued

(c.) To find p4, we must find CI which is the output capacitance of the first stage of the
op amp. CI consists of the following capacitors,
CI = Cbd2 + Cbd4 + Cgs6 + Cgd2 + Cgd4
For Cbd2 the width is 1.5µm  L1+L2+L3=3µm  AS/AD=4.5µm2 and PS/PD=9µm.
For Cbd4 the width is 15µm  L1+L2+L3=3µm  AS/AD=45µm2 and PS/PD=36µm.
From Table 3.2-1:
Cbd2 = (4.5µm2)(770x10-6F/m2) + (9µm)(380x10-12F/m) = 3.47fF+3.42fF ≈ 6.89fF
Cbd4 = (45µm2)(560x10-6F/m2) + (36µm)(350x10-12F/m) = 25.2fF+12.6F ≈ 37.8fF
Cgs6 in saturation is,
Cgs6=CGDO·W6+0.67(CoxW6L6)=(220x10-12)(85x10-6)+(0.67)(6x10-15)(42.5)
= 18.7fF + 255fF = 273.7fF
Cgd2 = 220x10-12x1.5µm = 0.33fF and Cgd4 = 220x10-12x15µm = 3.3fF
Therefore, CI = 6.9fF + 37.8fF + 273.7fF + 0.33fF + 3.3fF = 322fF. Although Cbd2 and
Cbd4 will be reduced with a reverse bias, let us use these values to provide a margin.
Thus let CI be 322fF.
In Ex. 23-2, Rz was 4.564k which gives p4 = - 0.680x109 rads/sec.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-8

Example 27-1 - Continued

Therefore, the roots are:
jw
p2 = -0.095G New GB
z3 = -2.5G p3 = -1.25G p4 = -0.68G
s x 109
-3 -2 -1
070503-01

When p2 is cancelled, the next smaller pole is p4 which will define the new GB. 2.)
Using the nulling zero, z1, to cancel p2, gives p4 as the next smallest pole.
For 60° phase margin GB = |p4|/2.2 if the next smallest pole is more than 10GB.
 GB = 0.680x109/2.2 = 0.309x109 rads/sec. or 49.2MHz.
This value of GB is designed from the relationship that GB = gm1/Cc. Assuming gm1 is
constant, then Cc = gm1/GB = (94.25x10-6)/(0.309x109) = 307fF. It might be useful to
increase gm1 in order to keep Cc above the surrounding parasitic capacitors (Cgd6 =
18.7fF). The success of this method assumes that there are no other roots with a
magnitude smaller than 10GB.
The result of this example is to increase the GB from 5MHz to 49MHz.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-9

Example 27-2 - Increasing the GB of the Folded Cascode

VDD
Use the folded-cascode op amp designed in
VPB1
Example 24-4 and apply the above approach to I4 I5
increase the gainbandwidth as much as possible. M4 M5
Assume that the drain/source areas are equal to
RA VPB2 RB
2µm times the width of the transistor and that all I1 I2
I6 I7
voltage dependent capacitors are at zero voltage. M6 M7
vOUT
+
M1 M2 VNB2
Solution vIN
- M8 M9 CL
The poles of the folded cascode op amp are: M3
VNB1 I3 M11
-1 M10
pA ≈ R C (the pole at the source of M6 )
A A 060628-04

-1
pB ≈ R C (the pole at the source of M7)
B B
-gm10 M6
p6 ≈ C (the pole at the drain of M6)
6 IT = gm8VT rds8 gm10
IT M8
-gm8rds8gm10 VT 1 M10
p8 ≈ (the pole at the source of M8) R8 = = +
C8 IT gm8rds8 gm10 VT
- 150708-01
-gm9
p9 ≈ C (the pole at the source of M9)
9
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-10

Example 27-2 - Continued

Let us evaluate each of these poles.
1.) For pA, the resistance RA is approximately equal to gm6 and CA is given as
CA = Cgs6 + Cbd1 + Cgd1 + Cbd4 + Cbs6 + Cgd4
From Ex. 24-4, gm6 = 774.6µS and capacitors giving CA are found as,
Cgs6 = (220x10-12·80x10-6) + (0.67)(80µm·0.5µm·6fF/µm2) = 177.6fF
Cbd1 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgd1 = (220x10-12·16.5x10-6) = 3.6fF
Cbd4 = Cbs6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
and
Cgd4 = (220x10-12)(80x10-6) = 17.6fF
Therefore,
CA = 177.6fF + 39.5fF + 3.6fF + 147fF + 17.6fF + 147fF = 0.532pF
Thus,
-774.6x10-6
pA = 0.532x10-12 = -1.456x109 rads/sec.
2.) For the pole, pB, the capacitance connected to this node is
CB = Cgd2 + Cbd2 + Cgs7 + Cgd5 + Cbd5 + Cbs7
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-11

Example 27-2 - Continued

The various capacitors above are found as
Cgd2 = (220x10-12·16.5x10-6) = 3.6fF
Cbd2 = (770x10-6)(16.5x10-6·2x10-6) + (380x10-12)(37x10-6) = 39.5fF
Cgs7 = (220x10-12·80x10-6) + (0.67)(80µm·0.5µm·6fF/µm2) = 177.6fF
Cgd5 = (220x10-12)(80x10-6) = 17.6fF
and
Cbd5 = Cbs7 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
The value of CB is the same as CA and gm6 is assumed to be the same as gm7 giving pB =
pA = -1.456x109 rads/sec.
3.) For the pole, p6, the capacitance connected to this node is
C6= Cbd6 + Cgd6 + Cgs10 + Cgs11+ Cbd8 + Cgd8
The various capacitors above are found as
Cbd6 = (560x10-6)(80x10-6·2x10-6) + (350x10-12)(2·82x10-6) = 147fF
Cgs10 = Cgs11 = (220x10-12·10x10-6) + (0.67)(10µm·0.5µm·6fF/µm2) = 22.2fF
Cbd8 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF
Cgd8 = (220x10-12)(10x10-6) = 2.2fF and Cgd6 = Cgd5 =17.6fF
Therefore, C6 = 147fF + 17.6fF + 22.2fF + 22.2fF + 2.2fF + 17.6fF = 0.229pF
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-12

Example 27-2 - Continued

From Ex. 24-4, gm10 = 600x10-6. Therefore, p6, can be expressed as M6
1
600x10-6 gm10
-p6 = -12 = 2.62x109 rads/sec.
0.229x10 M8

4.) Next, we consider the pole, p8. The capacitance connected to this node is M10
C8= Cbd10 + Cgd10 + Cgs8 + Cbs8 150504-02

These capacitors are given as,

Cbs8 = Cbd10 = (770x10-6)(10x10-6·2x10-6) + (380x10-12)(2·12x10-6) = 24.5fF
Cgs8 = (220x10-12·10x10-6) + (0.67)(10µm·0.5µm·6fF//µm2) = 22.2fF
and
Cgd10 = (220x10-12)(10x10-6) = 2.2fF
The capacitance C8 is equal to
C8 = 24.5fF + 2.2fF + 22.2fF + 24.5fF = 73.4FF
Using the values of Ex. 24-4 of 600µS, the pole p8 is found as,
-p8 = gm8rds8 gm10/C8 = -600µS·600µS·/4.5µS·73.4fF = -1090x109 rads/sec.
5.) The capacitance for the pole at p9 is identical with C8. Therefore, since gm9 is
600µS, the pole p9 is -p9 = 8.17x109 rads/sec.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-13

Example 27-2 - Continued

The poles are summarized below:
pA = -1.456x109 rads/sec pB = -1.456x109 rads/sec p6 = -2.62x109 rads/sec
p8 = -1090x109 rads/sec p9 = -8.17x109 rads/sec
jw
p8 = -1090G pA = pB New GB
p9 = -8.17G p6 = -2.62G = -1.456G = 0.2x109
-8 -7 -6 -5 -4 -3 -2 -1 s x 109
070503-02

The smallest of these poles is pA or pB. Since p6 is not much larger than pA or pB, we
will find the new GB by dividing pA or pB by 4 (which is a guess rather than 2.2) to get
364x106 rads/sec. Thus the new GB will be 364/2 or 58MHz.
Checking our guess gives a phase margin of,
PM = 90° - 2tan-1(0.364/1.456) - tan-1(0.364/2.62) = 54° which is okay
The magnitude of the dominant pole is given as
pdominant = GB/Avd(0) = 364x106/3,678 = 99,000 rads/sec.
The value of load capacitor that will give this pole is
CL = (pdominant·Rout)-1 = (99x103·7.44M)-1 = 1.36pF
Therefore, the new GB = 58MHz compared with the old GB = 10MHz.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-14

Elimination of Higher-Order Poles

Principle - minimize the number of nodes in the amplifier.
The minimum circuitry for a cascode op amp is shown below:
VDD

vin + VPB1
M4 Non-
dominant
VPB2 M3 Pole
vout
Dominant Pole
VNB2 M2 CL

Non-
M1 dominant
vin + VNB1 Pole
060710-01

If the source-drain area between M1 and M2 and M3 and M4 can be minimized, the non-
dominant poles will be quite large.

CMOS Analog Circuit Design © P.E. Allen - 2016

 Lecture 27 – High Speed Op Amps (6/25/14) Page 27-15

Dynamically Biased, Push-Pull, Cascode Op Amp

Push-pull, cascode amplifier: M1-M2 and M3-M4
Bias circuitry: M5-M6-C2 and M7-M8-C1

Operation:
VDD VDD
+
VB2 VDD-VB2-(vin+-vin-)
M8 - M4

M7 + + M3
C1 VDD-VB2-vin+ VDD-VB2-vin+ C1
- vin- - vout
IB vin+
+ +
C2 vin+-VSS-VB1 vin+-VSS-VB1 C2
M6 - - M2

M5 + M1
VB1 VSS+VB1-(vin+-vin-)
-
VSS VSS
Equivalent circuit during the f1 clock period Equivalent circuit during the f2 clock period.
120523-07 120523-08

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-16

Dynamically Biased, Push-Pull, Cascode Op Amp - Continued

This circuit will operate on both clock phases† .

Performance (1.5µm CMOS):

• 1.6mW dissipation
• GB  130MHz (CL=2.2pF)
• Settling time of 10ns (CL=10pF)

This amplifier was used with a

28.6MHz clock to realize a 5th-order
switched capacitor filter having a
cutoff frequency of 3.5MHz.

† S. Masuda, et. al., “CMOS Sampled Differential Push-Pull Cascode Op Amp,” Proc. of 1984 International Symposium on Circuits and Systems,
Montreal, Canada, May 1984, pp. 1211-12-14.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-17

CASCADED AMPLIFIERS USING VOLTAGE AMPLIFIERS

Bandwidth of Cascaded Amplifiers
Cascading of low-gain, wide-bandwidth amplifiers:
Ao Ao Ao
s/w1+1 s/w1+1 s/w1+1
Vin Vout
A1 A2 An

Ao n
s/w1+1 060710-02

Overall gain is Aon

-3dB frequency is,
-3dB = 1 21/n-1
If Ao = 10, 1 = 300x106 rads/sec. and n = 3, then
Overall gain is 60dB and -3dB = 0.511 = 480x106 rads/sec.  76.5 MHz

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-18

Voltage Amplifier Suitable for Cascading

VDD
VPB1 VPB1
I5 I3 I4 I6
M5 M3 Vout M4 M6
M1 - + M2
+ I1 I2
Vin
-
VNB1 I7
M7
060710-03

Voltage Gain:
Vout gm1 Kn'(W1/L1)(I3+I5)
Vin = gm3 = Kp' (W3/L3)I3
gm3
-3dB ≈ C
gs1

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-19

Ex. 27-3 - Design of a Voltage Amplifier for Cascading

Design the previous voltage amplifier for a gain of Ao = 10 and a power dissipation of no
more than 1mW. The design should permit Ao to be well defined. What is the -3dB for
this amplifier and what would be the -3dB for a cascade of three identical amplifiers?
Solution VDD
To enhance the accuracy of the gain, we replace M3 VPB1 VPB1
I5 I3 I4 I6
and M4 with NMOS transistors to avoid the M5 M3 M4 M6
Vout
variation of the transconductance parameter. This M1 - + M2
assumes a p-well technology to avoid bulk effects. + I1 I2
Vin
The gain of 10 requires, -
W1 W3 VNB1 I7
M7
L1 (I3+I5) = 100 L3 I3 060711-01

If VDD = 2.5V, then 2(I3+I5)·2.5V = 1000µW.

Therefore, I3+I5 = 200µA. Let I3 = 20µA and W1/L1 = 10W3/L3.
Choose W1/L1 = 5µm/0.5µm which gives W3/L3 = 0.5µm/0.5µm. M5 and M6 are
designed to give I5 = 180µA and M7 is designed to give I7 = 400µA.
The dominant pole is gm3/Cout.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-20

Ex. 27-3 – Continued

Cout = Cgs3+Cbs3+Cbd1+Cbd5+Cgd1+Cgd5+Cgs1(next stage) ≈ Cgs3 + Cgs1
Using Cox = 60.6x10-4 F/m2, we get,
Cout ≈ (2.5+2.5)x10-12 m2x 60.6x10-4 F/m2 = 30.3fF  Cout ≈ 30fF
gm3 = 2·120·1·20 µS = 69.3µS
 Dominant pole ≈ 69.3µS/30fF = 23.1x108 rads/sec. f-3dB = 368MHz
The bandwidth of three identical cascaded amplifiers giving a low-frequency gain of
60dB would have a f-3dB of
f-3dB(Overall) = f-3dB 21/3-1 = 368 MHz (0.5098) = 187 MHz.
Pdiss = 3mW dB
3 cascaded stages
60
2 cascaded stages -60dB/dec.
40
Single stage -40dB/dec.
20
187MHz -20dB/dec.
0 log10(f)
368MHz 060711-02
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-21

CASCADED AMPLIFIERS USING CURRENT FEEDBACK AMPLIFIERS

Advantages of Using Current Feedback
Why current feedback?
• Higher GB
• Less voltage swing  more dynamic range
What is a current amplifier?

Requirements:
io = Ai(i1-i2)
Ri1 = Ri2 = 0
Ro = 
Ideal source and load requirements:
Rsource = 
RLoad = 0

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-22

Bandwidth Advantage of a Current Feedback Amplifier

Consider the inverting voltage amplifier
shown using a current amplifier with negative
current feedback:
The output current, io, of the current
amplifier can be written as
io = Ai(s)(i1-i2) = -Ai(s)(iin + io)
The closed-loop current gain, io/iin, can be found as
io -Ai(s)
iin = 1+Ai(s)
However, vout = ioR2 and vin = iinR1. Solving for the voltage gain, vout/vin gives
vout ioR2 -R2  Ai(s) 
  
vin = iinR1 =  R1  1+Ai(s)
Ao
If Ai(s) = , then
(s/A) + 1
vout -R2  Ao   A(1+Ao)  -R2Ao
=     Av(0) =
vin  R1  1+Ao s + A(1+Ao) R1(1+Ao)
and -3dB = A(1+Ao)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-23

Bandwidth Advantage of a Current Feedback Amplifier - Continued

The unity-gainbandwidth is,
R2 A o R2 R2
GB = |Av(0)| -3dB = R (1+A ) · A(1+Ao) = R Ao·A = R GBi
1 o 1 1
where GBi is the unity-gainbandwidth of the current amplifier.
Note that if GBi is constant, then increasing R2/R1 (the voltage gain) increases GB.
Illustration:

Note that GB2 > GB1 > GBi

The above illustration assumes that the GB of the voltage amplifier realizing the voltage
buffer is greater than the GB achieved from the above method.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-24

Current Feedback Amplifier

In a current mirror implementation of the current amplifier, it is difficult to make the
input resistance sufficiently small compared to R1.
This problem can be solved using a transconductance input stage shown in the following
block diagram:
RF

+
Vin GM
- Ai Vout
060711-04

Vout -GMRFAi
Vin = 1 +Ai

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-25

Differential Implementation of the Current Feedback Amplifier

VDD
VPB1

VPB2
Rin
Vin+ Vin-
M1 R Iin M2
F RF
+ Vout -
I nI nI
I
VNB2

nIin nIin
1:n 1:n
150504-03

gm1 Vin+- Vin- n (2RF)

Iin = 1+ 0.5g R   , Iin = (1+n)I, and Vout = 1+n Iin
m1 in  2 
Vout 2nRF
∴ V ≈ (1+n)R
in in
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 27 – High Speed Op Amps (6/25/14) Page 27-26

A 20dB Voltage Amplifier using a Current Amplifier

The following circuit is a programmable voltage amplifier with up to 20dB gain:
VDD

R1

vin+ vin-
M1 M2
R2 R2
+1 + vout - +1

VBias

x4 x2 x1 VSS x1 x2 x4
=1/8 = 1/4 =1/2 =1/2 = 1/4 =1/8
Fig. 7.2-135A
R1 and the current mirrors are used for gain variation while R2 is fixed.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-27

Frequency Response of a 60dB PGA

Includes output buffer:

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 27 – High Speed Op Amps (6/25/14) Page 27-28

SUMMARY
• Increasing the GB of an op amp requires that the magnitude of all non-dominant poles
are much greater than GB from the origin of the complex frequency plane
• The practical limit of GB for an op amp is approximately 5-10 times less than the
magnitude of the smallest non-dominant pole (≈ 100MHz)
• To achieve high values of GB it is necessary to eliminate the non-dominant poles
(which come from parasitics) or increase the magnitude of the non-dominant poles
• The best way to achieve high-bandwidth amplifiers is to cascade high-bandwidth
voltage amplifiers
• If the gain of the high-bandwidth voltage amplifiers is well defined, then it is not
necessary to use negative feedback around the amplifier
• Amplifiers with well-defined gains are achievable with a -3dB bandwidth of 100MHz

CMOS Analog Circuit Design © P.E. Allen - 2016