IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO.

12, DECEMBER 2013 3107

A Digital-Based Analog Differential Circuit

Paolo S. Crovetti, Member, IEEE

Abstract—A novel, digital-in-concept approach in the design

of analog differential circuits, suitable to very low voltage, ag-
gressively scaled, pure digital integrated circuit technologies, is
explored in this paper. A differential stage based on the proposed
technique is presented and its operation as a voltage comparator
and as an operational amplifier in negative feedback configura-
tions is discussed and demonstrated on the basis of theory and
simulations. The practical feasibility of the proposed approach is
finally verified by experiments carried out on a proof-of-concept
prototype.
Index Terms—Differential circuit, operational amplifier,
ultra-low voltage analog circuits, voltage comparator.

I. INTRODUCTION Fig. 1. A CMOS differential pair.

G EOMETRICAL and power supply scaling in recent

CMOS technologies have greatly improved the perfor-
mance of digital integrated circuits (ICs) over the last decades.
in applications. This last approach is particularly attractive
since it fully takes advantage of present day high-performance
digital technologies and of the computer-aided design (CAD)
Nonetheless, analog ICs have scarcely taken advantage of
and verification/test techniques that are commonly employed
CMOS technology enhancements and, on the contrary, reduced
in the digital field. Unfortunately, however, only a few analog
supply levels, short-channel effects, increased process vari-
functions have been re-thought in digital terms so far and
ability have made the integration of analog blocks in present
traditional analog implementations are the only options for fun-
day Systems-on-a-Chips (SoCs) more and more challenging
damental blocks like voltage comparators and opamp circuits.
[1], [2].
In this paper, a fully digital implementation of an analog dif-
The limitations of analog ICs fabricated in present day
ferential circuit is proposed. To this purpose, the function of a
digital processes have been primarily addressed in recent
standard analog differential circuit, like the CMOS differential
literature by novel ad hoc topologies and/or design techniques.
pair (DP) in Fig. 1, is considered and described in digital terms
In particular, standard CMOS operational amplifiers (opamps)
in Section II. In the same Section, a digital circuit with a sim-
[3] and voltage references [4] have been replaced by topolo-
ilar behavior is presented and an analytical model of the new
gies operating from very low power supply voltages [5]–[9],
structure is introduced in Section III. On the basis of this model,
current-mode techniques have been extensively employed
the operation of the proposed digital circuit as a voltage com-
[10] and analog circuits robust to noise and interference have
parator and as an opamp in negative feedback configurations
been developed to operate properly with a reduced voltage
is illustrated in Section IV and its performance is discussed in
swing [11]–[13]. Most of the proposed solutions, however,
Section V. Moreover, a CMOS implementation of the proposed
alleviate specific technology-related inconveniences at the cost
differential circuit is analyzed in Section VI by transistor-level
of increased design complexity and/or reduced performance.
simulations and then, in Section VII, a proof-of-concept pro-
An alternative approach to the challenges of present day
totype of the same circuit is tested by experiments. Finally, in
microelectronics is to re-think analog functions in digital terms
Section VIII, some concluding remarks are drawn.
so that they can be implemented by circuits and design method-
ologies which are as close as possible to the digital world. II. A DIGITAL-BASED DIFFERENTIAL CIRCUIT
Following this idea, analog-to-digital (A/D) converters, [14], A differential circuit or differential stage is an elec-
[15], phase-lock loops (PLLs) [16] and class-D amplifiers [17], tronic subsystem designed to provide an output signal that
whose operation can be (almost) completely described in digital is (possibly nonlinearly) related to the difference of two input
terms, have been proposed and are nowadays widely employed voltages and , i.e., to the differential mode (DM) input
voltage , and that is not influenced by the ab-
Manuscript received October 22, 2012; revised January 28, 2013 and Feb- solute value of the input voltages with respect to the reference
ruary 19, 2013; accepted March 05, 2013. Date of publication April 11, 2013; voltage (0V), i.e., which is insensitive to the common-mode
date of current version November 21, 2013. This paper was recommended by
Associate Editor J. B. da Silva. (CM) voltage .
The author is with the Department of Electronics and Telecommu- An analog differential circuit is typically implemented in
nications (DET), Politecnico di Torino, Torino I-10129, Italy (e-mail: CMOS technology as a DP including two identical source-cou-
paolo.crovetti@polito.it).
Color versions of one or more of the figures in this paper are available online
pled MOS transistors M1 and M2 biased in the saturation
at http://ieeexplore.ieee.org. region by a constant current source , as depicted in Fig. 1. In
Digital Object Identifier 10.1109/TCSI.2013.2255671 a CMOS DP, the voltage at the common-source node S, which

1549-8328 © 2013 IEEE

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 3108 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 12, DECEMBER 2013

If just the input configurations and

were possible, i.e., if the inputs can be
expressed as

(5)

with

(6)

one would have

(7)
Fig. 2. A pair of single-ended digital buffers as a digital differential stage (a)
and input/output characteristic of each digital buffer (b). (8)

ideally tracks the CM input voltage variations, is subtracted so that the output logical values would
from the input voltages and so that the gate-source be uniquely related to the (two-level quantized) DM input
voltages of M1 and M2 are not affected by the CM input. As a voltage regardless of the CM component, as expected in a
consequence, neglecting channel length modulation, the output (digital-output) differential circuit.
currents and are independent of the CM input voltage, as Unfortunately, the configurations and
expected in a differential circuit. are also possible. When these inputs are
A CMOS DP, however, is not well suited to present day dig- applied, the buffer outputs are and
ital CMOS technologies since it suffers of limitations in terms of , respectively, and are no longer
CM input range, minimum supply voltage, output signal swing, related to the DM input voltage . In such configurations,
which have been extensively discussed in the literature [5]–[8]. in fact, the input voltages can be expressed as in (5), with
The possibility of implementing a differential circuit exploiting and the dominant CM component
digital concepts is explored in this section to address the chal- makes the circuit in Fig. 2(a) insensitive to the DM component.
lenges of present day CMOS technologies. In these last two cases, however, the digital outputs provide
some information on the CM input voltage. Since
A. Two Digital Buffers as a Differential Circuit
(9)
The circuit in Fig. 2(a), which includes a pair of single-ended
non-inverting digital buffers, is first considered as a possible in fact, it follows that
fully digital implementation of a differential stage. Each buffer
provides a high digital output signal , i.e., an output (10)
voltage , when an input signal
is applied and a low digital output signal , i.e., and similarly, since
an output voltage , when , as
(11)
depicted in Fig. 2(b), and can be implemented in digital tech-
nology as the cascade connection of an even number of CMOS it follows that
inverters. The input terminals of the buffers in Fig. 2(a) are con-
nected to the external inputs and and their outputs are (12)
taken as the digital output of the differential
circuit. On the basis of (2), (4), (10) and (12), the information about
Depending on the input signals and , it can be observed the DM and CM input voltage provided by the four possible
that output of the circuit in Fig. 2(a) is related to the DM input configurations of the digital signals can be
voltage as in a differential circuit. In particular, since summarized as depicted in Fig. 3. Such information is exploited
in the following to transform the simple circuit in Fig. 2(a) into
(1) a digital-based differential circuit.

it follows that B. A Digital-Based Differential Circuit

The circuit in Fig. 2(a) operates like a differential stage only
(2)
when condition (6) is satisfied by the external inputs. Nonethe-
Similarly, since less, it can be transformed into a real differential circuit, pro-
vided that the CM input of the digital buffers is corrected in real
(3) time so that condition (6) is verified independently of the ex-
ternal CM input voltage.
it follows that To this purpose, the information about the CM input provided
by output configurations (10) and (12) can be exploited to gen-
(4) erate a CM compensation analog signal to be added to the

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 CROVETTI: DIGITAL-BASED ANALOG DIFFERENTIAL CIRCUIT 3109

Fig. 4. A digital-based differential circuit.

Fig. 3. Digital output configurations and implications on DM and CM input

signals.

external inputs and so that condition (6) is enforced by

negative feedback. Such a CM compensation method is analo-
gous in concept to the CM rejection mechanism of the standard
CMOS DP in Fig. 1, where the S common source node voltage,
which tracks the CM input, is subtracted from the external in-
puts and CM-independent gate-source voltages are applied to
the input devices.
The idea, that has been outlined above, is exploited in the
circuit in Fig. 4 where the compensation signal is added
to the external input signals and by a summing network
so that the actual input signals of the digital buffers and
can be expressed as
Fig. 5. Summing network implementation using a resistive network (a) and a
(13) quasi-floating gate network (b).

and their DM and CM components are related to external DM turned on so that to decrease up to enforce condition (6).
and CM components as For the (1,0) and the (0,1) configurations, both M1 and M2 are
off, no current is injected into , and the signal is
(14) kept constant1.
Thanks to negative feedback, the internal CM voltage in
In Fig. 4 a resistive summing network is included for the sake of Fig. 4 is therefore controlled to enforce (6) independently of the
simplicity, nonetheless such a function can be conveniently im- external CM voltage . When condition (6) is met, the buffer
plemented in CMOS technology by quasi-floating gate (QFG) output signals are not influenced by and the circuit operates
techniques [18], [19], as shown in Fig. 5, where the DC biasing as a differential stage. In this case, the CM control loop is open
resistor is obtained exploiting an MOS device oper- and is driven by the external input signals only. As soon
ating in the subthreshold region. as condition (6) is no longer verified, however, the CM control
The compensation signal can be obtained by a bang- loop is established again and condition (6) is re-enforced.
bang negative feedback control loop exploiting the information An output stage, including a three-state inverter M3–M4
from (10) and (12). To this purpose, the CM extractor block loaded by a capacitor and driven by the digital sig-
in Fig. 4, including a three-state inverter M1-M2 loaded by a nals completes the circuit of Fig. 4 to get
capacitor , is employed. a single-ended DM output analog signal from the digital
The operation of the CM extractor block can outputs . To this purpose, M3 is turned
be described as follows: when , i.e., on when so that to increase
when , the pull-up pMOS transistor the output voltage , whereas M4 is turned on when
M1 is turned on to inject a positive current into the capacitor so that to decrease . When
, so that to increase and consequently , which configurations (1,1) and (0,0) are applied, i.e., when the CM
is expressed in terms of by (14). The increase of control is active, both M3 and M4 are off and is kept
makes it closer to , thus reducing , constant.
up to enforce condition (6). Following the same principle, if 1To be precise, the capacitor is slowly discharged through the sum-
, the pull-down nMOS device M2 is ming circuit.

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 3110 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 12, DECEMBER 2013

In conclusion, the overall circuit in Fig. 4 can be regarded as

an operational transconductance amplifier (OTA), with analog
inputs , and analog output , whose operation is com-
pletely based on digital gates. Such a stage can be directly em-
ployed as a voltage comparator or, alternatively, as an opamp
circuit to be connected in negative feedback configurations. A
mathematical model of the proposed differential circuit and a
more detailed discussion on its operation are presented in the
following Sections III and IV.

III. DIGITAL-BASED DIFFERENTIAL CIRCUIT MODEL

In this Section, a mathematical model of the digital-based
differential circuit introduced in this paper is proposed to get
further insight into its operation.
To this purpose, the state variables and of the
circuit in Fig. 4 can be expressed in terms of the external inputs
by the following delay differential equations [20]:

(15)

where
Fig. 6. Differential stage in Fig. 4 employed as a voltage comparator with
threshold voltage (normalized units) simulated with reference to
the model (15): Input voltage , buffer output voltages and ,
CM compensation voltage and overall output waveforms.

Section on the basis of the mathematical model (15) by

Matlab simulations. For the sake of simplicity, the currents
in (15) are now assumed to
in which be equal and independent of , i.e., it is assumed
that .
Such a condition could be achieved in practice replacing the
three state inverters in Fig. 4 with a charge pump circuit similar
to those employed in fully digital PLLs [21]. Moreover, the
and with initial history
delays appearing in (15) are also assumed to be equal, i.e.,
and the threshold voltage of digital
gates is set to zero. The operation of a CMOS implementation
of the circuit without simplifying hypotheses will be addressed
in Sections VI and VII on the basis of transistor-level circuit
In the above expressions, and are related to the simulations and experimental results.
input voltages and by (13), and
( and ) are the drain currents of the pMOS and A. Digital-Based Voltage Comparator Operation
nMOS devices in the output (CM extractor) stage when they are The proposed digital-based differential circuit, employed as
turned on and depend, in general, on the output voltage a voltage comparator as depicted in Fig. 6, is first analyzed on
(on the compensation voltage ) and is the basis of the model in (15). To this purpose, a comparator
the 50% propagation delay from the input of the digital buffers threshold (normalized units) and a unitary peak
to the gate voltages of the transistors in the output (CM ex- amplitude sine wave input are considered. The waveforms
tractor) stage in Fig. 4. In such a model, it is assumed that all of the input , of the overall output , of the digital
the digital gates show an ideal threshold behavior and that their buffer outputs and of the CM compensation
dynamic performance can be completely described in terms of signal are reported in Fig. 6.
the delays and . Moreover, it is assumed that With reference to such a figure, both the and the
resistors in the summing network have a sufficiently high re- voltages are positive in the first time interval, as a consequence
sistance so that their loading effect can be neglected. is decreased in order to meet condition (6). Whenever
Based on the model (15), the operation of the proposed dif- (6) is met, the circuit operates as a differential stage and, being
ferential circuit as a voltage comparator and as an opamp is dis- decreases and saturates to zero. Since is
cussed in the next Section under some simplifying assumptions. varying, needs to be modified in real time to meet con-
dition (6), so the circuit oscillates between the differential cir-
IV. DIGITAL DIFFERENTIAL CIRCUIT OPERATION cuit mode and the CM compensation mode, as observed from
The operation of the differential circuit in Fig. 4 as a the waveform. After exceeds is increased
voltage comparator and as an opamp is described in this and saturates to one. On the other hand, when drops below

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 CROVETTI: DIGITAL-BASED ANALOG DIFFERENTIAL CIRCUIT 3111

Fig. 8. Detail of the waveforms presented in Fig. 7 with reference to the digital
opamp in Fig. 4 connected in the voltage follower configuration and
described by the model (15): (1) input voltage and output voltage
waveforms, (2) CM compensation voltage waveform, (3) and
waveforms, (4) and .
Fig. 7. Digital differential circuit in Fig. 4 employed as an opamp in a resistive
negative feedback configuration and simulated with reference to the model (15) forms on a magnified time scale, as reported in Fig. 8. In such a
for (i.e., for , voltage follower configuration): Input voltage scale, the time delay of the digital gates which is about
, output voltage , CM compensation voltage and input
differential voltage waveforms. with respect to the period of the input sine wave, has been con-
sidered as the time unit. The waveforms in Fig. 8 are discussed
is decreased and saturates to zero, as expected in an in the following: the case of constant external input (
analog voltage comparator. It can be observed that for in Fig. 8) is first considered, then, the response of the circuit to
condition (6) is always verified except at transitions, so the external input variations is analyzed ( in Fig. 8).
signal is almost constant. 1) Constant External Input: An external input constant
and equal to zero is applied up to in the simulation
B. Digital-Based Opamp Operation reported in Fig. 8. Under such conditions, so the
The operation of the proposed differential circuit as an opamp CM extractor block is active, the output stage is not enabled,
in resistive negative feedback configurations is now analyzed the system operates as a single-input limit cycle control system
with reference to the model (15): to this purpose, its output is and the and signals oscillate around zero.
connected to the inverting input by a voltage divider so that Such an oscillation can be analyzed with reference to the first
and an external input time interval highlighted in Fig. 8: as soon as
signal is applied as the opamp non-inverting input voltage (triggering event), in (15) should be equal to ,
, as depicted in Fig. 7. The internal signals and i.e., the CM extractor stage should be operated by negative
of the circuit in Fig. 4 are therefore expressed as feedback so that to increase and bring equal to
. In practice, however, the CM extractor stage is
operated only after a delay . Before the delay is elapsed,
(16) is decreased instead of being increased, so drops
down to . After the delay , the
(17) error starts being corrected and goes to zero after the next
time interval . When crosses the threshold, the inputs
Taking into account of (16) and (17), the model (15) has been trigger a reduction of . Since this reduc-
simulated considering an input sine-wave signal with unitary tion is performed only after a further delay , however, the
amplitude and frequency. The results of such simulations for error in reaches a positive peak
(voltage follower configuration) are shown in Fig. 7 and before being corrected. This behavior is repeated periodically
it can be observed that the output voltage closely tracks the input in time so that shows a triangular wave oscillation around
voltage, i.e., the (external) DM input voltage zero with a peak amplitude
is kept very close to zero, as expected in a negative feedback
circuit. Moreover, the CM compensation signal is prop- (18)
erly generated so that the overall internal CM input voltage
is kept close to the threshold voltage and with a period
independently of the external input, as expected from
the discussion in Section II. (19)
Further insight into the operation of the circuit in Fig. 4 can
be gained by analyzing the and waveforms, the 2) Effect of External Input Variations: The effect of external
waveform, the and waveforms, the and wave- input variations is now considered with reference to Fig. 8 for

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 3112 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 12, DECEMBER 2013

, i.e., when the external input signal starts increasing. impedances, CM rejection, power consumption, unity-gain fre-
Since the increase in gives rise to a nonzero DM input, quency, phase margin, slew rate) will be considered and the
crosses the zero threshold a time before so that potential effectiveness of the proposed circuit in scaled digital
and in the second time interval highlighted in Fig. 8. technologies will be highlighted.
For small variations of and taking into account of (14), the
time interval can be estimated on the basis of the slew rate A. Common-Mode Input Range, Output Swing and Minimum
of the CM extractor stage as Power Supply Voltage
The CM input range limitation of the proposed differential
(20) circuit arises from the limited swing of the CM extractor stage
in Fig. 4. The internal CM voltage of the circuit in Fig. 4,
where is the instant in which crosses the zero in fact, is kept (almost) equal to by the compensation signal
threshold. After a time from the zero crossing, the , i.e.
output buffer is operated so that to increase the output voltage
for a time interval given by (20) and the net increment (24)
of after can be therefore expressed as
If the swing ofthe compensation signal is
(21) , the condition expressed by (24) can
be achieved if the external CM input signal is limited so that

where . (25)
Since , the increment in (21)
corresponds to an overall reduction of Assuming , , ,
which are reasonable values for the circuit in Fig. 4, (25) gives

(22) (26)

which is proportional to , as expected in a linear negative i.e. the proposed differential circuit shows a rail-to-rail CM
feedback system. input range. Moreover, since the output voltage is pro-
On the basis of (22), the evolution of the differential voltage vided by a CMOS inverter, the proposed circuit also shows a
sampled over the instants2 at the end of rail-to-rail output voltage swing. Finally, being the novel stage
each phase in which condition (6) holds, can be described in the entirely based on digital gates, unlike low voltage differential
discrete time domain as circuits previously presented in the literature, it can be operated
at a power supply voltage as low as the minimum requested
(23) for the operation of digital gates. The features discussed so far
make the proposed circuit intrinsically well suited to very low
where the forcing term is voltage digital CMOS technologies.
related to the variations of the external input. Equation (23) can
be regarded as the state equation of a linear, discrete-time, non- B. Input Offset Voltage
uniformly sampled, negative feedback system, which is stable The performance of the proposed differential circuit in terms
for . Under such condition, converges to zero of DC offset can be related to mismatch in the threshold volt-
unless further variations of the external input are expe- ages and in the delays of the buffers in Fig. 4 With a reasoning
rienced and reacts to the external input changes that is analogous to the standard analog implementation [3], in
so that to enforce at discrete time instants , as ex- fact, it can be observed that a mismatch in the threshold volt-
pected in a negative-feedback opamp circuit. ages and of the input buffers gives rise to an input
Since the operation of the proposed stage as a differential cir- offset voltage . Similarly, taking
cuit has been illustrated above, its performance can be discussed into account of (21), a mismatch in the rising (falling) time de-
in terms of the same parameters which are commonly employed lays of the digital buffers gives rise
for analog differential stages [3]. This analysis is proposed in the to an input offset voltage , with
next Section. . As a consequence,
the overall input offset voltage can be estimated as
V. DIGITAL-BASED DIFFERENTIAL CIRCUIT PERFORMANCE
PARAMETERS (27)
In this section, the possibility to describe the performance of
The second term in (27) can be reduced either increasing the
the proposed digital differential circuit in terms of the same pa-
output capacitance or decreasing the output current.
rameters, which are employed for analog differential circuits, is
It is worth noting that mismatch in the input summing net-
addressed. In particular, the main static limitations (CM input
works does not affect the offset voltage of the proposed stage.
range, output voltage range, minimum supply voltage, input
The offset voltage, in fact, is defined considering the circuit
offset voltage) and its dynamic performance (input and output
in Fig. 4 with its external inverting and non-inverting inputs
2Instants are, in general, non-uniformly spaced in time. shorted together. Under this condition, no current flows through

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 CROVETTI: DIGITAL-BASED ANALOG DIFFERENTIAL CIRCUIT 3113

D. Power Consumption and Output Driving Capability

Fig. 9. Magnitude and phase of the differential amplification frequency-do-
main transfer function of the proposed digital differential circuit with
obtained from (29) (continuous line), evaluated on the basis of time-domain
simulations (crosses) and evaluated considering the integrative approximation
in (30) (dashed line).
The power consumption of the internal part of the circuit
in Fig. 4, excluding the drivers M1–M4, can be estimated4, like
in any CMOS digital circuit, as where is a
constant related to the number of gates and their switching ac-
tivity, is the switching frequency, related to the voltage
oscillation period in (19), is the average gate input capaci-
tance and is the power supply voltage. Since, for a fixed
, both and decrease with the technology feature size,
geometrical scaling is expected to have a beneficial impact on
the power consumption of the stage.
Moreover, the output driving capability of the stage is related
to the characteristics of the digital output stage and depends on
, the aspect ratios of transistors M3 and M4 in Fig. 4. Such an
output stage operates in class B and its performance in terms of
power efficiency are therefore rather good.

E. Frequency-Domain Analysis, Unity-Gain Frequency and

Phase Margin
The frequency-domain analysis of the proposed differential
circuit in negative feedback configurations can be rather com-
plex since it operates as a non-uniformly sampled discrete-time
system, where sampling instants considered in (23) de-
pend, in general, on the DM and CM input signals. With ref-
erence to Fig. 8, however, for small input signals, the duration
of the transition time can be neglected, the voltage can
be reasonably considered periodic with period
and it can be assumed that sampling instants occur in cor-
respondence of the zero-crossings of the waveform oscil-
lation. Under these hypotheses, the relation between
and can be approximated as
Fig. 10. Simulated input and output voltages for the proposed differential cir-
cuit employed as a voltage comparator circuit.
(28)

the resistors of the input summing network and the internal volt- where it is also assumed that the input is a piecewise con-
ages and are therefore both equal to regardless of stant function that varies only in correspondence of the sampling
their resistance values. instants , i.e., that is the sampled-and-held approxi-
mation of the actual differential voltage.
Taking the Fourier transform of (28), the differential amplifi-
C. Input/Output Impedances and CMRR cation of the proposed opamp can be estimated as
The open loop3 DM and CM input impedances and
of the proposed circuit are mainly related to its summing (29)
network and can be expressed as and
where for the resistive summing network in Fig. 5(a) and it can be approximated as an integrative transfer function
whereas for the QFG summing network in
Fig. 5(b). The open-loop output impedance of the stage is (30)
mainly related to the output capacitor .
Moreover, mismatch in the input summing network gives
rise to CM-to-DM conversion, which limits the performance in for . The magnitude and the phase of the transfer
terms of common-mode rejection of the stage. In particular, as- function in (29) for and of its integrative approximation
suming that mismatched impedances and ( and (30) are plotted versus frequency in Fig. 9 and are compared
) are employed in the voltage divider at the non-inverting with simulated values estimated from the Fast Fourier Trans-
(inverting) inputs, the Common-Mode Rejection Ratio (CMRR) form of time-domain waveforms obtained with reference to the
of the stage can be estimated as , where model in (15).
. On the basis of (29), the unity-loop gain frequency of the
proposed opamp in a resistive negative feedback configuration
3It should be remarked that the DM input impedance and the output
impedance of the stage in Fig. 4 are affected by negative feedback as in 4Cross-conduction power dissipation in the buffer input stages could be also
standard analog opamps. relevant since they are operated close to their threshold voltage.

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 3114 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 12, DECEMBER 2013

Fig. 11. Simulated input and output voltages of the digital opamp connected in the voltage follower configuration (a) and in the non-inverting voltage amplifier
configuration (b) with amplification .

with feedback factor , defined as the frequency
, can be calculated as
and is therefore directly related to the propagation delay
. Moreover, the corresponding phase margin can be
evaluated from (29) and (31) as
for which A. Voltage Comparator
The differential circuit in Fig. 4 has been first simulated in
a voltage comparator configuration, as depicted in the inset of
(31) Fig. 10. A sine wave input signal with a frequency of 20 kHz, an
amplitude of 500 mV and an offset of 2 V has been applied and
different threshold voltages of 2.25 V, 2 V and 1.75 V have been
considered. The waveforms of the simulated input and output
voltages are reported in Fig. 10, where it can be observed that the
output logical value changes in correspondence of the threshold
crossings of the input voltage.
(32)
B. Voltage Follower Opamp

From (32), if the stability condition arising from
(23) is met, the circuit shows a minimum phase margin of 60
for and for . As a consequence,
according to this analysis, the proposed opamp is intrinsically
stable in any resistive negative feedback configuration and does
not require frequency compensation. Moreover, from (31), its
performance in terms of bandwidth takes advantage of the re-
duced propagation delays of present-day digital technologies.
F. Slew Rate
The slew rate of the novel differential circuit
is mainly limited by the DM output slew rate appearing in
(15), so and is therefore related to the
maximum current that can be delivered by the output stage and
to the value of the output capacitance . by the DM input voltage, is sufficient to trigger the output cir-
VI. COMPUTER SIMULATIONS
While the basic principle of the novel differential circuit has
been illustrated in the previous Sections on the basis of a sim-
plified analytical model, the operation of an actual CMOS im-
plementation of such a circuit in a CMOS technology is now
discussed on the basis of Spice computer simulations. To this
purpose, the circuit in Fig. 4 has been simulated in different
configurations, i.e., as a voltage comparator, as an opamp in
the voltage follower configuration and as an opamp in a non-in-
verting voltage amplifier circuit. The simulated circuits are op-
erated from a 3.3 V supply and include a QFG summing network
as reported in Fig. 5 with capacitors.
As a second application example, the circuit in Fig. 4 has
been connected in the voltage follower configuration, as de-
picted in the inset of Fig. 11(a), and a sine wave input signal
with a frequency of 20 kHz and an amplitude of 1 V has been
applied. The simulated input and output voltages are reported in
Fig. 11(a). After the initial transient, it can be observed that the
output voltage tracks the input voltage as expected.
In analogy with Fig. 8, the main internal waveforms of the
simulated circuit are reported in Fig. 12. The operation of the
circuit is qualitatively similar to what expected on the basis of
the simplified model. Nonetheless, the slopes of the rising and
falling edges of the waveform, as well as the rising and
falling delays and , which were assumed equal in the
idealized model, are different in this simulation. Moreover, the
time shift between the and waveforms, which is induced
cuit in correspondence of the falling edges of the CM waveform
but is not sufficient to trigger it in correspondence of the rising
edges.
C. Non-Inverting Opamp Circuit
The digital differential circuit presented in this paper has been
finally employed in a non-inverting configuration with a DC
gain of two, as shown in the inset of Fig. 11(b). A sine wave
input signal with a frequency of 20 kHz and an amplitude of
500 mV has been applied and the simulated input and output
voltages are reported in Fig. 11(b). It can be observed (the initial
transient has been cut from the plot) that the circuit operates
properly also in this negative feedback configuration.

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 CROVETTI: DIGITAL-BASED ANALOG DIFFERENTIAL CIRCUIT
Fig. 12. Simulated waveforms for the digital opamp connected in the voltage
follower configuration.
Fig. 13. Proof-of-concept implementation of the digital-based differential cir-
cuit in Fig. 4 connected in the voltage follower configuration using off-theshelf
digital components.
VII. EXPERIMENTAL RESULTS
The feasibility and the effectiveness of a differential circuit
based on the technique introduced in this paper is now verified
on the basis of the results of experimental tests which have been
carried out on a proof-of-concept opamp prototype that has been
assembled on a breadboard using off-the-shelf components. The
prototype that has been considered for tests is first introduced
and then, experimental results are presented.
A. Proof-of-Concept Prototype
In order to validate the results discussed so far, a proof-of-
concept opamp circuit based on the digital differential stage in
Fig. 4 has been implemented using off-the-shelf components
and has been connected in the voltage follower configuration. In
such a prototype, whose block schematic is reported in Fig. 13,
CD74HC4050 digital buffers are employed in the input stage.
Moreover, both the CM extractor and the DM amplifier in Fig. 4
are implemented by three-state CMOS buffers CD74HC241.
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3115
Fig. 14. Photograph of the proof-of-concept prototype considered in experi-
ments.
The enable signal (EN) of the buffers is provided by a
XOR gate (CD74AC86E) whose inputs are connected to the
signals from the input buffers: when the XOR
gate output is high, the DM amplifier is enabled and drives the
output voltage depending on the logical value of ,
which is high for and low for . When the XOR
gate output is low, the output is in a high impedance state as in
the circuit of Fig. 4. Similarly, when the XOR gate output is
low, the CM extractor is enabled and drives depending
on the logical value of , which is high for
and low for . When the XOR gate output is high, the
CM extractor is disabled and its output is in a high impedance
state.
A photograph of the prototype, assembled on a breadboard
using off-the-shelf digital integrated circuits and passive com-
ponents, is reported in Fig. 14. The results of experiments car-
ried out on such a prototype are discussed in the following.
B. Test Results
The prototype opamp circuit described above, which operates
from a 5 V power supply, has been connected in the voltage fol-
lower configuration as depicted in Fig. 13(a) and has been tested
by applying a sine wave input signal with 2.5 V offset, a
rail-to-rail peak amplitude of 2.5 V and a frequency of 1 kHz.
The voltage follower input and output voltage waveforms have
been acquired by a digital sampling oscilloscope and are re-
ported in Fig. 15. In the same figure, the waveform of the
CM compensation voltage is also reported. From the first two
traces in Fig. 15, it can be observed that the circuit operates like
a rail-to-rail opamp as expected. Moreover, the third trace high-
lights how the CM extractor circuit provides a signal that
is inverted with respect to the external CM input (which is equal
to in a voltage follower). As a consequence, the internal CM
voltage is kept almost constant and equal to .
More details concerning the performance of the prototype are
reported in Table I. It can be observed that the performance
of the prototype are rather poor. Nonetheless, it should be re-
marked that such limitations can be related to the implementa-
tion of the circuit with off-the-shelf components, whereas better
performance could be expected for a fully integrated properly
designed circuit.
VIII. CONCLUSION
In this paper, an alternative, digital-in-concept, implementa-
tion of a differential stage has been presented and discussed on
the basis of theory and computer simulations. In particular, it has
 3116 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 12, DECEMBER 2013
Fig. 15. Experimental waveforms obtained from the circuit in Fig. 13: 1 kHz,
2.5 V sine wave input voltage (top trace), opamp output voltage
(middle trace), CM compensation signal (bottom trace).
TABLE I
DESIGN PARAMETERS AND MEASURED PERFORMANCE
been shown that such a circuit could be suitable to implement
voltage comparators, opamp circuits and all differential blocks
in present day very low voltage pure-digital IC technologies. A
proof-of-concept prototype of the proposed circuit has been also
assembled and its operation has been verified by experiments.
Much better performance is expected from a properly designed
monolithic implementation of the same circuit, which will be
considered in future work. Moreover, possible applications of
the proposed digital differential circuit in power electronics and
as an A/D converter will be also explored.
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Paolo S. Crovetti (S’00–M’03) was born in Torino,
Italy, in 1976. He received the Laurea (summa cum
laude) and Ph.D. degrees in electronic engineering
from the Politecnico di Torino, Torino, Italy, in 2000
and 2003, respectively.
Currently he is with the Microelectronics EMC
Group of the Department of Electronics and
Telecommunications (DET) of the Politecnico di
Torino, Italy, where he works as an Assistant Pro-
fessor of Electronics. His main research interests are
in the fields of analog integrated circuits, nonlinear
circuits, IC-level EMC. His recent research activities are focused on the
development of fully digital implementations of analog functions and on the
application of MIMO signal processing and RF techniques in the EMC field.
He is coauthor of more than 40 papers appearing in journals and international
conference proceedings.