Laboratory 4 - Capacitor Design Manual

Laboratory 3
Capacitor Design
Manual
Capacitor Design Manual Outline
• Part 1: MOS VARACTOR CAPACITOR

• Part 2: METAL into METAL CAPACITOR
• Part 3: FINGER-TYPE CAPACITOR
Resistor Design || MSU-IIT EECE 2

Layout Tips!
• Be familiar with the shortcut keys and minima Rule.
Practice a lot!
• Select Assist on the SmartDRD option. This will guide
you for the minimum rule.
• Always Check DRC even if you’re halfway your layout
process so you can check minor errors ahead. Refer
to DRC Verification Part of this manual for the DRC
settings.
• On this manual, refer to the property window for the
layer and size.
Add New Cell Category
Right Click.

Part 1: MOS VARACTOR
CAPACITOR
–Schematic
–Layout
–Verification

MOS VARACTOR CAPACITOR
SCHEMATIC

Add New Cell and View
Right Click.
Select.

Add Instance from Library
Click i

Choose MOS_VAR_B Cell from
tsmc18rf Library

Adjust the sizes of the Capacitor
Devices Click Q to view the
Property Window
Adjust segment length(L) and segment

width (W) to achieve desired capacitance.

Add PIN for Terminal A.
Make sure that the direction is

set into inputoutput

Add PIN for Terminal B.


Create the layout view in the same cell with the schematic and symbol.

DIFFUSION DRAWING
Schematic: Width = 10.03 µm Length = 7.72 µm
Layout: Diff Height = 10.03 µm Poly Width = 7.72 µm
Click R to create a rectangle. Adjust

Attributes according to the schematic
parameters.

POLY1 DRAWING
Layout: Diff Height = 10.03 µm Poly Width = 7.72 µm

parameters.

CONTACT DRAWING ON DIFFUSION
Add enough numbers of Contacts on the

Diffusion.

CONTACT DRAWING ON POLY
Add enough numbers of Contacts on the

Diffusion.

CONTACT DRAWING
Contacts on Diffusion and Poly

layers.

METAL1 DRAWING OVER POLY
Add Metal1 over the Poly

connecting the contacts on the
upper and lower portion of the Poly.

METAL1 ON DIFFUSION CONTACTS

MULTIPLE FINGERS
For Multiple Fingers, select the first

finger and copy (Click C) to create
another finger. Observe minima rule for
the distance. Extend the Diffusion Layer
by stretching (Click S).

METAL1 AND DIFFUSION CONTACTS
Copy and place Metal1 and

Contacts on the other end of
the Diffusion.

N+ IMPLANT LAYER
Add NIMP Layer. Observe Minima

Rule.

NWELL LAYER
Add NWELL Layer. Observe Minima

Rule.

NWELL AND NIMP
Stretch the NWELL and NIMP Layers to

cover the whole MOS Capacitor.

METAL1 LAYER
Add a wide Metal1 Layer on top.

Observe Minima Rule.

METAL1 LAYER
Add wide Metal1 Layer at bottMetal1

over the Polyom and connect the.
Observe Minima Rule.

METAL1 LAYER
Stretch the Metal1 from the top to the

Metal1 with Diffusion contacts. Observe
45 degrees on the intersection.

VARDUMMY DRAWING
Add VARDUMMY Drawing. Observe

Minima Rule.

PIN A
Make sure metal pin is the same with

the layer. Name is the same with the
schematic.

PIN B

schematic.

MOS VARACTOR CAPACITOR Layout
Perform Verifications:
(Refer to the Verification Part of the Manual)
DRC, LVS and LPE
Results example:
DRC RESULT
LVS and LPE RESULT
Parasitic Capacitance
Capacitance (Cg B A) = 2.33378 pF

DRC Verification
Add Runset file.

Path: /home/documents/TSMC_018um/hercules/drc
Then Click OK.
You must only this kind of error on the DRC Errors

Tab. This is just fine for this Laboratory.

LVS Verification
Go back to the terminal. Type gedit
empty.subckt & then Enter. It will
open a gedit window where you can
edit the file. Add the subckt name
for nwell with its ports.

LVS Setup P.1
Add Runset file.
Path:
/home/documents/TSMC_018um/hercules/lvs
On the Netlisting Option Tab, NetRan Option:

-cdl-a –cdl-p –mprop –sp
/home/accountname/empty.subckt

LVS Setup P.2
Select layer map.

Path: account/TSMC018UM/tsmc18rf/
Then RUN LVS.

LVS Result
This is verifies that the layout design matches the schematic design.
If not, debug the errors.

LPE Verification
Setup P.1
Select Runset file.

Path: /home/documents/TSMC_018um/hercules/starrc

LPE Setup P.2
Select MilkyWay XTR View. Go to the lvs folder from the
LVS verification.
Path: /home/account/TSMC018UM/Inverter/hercules_lvs
Select Mapping file.

LPE Setup P.3
Select GRD file.
Select Output Runset Path. Path: /home/account/TSMC018UM/EE270/Lab1_Inverter/

Create new Folder Output. create filename, output.spf then save and Run LPE.
LPE Result
Refer to the Custom Designer Console of This is verifies that the layout design has no errors
in terms of the parasitic extraction.
LPE output can be viewed on gedit. Go

back to xtart terminal window, type gedit
& then Click Enter. It will open a new
window of gedit. Click Open to open the
file: output.spf.

Part 2: Metal into Metal
Capacitor (MiM)
– Calculation
– Schematic
– Layout
– Verification

MiM CALCULATION

MiM CALCULATION
Assigned Capacitor = 2.35 pF
The Synopsys tool provides the capacitance of the

single segment once Width and Length are given.
Choose preferred width and length (where W=L).
Check the capacitance of single segment based on
the Property Window. Calculate for the number of
segments.
For PARALLEL connection: Preferably use this connection

#
= ( )
# of segments = must be perfect square i.e. 25, 36,

81, etc
In this design,
# of segments = 121 connected in parallel
Cs = 0.8745155 pF
Ctotal= 2.35 pF

Click i

Choose MIMCAP_M4 Cell from
tsmc18rf Library

Device Click Q to view the
Property Window
Adjust segment length(L) and segment

width (W) to achieve desired capacitance.

Multiples

Connect the terminals in parallel to
Terminal A.
Add Pin A. Make sure that the

direction is set into inputoutput

Connect the other terminals in parallel
to Terminal B.
Add Pin B. Make sure that the

direction is set into inputoutput



METAL4 DRAWING
Layout: Height = 28.74 µm Width = 28.74 µm

parameters.

CTM3 DRAWING

parameters.

METAL3 DRAWING

parameters.

CTMDUMMY DRAWING

parameters.
METAL3-METAL4 VIA
Fill in the metal with via34 . Balance the vias

(centered from either top or side)
Single Segment MiM

Multiple Segments
No minimum distance for each unit

capacitor. Just makes sure it doesn’t
overlap.

Multiple Segments
Duplicate to # of segments. For

this, 121 segments formed into
square.

METAL3 CONNECTION
Connect all metal 3.

METAL4 CONNECTION
Connect all metal 4.

PIN A

schematic.

PIN B

schematic.

MiM Capacitor Layout
DRC, LVS and LPE
Results example:
DRC RESULT
LPE RESULT
Capacitance (C2 B A) = 2.34781 pF

LVS Verification
• For this device, the only purpose why we
need to perform the LVS is in order for it to
generate the MILKWAY_OUTPUT folder
necessary during LPE, to get its capacitance.
This is because the device is not supported by
the present LVS runset.

LVS Setup P.1
Add Runset file.
Path:


LVS Setup P.2
Select layer map.

Then RUN LVS.

LPE Verification
Setup P.1
Select Runset file.


LPE Setup P.2
LVS verification.

LPE Setup P.3
Select GRD file.
Select Output Runset Path. Path:

/home/account/TSMC018UM/EE270/Lab1_Inverter/
Create new Folder Output. create filename, output.spf
then save and Run LPE.
LPE Result
LPE output can be viewed on gedit. Go

back to xtart terminal window, type gedit
& then Click Enter. It will open a new
window of gedit. Click Open to open the
file: output.spf.
IMPORTANT NOTE!
***Capacitance value is greatly affected
by the metal sizes used to connect the
segments. Make sure to use minima rule
as much as possible.
If the Capacitance Value needed is not
achieved on first try, adjust sizes of the
metal connections until such Capacitance
is obtained.
Part 3: FINGER-TYPE
CAPACITOR
–Schematic
–Layout
–Verification

• Create a schematic cellview and create a schematic circuit as shown. This is just
an ideal capacitor because the finger-type capacitor is not yet supported by the
0.18μm library.

Click i

Choose CAP Cell from tsmc18rf Library

Device
Simply add the capacitance of the device.

Add PIN for Terminal A.


Add PIN for Terminal B.


FINGER-TYPE CAPACITOR LAYOUT
*Layout of the Finger-Type Capacitor for this Laboratory utilizes Trial and Error... Set a
certain width and height for the metals. Stack up metal1 to metal 5, connected
through vias. Run LPE to check the Capacitance. Try to add more fingers until desired
capacitance is achieved.
METAL1 DRAWING

parameters.

METAL1-METAL2 VIA
Add via M1_M2

METAL2 DRAWING

parameters.

METAL5
Repeat adding via and then next

metal layer until metal layer 5.

METAL LAYER ON FINGER
Draw a Metal1 Layer representing a

finger of the capacitor.

FINGER FORMATION
Stretch all the metals to over lap with the

“finger”.

METAL5 LAYER ON “ODD” FINGER
Add Metal5 Layer with the same

size of the Metal1 Layer.

METAL3 LAYER ON “ODD” FINGER


“EVEN” FINGER
Form the “Even” Finger by copying

the metal layers 1-5 with vias.

METAL2 ON “EVEN” FINGER

METAL4 LAYER ON “EVEN” FINGER


“EVEN” FINGER

MULTIPLE FINGERS FORMATION
Copy the single even and odd

fingers to form multiple fingers
layers.

Just stretch the stacked metals 1-5 to the

end of the finger. At the top, there must
be a extension aligned to the last finger.

Just stretch the stacked metals 1-5 to the

end of the finger. Align the stacked metals
with the last Finger.

PIN A

schematic.

PIN B

schematic.

FINGER-TYPE
A partial layout of the Finger Type capacitor. It needs to be checked on LPE for the
capacitance value. Here comes the trial and error part. Check for LVS and LPE.
For the LPE, check the capacitance., if the desired value is not met, add or
subtract fingers. Then run again the LPE to check the capacitance.
Finger-Type Capacitor Layout
DRC, LVS and LPE
Results example:
DRC RESULT
LVS and LPE RESULT
Parasitic Capacitance
Capacitance (Cg B A) = 2.33378 pF

LVS Verification
• For this device, the only purpose why we
need to perform the LVS is in order for it to
generate the MILKWAY_OUTPUT folder
necessary during LPE, to get its capacitance.
This is because the device is not supported by
the present LVS runset.

LVS Setup P.1
Add Runset file.
Path:


LVS Setup P.2
Select layer map.

Then RUN LVS.

LVS Result
This is verifies that the layout design matches the schematic design.
If not, debug the errors.

LPE Verification
Setup P.1
Select Runset file.


LPE Setup P.2
LVS verification.

LPE Setup P.3
Select GRD file.
Select Output Runset Path. Path: /home/account/TSMC018UM/EE270/Lab1_Inverter/

Create new Folder Output. create filename, output.spf then save and Run LPE.
LPE Result
LPE output can be viewed on gedit. Go back to xtart

terminal window, type gedit & then Click Enter. It will
open a new window of gedit. Click Open to open the
file: output.spf.
Capacitance is not what is desired so try to add more

fingers to the design.
Then Run LVS and LPE, then check LPE output again.
LPE Result (Final)
The desired Capacitance is achieved.

Done!
Congratulations!

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Laboratory 3

• Part 1: MOS VARACTOR CAPACITOR

Resistor Design || MSU-IIT EECE 2

Resistor Design || MSU-IIT EECE 4

Resistor Design || MSU-IIT EECE 5

Resistor Design || MSU-IIT EECE 6

Resistor Design || MSU-IIT EECE 7

Resistor Design || MSU-IIT EECE 8

Resistor Design || MSU-IIT EECE 9

Adjust segment length(L) and segment

Resistor Design || MSU-IIT EECE 10

Make sure that the direction is

Resistor Design || MSU-IIT EECE 11

Make sure that the direction is

Resistor Design || MSU-IIT EECE 12

Resistor Design || MSU-IIT EECE 13

Click R to create a rectangle. Adjust

Resistor Design || MSU-IIT EECE 14

Click R to create a rectangle. Adjust

Resistor Design || MSU-IIT EECE 15

Add enough numbers of Contacts on the

Resistor Design || MSU-IIT EECE 16

Add enough numbers of Contacts on the

Resistor Design || MSU-IIT EECE 17

Contacts on Diffusion and Poly

Resistor Design || MSU-IIT EECE 18

Add Metal1 over the Poly

Resistor Design || MSU-IIT EECE 19

Resistor Design || MSU-IIT EECE 20

For Multiple Fingers, select the first

Resistor Design || MSU-IIT EECE 21

Copy and place Metal1 and

Resistor Design || MSU-IIT EECE 22

Add NIMP Layer. Observe Minima

Resistor Design || MSU-IIT EECE 23

Add NWELL Layer. Observe Minima

Resistor Design || MSU-IIT EECE 24

Stretch the NWELL and NIMP Layers to

Resistor Design || MSU-IIT EECE 25

Add a wide Metal1 Layer on top.

Resistor Design || MSU-IIT EECE 26

Add wide Metal1 Layer at bottMetal1

Resistor Design || MSU-IIT EECE 27

Stretch the Metal1 from the top to the

Resistor Design || MSU-IIT EECE 28

Add VARDUMMY Drawing. Observe

Resistor Design || MSU-IIT EECE 29

Make sure metal pin is the same with

Resistor Design || MSU-IIT EECE 30

Make sure metal pin is the same with

Resistor Design || MSU-IIT EECE 31

LVS and LPE RESULT

Resistor Design || MSU-IIT EECE 32

Add Runset file.

You must only this kind of error on the DRC Errors

Resistor Design || MSU-IIT EECE 33

Resistor Design || MSU-IIT EECE 34

On the Netlisting Option Tab, NetRan Option:

Resistor Design || MSU-IIT EECE 35

Select layer map.

Resistor Design || MSU-IIT EECE 36

Resistor Design || MSU-IIT EECE 37

Select Runset file.

Resistor Design || MSU-IIT EECE 38