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Z0103MN, Z0107MN, Z0109MN Sensitive Gate Triac Series: Silicon Bidirectional Thyristors
Z0103MN, Z0107MN, Z0109MN Sensitive Gate Triac Series: Silicon Bidirectional Thyristors
Z0109MN
Peak Non−repetitive Surge Current (One Full ITSM 8.0 A A = Assembly Location
Cycle Sine Wave, 60 Hz, TC = 25°C) Y = Year
W = Work Week
Circuit Fusing Considerations I2t 0.4 A2s 10XMN = Device Code
(Pulse Width = 8.3 ms) x = 3, 7, 9
Average Gate Power (TC = 80°C, t v 8.3 ms) PG(AV) 1.0 W G = Pb−Free Package
(Note: Microdot may be in either location)
Peak Gate Current (t v 20 ms, TJ = +125°C) IGM 1.0 A
Operating Junction Temperature Range TJ −40 to °C
+125
PIN ASSIGNMENT
Storage Temperature Range Tstg −40 to °C 1 Main Terminal 1
+150
2 Main Terminal 2
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended 3 Gate
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability. 4 Main Terminal 2
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
ORDERING INFORMATION
THERMAL CHARACTERISTICS
Device Package Shipping†
Characteristic Symbol Max Unit
Z0103MNT1G SOT−223 1000/Tape & Reel
Thermal Resistance, Junction−to−Ambient PCB RqJA 156 °C/W
Mounted per Figure 1 (Pb−Free)
Thermal Resistance, Junction−to−Tab Meas- RqJT 25 °C/W Z0107MNT1G SOT−223 1000/Tape & Reel
ured on MT2 Tab Adjacent to Epoxy (Pb−Free)
Maximum Device Temperature for TL 260 °C Z0109MNT1G SOT−223 1000/Tape & Reel
Soldering Purposes for 10 Secs Maximum (Pb−Free)
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted; Electricals apply in both directions)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Blocking Current TJ = 25°C IDRM, IRRM − − 5.0 mA
(VD = Rated VDRM, VRRM; Gate Open) TJ = +125°C − − 500 mA
ON CHARACTERISTICS
Peak On−State Voltage VTM − − 1.56 V
(ITM = "1.4 A Peak; Pulse Width v 2.0 ms, Duty Cycle v 2.0%)
Gate Trigger Current (Continuous dc) Z0103MN IGT mA
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+) 0.15 − 3.0
MT2(+), G(−) 0.15 − 3.0
MT2(−), G(−) 0.15 − 3.0
MT2(−), G(+) 0.25 − 5.0
Gate Trigger Current (Continuous dc) Z0107MN IGT mA
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+) 0.15 − 5.0
MT2(+), G(−) 0.15 − 5.0
MT2(−), G(−) 0.15 − 5.0
MT2(−), G(+) 0.25 − 7.0
Gate Trigger Current (Continuous dc) Z0109MN IGT mA
(VD = 12 Vdc, RL = 30 Ohms)
MT2(+), G(+) 0.15 − 10
MT2(+), G(−) 0.15 − 10
MT2(−), G(−) 0.15 − 10
MT2(−), G(+) 0.25 − 10
Latching Current (VD = 12 V, IG = 1.2 x IGT) Z0103MN IL mA
MT2(+), G(+) All Types − − 7.0
MT2(+), G(−) All Types − − 15
MT2(−), G(−) All Types − − 7.0
MT2(−), G(+) All Types − − 7.0
Latching Current (VD = 12 V, IG = 1.2 x IGT) Z0107MN IL mA
MT2(+), G(+) All Types − − 10
MT2(+), G(−) All Types − − 20
MT2(−), G(−) All Types − − 10
MT2(−), G(+) All Types − − 10
Latching Current (VD = 12 V, IG = 1.2 x IGT) Z0109MN IL mA
MT2(+), G(+) All Types − − 15
MT2(+), G(−) All Types − − 25
MT2(−), G(−) All Types − − 15
MT2(−), G(+) All Types − − 15
Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 30 Ohms) VGT − − 1.3 V
Gate Non−Trigger Voltage (VD = 12 V, RL = 30 Ohms, TJ = 125°C) VGD 0.2 − − V
All Four Quadrants
Holding Current (Z0103MA) IH − − 7.0 mA
(VD = 12 Vdc, Initiating Current = 50 mA, Gate Open) (Z0107MA, Z0109MA) − − 10
DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current di/dt(c) 1.6 − − A/ms
(VD = 400 V, ITM = 0.84 A, Commutating dv/dt = 1.5 V/ms, Gate Open,
TJ = 110°C, f = 250 Hz, with Snubber)
Critical Rate of Rise of Off−State Voltage (VD = 67% Rated VDRM, Exponential dv/dt V/ms
Waveform, Gate Open, TJ = 110°C) Z0103MN 10 30 −
Z0107MN 20 60 −
Z0109MN 50 75 −
Repetitive Critical Rate of Rise of On−State Current, TJ = 125°C di/dt − − 20 A/ms
Pulse Width = 20 ms, IPKmax = 15 A, diG/dt = 1 A/ms, f = 60 Hz
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Z0103MN, Z0107MN, Z0109MN
Quadrant 1
MainTerminal 2 +
Symbol Parameter VTM
VDRM Peak Repetitive Forward Off State Voltage
on state
IDRM Peak Forward Blocking Current IH
VRRM Peak Repetitive Reverse Off State Voltage IRRM at VRRM
IRRM Peak Reverse Blocking Current
VTM Maximum On State Voltage off state + Voltage
IH Holding Current IH IDRM at VDRM
Quadrant 3
VTM
MainTerminal 2 −
MT2 POSITIVE
(Positive Half Cycle)
+
MT1 MT1
REF REF
IGT − + IGT
MT1 MT1
REF REF
−
MT2 NEGATIVE
(Negative Half Cycle)
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Z0103MN, Z0107MN, Z0109MN
0.15
3.8
0.079
2.0
0.244
0.091 0.091 6.2
2.3 2.3
0.079
2.0
inches
0.059 0.059 0.059 BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR.
mm
0.984 1.5 1.5 1.5 BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL.
25.0 MATERIAL: G10 FIBERGLASS BASE EPOXY
0.059 0.059
1.5 1.5
0.472
12.0
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Z0103MN, Z0107MN, Z0109MN
RESISTANCE, ° C/W
1.0 FIGURE 1 AREA = L2 4
110 PCB WITH TAB AREA
100 AS SHOWN
90 1 2 3
80
0.1
70
TYPICAL AT TJ = 110°C 60
MAX AT TJ = 110°C 50 MINIMUM
MAX AT TJ = 25°C 40 FOOTPRINT = 0.076 cm2
0.01 30
0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 6.0 8.0 10
vT, INSTANTANEOUS ON‐STATE VOLTAGE (VOLTS) FOIL AREA (cm2)
110 110
α
100 α
100
30° 30°
60° AMBIENT TEMPERATURE ( °C) 60°
T A , MAXIMUM ALLOWABLE
90 90
α = CONDUCTION
90° 90°
ANGLE
80 80
dc dc
70 70
α = 180° α = 180°
60 120° 60 120°
50 50 1.0 cm2 FOIL AREA
MINIMUM FOOTPRINT α
50 OR 60 Hz
40 40 α
50 OR 60 Hz
30 30 α = CONDUCTION
ANGLE
20 20
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IT(RMS), RMS ON‐STATE CURRENT (AMPS) IT(RMS), RMS ON‐STATE CURRENT (AMPS)
Figure 4. Current Derating, Minimum Pad Size Figure 5. Current Derating, 1.0 cm Square Pad
Reference: Ambient Temperature Reference: Ambient Temperature
T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( °C)
110 110
α 30°
100 α 105
30°
60°
T(tab) , MAXIMUM ALLOWABLE
dc
60° α = CONDUCTION
TAB TEMPERATURE ( °C)
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Z0103MN, Z0107MN, Z0109MN
1.0 1.0
α
0.9
α
POWER DISSIPATION (WATTS)
RESISTANCE (NORMALIZED)
0.8
α = CONDUCTION
0.7
ANGLE
0.6
120°
0.5 0.1
30°
0.4 α = 180°
60°
0.3
dc 90°
0.2
0.1
0 0.01
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0001 0.001 0.01 0.1 1.0 10 100
IT(RMS), RMS ON‐STATE CURRENT (AMPS) t, TIME (SECONDS)
Figure 8. Power Dissipation Figure 9. Thermal Response, Device
Mounted on Figure 1 Printed Circuit Board
LL 1N4007
200 VRMS
ADJUST FOR MEASURE
ITM, 60 Hz VAC RS
I
TRIGGER CONTROL
CHARGE
TRIGGER CONTROL -
CHARGE 200 V
CS ADJUST FOR +
MT2 dv/dt(c)
1N914 51 W
NON‐POLAR MT1
CL G
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dv/dt)c
10 10
60 Hz
80° 60°
180 Hz
400 Hz
COMMUTATING dv/dt
COMMUTATING dv/dt
300 Hz
dv/dt c , (V/ μ S)
dv/dt c , (V/ μ S)
110°
ITM
100° VDRM = 200 V
tw
1
f=
2 tw 6fI
TM
VDRM (dińdt) c + 1000
1.0 1.0
1.0 10 60 70 80 90 100 110
di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Typical Commutating dv/dt versus Figure 12. Typical Commutating dv/dt versus
Current Crossing Rate and Junction Temperature Junction Temperature at 0.8 Amps RMS
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Z0103MN, Z0107MN, Z0109MN
60 10
600 Vpk IGT3
IGT4
IGT1
40 1.0
30
MAIN TERMINAL #1
POSITIVE
20 0.1
10 100 1000 10,000 -40 -20 0 20 40 60 80 100
RG, GATE - MAIN TERMINAL 1 RESISTANCE (OHMS) TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Exponential Static dv/dt versus Figure 14. Typical Gate Trigger Current Variation
Gate − Main Terminal 1 Resistance
6.0 1.1
4.0 VGT3
MAIN TERMINAL #2 VGT4
POSITIVE
VGT2
3.0
VGT1
2.0
MAIN TERMINAL #1
POSITIVE
1.0
0 0.3
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Typical Holding Current Variation Figure 16. Gate Trigger Voltage Variation
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Z0103MN, Z0107MN, Z0109MN
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ANSI
b1 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
4
A 1.50 1.63 1.75 0.060 0.064 0.068
HE E A1 0.02 0.06 0.10 0.001 0.002 0.004
1 2 3 b 0.60 0.75 0.89 0.024 0.030 0.035
b1 2.90 3.06 3.20 0.115 0.121 0.126
c 0.24 0.29 0.35 0.009 0.012 0.014
D 6.30 6.50 6.70 0.249 0.256 0.263
E 3.30 3.50 3.70 0.130 0.138 0.145
b e 2.20 2.30 2.40 0.087 0.091 0.094
e1 e1 0.85 0.94 1.05 0.033 0.037 0.041
e L1 1.50 1.75 2.00 0.060 0.069 0.078
HE 6.70 7.00 7.30 0.264 0.276 0.287
C q 0° − 10° 0° − 10°
q STYLE 11:
A PIN 1. MT 1
2. MT 2
0.08 (0003)
A1 3. GATE
L1 4. MT 2
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
6.3
2.3 2.3
0.248
0.091 0.091
2.0
0.079
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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