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Ideal Inverter Voltage Transfer Characteristics

MOS/CMOS INVERTERS

Voltage transfer characteristic (VTC) of

the ideal inverter.

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MOS Inverter: Actual Voltage Transfer Voltage Transfer Characteristics

Characteristics
● Applying Kirchhoff’s Current Law to this circuit, we can see that the load
current is always equal to the nMOS drain current.
ID (Vin, Vout) = IL (VL)

● On VTC, 3 important points

o One point at which Vout = Vin
o 2 points at which

● The smaller input voltage value satisfying this condition is called the input low voltage
VIL
● The larger input voltage satisfying this condition is called the input high voltage VIH
General circuit structure of an nMOS
inverter.
● The inverter threshold voltage/switching threshold/midpoint voltage, Vth
or VM is defined as the point where Vout = Vin on the VTC.
VOH: Maximum output voltage when the output level is logic " 1"
VOL: Minimum output voltage when the output level is logic "0"
VIL: Maximum input voltage which can be interpreted as logic "0"
VIH: Minimum input voltage which can be interpreted as logic " 1"
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NOISE MARGIN NOISE IMMUNITY AND NOISE MARGINS

● The ability of an inverter to interpret an input signal within a voltage range as
either a logic ”0" or as a logic "1" allows digital circuits to operate with a
certain tolerance to external signal perturbations. NM H = V OH – V IH

● Noise can be a change in voltage (many a times it is a drop) that results form NM L = V IL – V OL
an interconnect (inductively coupled, resistive loses etc.)
o The signal level at one end of an interconnection line may be significantly
different from the signal level at the other end.

VOL, VOH, VIL, VIH, Vth determine:

• DC input-output behaviour,
• Noise Margins,
• Width and Location of Transition Region

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● Justification for VIL and VIH ● The boundaries of the valid input signal regions are the voltage points where
the magnitude of the inverter voltage gain is equal to unity
Vout = f(Vin)
● The input voltage range between VIL and VIH, may not be processed correctly
Vout’ = f(Vin+ΔVnoise) either as a logic "0" input or as a logic "1" input by the inverter. This region
is called the uncertain region or, the transition region.
● By using a simple first-order Taylor series expansion and by neglecting
higher-order terms ● Ideally, the slope of the voltage transfer characteristic should be very large
between VIL and VIH.

● A narrow uncertain (transition) region allows for larger noise margins.

o One of the most important design objectives.
Perturbed Output = Nominal Output + Gain x External Perturbation

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POWER DISSIPATION Inverter: DC Analysis

● Since each gate on the chip dissipates power and thus generates heat, the ● DC Analysis
removal of this thermal energy, i.e., cooling of the chip, becomes an essential o DC value of a signal in static conditions
and usually very expensive task. o Voltage Transfer Characteristic (VTC)
● plot of Vout as a function of Vin
PDC = VDD.IDC ● vary Vin from 0 to VDD
● find Vout at each value of Vin

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Inverters: Resistive load Inverter

Assume VSB = 0 => VT,n = VT0,n

λ=0

Input Voltage Range Operation Mode ID Calculation of VOH A

Vin < VT0,n Cut-off 0
Vout = VDD – ILRL
VT0,n ≤ Vin < Vout + VT0,n Saturation
In region A, Vin < VT0,n => nMOS Cut-off
Vin ≥ Vout+ VT0,n Linear IL = ID = 0 => V OH = VDD
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● Calculation of VOL ● Calculation of VIL B

C

Find out Vout at Vin = VIL

Solution is with the negative sign

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● Calculation of VIH C
● Calculation of Vth

Find out Vout at Vin = VIH

Substitute the expression for Vout in VIH

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Summary Summary

VOH = VDD VOH = VDD

But putting a larger resistance would
also mean:
• larger resistor length
• greater switching delays

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POWER DISSIPATION Resistive load Inverter

Issues
● Large area requirements of resistor
When Vin = VOL: Driver nMOS is in cut-off
● Process variations of the resistor
● Huge chip area requirements
● Larger DC power consumption
● VIL ≠ 0
When Vin = VOH:
● Noise margins and output swing can be too low or too slow

Assuming 50% of duty cycle (input voltage is low during

50% of operation time and high during the remaining
50% of time)

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Inverters: Enhancement mode n-MOSFET as

Inverters: MOSFET as load load
● Resistive-load inverter - large area occupied by the load resistor
● The main advantages of using a MOSFET as the load device
o Smaller silicon area occupied by the transistor
o Process variations can be reduced compared to resistive load inverter

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Inverters: Saturated Enhancement n-MOSFET

as load
● Load à Saturation, Driver à Cutoff A VOH

VOH < VDD

VOL > 0
● Load à Saturation, Driver à Saturation B VIL

VSB,d = 0 => VT,d = VT0,n

VSB,L = Vout > 0 => VT,L ≠ VT0,n ● Load à Saturation, Driver à Linear C VIH, VOL
Load: Saturation condition is always satisfied
VGS, L = VDS, L => VDS, L > VGS, L – VT,L

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SUMMARY CMOS Inverter

● The saturated enhancement-load inverter
o A single voltage supply
• All static parameters of CMOS inverters are superior to those of NMOS
inverters
o A relative simple fabrication process
o VOH = VDD - VT,load
• CMOS is the most widely used digital circuit technology in comparison to
other logic families.
● The linear enhancement-type load • lowest power dissipation
o VOH = VDD • highest packing density
o Higher noise margins • Increased process complexity (to provide isolated transistors of both polarity
o Two separate power supply voltage (drawback) types)

● Both suffer from relatively high stand-by power dissipation

● Not used in any large-scale digital applications

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CMOS Inverter CMOS Inverter

Region Vin Vout nMOS pMOS Region Vin Vout nMOS pMOS
A < VTN VOH Cut-off Linear A < VTN VOH Cut-off Linear
B VIL ≈VOH Saturation Linear B VIL ≈VOH Saturation Linear
C VTH VTH Saturation Saturation C VTH VTH Saturation Saturation
D VIH ≈VOL Linear Saturation D VIH ≈VOL Linear Saturation
E > VDD +VTP VOL Linear Cut-off E > VDD +VTP VOL Linear Cut-off

Vin = Vgsn = Vgsp + VDD Vin = Vgsn = Vgsp + VDD

Vout = Vdsn = Vdsp + VDD Vout = Vdsn = Vdsp + VDD

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Calculate V OH CMOS INVERTER: ESTIMATION OF VIL

IDp = IDn

0
0 1
VGSn = Vin VGSp = Vin - VDD VDSp = Vout – VDD

Calculate V OL

0 2
0

Solve Eq: 1 and 2 for VIL and Vout

VIL depends on the output voltage
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CMOS INVERTER: ESTIMATION OF VIH

CMOS INVERTER: ESTIMATION OF Vth
VGSn = Vin VDSn = Vout VGSp = Vin - VDD Threshold voltage of inverter, Vth = Vin = Vout

VGSn = Vin VGSp = Vin - VDD

Solve Eq: 3 and 4 for VIH and Vout

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Effect of kR on Vth

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POWER SUPPLY CURRENT vs VIN DESIGN OF CMOS INVERTERS

ID = 0, V in < V T0n
ID = 0, V in > V DD + V T0p
ID = Max, V in = V th
For ideal inverter:

If VT0 = VT0n = - VT0p => kR = 1 => Symmetric Inverter

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DESIGN OF CMOS INVERTERS (Cont..) Example

kn’ = 140μA/V2, VTn = 0.7V, VDD = 3V

kp’ = 60μA/V2, VTn = -0.7V

a. Find transistor size ratio, so that VM = 1.5V

b. VM if transistors are of same size.

Note: VIL + VIH = VDD

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POWER DISSIPATION

When Vin = VOL

PDC = 0
When Vin = VOH

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