FFH-CDMA IMPLEMENTATION USING FPGA AND DDS

Anael SAM (1), Vladimr TOFANIK (2), Igor BAL (3)

(1)

Dept. of Electronics and Telecommunication Engineering, Dar Es Salaam Institute of Technology (DIT), P.O.Box 2958, Dar Es Salaam, Tanzania.
(2)

Institute of Physics, Slovak Academy of Sciences, Dbravsk cesta 9, 84511 Bratislava, Slovak Republic

(3)

Dept. of Radio and Electronics, FEI, Slovak University of Technology, Ilkoviova 3, 812 19 Bratislava, Slovak Republic sam@kre.elf.stuba.sk, fyzistof@savba.sk, balash@kre.elf.stuba.sk

Abstract The paper discusses implementation of FFH-CDMA modulator using the FPGA (XC2S15) and the single-chip DDS (AD9857). The generation of PN code sequence, timing and control signals were made within the FPGA. 1. Introduction Code Division Multiple Access (CDMA) is a technology, which enhances the capacity of competitive Wireless Communication Systems (WCS). It enables WCS to deliver information content while utilizing optimal frequency bandwidth. CDMA is capable of combating interference such as adjacent channel interference using Pseudo-random Noise (PN) codes with minimum cross correlation. The combination of fast frequency hopping (FFH) and CDMA forms FFH-CDMA multiple access scheme, which brings together the benefits as a enhanced capacity, frequency diversity, low probability of intercept, anti-jam, etc. The PN code sequence determines the frequency shift of the FFH-CDMA carriers. The interference levels of every channel in FFH-CDMA system can be searched using a search algorithm. The FFH-CDMA can adapt to the different interference levels in the hopping sequence by either skipping the highly interfered channels or assigning them with minimum bit rates [1]. The paper deals with an effective FFH-CDMA system implementation based on FPGA (XC2S15) and single-chip DDS-QAM modulator (AD9857). The PN code sequence generation together with the timing and control signals is generated within the FPGA. This enables effective circuit resources utilization, hence making an efficient FFH-CDMA system. 2. System Description Detail description of the evaluation board has been made in [2]. The used PN code sequence is of the Gold code type. The properties of Gold code sequence have been described in [2] and [3]. The Gold codes have been described as a set of small correlation PN codes generated by modulo-2 addition of outputs of two Linear Feedback Shift Registers (LFSR). Two primitive polynomials of 41 degree (1) and (2) form the used Gold code (3):

y1 ( x ) = x 41 + x 20 + 1 y2 ( x ) = x + x + 1 y ( x ) = y1 ( x ) + y2 ( x )
41 3

(1) (2) (3)

FPGA - XC2S15 DATA 14 BUFFER GOLD-CODE GENERATOR LFSR1

D 7-BIT SHIFT REGISTER CLK

14

D0 - D13

LFSR2

DDS AD9857 OUTPUT

A0 - A6 LOOK-UP TABLE CLK

SDI SCLK CS FUD CLK

REFERENCE OSCILLATOR

TIMING CIRCUITS

Fig. 1 Simplified block diagram of the FFH-CDMA modulator implementation using the evaluation board Captured in Fig. 1, is the simplified block diagram of FFH-CDMA implementation incorporating the designed evaluation board. Two primitive polynomials of 41 degree are used in our system; 41-stage LFSR1 and LFSR2 in Fig. 1. Both LFSRs together with the exclusive-OR gate represent the Gold code generator. Seven least significant bits of the Gold code sequence are used to select one carrier from a set of a maximum 128 different carriers. These seven bits are converted to parallel form in the shift register. The output of the register defines the address in the look-up table. The table stores up to 128 frequency-tuning words, which correspond to a given set of carrier frequencies. At a given instance the set of carriers is formed from one to seven bits. Each frequency-tuning word comprises of 32 bits. The corresponding frequency-tuning word is shifted to the AD9857 via serial peripheral interface. The carrier switching is synchronized by the frequency update signal (FUD), which determines the beginning of the new frequency synthesis process. The hardware description and design of PN code generation has been done using the Verilog hardware description language (HDL). Postfix simulation of the designed modules has been done using the HDL simulator to verify the description. It follows the synthesis to optimize the design and then the implementation of the modules into the FPGA. The carrier frequency of the DDS is set periodically via serial bus. PN codes are used to spread the bandwidth of the modulated signal over a wide radio spectrum and uniquely code individual user signals across the transmission interface. The circuit implementation is made in FPGA for the frequency control words, which are used to update tuning frequency of the DDS. Also synchronization signals to the DDS are generated within FPGA. The frequency control word, which synchronizes the DDS and external timing requirements, are programmed into the DDS via the serial port. 3. Spectrum Measurements The spectra measurements have been done using S-TEAM RF/MW spectrum analyzer SPARE 0122. The maximum resolution bandwidth of 10 kHz was set for detailed measurements.

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64 carriers -32.23dBm Second harmonics of the carriers

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f[MHz]

Fig. 2 Spectrum of 64 hopped carriers; frequency update rate was 8s

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16 carriers

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Fig. 3 Spectrum of 16 hopped carriers; frequency update rate was 80s Measured spectrum of a set of 64 selected carriers with 8 s frequency update rate is shown Fig. 2. The lowest carrier frequency was 30 MHz and the carrier spacing was 200 kHz. Using a band-pass filter the 2nd harmonics of the carrier can be filtered out obtaining suitable SNR for use in WCS. Measured spectrum of a set of 16 selected carriers with 80 s frequency update rate is captured in Fig. 3. The lowest carrier frequency was again 30 MHz but the carrier spacing was 1.25 MHz. From the spectrum one can see that the largest spur was about 40 dB below the carrier level. Figure 4 shows two measured spectra of a set of 64 selected carriers in the case when frequency update rate was 80 s and when it was 1 ms. The lowest carrier frequency was again 30 MHz. Now the carrier spacing was 200 kHz. One can see that with faster frequency update the noise floor rises.

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-10 -20 -30 -40 -50 -60 -70 28 A - Frequency update rate was set 80 microseconds B - Frequency update rate was set 1ms

A B

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46 48 f[MHz]

Fig. 4 Spectra of 64 frequency hopped carriers; frequency update rate was 1ms and 80s 4. Conclusions In FFH-CDMA the information bits are transmitted using different carriers and the presence of narrow band interference will be just a minor part of the signal spectrum. In addition, the interference effects can be mitigated using redundancy codes (e.g. convolution coding). Also using a search algorithm the highly interfered channel could either be skipped or assigned with minimum bit rates. We have realized FFH-CDMA modulator utilizing only minimum resources of the used FPGA and the single-chip DDS-QAM modulator. Reasonable frequency update interval of 80 s has been obtained and the purity of the measured spectra proves that FFH-CDMA can be used to cater the drawbacks of DS-CDMA, which widely used in WCS. Acknowledgements We would like to express our thanks the collective of the microwave section in the department of Radio and Electronics, FEI STU, for providing us with their S-TEAM RF/MW spectrum analyzer SPARE 0122, which enabled us to realize the measurements of the spectra. References [1] Wang, C. C., Pottie, G. J.: Variable Bit Allocation for FH-CDMA Wireless Communication Systems, IEEE Transactions on Communications, Vol. 50, No. 10, July 2002, pp. 1637-1644. [2] Sam, A. E., Stofanik, V., Balaz, I.: Evaluation Board for Frequency Hopping-CDMA systems, Proceedings of the 13th International Scientific Conference Radioelektronika 2003, Brno, Czech Republic, 2003, pp. 411-414. [3] George, M., Hamid, M., Miller, A.: Gold Code Generators in Virtex Devices, Application note XAPP217, XILINX Inc., January 2001.