PLACEMENT

PHYSICAL DESIGN
 Prerequisite

Must be aware of the floor planning and

the power planning concepts.

Must be aware of the commonly used

terms and basic design.

This presentation will help you to get the

placement related knowledge of a design.
 GOALS
Design goals can be timing, power and area.

Guarantee the router can complete the

routing step

Minimize all the critical net delays

Make the chip as dense as possible

 DISCUSSIONS
What is placement and its need in physical
design.

What is pre, in, post placement optimization

stages.

Additional constraints to improve placement

related issues.
ZERO INTERCONNECT TIMING ANALYSIS
Before you start with placement:

Perform a 'Timing Sanity Check' or zero

interconnect timing analysis.

Check the violations

If zero violations : Continue on to
placement

If still violating: Go back to Synthesis!

 Placement flow in the physical design

Design setup and Timing

floor plan data OK ?
YES
No
Detach scan chain
Additional Perform cts
optimization
Set Placement
options

Auto place

YES
NO
Congestion
OK ?
 SCAN CHAIN HANDLING
Disconnect the scan chains prior to placement to focus on the
functional critical paths.

If serially connected FFs are placed far apart this may require a lot
more routing resources than necessary.

If FFs are placed close together, according to their scan chain

ordering, this may hurt timing along functional critical paths.

Scan chains will be reconnected after CTS

Same grouping of FFs
Different ordering: based on placement, to minimize
routing resources
 Specify
The Place menus Specify forms enable you to specify and
assign spare cells, scan cells, JTAG cells, and placement
blockage for power and ground stripes. You must assign
these objects before running placement.

The Specify submenu provides access to the following

features:
Spare cells
Cell paddings
Jtag cells
Placement blockages
 PLACEMENT
Before the start of placement optimization all Wire Load
Models (WLM) are removed. Placement uses RC values
from Virtual Route (VR) to calculate timing.
VR is the shortest Manhattan distance between two
pins.
VR RCs are more accurate than WLM RCs.
Placement is performed in four optimization phases:
Pre-placement optimization
In placement optimization
Post Placement Optimization (PPO) before clock tree synthesis
(CTS)
PPO after CTS.
 PRE PLACEMENT OPT
Optimizes the netlist before placement, HFNs are
collapsed.

It can also downsize the cells.

 IN PLACEMENT OPT
Re-optimizes the logic based on VR.

This can perform cell sizing, cell moving, cell

bypassing, net splitting, gate duplication, buffer
insertion, area recovery.

Optimization performs iteration of setup fixing,

incremental timing and congestion driven
placement.
 PPO BEFORE CTS
Before CTS performs netlist optimization with
ideal clocks.

It can fix setup, hold, max trans/cap violations.

It can do placement optimization based on

global routing.

It re does HFN synthesis.

 PPO AFTER CTS

After CTS optimizes timing with propagated

clock.

It tries to preserve clock skew.

 What Does it mean if TNS >>WNS?
A large TNS implies that there could be many
sub-critical violations that are almost as bad as
the critical path violation.

It is also possible that these paths are related

or share logic.

We can verify by analyzing the sub-critical

paths with detailed timing reports.
What does Optimization Do By Default?
By default, logic optimization during
placement works only on the critical path
of each clock domain, and stops when it
cannot further improve its timing.

Sub-critical paths are not optimized in this

stage of optimization.
Critical Range Optimization

Critical Range Optimization (CRO) works on

the sub critical paths, which reduces the
total number of violations paths and the
TNS.
CRO may also help to reduce the critical
path violations if it is 'related to some of
the sub-critical paths
Goals for placement optimization

Performance : Such as Timing

Logical DRCS

Routability or congestion

Area

Leakage Power
Some commands used in cadence