Clock Training

Innovus 18.
1 CTS
Innovus Product Engineering

2018-05-23
Copyright Statement
• © 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the
Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are
the property of their respective holders.
Topics
Key
• CTS in the Innovus flow
• Setup 18.1 New in 18.1
• TAT
• Concepts common_ui_command
• Clock power
• Flexible H-tree & multi-tap legacyUICommand
• Common UI (CUI)
3 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

CTS in the Innovus flow

18.1
CTS in the Innovus flow – Overview
• Early clock in place_opt_design
(optional)
– Clock congestion awareness
place_opt_design – Clock gate enable timing optimization
optionally with early clock – Useful skew with estimate of clock delays
ccopt_design
• CTS : ccopt_design
– CTS & datapath optimization
route & post-route opt – Standard effort or extreme effort
– Switch to propagated clock timing & source
latency update
• Useful skew at all steps by default
– pre-cts useful skew or early clock useful skew
• For CTS only without datapath optimization – standard effort or extreme effort CCOpt
clock_design / ccopt_design –cts – post-route useful skew

CTS in the Innovus flow – Early clock flow (ECF)
place_opt_design • Awareness of clock routes & clock cell placement
with
early placement – Improved accuracy for congestion, RC, layer
clock assignment, and other optimizations
global opt
merge FF
• Optimization of clock gate enable timing
• Useful skew with estimate of clock delays
cluster & virtual balance
• Additional optimization transforms possible
timing compared to post-CTS
opt
power split • Setup CTS before place_opt_design
opt FF
– NDRs, cells, clock spec, ...
cong useful • Command to enable
repair skew set_db design_early_clock_flow true
setDesignMode –earlyClockFlow true
ccopt_design
CTS in the Innovus flow – Early clock – How it works
place_opt_design
with
early placement • Clustering and balancing with virtual delays
clock
global opt • CTS timing used to annotated clock latencies for
merge FF ideal clock mode timing analysis
cluster & virtual balance
• Skewing adjusts the latencies
• Latencies are communicated to later CTS via pin
timing
opt insertion delays in the in-memory clock tree spec
power split
opt FF
cong useful
repair skew
Note: Do not use reset_cts_config /
reset_ccopt_config before ccopt_design,
doing so will delete the pin insertion delays.
ccopt_design
CTS in the Innovus flow – Useful skew controls – Common UI
set_db opt_useful_skew_pre_cts true* | false

set_db opt_useful_skew_ccopt none|standard*|extreme
– Determines useful skew flow inside ccopt_design
– none : No useful skew
– standard : Standard effort ccopt_design
– extreme : Extreme effort ccopt_design
set_db opt_useful_skew_post_route true* | false
set_db opt_useful_skew true* | false
– Master switch to disable all useful skew
– Getting useful skew requires both opt_useful_skew AND opt_useful_skew_<FlowStep>
– set_db design_flow_effort standard* | extreme
– At start of ccopt_design, the opt_useful_skew_ccopt setting inherits this standard or
extreme setting unless opt_useful_skew_ccopt has been explicitly set by the user

CTS in the Innovus flow – Useful skew controls – Legacy UI
setOptMode –usefulSkewPreCTS true* | false

setOptMode –usefulSkewCCOpt none|standard*|extreme
– Determines useful skew flow inside ccopt_design
– none : No useful skew
– standard : Standard effort ccopt_design
– extreme : Extreme effort ccopt_design
setOptMode –usefulSkewPostRoute true* | false
setOptMode –usefulSkew true* | false
– Master switch to disable all useful skew
– Getting useful skew requires both –usefulSkew true AND –usefulSkew<FlowStep>
– setDesignMode –flowEffort standard* | extreme
– At start of ccopt_design, the usefulSkewCCOpt setting inherits this standard or extreme
setting unless usefulSkewCCOpt has been explicitly set by the user

Setup

Setup – Standard settings
• Must configure
create_route_type –name CLK_NDR ...
set_db cts_route_type_top/trunk/leaf ...
– Route types with NDRs
– Cell lists
set_db cts_buffer_cells ... – Transition target
set_db cts_inverter_cells ... – Skew target
set_db cts_gating_cells ...
(set_db cts_logic_cells ...) – Top net fanout threshold if using top nets
• Run check_design
set_db cts_target_max_transition_time ...
set_db cts_target_skew ...
– Identifies common setup mistakes
– Identifies issues in the design data
create_clock_tree_spec – Identifies overly aggressive constraints
• Customizing the clock spec
check_design [-type cts]
– Set stop & ignore pins before creating the spec
(place_opt_design if using ECF)
– Use create_skew_group,
update_skew_group and other spec
manipulation commands instead of editing the
ccopt_design / clock_design
clock spec file
18.1
Setup – Check Design
• check_design –type cts

– Many new checks added Examples:
– Check basic settings are present
> help CHKCTS-010
– Check for missing or overly aggressive targets Error/Warning message: CHKCTS-010:
– Check routing configuration Route type(s) %s used for trunk or
top clock nets do not have an non-
– Check don’t touch, fixed & related default rule (NDR) set.
– Check multi-tap, e.g. uncloneable instances
– ... 40+ individual checks in total
> help CHKCTS-051
Error/Warning message: CHKCTS-051:
The timing analysis type is not
• check_design –type all set to OCV (on chip variation).
– Includes CTS checks only if clock spec is loaded

Setup – Net types
• Top net type applies to all nets with a sub-tree sink Default is unset –
count greater than a user set threshold top net type is not
top set_db cts_top_fanout_threshold 1000
used by default
set_ccopt_property routing_top_min_fanout 1000
trunk • Leaf net type applies to any net directly connected to a sink
• Can force the net connected to a sink to be considered trunk
set_db pin:name .cts_routing_trunk_override true
leaf set_ccopt_property trunk_override –pin name true
• Overriding the route type for a particular net

create_route_type –name rt1 ...
set_db pin:i0/ckout .cts_pin_route_type rt1
• Each sink counts as 1, but user can override: set_copt_property pin_route_type rt1 -pin i0/ckout
set_db pin:name
.cts_top_fanout_count_override 100 before cts
set_ccopt_property i0 i1
routing_top_fanout_count 100 -pin name
propagates over buffering
after cts
i0 i1

Setup – Sink offsets cts_pin_insertion_delay
Insertion delay
• SDC / user command approach
– Specify early or late clock arrival time note
– Early typically negative due to 0 network latency inverted
macro m0
set_clock_latency -1 [get_pins {m0/ck}] sign
ck
• CTS pin insertion delay approach
– Specify the clock insertion delay inside the macro
set_db pin:macro/CK .cts_pin_insertion_delay 1ns
set_ccopt_property insertion_delay 1ns –pin m0/CK
• Library max clock tree path approach • create_clock_spec converts SDC
clock latency to CTS pin insertion
– Library specifies the clock insertion delay inside the macro delay
convert_lib_clock_tree_latencies
• To delay sinks instead of advancing
• Recommendation them, invert the sign
– Specify in SDC or use library max clock tree path • Reporting – .logv or command
– Visible to slack driven placement and non-ECF pre-cts report_pin_insertion_delays
optimization report_ccopt_pin_insertion_delays
Setup – Stop & ignore pins
• Stop & ignore pins set_db pin:name cts_sink_type
– Clock spec creation stops tracing at the pin stop
– Clock spec creation will trace to this pin, even set_ccopt_property sink_type
if SDC clocks do not stop –pin name
• Stop pin
– The pin is considered a sink to be balanced in set_db pin:name cts_sink_type
any skew groups which reach it, even if the pin ignore
is not identifiable as a “clock pin” from the
library model set_ccopt_property sink_type
ignore –pin name
• Ignore pin
– The pin is not balanced
update_skew_group ... –
• Skew group specific ignore pin add_ignore_pins ...
– A pin which is ignored in a skew group, but modify_ccopy_skew_group ... –
may be balanced in other skew groups add_ignore_pins ...

17.1
Setup – Cells & library trimming
25
20
DRIVE STRENGTH
15
• CTS will filter the supplied cell lists 10

Drive Strength
Area
to remove inferior cells 5
– Improved clock QOR and run-time

0
– Filtering based on cell drive versus area 0 10 20 30 40 50 60 70
60
cells
BUFFER INDEX (SORTED BASED ON DRIVE)
– Applies to buffers, inverters, clock gates
25
• Recommendation: Continue to 20
11
specify only LVT cells for clock cells
DRIVE STRENGTH
15
Drive Strength
10
Area
0
0 2 4 6 8 10 12
BUFFER INDEX (SORTED BASED ON DRIVE)

18.1
Setup – Cell filtering report
• Report on why CTS rejected cells which the user specified

• report_cts_cell_filtering_reasons (report_ccopt_cell_filtering_reasons)
• Report included in verbose log (innovus.logv) output near start of CTS

• Refer to man page for explanation of reasons
• Note: If run in the same Innovus session after CTS it will execute quickly, otherwise it will run CTS initialization
to perform the filtering.

Turn Around Time (TAT)

18.1
TAT – 18.1 Improvement Project
CTS Core Minutes per 1M instances
CPU + Services 250
• Block level
Inst 235
count
freq / (mins) designs
#CPUs
Ref 18.1 200 190 191
• CPU, GPU,
Automotive,
1.4 M 2.3G/16 168 57 Networking
149
150
2.3 M 2.3G/16 436 114 120

132 135
119 17.1 • All ≤16nm

4.8M 2.3G/16 635 221 100
18.1
• 3.1x average
81
70
62
speed up
4.2 M 3.0G/16 566 227 50
54
48
• 1hour / 1M
50 46
41
34 33
2.3 M 2.3G/16 343 111
instances
0
1.8 M 2.3G/16 145 61 1 2 3 4 5 6 7 8 9 average
2.3 M 3.0G/16 541 162 • Core CTS & services (legalization, routing)
2.2 M 3.0G/16 420 137 • Multi-threading in some steps & reporting
5.6M 2.3G/16 667 182 • Post-CTS opt excluded
Concepts

Concepts – Transition to propagated mode timing
Question – What happens at CTS?
✓Add buffering & size/place clock cells for drive and delay
Sounds straightforward, but now timing is with propagated clocks:

✓SOCV/AOCV/derates impact timing from non-common clock path
✓Clock gate enable timing is no longer ideal
✓Inter clock timing depends on achievable insertion delays
✓Clock generator control logic timing is no longer ideal
✓Single CTS unbufferable net can impact entire design timing
➢ More than just buffering clock nets!

Concepts – Clock trees & skew groups
ck1 ck2 skew

group
2
• Clock trees
G
– Physical constraints
skew
– DRV, NDR group
• Skew groups 1
– Balancing constraints
– Auto spec 1:1 named
clock/analysis_view
G
• Clocks
– Timing reports skew
group
– SDC / CTE
1&2 ... ... ...

Concepts – Auto clock spec – Single mode example
clock_tree:ck2 create_clock
create_clock skew_group:ck2 [get_ports
[get_ports ck1 ck2 {ck2}]
{ck1}] clock_tree:ck1
skew_group:ck1
generated clock tree
create_generated_clock d1/CK ignored in
ck2_generator_for_gck2<1>
-name gck1 skew_group:ck2
-divide_by 2 create_generated_clock
[get_pins {d1/Q}] -name gck2
-source -divide_by 2
[get_pins {d1/CK}] d1 d2 [get_pins {m0/Y}]
-master_clock G -source
[get_clocks {ck1}] [get_pins {d2/CK}]
generated m0 no clock
clock_tree:gck1, tree,
reporting only reporting
skew group only skew
group
f1 f2 f3 f4 green - SDC
blue - clock spec
Note: Skew groups and clock trees often have the same name
Concepts – Auto clock spec – Multi mode example
ck mode0.sdc
create_clock [get_ports {ck}]
create_generated_clock -name gck -divide_by 2
[get_pins {d1/Q}] -source [get_pins {d1/CK}]
set_case_analysis 0 [get_ports {sel_div}]
d1 mode1.sdc
create_clock [get_ports {ck}]
create_generated_clock -name gck -divide_by 2
sel_div [get_pins {d1/Q}] -source [get_pins {d1/CK}]
0 1
set_case_analysis 1 [get_ports {sel_div}]
update_skew_group –skew_group ck/mode0

skew_group:ck/mode0 -add_ignore_pins mux/I1
skew_group:ck/mode1 update_skew_group –skew_group ck/mode1
-add_ignore_pins mux/I0
• Two skew groups with source at ‘ck’ input – one per clock per mode blue – mode0
green – mode1
• One ignored at mux ‘0’ input and other ignored at mux ‘1’ input
• Paths through the mux ‘0’ input are not balanced with paths through the mux ‘1’ input
Concepts – CTS internal flow – Standard effort
library trimming, identify placeable area,
Initialization
validate transition & skew targets, log settings
Construction clustering, legalization, DRV repair
Implementation optimize insertion delay and power, balancing

ccopt_design
EGR Post-Conditioning early global route, area reclaim, DRV repair
Clock Routing detailed routing along early global route guides
NR Post-Conditioning DRV and skew repair
Post-CTS Optimization scan re-order, datapath optimization, useful skew

DAG Stats – Reported at each step and sub-steps: Clock
area, cap, cell counts, transitions, insertion delay, skew, ...
18.1
Concepts – Clock routing
• Early global route post-conditioning
Initialization • Clock nets are detail routed with NanoRoute
Construction
• Post-conditioning may resize and move clock
cells small distances leaving small opens in
clock nets
ccopt_design
Implementation
• Optimization may modify or add clock cells, or
EGR Post-Conditioning re-size flops, also leaving small opens in clock
nets
Clock Routing • Design routing repairs clock nets first, closing
the opens
NR Post-Conditioning • Post-route optimization includes CTS PRO to
further repair clock DRVs
Post-CTS Optimization
18.1: Many improvements in EGR, EGR
Post-Conditioning, NR Post-Conditioning
route & post-route opt
Concepts – DAG Stats
Clock DAG stats after update timingGraph:
cell counts : b=719, i=2653, icg=6495, nicg=0, l=824, total=10691
cell areas : b=1668.215um^2, i=8067.257um^2, icg=54799.189um^2, nicg=0.000um^2, l=7370.830um^2, total=71905.491um^2
cell capacitance : b=1.024pF, i=15.171pF, icg=15.285pF, nicg=0.000pF, l=3.642pF, total=35.122pF
sink capacitance : count=104926, total=255.000pF, avg=0.002pF, sd=0.001pF, min=0.001pF, max=0.040pF counts, area,
wire capacitance : top=0.000pF, trunk=98.883pF, leaf=162.988pF, total=261.871pF cap, length
wire lengths : top=0.000um, trunk=573904.625um, leaf=776348.715um, total=1350253.340um
Clock DAG net violations after update timingGraph:
Remaining Transition : {count=1, worst=[9.7ps]} avg=9.7ps sd=0.0ps sum=9.7ps drv violations
Fanout : {count=3, worst=[20, 20, 6]} avg=15.333 sd=8.083 sum=46
Capacitance : {count=4, worst=[1.714pF, 1.451pF, 1.166pF, 0.002pF]} avg=1.083pF sd=0.755pF sum=4.333pF
Clock DAG primary half-corner transition distribution after update timingGraph:
transition
Trunk : target=300.0ps count=3849 avg=90.5ps sd=77.4ps min=0.0ps max=300.0ps {3135 <= 180.0ps, 459 <= 240.0ps, 174times
<=
270.0ps, 44 <= 285.0ps, 37 <= 300.0ps}
Leaf : target=300.0ps count=6980 avg=166.2ps sd=67.5ps min=16.7ps max=309.7ps {4178 <= 180.0ps, 1714 <= 240.0ps, 619 <=
270.0ps, 296 <= 285.0ps, 172 <= 300.0ps} {1 <= 315.0ps, 0 <= 330.0ps, 0 <= 360.0ps, 0 <= 450.0ps, 0 > 450.0ps}
Clock DAG library cell distribution after update timingGraph {count}:
Bufs: CTB_F4_SVT: 27 GLITCHGOBBLER_F4_DH_SVT: 2 CTB_F1_SVT: 690
Invs: INV_B16_SVT: 67 INV_B14_SVT: 68 INV_B12_SVT: 137 INV_B10_SVT: 175 INV_B8_SVT: 122 INV_B6_SVT: 186 INV_B5_SVT: 117
CTI_F4_SVT: 123 INV_B4_SVT: 141 INV_B3_SVT: 189 INV_B2_SVT: 258 INV_B1_SVT: 1070
library cell usage
ICGs: ICG_F6_SVT: 81 ICG_F5_SVT: 72 ICG_F4_SVT: 942 ICG_F3_SVT: 385 ICG_F2_SVT: 1792 ICG_F1_SVT: 3223
Logics: CTNAND2_F4_AHP_SVT: 2 CTOR2_F4_AHP_SVT: 67 CTMUX2_F4_SVT: 685 CTEXOR2_F4_SVT: 5 CTENOR2_F4_AHP_DH_SVT: 5
CTAND2_F4_SVT: 58 NOR2IA_F8_4SR_75LL: 1 CTOR2_F4_SVT: 1
Primary reporting skew group after update timingGraph:
skew_group PLLCLK/DFT: primary reporting skew group
Half-corner MAX_DELAY_CORNER:setup.late: insertion delay [min=7146.5, max=7596.1, avg=7428.6, sd=90.2], skew [449.6 vs
400.0*], 99.2% {7182.6, 7582.6} (wid=1060.4 ws=584.8) (gid=7052.3 gs=859.6)
Skew group summary after update timingGraph:
... all skew groups
Concepts – Clock tree debugger (CTD)
Insertion delay Unit delay • Open in unit delay view
to avoid invoking RC
extraction or delay
calculation, e.g. on un-
placed design, or at
post-route
gui_open_ctd
-unit_delay
ctd_win
-unit_delay
• Coloring by clock tree, skew • Dotted line

group, net type, cell type, indicates
transition time, activity, ... multiple input
• Cross probing with layout view cell present
in more than
one clock
tree
18.1
Concepts – Don’t touch means don’t size
• 18.1 CTS DOES NOT SIZE USER DON’T TOUCH INSTS

– Previous tool versions resize don’t touch instances by default
– New behavior is consistent with other parts of Innovus and other tools
• How to say don’t touch but permit resize

– set_db inst:name .dont_touch size_ok
– (dbSet [dbGetInstByName name].dontTouch sizeOk)
– Note size_same_height_ok/size_same_footprint_ok not supported and do not enable sizing
• How to find clock tree instances which are fully don’t touch by user
– get_db clock_trees .insts -expr {"user true" in $obj(.dont_touch_sources)}’
– See also report_preserves to report on the whole design

18.1
Concepts – Don’t touch means don’t size – Warnings & checks
• CTS warning message

– IMPCCOPT-1437: Found %d clock tree instances which are user dont_touch and are
not resizable - this can impact clock QOR.
– The CUI version of this message also suggests the command given on the previous slide.
• Check design warns about don’t touch instances

– Includes checks for resizable instances and ones which are don’t touch from other sources
– check_design [-type cts]
– CHKCTS-052: Found %d instances which are user don't touch. Refer to CHKCTS-58
for a list of instances.
• Some existing users are already using “don’t touch means don’t size”
– Setting was “set_ccopt_property allow_resize_of_dont_touch_cells false”.
– This property, and the corresponding private CUI attribute, will be phased out in 18.2/19.1
Concepts – Get CTS right before optimizing timing
✓ Run check_design • Cluster run
✓ Check warnings and errors in the log set_db cts_balance_mode cluster
set_ccopt_property
✓ Check maximum insertion delay cts_balance_mode cluster
– If too large consider cluster run, and check the maximum
insertion delay path in the CTD & layout
• Disable detail routing to save time
✓ Check no unbuffered nets and DRV violations set_db cts_route_clock_tree_nets
– Check warnings in the log, color options in the CTD false
– Check in CTD and layout view set_ccopt_property
– Check MSV warnings & setup use_estimated_routes_during_fina
l_implementation true
– Use cluster run to debug if needed
✓ Get CTS right before optimizing timing
– No optimization – clock_design / copt_design –cts • Measuring cost of balancing
– Check skew group insertion delay & skew occupancy – Clustering depends on the skew target.
– Check report_clock_trees/report_skew_groups Cluster run skips some optimizations.
– Check DAG stats at CTS internal flow steps – Recommend to increase the skew
target rather than use cluster run.
– Look at the clock tree debugger
18.1
Concepts – Max clock tree path – Overview
• Cell library optional max_clock_tree_path attribute
– Specifies cell internal clock tree delay, index by input transition
– Is NOT a timing arc, not included in any timing analysis/report
• Timing significance
– Missing early offsets for memories a common cause of bad
Insertion delay
reg2mem hold TNS
– Optimistic/pessimistic setup timing for reg2mem/mem2reg
• Historical CTS support
– Off by default, behaves like an additional pin insertion delay
– Too late in the flow – no visibility at placement
• New command convert_lib_clock_tree_latencies
– Convert MCTP data to per pin clock latencies macro
– Aware that SDC pin latencies override SDC clock latencies max_clock_tree_path
– Updates in-memory timing constraints or export SDC text
18.1
Concepts – Max clock tree path – Flow
converts .lib max_clock_tree_path to
set_clock_latency [get_pins]
unplaced initial DB
convert_lib_clock_tree_latencies
convert_lib_clock_tree_latencies [-views <views>]
[-latency_file_prefix <string>]
[-pins <pins>]
create_clock_tree_spec
[-override_exising_latencies[_pins
<pins>]]
place_opt_design [-sum_existing_latencies[_pins <pins>]]
• Default behavior is to generate and apply

ccopt_design set_clock_latency commands for all clock pins with
MCTP data over all views, excluding pins which have an
existing latency in any view
converts set_clock_latency
[get_pins] to set_db • Utility command to get access to MCTP data
cts_pin_insertion_delay get_lib_clock_tree_path_delay -base_pin <...>
-edge rise -power_domain <...>
-transition <...> -view <...>
Concepts – Clock gate merging
Globally unique enables - The number of clock gates which
Merging duplicate siblings in DAG... have a unique enable input as per this definition: Imagine
Resynthesising clock tree into netlist...
Reset timing graph... all buffers and logical pairs of inversions are deleted from
Reset timing graph done. the datapath and the clock tree. A set of 1 or more clock
Resynthesising clock tree into netlist done. gates with their enable input driven by the same pin would
Summary of the merge of duplicate siblings
be a “globally unique enable”.
---------------------------------------------------------------
Description Number of occurrences
---------------------------------------------------------------
Total clock gates 4314 Potentially mergeable clock
Globally unique enables 4263
Potentially mergeable clock gates 51
gates: This is defined as the
Actually merged 1 total number of clock gates
--------------------------------------------------------------- minus the number of globally
Cannot merge reason: UniqueUnderParent 49 unique enables.
Cannot merge reason: IsDontTouch 1
---------------------------------------------------------------
Cannot merge reason: UniqueUnderParent This means two clock gates have the same ‘globally unique enable’
controlling their enable input, but are in the fanout of logically different clock gates further up the tree. Merging
these would be logically inequivalent.

Concepts – Clock gate merging – Example
• Pretend all datapath buffers and matching pairs of
clock inverters are removed.
data • G4 and G5 can be merged because they are enabled
by the same logic instance i2.
• G1 and G2 can not be merged because they are
enabled by different logic instances i0 and i1.
i0 G1 i1 G2
• G3 can not be merged with G4/G5 because G1 and G2
have different enables.
Total clock gates: 5

Globally unique enables: 3
Potentially mergeable clock gates: 5-3=2
G3 G4 G5 Cannot merge: UniqueUnderParent : 1
Number of clock gates actually merged: 2-1=1
i2 (G4 is merged with G5 reducing the clock gate count by 1)

Concepts – Source latency update
• Before CTS
set_clock_latency –source 0 [get_clocks ck]
virtual – Network latency: 0 / not set
time
zero -3.5ns – Source latency: 0 / not set
0ns set_clock_latency –source -3.5 – Clock arrival time at flops: 0
pseudo timing graph representation
‘clock [get_pins ck]

object’ – Clock arrival time at IOs: 0
clock root pin
• After CTS & source latency update
set_clock_latency 0 – Clock insertion delay: 3.5ns
[get_clocks ck]
– Source latency change at clock input: -3.5ns
0ns – Clock arrival time at flops: 0
– Clock arrival time at IOs: 0
CTS insertion delay of 3.5ns
• Source latency adjustment
– Source latency is applied to clock inputs
average clock not clock objects
arrival time 0ns
– report_clocks still lists clocks as ‘ideal’,
set_db cts_update_clock_latency true* | false scope for future reporting improvement
set_ccopt_property update_io_latency true* | false
Concepts – CTS Skew vs Skew
CTE times using delay corner

CTS times using single half-corner –
with early & late derates, min &
delay corner with late derates, max
max delays/caps, and CPPR
delays/caps
Global skew Local skew
• Sink 1 : 2.0*1.1 = 2.2 • Launch : 2.0*1.1 = 2.2

including late derates including late derates
• Sink 2 : 1.9*1.1 = 2.09 • Capture : 1.9*0.9 = 1.71

including late derates including early derates
• Skew = 2.2-2.09 = 0.11 • Skew = 2.2-1.71 - CPPR

= 0.49 - CPPR
Note: Similar situation with SOCV delay sigma – CTS excludes, CTE includes
18.1
Concepts – Antenna diodes
input port
block design
• Some flows have antenna diodes present pre-CTS
– For example if added at clock input ports during top level preserved
partitioning
• Antenna diodes connected directly to a clock input port internal

– Remain connected directly to that clock input port flops
– Are not re-placed by CTS, expectation is the initial placement is
sensible
deleted
– Are treated as an ignore pin by CTS
• Antenna diodes found anywhere else in a clock tree

– Deleted by CTS, unless they are dont_touch

18.1
Concepts – Port isolation buffers
input port
block design
• ≤17.1 – Only input ports supported
– set_ccopt_property add_driver_cell <lib_cell>
– Add the specified cell at clock input ports, or two cells if inverter
– Global or per clock tree
internal
– Now obsolete, will be discontinued in a future release flops
• 18.1 – Per port control, input & output ports

– set_db port:ck .cts_add_port_driver base_cell:BUFX2
– set_ccopt_property add_port_driver BUFX2 –pin ck
– If using inverters, only one inverter placed near the port, other
inversion can be freely combined with CTS and/or shared with other
ports.
output port

18.1
Concepts – Per power domain transition targets
• ≤17.1 Does not support per power domain max

transition targets
low volt
– Transition target applied to entire design
– Problem if some power domains are low voltage and the
target for normal voltage power domains is not achievable in
the lower voltage
• 18.1 Permits indexing by power domain

– set_db cts_target_max_transition_time ...
–index power_domain:<pdname>
• Note transition target is applied to the effective power

domain

18.1
Concepts – Instance naming
• ≤17.1 Problems
– Temporary ‘uid’ names appeared in the log but
renamed before CTS completes
– Clock name depends on SDC ordering if more than
CTS_ccl_BUF_TCLK_G2
one parent _L12_2
– Level numbers often incorrect, e.g. post-route repair
• 18.1 Solution
– Avoids all the problems with the old scheme
– Easy to write down with pencil & paper
CTS_ccl_buf_1234
– The number is unique over all CTS inserted cell
instances

Concepts – Worst chain
T
clock
• Worst chain reports in the

log for
– Extreme effort CCOpt
G
– Early clock step
– Look for worst chain
report(s) after skewing
steps and not after re-
clustering steps
– Log shows ASCII art
representation
• Example shows looping chain with ICG • Reporting at other flow

– Adjusting clock delays to the ICG can impact sinks under the ICG steps is not recommended
• Other possibilities include
– Loop without ICG – Chain starting and/or ending at an IO
– Macro – Loop between an ICG driving a single sink
Concepts – Clock groups
ck
create_clock ck
• Avoid balancing [get_ports {ck}]
clocks which are create_generated_clock

asynchronous -name gck
-source
according to [get_pins {d1/CK}]
set_clock_groups or -master_clock d1
[get_clocks {ck}] d1
clock-to-clock false gck
gck
paths set_clock_groups
-group {ck}
• Common case is –group {gck}
or
generated clock set_false_path
asynchronous to –from [get_clocks ck]
–to [get_clocks gck]
master clock set_false_path
–from [get_clocks gck] master generated
master generated
–to [get_clocks ck] clock clock
clock clock flops flops
• User control: flops flops
set_db timing_connectivity_based_skew_groups off setting clock_false_path

off* | clock_false_path single skew group separate skew groups
Concepts – Skew vs insertion delay conflict
sg1 sg2 sg1 sg2
Delay to balance 50 Delay to balance 50
sinks with 100,000 sinks with 100,000
Delay to must go here can go here
match
“red”
delay create_gene
ends up rated_clock
here logic –master_clk logic
sg2
2000 50 100,000 2000 50 100,000

sinks sinks sinks sinks sinks sinks
Significant cluster buffering

delay due to large sink count
Clone the mux to resolve the problem
• Complaint – Insertion delay of sg1 is increased significantly between cluster and balance
steps – this is necessary to balance the skew within sg1 and skew within sg2
• General case – a net with different sets of skew groups at it’s immediate fanout
– In the example above the mux has one fanout with {sg1,sg2} and one fanout with {sg2}
Clock Power

Clock Power – Placement impact
• Clock power is significantly influenced by flop placement
– Leaf level clock gating divides flops into groups
– Tight non-overlapping placement of each group key to clock power reduction
• Design mode power effort or placement controls
set_db design_power_effort none|low|high
OR
set_db place_global_clock_power_driven true
set_db place_global_clock_power_driven_effort standard|high
(set_db place_global_clock_gate_aware false)
F F
F F
F F F IC F
Bad F F F IC F G Good
F IC F IC
for F G
G F
G F FF for
clock F IC F F F
IC F F IC F F IC F clock
power
G F G
F
G G power
F F F F F F F
F F
F
Clock Power– Buffering under leaf ICGs
• High up ICGs with

buffering sub-tree – good
for power
• Many ‘leaf’ ICGs having 1-

3 buffers/inverters under
them – something is
probably wrong
– Check placement, transition
target, leaf NDR/vias, max
fanout constraint

Flexible H-tree & multi-tap

Flexible H-tree – Flow H-tree with early clock flow
• Build H-tree before CTS, or create_clock_tree_spec

before placement if using … early clock flow & CTS
ECF configuration here ...
check vias or
use stacked vias
• Further details in App Note Top routing rule NDR
create_route_type … -shield_net …
– “Flexible H-tree and Multi-Tap Clock Flow in set_db cts_route_type_top ...
Innovus”, support.cadence.com
set_db
H-tree transition constraint
cts_target_max_transition_time_top …
create_flexible_htree …
Define H-tree(s)
[create_flexible_htree …]
Build/Debug H-tree(s) synthesize_flexible_htrees …
Multi-tap in ECF place_opt_design
Multi-tap CTS ccopt_design

18.1
Flexible H-tree – New algorithm
• Redesigned algorithm
– Makes trade-offs between turns, source-to-sink and
net length balancing
– Works on EGR routing grid instead of coarse grid, for
improved routing – especially around power grid
• Reduced wire length and power Less of this
• Gives a more ‘clean looking’ H-tree structure
Design Skew (ps) Max latency (ps) Wire length (um) Runtime (s)
old new old new old new old new
1 2.46 0.71 100 100 -0% 3529 2765 -22% 1067 316 -70%
2 3.50 0.10 78 88 +13% 5171 5430 +5% 672 678 +1%
3 0.18 0.25 151 150 -1% 2699 2814 +4% 204 241 +18%
4 2.37 0.61 155 145 -6% 2447 2614 +7% 39 77 +97%
5 4.21 1.50 79 68 -14% 1258 1089 -13% 167 171 +2%
6 2.30 1.40 63 44 -31% 1091 1093 +0% 167 171 +2%
7 28.71 7.72 204 186 -9% 37068 33792 -9% 3051 2852 -7%
8 1.05 0.11 102 54 -47% 3281 3086 -6% 383 216 -44%
9 9.24 5.75 231 206 -11% 17877 15624 -13% 7941 3533 -56%
10 32 36 721 664 -8% 66699 53420 -20% 3895 3870 -1%
18.1
Flexible H-tree – New algorithm – Stress test 60 sinks
OLD NEW
Wire length 15141um Wire length 14598um

Skew 12ps Skew 4ps

Flexible H-tree – Distance based mode & debug
• Distance mode DRV checks • Dry run and image debug output
-mode {drv | Specify distance to enable the distance
distance} based mode. The default is drv.
- Specify the maximum permitted total
max_driver_distance
<value in um> length of any net driven by an H-tree
driver. Both -mode distance and -
max_driver_distance must be
specified together.
-max_root_distance Specify the maximum permitted total
<value in um>
length of the net driven by the H-tree
root pin. Defaults to the
max_driver_distance setting if not
specified.
• Debug – Build the H-tree based on

expected max distances, then debug
mkdir debug
issues such as large transition times due create_flexible_htree
to incorrect via setup -image_directory debug ...
synthesize_flexible_htrees -dry_run
Flexible H-tree – Clock spec updates
create_skew_group
-name flexible_htree_myhtree/reporting_only
-constrains none -source ck
-sinks {...}
clock_tree ck
• Clock tree source group
skew_group ck
and generated clock
trees added – needed
for multi-tap CTS
• Reporting only skew

group added
clock_tree_source_group myhtree
generated clock_tree
flexible_htree_myhtree_0...3

18.1
Multi-tap – Clustering based tap assignment
• Cluster driven tap • This setting not required
assignment is cts_spec_config_create_
default (16.21), clock_tree_source_groups
targets limited extract_balance_multi_
increase in ICG source_clocks
count – Continue to use only if
requiring clock spec creation to
boundary
create clock tree source groups
few um
for multi-source SDC clocks
DFF
DFF • Improved support for fine
tap grids
ICG
– Auto maximum radius per
tap avoid ‘reaching too far
over’ other taps (18.11)
set_db cts_clustering_source_group_max_cloned_fraction 0.2
set_ccopt_property – Less need to increase the
clustering_source_group_max_cloned_fraction 0.2 permitted amount of clock
gate cloning
cloning
Multi-tap – Debug tips – Uncloneable nodes A A G
G G
B B
• Log output – all clear

There are no uncloneable nodes in this source group
• Uncloneable nodes are the

• Log output – check if expected or not most common cause of
– check_design also checks this
bad multi-tap QOR
Uncloneable nodes:
-------------------------------------------------------------------------------------
Node Level Downstream Sinks Reasons
-------------------------------------------------------------------------------------
block_icg_0 5 3081 dont_touch.user
some/dont_touch_buffer/here/i0 2 5 dont_touch.user
some_other/dont_touch_buffer/i1 1 4 dont_touch.user
a/leaf/level/mux/driving/one/sink 0 1 dont_touch.user
-------------------------------------------------------------------------------------
Multi-tap – Debug tips – Tap allocation
• Log output – tap allocation stats

– Check for unused taps
– Check for taps with disproportionate number of sinks or very large radius
[CLU] Tap allocation statistics:

[CLU] tap anchor size radius hpwl mst L1ICGs
[CLU] ============================================================================
[CLU] clk_0 ( 138.560, 63.220) 1419 160.78 322.97 8161.65 49
[CLU] clk_7 ( 297.792, 63.220) 1672 167.35 311.98 9721.78 82
[CLU] clk_1 ( 138.560, 168.820) 1694 176.90 325.37 8822.09 59
[CLU] clk_8 ( 297.792, 168.820) 1706 136.89 347.87 9208.19 71
[CLU] clk_2 ( 138.560, 274.420) 2004 151.03 378.45 11453.22 69
[CLU] clk_9 ( 297.792, 274.420) 5317 155.82 344.99 18088.76 593

Multi-tap – Debug tips – Cluster CTS
• Check cluster only CTS

– Insertion delay under each tap buffer should be roughly the same if the tap
locations and tap assignment are good
– Taps with less delay will be padded out by CTS to match the slowest sub-tree
18.1
Multi-tap – Merging between taps
Initial section of CTS flow
• CTS merges (de-clones) clock gates & logic and
then performs tap assignment
• ≤17.1 Merge did not merge between taps Remove existing drivers
– Existing cloned clock gates under different taps would
remain as clones and be allocated to new taps, perhaps Merge
even the same tap, or perhaps be cloned further
Tap assignment
• 18.1 enables merging between taps by default
• Important for flows which perform tap assignment Clustering
more than once
– Early clock flow
– User assign_clock_tree_source_groups before
CTS Note: Known corner case: Tap
– Additionally tap assignment approximately places clones assignment can clone clock gates
leading to macros/memories but merging
does not merge such clock gates by
default.
Multi-tap – Tap buffer sizing
• Clock tree sources resizable by CTS

– Aids balancing
– Downsizing saves power, e.g. on lightly
loaded tap buffer
– Only clock sources which are buffers,
Resizable
inverters, clock gates, or single output
logic can be sized
set_db cts_size_clock_sources true

set_db cts_clock_source_cells <list> <base cell names>
set_ccopt_property size_clock_source true
set_ccopt_property clock_source_cells <base cell names>

Common User Interface (CUI) inst:cts_cui

CUI – Legacy property behavior refresher
• Generic form
– set_ccopt_property <property name> <value> [-<object_type> <object name>]
– get_ccopt_property <property name> [-<object_type> <object name>]
• What happens when object/index is not specified?
– set_ccopt_property target_skew 0.123
– Sets skew target on all existing skew groups as well as the skew target used for any future created skew groups
– get_ccopt_property target_skew
– Returns single value only if all skew groups and the ‘unkeyed’ value used for new skew groups are same setting
– Otherwise returns an unfriendly list of skew group names and targets not accepted by set_ccopt_property
• Known as “Last one wins”

– No rule which says per skew group value overrides global value
– Easy to overwrite existing settings
• Used for all index types except for delay_corner
– delay_corner defaults to the primary half corner, and ‘late’ is assumed by default
18.1
CUI – 18.1 Cleanup
• Major review of public CUI attributes and commands – CUI production status
• Some changes are not 100% backward compatible – this was unavoidable
– Most users will NOT have a problem
– Scripts configuring standard settings should continue to work, perhaps with warnings
• Attribute naming and cleanup
– Many attributes renamed – old names continue as aliases and issue a warning
– Many attributes which should have been private are now private
– ‘Exploded’ attribute names with _early/late, _min/max, _rise/fall suffixes hidden
– cts_<attribute> becomes equivalent to cts_<attribute>_late_max_rise
– Attributes which exist on root and other object types
– get_db returns only the root setting, not an unfriendly list
– Attributes which only make sense on individual objects removed from root
– Newer attributes accept and return DPOs
– Some less used attributes to be cleaned up in 18.2 Note: “root” means “CUI root object”,
• No plan to apply cleanup to legacy UI not the root of a clock tree
18.1
CUI – Commands
• Legacy (LUI) CCOpt commands mapped to CUI commands

– get_common_ui_map <legacy command name>
• DPO = Tcl Dual Ported Object
– To the user looks like object_type:name, for example clock_tree:clk1
– Compare to plain text name clk1
• Commands now accept DPOs
– Example: report_skew_groups –skew_groups skew_group:clk1
– Commands continue to accept plain text names for compatibility
– Note: Some internal debugging and private commands may not accept DPOs
• Use get_db instead of get_ccopt_* & get_clock_tree_*
– Previous CUI get_clock_tree_* commands to get cells, instances, sinks are deprecated
– Example:
get_common_ui_map get_ccopt_clock_tree_cells
suggests using get_db clock_trees .insts
18.1
CUI – Attributes – Overview
• Legacy CCOpt properties mapped to CUI CTS attributes

– get_ccopt_property_common_ui_map <legacy property name>
– Note: All properties are mapped, not just public ones, private attributes subject to future review
• Types of indexing
– By attributes on different object types: skew_group, clock_tree
– By net type: top/trunk/leaf
– By object type: power_domain, delay_corner, ...

18.1
CUI – Attributes – Common Get Examples
• Getting clock trees

– get_db clock_trees
• Getting skew groups
– get_db skew_groups
• Getting clock tree instances
– get_db clock_trees .insts get_db clock_tree:clk1 .insts
• Getting clock tree nets
– get_db clock_trees .nets get_db clock_tree:clk1 .nets
• Getting clock tree sinks and source
– get_db clock_trees .sinks get_db clock_tree:clk1 .source
• Getting skew group sinks, active sinks, ignore pins and sources
– get_db skew_group:ck .sinks get_db skew_group:ck .sinks_active
– get_db skew_group:ck .ignore_pins get_db skew_group:ck .sources

18.1
CUI – Attributes – Common Set Examples
• Setting skew target for current and future defined skew groups
– set_db cts_target_skew 200ps
• Setting max transition target

– set_db cts_target_max_transition_time 150ps
• Setting route type assignments

– create_route_type –name trunkrt ...
– set_db cts_route_type_trunk trunkrt
• Setting a pin insertion delay

– set_db pin:mem0/ck .cts_pin_insertion_delay 1ns

18.1
CUI – Attributes – Naming convention
• Attributes on root always have cts_ prefix
– Corresponding attribute on CTS specific object, e.g. skew_group, has the same name
– Exceptions are ccopt_ and ctd_ prefix for useful skew controls and clock tree debugger
– Example: cts_target_skew
• Attributes only on CTS objects have cts_<object_type> prefix for consistency, and
clarity
– Example: skew_group:sg1 .cts_skew_group_constrains
• Attributes on other DB objects, e.g. pin/port/inst have cts_ prefix
– Example: pin:f0/ck cts_sink_type
– Note: cts_pin_insertion_delay is an exception
• Attributes controlling create_clock_tree_spec have prefix cts_spec_config_
– Example: cts_spec_config_create_clock_tree_source_groups
• DB related attributes, i.e. pins/nets/insts on CTS objects are unprefixed
– Example: get_db skew_group:ck .sinks_active
18.1
CUI – Attributes – Indexing – Root vs specific objects
• Some attributes exist on both the root object and on specific CTS objects
– Technically these are different attributes, but they have the same name
• Set/reset the attribute on root also sets/resets the attribute on all CTS objects
• Getting the attribute on root returns the root attribute value only
• Example root sg1 sg2
set_db cts_target_skew 0.1 set all to 0.1 0.1 0.1 -
get_db cts_target_skew root returns 0.1 0.1 0.1 -
set_db skew_group:sg1 .cts_target_skew 0.2 set sg1 to 0.2 0.1 0.2 -
get_db cts_target_skew root returns 0.1 0.1 0.2 -
create_skew_group –name sg2 ... create sg2 0.1 0.2 0.1
get_db skew_group:sg1 .cts_target_skew sg1 returns 0.2 0.1 0.2 0.1
set_db cts_target_skew 0.3 set all to 0.3 0.3 0.3 0.3
18.1
CUI – Attributes – Indexing – Net type
• Attribute name with net type suffix
– <base name>_top, <base name>_trunk, <base name>_leaf
– Set the attribute for a particular net type only
– Example: create_route_type –name trunkrt ...
set_db cts_route_type_trunk trunkrt • cts_route_type_<nettype>
is a special case, as plain
cts_route_type attribute is
• Attribute name without net type suffix not defined
– <base name>
– Get always returns a Tcl dict as a list: top <value> trunk <value> leaf <value>
– Set using a single value to change top, trunk and leaf setting
– Set using a Tcl dict to set one or more of top, trunk and leaf
– See man dict for more information on Tcl dict
– Only exists for some attributes, notably plain cts_route_type is not available
– Example: > get_db cts_target_max_transition_time
top 0.15 trunk 0.15 leaf 0.15
18.1
CUI – Attributes – Indexing – -Index
• Indexing by other objects

– get_db/set_db -index
– Specify index type and index value
– Example: set_db cts_inverter_cells <list> -index power_domain:pd_lowvolt
• If index is not specified

– set_db : Setting applies to all possible values of the index, e.g. all power domains
– get_db : Value returned applies to ‘unindexed’ use, e.g. the value which is used for power
domains which do not have a power domain specific value set
– Special case: If -index delay_corner:name is not specified then the get/set operation
applies only to the currently set primary half corner.

18.1
CUI – Examples
> highlight [get_db clock_trees .nets
-if {.cts_net_type == leaf}] -color green
> highlight [get_db clock_trees .nets
-if {.cts_net_type != leaf}] -color red
> set clock_wire_length [tcl::mathop::+ {*}[

get_db -unique clock_trees .nets.wires.length]]
804.69
> set icg_power [tcl::mathop::+ {*}[get_db

[get_db -unique clock_trees .insts
-if {.cts_node_type == clock_gate}] .power_total]]
0.1322357
Support & Feedback
• Support
• Cadence Support Portal provides access to support resources, including an extensive
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• Feedback
• Email comments, questions, and suggestions to content_feedback@cadence.com.
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Innovus 18.

Innovus Product Engineering

3 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

4 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

5 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

set_db opt_useful_skew_pre_cts true* | false

8 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

setOptMode –usefulSkewPreCTS true* | false

9 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

10 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• check_design –type cts

12 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• Overriding the route type for a particular net

13 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

15 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• CTS will filter the supplied cell lists 10

– Improved clock QOR and run-time

16 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• Report on why CTS rejected cells which the user specified

• Report included in verbose log (innovus.logv) output near start of CTS

17 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

18 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

2.3 M 2.3G/16 436 114 120

119 17.1 • All ≤16nm

20 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

Sounds straightforward, but now timing is with propagated clocks:

21 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

ck1 ck2 skew

22 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

update_skew_group –skew_group ck/mode0

Implementation optimize insertion delay and power, balancing

EGR Post-Conditioning early global route, area reclaim, DRV repair

Clock Routing detailed routing along early global route guides

NR Post-Conditioning DRV and skew repair

Post-CTS Optimization scan re-order, datapath optimization, useful skew

• Coloring by clock tree, skew • Dotted line

• 18.1 CTS DOES NOT SIZE USER DON’T TOUCH INSTS

• How to say don’t touch but permit resize

29 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• CTS warning message

• Check design warns about don’t touch instances

• Default behavior is to generate and apply

34 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

Total clock gates: 5

35 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

‘clock [get_pins ck]

CTE times using delay corner

Global skew Local skew

• Sink 1 : 2.0*1.1 = 2.2 • Launch : 2.0*1.1 = 2.2

• Sink 2 : 1.9*1.1 = 2.09 • Capture : 1.9*0.9 = 1.71

• Skew = 2.2-2.09 = 0.11 • Skew = 2.2-1.71 - CPPR

• Antenna diodes connected directly to a clock input port internal

• Antenna diodes found anywhere else in a clock tree

38 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• 18.1 – Per port control, input & output ports

39 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• ≤17.1 Does not support per power domain max

• 18.1 Permits indexing by power domain

• Note transition target is applied to the effective power

40 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

41 © 2018 Cadence Design Systems, Inc. All rights reserved worldwide..

• Worst chain reports in the

• Example shows looping chain with ICG • Reporting at other flow

clocks which are create_generated_clock

• Sink 1 : 2.01.1 = 2.2 • Launch : 2.01.1 = 2.2

• Sink 2 : 1.91.1 = 2.09 • Capture : 1.90.9 = 1.71