CSE 2006 –

Microprocessors and
Interfacing
Module – 1
Pin Diagram, Memory Segmentation

Dr. K. Chitra
Professor
School of Electronics Engineering
VIT University, Chennai
1
Pin Configuration of 8086

2
Signal Description –Common for MAX/MIN
mode
AD15-AD0
• Time multiplexed I/O address and data lines
• Address available during T1 state
• Data available during T2,T3,Tw,T4 state
• Where T1,T2,T3,Tw&T4 are clock state of machine
cycle
A19/S6,A18/S5,A17/S4,A16/S3
• Time multiplexed address and status lines
• Address available during T1
• Status information available at T2,T3,Tw,T4
3
• S4 & S3 indicates segment registers currently used for
memory access

• S6 address is always low

• S5 indicates interrupt enable flag bit
BHE/S7 –Bus High Enable
• Indicates the data transfer over D15-D8 higher order
• Used to select odd address memory banks
• Status information is available at T2,T3,T4
• S7 is not currently used

4
RD-Read
• When it is low indicates the peripherals that processor is performing
memory or I/O read operation
READY
• It indicates acknowledgement from the slow devices or memory that they
have completed data transfer
5
6
INTR-Interrupt request
• Level Triggered input
• When, it is 1 CPU prepares to service the interrupt
• If any Interrupt request is pending,CPU enters Interrupt ack cycle

TEST
• This is examined by the WAIT instruction
• If low, execution will continue
• Else processor remains idle

NMI-Non Mask able Interrupt

• This is edge triggered input
• NMI is not maskable internally by software
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RESET -clears all the CS,DS,ES,SS and starts new execution

CLK -Clock input provided basic timing for processor and bus
control activity

VCC -+5V power supply

GND-ground

MN/MX- Decides whether the processor is to operate in either

Minimum mode (Single processor) Or Maximum Mode
(Multiprocessor)

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Following pin function of Minimum Mode
operation
M/ I/0 –Memory / I/O
• When it is low indicates CPU is having I/O operation
• When it is high indicates CPU is having memory operation

INTA –Interrupt Acknowledgement

• When it goes low indicates processor has accepted the
interrupt

ALE –Address Latch Enable

• Indicates availability of valid address on address/data lines

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DT/R – Data Transmit /Receive
• Decides the direction of flow through buffer
• If high, Processor sends data out
• Else ,Processor receives data

DEN –Data Enable

• Indicates availability of valid data address/data lines
• Used to enable transceivers to separate data from the
multiplexed address and data segment

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HOLD/HLDA - Hold/Hold Ack

• When it is high ,indicates that another master is requesting

bus access

• On receiving HOLD request processor issues hold

acknowledgement HLDA

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Following pin function are applicable for Maximum
Mode
S2,S1,S0 -Status Lines
• Indicates type of operation carried by the processor

12
LOCK
• While low,it indicates that the other system will be
prevented by accessing the system bus

QS1,QS0 -Queue Status

• Gives information about the status of code prefetch
queue(Instruction queue)

13
RQ/GT0 , RQ/GT1 –Bus Request/Bus Grant
• These pins are used by the other local bus master in
Max mode
• Force the processor to release the local bus
• It is similar to HOLD/HLDA of minimum mode
• Processor communicate that the request is granted by
grant signal

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Physical Memory Organization
• 1 Mbyte memory is physically organized as odd bank and even bank
each of 512 Kbytes
• Addressed in parallel
• Byte(word) data with even address is transferred to D7-D0
• Byte data with odd address is transferred to D15-D8
• BHE & A0 used to choose the banks

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