ANNAMACHARYA INSTITUTE OF

TECHNOLOGY AND SCIENCES

BY
J. BHAVYA SREE
Under the guidance of
Dr.A.Maheswara Reddy M.Tech., Ph.D.
A 64-Bit Implementation of Parallel Prefix
Adder With Less Hardware Complexity
 Objective
To reduce the delay and design complexity of
Kogge Stone Adder.
Introduction

 Adders play an important role for performing

the basic arithmetic operations, such as addition,
substraction,multiplication,division.
 A Parallel prefix adder is considered effective
adder for performing the addition of two multi
bit numbers.
Existing System
 KSA is parallel prefix from carry look ahead
adder,which has minimum delay.
 Kogge stone adder is widely used in high
performance applications.
Internal diagrams
a b g h gprev g h gprev hprev h g

c
g h
g g h s
g=a and b g=(h and gprev)or g g=(h and gprev)or g s=h xor g
h=a xor b h=h and hprev
Structure of KSA
a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0
Cin


g h g h g h g h g h g h g h g h

s4 s3 s2 s1
s5 s0
s7 s6
 0 0 0 0
0 0
a a a b Cin=0 For white cell
b b
g=a AND b
h=a XOR b
g h
(0)g h g h
(0) (0) (0) For gray cell
(0) (0)
g=(h AND gprev) OR g

g h (0) For black cell

(0) g=(h AND gprev) OR g
h=h AND hprev

S2=0 S1=0 S0=0

Binary example of 8 bit KSA
A=11111000
B=00010000
1 00001000
1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0

0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0

0 1 0 1 1 0 1 0 0 0 0 0 0

1 0 1 0 1 0 1 0 0 0

1 1 1 1

(0) (0) (1) (0) (0)

(0) (0) (0)
Simulation result of 16-bit KSA
Simulation result of 32-bit KSA
Simulation result of 64-bit KSA
Drawback

 High design complexity

Modified Parallel Prefix Adder

 Modified parallel prefix adder is developed for

reducing the hardware complexity of Kogge
stone adder.
Structure of modified PPA
a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0
Cin

g h g h g h g h g h g h g h g h

S4 S3 S2 S1 S0
S7 S6 S5
Binary example
A=11101100
B=11111111
011101011
1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 0

1 0 1 0 1 0 0 1 1 0 10 01 01

1 0 1 0 1 0 1 0 1 0 1 0 0

1 0 1 0 1 1

1 1 1 1

(1) (0) (1) (0) (1) (1)

(1) (1)
Simulation result of modified 16-bit PPA
Simulation result of modified 32-bit PPA
Simulation result of modified 64-bit PPA
Comparison Tables
Existing System

Type of PPA Number of Number of Delay(ns)

IOB’s LUT’s
16-bit 49 94 13.319
32-bit 97 220 15.729
64-BIT 193 456 18.938

Proposed System

Type of PPA Number of Number of Delay(ns)

IOB’s LUT’s
16-bit 49 31 4.381
32-bit 97 67 7.863
64-bit 193 209 8.947
Software Used

Xilinx 13.2 ISE design suite

Language

Verilog HDL
Applications

 Multipliers
 DSP operations
 Communications
Conclusion

 Finally conclude that modified PPA has less

delay and less complexity compare to
conventional adder.
Refrencess
[1] Geeta Rani, Sachin Kumar. “Delay Analysis of Parallel-Prefix
Adders”.International Journal of Science and Research (IJSR),
ISSN: 2319-7064, Impact Factor (2012): 3.358. Volume 3 Issue 6,
June, 2014. pp. 2339.
[2] Reto Zimmermann. Jkv Adder Architectures for Cell-Based VLSI
and their Synthesis. Thesis for the degree of Doctor of technical
sciences. Zurich. 1997. pp. 5-7.
[3] Sunil.M, Ankith.R.D, Manjunatha.G.D and Premananda.B.S.
Design and implementation of faster parallel prefix Kogge Stone
adder. International Journal of Electrical and Electronic Engeering
& Telecommunications 2014. ISSN 2319 – 2518. Vol. 3, No. 1,
January 2014. pp. 116.
THANK YOU
QUERIES