1

Behavioral Modeling
• Entity & Architecture
• Process statement
• Sequential statements
• Signal & Variable assignment
• Multiple Process
 2
Behavioral Modeling
• In this style of modeling, the behavior of the
entity is expressed using sequentially
executed, procedural code, which is very
similar in syntax to that of a high-level
programming language like C or Pascal.

• Process statement: Key to model the

behavior of an entity.
 Entity Declaration 3

• VHDL Syntax :
entity entity-name is
[generic( list-of-generics-and-their-types );]
[port( list-of-interface-port-names-and-their-
types );]
( entity-item-declarations ]
[begin
entity-statements ]
end [entity][ entity-name];
entity half_adder is port (
a,b: in bit;
CS: out bit_vector (1 downto 0);
end half_adder ;
 Entity Declaration 4

• Ports : Each i/o signal in entity declaration is referred to as a

port , which is analogous to a pin in a schematic symbol.
• A port is a data object which can be assigned values and used
in expressions.
• The set of ports defined for an entity is referred to as port
declaration.
• Each port we declare must have a name , a direction[mode],
and a data type.
• Modes : the modes describe the direction in which data is
transferred through a port.
• Can be one of four values : in, out, inout or buffer.
• If the mode of a port is not specified then the port is of default
mode in.
 5

Modes & their signal sources

 6

Modes & their signal sources

in: The value of an input port can only be read within the
entity model.[I.e. data flows only into the entity.]
out: The value of an output port can only be updated
within the entity model; it cannot be read.[I.e data
flows only from its source to the output port of the
entity.] So feedback is not allowed.
inout: The value of a bi-directional port can be read
and updated within the entity model.[I.e. used for bi-
directional lines]
buffer: The value of a buffer port can be read and
updated within the entity model. However, it differs
from the inout mode in that it cannot have more than
one source.Similar to mode out except that it does
allow for internal feedback.
 7
Architecture Body
• An architecture body
Associated with an entity.
Describes the internal view of an entity.
(i.e.functionality or the structure of the entity.)

• If the entity declaration is a black box , then

architecture body is the internal view of the black box.

• Three types of description is possible:

Behavioural : Process statement
Data flow : Concurrent signal assignment statement
Structural : Component Instantiations
 Architecture Body 8

• VHDL Syntax :
Architecture architecture name of entity-name is
[architecture-item-declarations ]
begin
concurrent-statements ; these are -->
process-statement
block-statement
concurrent-procedure-call-statement
concurrent-assertion-statement
concurrent-signal-assignment-statement
component- instantiation -statement
generate-statement
end [ architecture ][architecture-name ];
 9
Architecture Body
• All concurrent statements execute in parallel;
therefore, their textual order of appearance within the
architecture body has no impact on the implied
behavior.
• Items declared in the entity declaration, are available
for use within the architecture body due to the
association of the entity name with the architecture
body by the statement:
architecture architecture-name of entity-name is .
• An entity is represented using one entity declaration
( provides the external view) and one or more
architecture bodies (provide the internal view).
 Process Statement 10

VHDL Syntax :
[ process-label : ] process [(sensitivity-list) ][is]
[ process-item-declarations ]
begin
sequential-statements; these are -->
variable-assignment-statement
signal-assignment-statement
wait-statement
if-statement
case-statement
loop-statement
null-statement
exit-statement
next-statement
assertion-statement
report-statement
procedure-call-statement
return-statement
end process [ process-label ] ;
 Process Statement 11

• A process statement is a concurrent statement which contains

only sequential statements. It can exist in an architecture and
defined regions in the architecture where all statements are
sequential.
• A set of signals to which the process is sensitive is defined by
the sensitivity list. So each time an event occurs on any of the
signals in the sensitivity list, the sequential statements within
the process are executed in a sequential order, that is, in the
order in which they appear.
• The process then suspends after executing the last sequential
statement and waits for another event to occur on a signal in
the sensitivity list.
• Items declared in the item declarations part are available for
use only within the process.
• Every sequential statement can optionally have a label.
 Variable Assignment Statement 12

• Variables can be declared and used inside a process statement.

• Example
Signal A,Z:integer;
---
process (A)
variable v1,v2:integer := 3; -- Variable Declaration & initialization
begin
v1 := A - v2; -- variable assignment statement
Z <= -v1;
V2:= Z +v1*2;
end process;
 13
Variable Assignment Statement
• The expression (v1:=A-v2) is evaluated when the
statement is executed, and the computed value is
assigned to the variable object instantaneously, that
is, at the current simulation time.
• Variables are created at the time of elaboration and
retain their values throughout the entire simulation run
(like static variables in C). This is because a process
is never exited; it is either in an active state, that is,
being executed, or in a suspended state, that is,
waiting for a certain event to occur.
• A variable can also be declared outside of a process
or a subprogram. Such a variable can be read and
updated by more than one process. These variables
are called shared variables
 Signal Assignment Statement 14

• A signal assignment statement can appear

within a process or outside of a process.
– Outside : Concurrent signal assignment statement.
– Within : It is considered to be a sequential signal
assignment statement and is executed in sequence
with respect to the other sequential statements
which appear within that process.
• When a signal assignment statement is executed, the value of
the expression is computed immediately (current simulation
time), and this value is scheduled to be assigned to the
signal after the specified delay. If no after clause ("after
delay-value") is specified, the delay is assumed to be a default
delta delay.
• Example of signal assignment statement :
– COUNTER <= COUNTER + "0010"; -- Assign after a delta delay.
– Z <= (AO and Al) or (BO and B1) or (CO and C1) after 6 ns;
 15
Delta Delay
• A delta delay is a very small delay (infinitesimally small). It
does not correspond to any real delay, and actual simulation
time does not advance. This delay models hardware where a
minimal amount of time is needed for a change to occur.
• Each unit of simulation time can be considered to be
composed of an infinite number of delta delays. Therefore, an
event always occurs at a real simulation time plus an integral
multiple of delta delays. For example, events can occur at
• 15 ns, 15 ns +1, 15 ns + 2 & 22 ns, 22 ns + so on
 Signal v/s Variable Assignment 16

• Variable assignments cause variables to get their

values instantaneously, while signal assignments
always cause signals to get their values at a later
time (at least a delta delay later).
• Variable represent local storage ,as opposed to
signals, which represents circuit interconnects.
• When multiple assignments to a signal occur within
the same process statement,the last assigned value
will be the value propagated.
• Example Altera
 17
Wait Statement
• when a process has a sensitivity list, it always suspends after
executing the last sequential statement in the process.
• The wait statement provides an alternate way to suspend the
execution of a process.
• There are three basic forms of the wait statement,
– wait on sensitivity-list;-- signal changes
– wait until boolean-expression;--an expression is true .(At least one
of the values in the expression contain a signal ,b’cos only signals
have events on them & only signal can cause a wait statement to
reevaluate.)
– wait for time-expression ; --a specific amount of time

• They may also be combined in a single wait statement,like

wait on sensitivity-list until boolean-expression for time-
expression ;
 18
wait statement: examples
– wait on A,B, C;
– wait until A = B;
– wait for 10 ns; & Wait for 0 ns ;
– wait on CLOCK for 20 ns;
– wait until SUM > 100 for 50 ms;
– Wait until CLOCK=‘1’;
– wait on CLOCK until SUM > 100;
• It is possible for a process not to have an explicit sensitivity
list. In such a case, the process may have one or more wait
statements.It must have at least one wait statement;
otherwise, the process will never get suspended and would
remain in an infinite loop during the initialization phase of
simulation.
• It is an error if both a sensitivity list and a wait statement are
present within a process.
 19
If Statement
• An if statement selects a sequence of
statements for execution based on the value of
a condition. The condition can be any
expression that evaluates to a Boolean value.
VHDL Syntax :( BNF)(Bachus Naur Format)
if boolean-expression then
sequential-statements
{ elsif boolean-expression then -- 0 or more
sequential-statements }
{ else -- Optional
sequential-statements }
end if ;
 20
Case Statement
• VHDL syntax (BNF):
case expression is -- All possible values of the expression
-- must be covered exactly once
when choices => sequential-statements
when choices => sequential-statements
-- Can have any number of branches.
[ when others => sequential-statements]
--optional, To catch-all values,must be the last branch
end case;
• The case statement selects one of the branches
for execution based on the value of the
expression. The expression value must be of a
discrete type or of a one-dimensional array type.
 21
4-by-1 MUX Using CASE Statement
library IEEE;
use IEEE . STD_LOGIC_1164.all;
entity MUX is
port(A B, C, D: in STD_LOGIC;
CTRL: in STD_LOGIC_VECTOR(O to 1);
Z:out STD_LOGIC);
end MUX;
architecture MUX BEHAVIOR of MUX is
begin
PMUX: process (A, B, C, D, CTRL)
variable TEMP: STD_LOGIC;
begin
 22

4-by-1 MUX Using CASE Statement

case CTRL is
when "00" =>\
TEMP := A;
when "01" => TEMP := B;
when "10" => TEMP := C;
when "11" => TEMP := D;
when others => TEMP := 'X';
end case;
Z <= TEMP;
end process PMUX;
end MUX_BEHAVIOR;
 23
Null Statement

• null ,
is a sequential statement that does not
cause any action to take place;
execution continues with the next
statement.
• One example of this statement's use is in an
if statement or in a case statement where, for
certain conditions, it may be useful or
necessary to explicitly specify that no action
needs to be performed .
 24
Loop Statement
• A loop statement is used to iterate through a set of
sequential statements.
• VHDL syntax :
[ loop-label:] iteration-scheme loop
sequential-statements
end loop [loop-label];
• There are three types of iteration schemes:
1. For iteration scheme,
for identifier in range
For loop will loop as many times as specified in range.
– An example
FACTORIAL := 1;
for i in 2 to N loop
FACTORIAL := FACTORIAL * i;
end loop;
 25
Loop Statement
• The index value i is locally declared by the for statement,it does
not need to be declared explicitly in the process,function,or
procedure.If another variable of same name exists in the
process then these two variable are treated as separate
variables .

2. While iteration scheme,

• while boolean-expression
– An example
J := O; SUM := 10;
WH_LOOP: while J < 20 loop
SUM:=SUM*2;
J := J + 3;
end loop;
 26
Loop Statement
3 In third iteration scheme, all statements in the loop
body are repeatedly executed until some other action
causes the loop to exit. This action can be caused by
an exit statement, a next statement, or a return
statement.
• An example.
SUM := 1; J := O;
L2:loop --This loop also has a label.
J := J + 21;
SUM:= SUM* 10;
exit when SUM > 100;
end loop L2; -- This loop label, must be the same as the initial loop label.
 27
Exit statement
• The exit statement is a sequential statement
that can be used only inside a loop. It causes
execution to jump out of the innermost loop,(if
no loop label is specified ) or the loop whose
label is specified.
• VHDL Syntax :
exit [ loop-label ] [ when condition ] ;
• If the when clause is used, the specified loop is
exited only if the given condition is true;
otherwise, execution continue with the next
statement.
 28
Exit statement
Example one
Process (a)
Begin
First_loop :for I in 0 to 100 loop
Second_loop :for j in 0 to 10
------
exit Second_loop;
---------
exit first_loop;
end loop;
end loop;
End process;
Example two = Wait until a=b;
Loop
Wait on a,b;
Exit when a=b;
End loop;
 29
Next Statement
• The next statement is also a sequential
statement that can be used only inside a loop.
• VHDL syntax: Same as that for the exit
statement.
Next [ loop-label ] [ when condition];
• Current loop iteration of the specified loop to
be prematurely terminated; execution resumes
with the next iteration of this loop.
 30
Next Statement
Example

for J in 10 downto 5 loop

if SUM < TOTAL_SUM then
SUM := SUM + 2;
elsif SUM = TOTAL_SUM then
next;
else
null;
end if;
K := K + 1;
end loop;
 31

Assertion Statement
• Reporting textual string to the designer.
• VHDL Syntax:
assert boolean-expression
[report string-expression ]
[severity expression ] ;
• Checks the boolean expression :
– True: does nothing
– False:Output a user specified text string to the standard output to
the terminal with any of four severity levels: Note , warning,error
& failure.
Note: Inform the user that what is currently happening in the model
Warning: Alert the designer of conditions that,while not
catastrophic,can erroneous behavior later.
 Assertion Statement 32

• Error : Alert the designer of conditions

that,cause the model to work incorrectly or not
work at all.
• Failure : Alert the designer of conditions that
can have disastrous effect.
• Example, we may want to check if a signal
value lies within a specified range, or check the
setup and hold times for signal arriving at the
inputs of an entity. If the check fails, a message
is reported.
• It is currently ignored by synthesis tools.b’cos It is
used for exception handling, no hardware is built.
 33
Report Statement
• Can be used to display a message. It is
similar to an assertion statement, but
without the assertion check.
• VHDL syntax:
report string-expression
[ severity expression ] ;
Example:
if CLR = 'Z' then
report "Signal CLR has a high impedance value.";
--Default severity level is NOTE.
end if;
if CLK /= '0' and CLK /= '1' then
report "CLK is neither a '0' nor a '1'!!!!"
severity ERROR;
end if;
 Inertial Delay Model 34

• Models the delays often found in switching Circuits.

• An input value must be stable for a specified pulse
rejection limit duration before the value is allowed to
propagate to the output.Value appears at the output
after the specified inertial delay.If the input is not
stable for the specified limit,no output change occurs.
• VHDL Syntax
Signal-object <= [ [ reject pulse-rejection-limit] inertial] expression
after inertial-delay-value;
• If no pulse rejection limit is specified, the default pulse
rejection limit is the inertial delay value itself .The pulse
rejection limit cannot be –ve or greater than the value of
the inertial delay.
• Default delay model ,no keyword need be explicitly
specified.Often used to filter out unwanted spikes and
transients on signals.
 35

Inertial Delay Model

 36
Transport Delay Model
• Models the delays in hardware that do not exhibit
any inertial delay.
• Represents pure propagation delay ,that is, any
changes on an input are transported to the output, no
matter how small, after the specified delay.
• Keyword transport must be used in a signal
assignment statement.
Z<= transport A after 10 ns;
• Ideal delay modeling can be obtained.In this case,
spikes would be propagated through instead of being
ignored, as in the inertial delay case.
 37
Transport Delay Model
 38
Creating Signal Waveforms
• It is possible to assign multiple values to a
signal,each with a different delay value. For
example,
PHASE1 <= '0', '1' after 8 ns, ‘0' after 13 ns, '1' after 50 ns;

• Each waveform element has a value part, specified by

an expression, and a delay part, specified by an after
clause that specifies the delay.The delays in the
waveform elements must appear in increasing order.
• If no pulse rejection limit is specified in an assignment
using inertial delays,the delay of the first waveform
element becomes the default pulse rejection limit.
 39

Signal Drivers
• A driver is created for every signal that is assigned a
value in a process. The driver of a signal holds its current value
and all its future values as a sequence of one or more
transactions,where each transaction identifies the value to
appear on the signal along with the time at which the value is to
appear.
• An Example
process
begin
RESET <= 3 after 5 ns, 21 after 10 ns, 14 after 17 ns;
end process;
• All transactions on the driver are ordered in increasing order of
time. A driver always contains at least one transaction, which
could be the initial value of the signal.
 40
Effect of Transport Delay on Signal Drivers
Example 1:signal RX_DATA: NATURAL;
process
begin
RXDATA <= transport 11 after 10 ns;
RXDATA <= transport 20 after 22 ns;
RXDATA <= transport 35 after 18 ns;
end process; -- 11@ t+10 ns,35@t +18ns
Rules for adding transactions from a signal assignment
using transport delays
•All transactions on the driver that occur at or
after the delay time of the first new transaction
are deleted.
• All the new transactions are added at the end
of the driver.
 41
Effect of Inertial Delay on Signal Drivers
• When inertial delays are used, both the signal
value being assigned and the delay value affect
the deletion and addition of transactions.
• Example 1
process
begin
TX_DATA <= 11 after 10 ns;
TX_DATA <= reject 15 ns inertial 22 after 20 ns;
TX_DATA <= 33 after 15ns;
Wait;
End process;-- 33@15ns
 42
Effect of Inertial Delay on Signal Drivers
Rules for adding transactions from a signal assignment
using inertial delays are the following:
1. All transactions on a driver that are scheduled to occur
at or after the delay of the first new transaction are
deleted.(as in the transport case)
2. Add all the new transactions to the driver.
3. For all the old transactions on the driver that occur at
times between the time of the first new transaction (say
F) and F minus the pulse rejection limit, delete the old
transactions whose value is different from the value of
the first new transaction.
 Multiple Processes 43

• Since a process statement is a concurrent

statement, it is possible to have more than one
process within an architecture body.
• Processes within an architecture body
communicate, with each other using signals
that are visible to all the processes·
• When multiple processes exist within an
architecture body, it is possible for more than
one process to drive the same signal. In such a
case, that signal has multiple drivers and the
effective value of the signal is obtained by using
a resolution function.
 44

Multiple Processes
 Multiple Processes
entity INTERACTING is
45

port (SERIAL_IN, CLK: in BIT;

PARALLEL_OUT:out BIT_VECTOR (0 to 7));
end INTERACING;
architecture PROCESSES Of INTERACTING is
Signal READY, ACK: BIT
Signal DATA: BIT_VECTOR (O to 7);
Begin
RX: process
begin
READ_WORD (SERIAL_IN, CLK, DATA);
READY <= 'I';
wait until ACK = 'I';
READY <= '0';
wait for 40 ns;
end process RX;
MP: process
begin
wait for 25 ns;
PARALLEL_Out<.= DATA;
ACK <= ‘1', 'O' after 25 ns;
wait until READY = '1';
end process MP;
end PROCESSES;
 46

Thank you
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 53
If Statement
• The if statement is executed by checking
each condition sequentially until the first true
condition is found then, the set of sequential
statements associated with this condition is
executed.
• The if statement can have zero or more elsif
clauses and an optional else clause(maximum
one).It is a sequential statement.
 54

type WEEK_DAY is (MON,TUE, WED, THU, FRI, SAT,

SUN);
type DOLLARS is range O to 10;
variable DAY: WEEK_DAY;
variable POCKETMONEY: DOLLARS;
case DAY is
when TUE => POCKET_MONEY := 6;
when MON | WED => FOCKETMONEY := 2;
when FRI to SUN => POCKETMONEY := 7;
when others => POCKET_MONEY := 0;
end case;
Example: entity DFF is 55
port ( D, CK: in BIT; Q, NOTQ: out BIT);
end DFF;
architecture CHECK_TIMES of DFF is
constant HOLD_TIME: TIME := 5 ns;
constant SETUP_TIME: TIME:= 3 ns;
begin
Process( D,CK)
variable LastEventOnD, LastEventOnCk: TIME;
Begin -- Check for hold time:
if D'EVENT then
assert NOW = O ns or
(NOW - LastEventOnCk) >= HOLD_TIME
report "Hold time too short!"
severity FAILURE;
LastEventOnD := NOn~
end if;
if CK = '1' and CK'EVENT then -- Check for setup time:
assert NOW = O us or
(NOW - LastEventOnD) >= SETUPTIME
report "Setup time too short! "
severity FAILURE;
LastEventOnCk := NOW;
end if;
if CK = '1' and CK'EVENT then --BehaviorofFF:
Q <= D;
NOTQ <= not D;
end if;
end process; end CHECK_TIMES;