Agenda

Introduction to ARM Ltd

Programmers Model
Instruction Sets
System Design
Development Tools

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 ARM Partnership Model

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 ARM Powered Products

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 Programmers Model
The structure of the ARM
architecture
How it has developed
Register set, modes and
exceptions
The endian issue

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 The ARM Architecture

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R
TM
15 L D
 Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set

 Jazelle cores can also execute Java bytecode

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 Processor Modes

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 Current Visible Registers
The ARM Register Set
r0
Abort Mode
r1
r2
r3 Banked
Current Visible Registers r4
r5
r0
Undef
SVCMode
IRQ
FIQ
User Mode
Mode
Mode
Mode r6 User FIQ IRQ
r1
r7
r2
r8 r8
r3
r9
Banked out Registers r9
r4
r10 r10
r5
r6 User FIQr11 IRQ SVC r11
Undef Abort
r12 r12
r7
r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r8 r8 r8
r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r9 r9 r9
r15 (pc)
r10 r10 r10
r11 r11 r11
cpsr
r12 r12 r12
spsr spsr spsr
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

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 Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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 Program Status Registers

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 Program Status Registers
 Condition code flags
 N = Negative result from ALU
 Z = Zero result from ALU
 C = ALU operation Carried out
 V = ALU operation oVerflowed
 Sticky Overflow flag - Q flag
 Architecture 5TE/J only
 Indicates if saturation has
occurred
 J bit
 Architecture 5TEJ only
 J = 1: Processor in Jazelle state
39v10 The ARM Architecture
 Interrupt Disable bits.
 I = 1: Disables the IRQ.
 F = 1: Disables the FIQ.
 T Bit
 Architecture xT only
 T = 0: Processor in ARM state
 T = 1: Processor in Thumb state
 GE for SIMD instructions
 Mode bits
 Specify the processor mode
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 Program Counter (r15)

 When the processor is executing in ARM state:

 All instructions are 32 bits wide
 All instructions must be word aligned
 Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

 When the processor is executing in Thumb state:

 All instructions are 16 bits wide
 All instructions must be halfword aligned
 Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

 When the processor is executing in Jazelle state:

 All instructions are 8 bits wide
 Processor performs a word access to read 4 instructions at once

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 ‘s memory organization
 Byte addressed memory
 Maximum 232 bytes of memory NB
NB--Lowest
Lowestbyte
byte
 A word = 32-bits, half-word = 16 bits address
address== LSB
LSBof
of
 Words aligned on 4-byte boundaries word
word
“Little-endian”
“Little-endian”
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16
Word
Wordaddresses
addresses
follow
followLSB
LSBbyte
byte
12
address
address
8

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