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Design For Test: Digital Integrated Circuits © Prentice Hall 1995 Design Methodologies
Design For Test: Digital Integrated Circuits © Prentice Hall 1995 Design Methodologies
for Test
DFT Mantra
Provide controllability and observability
Module Module
M state regs
0 sa0
(output)
1
sa1
(input) Covers almost all (other)
occurring faults, such as
opens and shorts.
Z , : x1 sa1
x1
: x1 sa0 or
x2
x3 x2 sa0
: Z sa1
Digital Integrated Circuits Design Methodologies © Prentice Hall 1995
Problem with stuck-at model:
CMOS open fault
x1 x2
Z
x1
x2
Sequential effect
Needs two vectors to ensure detection!
C D
‘0’
sa0
1
Fault enabling 1 1
Out
1
1
Fault propagation
1 0
0
Memory Memory
address
data
address
data
test select
Processor
Processor
I/O bus
I/O bus
ScanIn ScanOut
Out
In Combinational Combinational
Register
Register
Logic Logic
A B
System Data D Q
System Clock C
SI L1
Scan Data
Q
Shift A Clock A
SO
Shift B Clock B L2
SO
SCANIN SCANOUT
IN
LOAD KEEP
Test
1
2
SCANIN
REG[1] REG[0]
REG[2] REG[3]
REG[4]
COMPIN
COMP
SCANOUT
REG[5]
OUT
normal interconnect
Scan-in si so
Scan-out
scan path
Bonding Pad
(Sub)-Circuit
Test
Test Controller
R R R
S0 S1 S2
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0
B1
ScanIn ScanOut
mux
R R R
S0 S1 S2
B0 B1 Operation mode
1 1 Normal
0 0 Scan
1 0 Pattern generation or
Signature analysis
0 1 Reset
ScanIn ScanOut
In Combinational Combinational
BILBO-B
Out
BILBO-A
Logic Logic
data -in
data-out
Memory Signature
FSM
Analysis
Under Test
address &
R/W control