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CIRCUIT DESIGN
PROCESSES
INTRODUCTION
• Objectives:
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Buried Contact
Contact Cut
NMOS ENCODING
UNIT – II CIRCUIT DESIGN PROCESSES
STICK DIAGRAMS
CMOS
ENCODING
Vdd = 5V
Vdd = 5V
pMOS
Vin Vout Vin Vout
nMOS
X
x x x
x X
Gnd Gnd
Vdd = 5V
Vout
Vin
“Micron” rules
Metal
Diffusion
Polysilicon
Metal
Diffusion
Polysilicon
Metal
Diffusion
Metal
Polysilicon
Advantage:
No buried contact mask required and avoids associated processing.
Insulating
Oxide
n+ n+
PolySi
2 Channel length
Buried contact 2
Diffusion
UNIT – II CIRCUIT DESIGN PROCESSES
DESIGN RULES
Contact Cut
• Metal connects to polySi/diffusion by contact cut.
• Contact area: 2 X 2
• Metal and polySi or diffusion must overlap this contact
area by l so that the two desired conductors encompass the
contact area despite any mis-alignment between
conducting layers and the contact hole
4
4
2
2
3
6
6
2
2
All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3
Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ
Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ
• Layer Types
– p-substrate
– n-well
– n+
– p+
– Gate oxide
– Gate (polysilicon)
– Field Oxide
• Insulated glass
• Provide electrical isolation
N+ N+
n+ n+ n+ n+ p+ p+ p+ p+
n-well
Shared drain/
source
Gnd
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Metal Interconnect Layers
• Metal layers are electrically isolated from each other
• Electrical contact between adjacent conducting layers requires contact cuts
and vias
Ox3
Via
Metal2
Active Ox2
contact
Metal1
Ox1
n+ n+ n+ n+
p-substrate
Metal1
Metal2
Metal1
MOS
Active contact
x y
A B C
x
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Parallel Connected MOS Patterning
x x
A B
A B
X X X
y
y
X X
A B
A B
X X
y y
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Basic Gate Design
• Both the power supply and ground are routed using the Metal
layer
• n+ and p+ regions are denoted using the same fill pattern. The
only difference is the n-well
• Contacts are needed from Metal to n+ or p+
X
x x
x X
X
Gnd
Gnd
X X
x x
X X
Gnd
x Gnd
x
Vp Vp
X X X
a.b
Gnd
a.b
a b
X X
a b
Gnd
Vp
Vp
X X
ab
ab
a b X
Gnd X X
a b
Gnd
• Efficient routing space usage. They can be placed over the cells
or even in multiple layers.
4. Floor Planning
5. Routing, Placement
6. On to Silicon
UNIT – II CIRCUIT DESIGN PROCESSES
ANY Qs?