Main Project Presentation

Linear Frequency Translation and Sampling rate Conversion of Signals using FPGA
Project Overview
Block Diagram
Detect
Sampling rate
 Project Overview
Sample Input Signal Spectrum
 Project Overview
Working

1. We know that 2sinAcosB=sin(A+B)+sin(A-B).

2. Assuming Input Audio is Sin(A) ,Then output of Direct digital synthesiser is Cos(0.9A).
3. On multiplying these two signals we get sin(A+B)+sin(A-B).
4. On passing this signal through a low pass filter we get output as sin(A-B) where B=0.9 A . So output
is Sin(0.1 A) which is frequency shifted version of input signal.
5. Now the sampling rate must be reduced for this lower frequency signal.
this can be achieved using the following techniques.
Polyphase Decimation Filter
Fir Decimation Filter
CIC filter
We have chosen Fir Decimation Filter For this purpose.
6. Now the signal is passed through a DAC to produce the analog output.
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Expected output Signal Spectrum
 Project Overview
Works Done
1. Sample Input signal Generated.
2. UART transmitter and receiver designed and implemented using VHDL.
3. FIR decimation filter designed and implemented using VHDL.
4. Low Pass Filter designed and implemented using VHDL.
5. Hilbert Transformer designed.
6. Direct Digital Syntesiser Designed and implemented.
THANK YOU