ELE-2213

Digital Circuits
 2.1 Identify the symbol, truth table
and Boolean equation for OR, AND,
NOT, NAND, NOR, XOR AND
XNOR logic gates

2
The Inverter
A X

The inverter performs the Boolean NOT operation.

operation
When the input is LOW,
LOW the output is HIGH;
HIGH when the input is
HIGH, the output is LOW.
Input Output
A X
LOW (0) HIGH (1)
HIGH (1) LOW(0)

The NOT operation (complement)

complement is shown with an overbar.
overbar
Thus, the Boolean expression for an inverter is X = A.
3
The Inverter
A X

Example waveforms:
A
X
Application Example : A group of inverters can be used to form
the 1’s complement of a binary number: Binary number
1 0 0 0 1 1 0 1

0 1 1 1 0 0 1 0
4 1’s complement
The AND Gate
A A
X & X
B B Rectangular outline symbol
Distinctive shape symbol

The AND gate produces a HIGH output when all inputs are
HIGH;
HIGH otherwise, the output is LOW. For a 2-input gate, the truth
table is Inputs Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

The AND operation is usually shown with a dot between the

variables but it may be implied (no dot). Thus, the AND
operation is written as X = A . B or X = AB.
AB
5
 The AND Gate
The total number of possible combinations of binary
inputs to a gate is determined by the following formula
:
N=2n
Where n is the number of possible input combinations
and n is the number of input variables:

6
The AND Gate /Applications:
/
1) The AND operation is used in computer programming as a selective
mask.
mask If you want to retain certain bits of a binary number but reset the other
bits to 0, you could set a mask with 1’s in the position of the retained bits.
If the binary number 10101011 is ANDed with the
1111 what is the result? 00001011
mask 00001111,

2) Seat belt alarm circuit

7
The OR Gate
A X A ≥1 X
B Distinctive shape symbol
B
Rectangular outline symbol

The OR gate produces a HIGH output if any input is HIGH;

HIGH if all inputs
are LOW,
LOW the output is LOW.
LOW For a 2-input gate, the truth table is
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1
The OR operation is shown with a plus sign (+) between the variables.
Thus, the OR operation is written as X = A + B.
B

8
The OR Gate
≥1

The OR operation can be used in computer programming to set

certain bits of a binary number to 1.

ASCII letters have a 1 in the 5th position for lower case letters and
a 0 in this position for capitals.
capitals What will be the result if you OR
an ASCII letter with the 8-bit mask 00100000?

The resulting letter will be lower case.

9
Application: Intrusion detection system

Application Examples:

Open door / window

Sensors

HIGH = Open Alarm

LOW = Closed circuit

Figure 6 A simplified intrusion detection system using an OR g

10
The OR Gate/ Example(1)
If the two input waveforms, A and B, in Figure below are
applied to the OR gate, what is the resulting output waveform?

11
The NAND Gate
A X A & X
B B
The NAND gate produces a LOW output when all inputs are
HIGH;
HIGH otherwise, the output is HIGH. For a 2-input gate, the truth
table is Inputs Output
A B X
0 0 1
0 1 1
1 0 1
1 1 0

The NAND operation is shown with a dot between the variables and
an overbar covering them. Thus, the NAND operation is written as
X = A .B (Alternatively, X = AB.)
AB
12
The NAND Gate
Example waveforms:

The NAND gate is particularly useful because it is a “universal” gate – all other
basic gates can be constructed from NAND gates.
gates
Negative-OR Equivalent Operation of a NAND Gate

How would you connect a 2-input NAND gate to form a basic

inverter?
13
Application: Liquid Tank Level Indicator#1

14
The NAND Gate/ Example(2)
Show the output waveform for the 3-input NAND gate in
Figure below with its proper time relationship to the inputs.

15
The NOR Gate
A X A ≥1 X
B B

The NOR gate produces a LOW output if any input is HIGH;

HIGH if all
inputs are LOW,
LOW the output is HIGH.
HIGH For a 2-input gate, the truth
table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
The NOR operation is shown with a plus sign (+) between the
variables and an overbar covering them. Thus, the NOR operation is
written as X = A + B.
B
16
 The NOR Gate
Example waveforms:

The NOR operation will produce a LOW if any input is HIGH.

Negative-AND Equivalent
Operation of the NOR Gate
+5.0 V

330 W
When is the LED ON for the circuit shown?
A
B X
The LED will be on when any of the C
D
17 four inputs are HIGH.
HIGH
The NOR Gate/ Example(3)
Show the output waveform for the 3-input NOR gate in
Figure below with the proper time relation to the inputs.

18
The XOR Gate
A X A =1 X
B B

The Exclusive OR (XOR) gate produces a HIGH output only when

both inputs are at opposite logic levels.
levels The truth table is
Inputs Output
A B X
0 0 0
0 1 1
1 0 1
1 1 0

The XOR operation is written as X = AB + AB. AB Alternatively, it can

be written with a circled plus sign between the variables as
X = A + B.
B
19
The XOR Gate
Example waveforms:

Notice that the XOR gate will produce a HIGH only when exactly one input is
HIGH.
HIGH

If the A and B waveforms are both inverted for the

above waveforms, how is the output affected?
affected
There is no change in the output.
20
The XNOR Gate
A X A =1 X
B B

The Exclusive NOR (XNOR) gate produces a HIGH output only

when both inputs are at the same logic level.
level The truth table is
Inputs Output
A B X
0 0 1
0 1 0
1 0 0
1 1 1

The XNOR operation shown as X = AB + AB. AB Alternatively, the

XNOR operation can be shown with a circled dot between the
variables. Thus, it can be shown as X = A . B.
B
21
The XNOR Gate
Example waveforms:

Notice that the XNOR gate will produce a HIGH when both inputs
are the same.
same This makes it useful for comparison functions.

If the A waveform is inverted but B remains the same, how

is the output affected?
The output will be inverted.
22
The XNOR & XOR Gates/ Example(4)

Determine the output waveforms for the XOR gate and for the
XNOR gate, given the input waveforms, A and B, in Figure below.

23
 2.2 Determine the Boolean equation
and truth table for a
combinational logic circuit with
one output and a maximum of 4
variable inputs.
2.3 Apply Boolean equations to
simplify Digital circuits.
24
Boolean operation & expressions
In Boolean algebra, a variable is a symbol used to represent an action, a
condition, or data.
data A single variable can only have a value of 1 or 0.
The complement represents the inverse of a variable and is indicated with an
overbar.
overbar Thus, the complement of A is A.
A literal is a variable or its complement.
complement
Addition is equivalent to the OR operation.
operation The sum term is 1 if one or more
of the literals are 1. The sum term is zero only if each literal is 0.
In Boolean algebra, multiplication is equivalent to the AND operation.
operation The
product of literals forms a product term.
term The product term will be 1 only if
all of the literals are 1.

Determine the values of A, B, and C that make the sum term of

the expression A + B + C = 0?

Each literal must = 0; therefore A = 1, B = 0 and C = 1.

25
Boolean operation & expressions

What are the values of the A, B and C if the product term of A.B.C =
1?
Each literal must = 1; therefore A = 0, B = 1 and C = 0.

A combination of logic gates interconnected to produce a

specific function.
function There is no feedback from output of the circuit
to the input. The output is a function of the current input status.
Combinational logic circuits uses some or all of the basic logic
gates AND, OR and NOT.

26
Boolean operation & expressions

Examples of combinational logic circuit:

27
Example (5)
Derive the logic circuit for the Boolean function defined as:
AB + BCD + AC

28
Example (6)
Apply Boolean algebra to derive the expression for X.

A
B
C
D

29
Lows of Boolean Algebra /Commutative Laws

The commutative laws are applied to addition and multiplication.

multiplication
For addition, the commutative law states
In terms of the result, the order in which variables are ORed
makes no difference.

A+B=B+A
For multiplication, the commutative law states
In terms of the result, the order in which variables are ANDed
makes no difference.

AB = BA

30
Associative Laws
The associative laws are also applied to addition and
multiplication.
multiplication
For addition, the associative law states
When ORing more than two variables, the result is the same
regardless of the grouping of the variables.
A + (B +C) = (A + B) + C
For multiplication, the associative law states
When ANDing more than two variables, the result is the same
regardless of the grouping of the variables.
A(BC) = (AB)C

31
Distributive Laws
The distributive law is the factoring law.
law A common variable can
be factored from an expression just as in ordinary algebra. That is

AB + AC = A(B+ C)
The distributive law can be illustrated with equivalent circuits:
A
AB
B B
B+ C
C X
X A
A AC
C

A(B+ C) AB + AC
32
 Basic Rules of Boolean Algebra

33
Proof of Rules11 & 12

34
Example (7)
Use Rules of Boolean Algebra to simplify the following Boolean expressions :

35
SOP and POS Forms
Boolean expressions can be written in the sum-of-products form
(SOP)
SOP or in the product-of-sums form (POS).
POS These forms can
simplify the implementation of combinational logic,
logic particularly
with PLDs. In both forms, an overbar cannot extend over more
than one variable.
variable
An expression is in SOP form when two or more product terms
are summed as in the following examples:
ABC+AB ABC+CD CD+E
An expression is in POS form when two or more sum terms are
multiplied as in the following examples:

(A + B)(A + C) (A + B + C)(B + D) (A + B)C

36
SOP Standard Form
In SOP standard form,
form every variable in the domain (the set of
variables contained in the expression in either complemented or
un-complemented form) must appear in each term.term This form is
useful for constructing truth tables or for implementing logic in
PLDs.
PLDs
You can expand a nonstandard term to standard form by
multiplying the term by a term consisting of the sum of the
missing variable and its complement.
Convert X = A B + A B C to standard form.
The first term does not include the variable C. Therefore,
multiply it by the (C + C), which = 1:
X = A B (C + C) + A B C
=ABC+ABC+ABC
37
POS Standard Form
In POS standard form,
form every variable in the domain must appear
in each sum term of the expression.
You can expand a nonstandard POS expression to standard form
by adding the product of the missing variable and its complement
and applying rule 12,
12 which states that (A + B)(A + C) = A + BC.

Convert X = (A + B)(A + B + C) to standard form.

The first sum term does not include the variable C.
Therefore, add C C and expand the result by rule 12.
X = (A + B + C C)(A + B + C)
= (A +B + C )(A + B + C)(A + B + C)

38
Example (8)

Develop a truth table for the standard SOP expression:

39
 Example (9)
Convert each the following Boolean Expressions to SOP
form
1. AB+B(CD+EF)

2. (A+B)(B+C+D)

4.

40
 Example (10)

41
 Example (11)

42
 Converting from SOP to POS

43
 Example (12)

44
Implementing Combinational Logic Circuits
Implementing a SOP ( sum of product) expression is done by first
forming the AND terms; then the terms are ORed together.
together
Show the circuit that will implement the Boolean
expression X = ABC + ABD + BDE. (Assume that the
variables and their complements are available.)
Start by forming the terms using three 3-input AND gates.
Then combine the three terms using a 3-input OR gate.
A
B
C
A X = ABC + ABD + BDE
B
D
B
D
E

45
Designing Combinational Logic Circuits

To solve any logic design problem:

Interpret the problem and set up its truth
table.
table
Write the AND (product) term for each
case where the output equals 1.
Combine the terms in OR form.
form
Implement the circuit .
 
46
Example (13)
Draw the truth table for the Boolean function defined as:
and derive the logic circuit.
circuit

47
Example (14)
For the given truth table, form a Boolean function and derive
the logic circuit:

48
Example (15)
For the circuit below:
1.Write the output expression
2.Develop the truth table.
table

C X

49
 Example(16)
A Petrol station has 2 underground tanks to store petrol. A level sensor
attached to each tank produces 0V when the level of the petrol in the
tank drops below a specified point.
point Design a circuit that will
produce 5V to turn on a light when the level in any two tanks
drops below the specified point.
point

Solution:
Interpret the problem and set up its truth table

Sensor = 0V when tank below specified level

5V when tank above specified level
Light = 5V Turn on
0V Turn off

50
 Example(16)
Truth Table A B Output
0 0 1
0 1 1
1 0 1
1 1 0

•Write the AND (product) term for A B Output

each case where the output equals 1. 0 0 1 AB
0 1 1 AB
•Combine the terms in OR form 1 0 1 AB
1 1 0
Output  A  B  A  B  A  B
51
Example(16)
Implement the circuit .

52
Example(16)
Using Boolean algebra the circuit can be minimised as follows:

53
Example(17)
Design & simplify combinational circuit that satisfy the given truth
table

54
Example(17)
G  xyz  xy z  xyz
The following circuit satisfies the
truth table.

The circuit can be minimised by using

Boolean Algebra:

55
Pulsed Waveforms/Example(18)
For combinational circuits with pulsed inputs,
inputs the output can be predicted by
developing intermediate outputs and combining the result. For example, For the
circuit shown Draw the output waveforms for G1 , G2 & G3

A
A
B G1
B
C G3
C
D G2
D
G1

G2
G3

56
Pulsed Waveforms/ Example(18)
Alternatively,
Alternatively you can develop the truth table for the
Inputs Output
circuit and enter 0’s and 1’s on the waveforms. Then
read the output from the table. A B C D X
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
A
G1 0 0 1 1 1
B 0 1 0 0 0
G3 0 1 0 1 1
C 0 1 1 0 1
G2 0 1 1 1 1
D 1 0 0 0 0
A 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0
1 0 1 0 0
B 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0
0 0 0 1 1 1 1 0 0 0 1 1 0 0 0
C
1 1 0 1 1
D 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1
1 1 1 1 1
G3 0 0 0 0 1 1 1 0 1 0

57
DeMorgan’s 1st Theorem
DeMorgan’s 1st Theorem
The complement of a product of variables is equal to the sum of
the complemented variables.
AB = A + B
Applying DeMorgan’s first theorem to gates:
A A Inputs Output
AB A+B
B B
A B AB A + B
NAND Negative-OR 0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0

58
DeMorgan’s 2nd Theorem
DeMorgan’s 2nd Theorem
The complement of a sum of variables is equal to the product
of the complemented variables.
A+B=A.B
Applying DeMorgan’s second theorem to gates:
A A Inputs Output
A+B AB
B B
A B A + B AB
NOR Negative-AND 0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0

59
DeMorgan’s Theorem/Example(19)
Theorem/

To apply DeMorgan’s theorem to the expression, you

can break the overbar covering both terms and change
the sign between the terms. This results in
=
X = C . D. Deleting the double bar gives X = C . D.

60
 DeMorgan’s Theorem/Example(20)
Theorem/

61
 Examples (21)

62
 Example (22)

63
Example (23)
When the output of a SOP form is inverted,
inverted the circuit is called an
AND-OR-Invert circuit. The AOI configuration lends itself to
product-of-sums (POS)
POS implementation.
An example of an AOI implementation is shown. The output
expression can be changed to a POS expression by applying
DeMorgan’s theorem twice.
A
B ABC
C X = ABC + DE X = ABC + DE AOI

D X = (ABC)(DE) DeMorgan
E DE X = (A + B + C)(D + E) POS

64
 2.4 Simplify a Boolean expression
and combinational logic circuit
using Boolean algebra and
Karnaugh logic maps.

65
Karnaugh map (K-map) SOP
The Karnaugh map (K-map) is a tool for simplifying
combinational logic with 2, 3, 4 or 5 variables (but we
discuss 3-variable and 4-variable situations only).
For 3 variables, 8 cells are required (23).
The map shown is for three ABC ABC
variables labeled A, B, and C.
Each cell represents one possible ABC ABC
product term.
term
ABC ABC
Each cell differs from an adjacent
cell by only one variable.
variable ABC ABC

66
Karnaugh maps-SOP
Cells are usually labeled using 0’s and 1’s to represent the variable
and its complement.
complement
C
AB 0 1

00

01

11

10

Ones are read as the true Alternatively, cells can

variable and zeros are read as be labeled with the
67 the complemented variable. variable letters.
Karnaugh maps
K-maps can simplify combinational logic by grouping cells and
eliminating variables that change.
change
Example(24): Group the 1’s on the map and read the minimum logic.

CC 00 11
AABB 1. Group the 1’s into two overlapping
11
000
0 groups as indicated.
B changes
across this 001
1 11 11 2. Read each group by eliminating any
boundary variable that changes across a
1111 boundary.

110
0 3. The vertical group is read AC.
C changes
across this 4. The horizontal group is read AB.
boundary
X = AC +AB
68
Karnaugh maps
A 4-variable map has an adjacent cell on each of its four
boundaries as shown.

CD CD CD CD

AB Each cell is different only by one

AB
variable from an adjacent cell.
cell
AB
Grouping follows the rules
shown in the next slide.
AB

69
Karnaugh maps
Grouping the 1’s
1.A group must contain either 1, 2, 4, 8 or 16 cells.
cells
2.Each cell in a group must be adjacent to one or more cells in
that group.
group
3.Always include the largest possible number of 1’s in a group
in accordance with rule 1).
4.Each 1 on the map must be included in at least one group.
group
The 1’s already in a group can be included in another group as
long as the overlapping groups include non-common 1s.1s

The following slide shows an example of reading a four variable

map using binary numbers for the variables…

70
Karnaugh maps
Example(25): Group the 1’s on the map and read the minimum logic.

C changes across
outer boundary
CD
AB
00 01 11 10 1. Group the 1’s into two separate
00 1 1 groups as indicated.
B changes 2. Read each group by eliminating
01 1 1 any variable that changes across
11 1 1
a boundary.
B changes 3. The upper (yellow) group is read as
10 1 1 AD.
C changes
4. The lower (green) group is read as
AD.
AD
X
X = AD +AD

71
Karnaugh maps/ Grouping/Example( 26)
Group the 1’s on the maps below , determine the product terms
for each of the Karnaugh maps and write the resulting minimum
SOP expression.
Karnaugh maps/ Grouping/Example( 27)
Group the 1’s on the maps below , determine the product terms
for each of the Karnaugh maps and write the resulting minimum
SOP expression.
Karnaugh maps/ Grouping/Example( 27)
Karnaugh maps/Example( 28)
Use Karnaugh map below to find the minimum SOP
Karnaugh maps/Example( 28)
Karnaugh maps/Example( 29)
Map & Find the minimum SOP for the following standard SOP
expression on a Karnaugh map:
Karnaugh maps/Example( 30)
Map & Find the minimum SOP for the following nonstandard
SOP expression on a Karnaugh map:
 Karnaugh maps/Example( 31)
Use a Karnaugh map to minimize the following SOP
expression:

79
Karnaugh maps “Don’t Care”
 Sometimes a situation arises in which some input variable
combinations are not allowed.
For example, in the BCD code, there are 6 invalid
combinations. Since these un-allowed states will never occur in
an application involving the BCD code, they can be treated as
“don’t care” terms with respect to their effect on the output. That
is, for these “don’t care” terms either a 1 or a 0 may be assigned
to the output; it really does not matter since they will never
occur. The “don’t care” terms can be used to advantage on the
Karnaugh map.
A don’t care condition can be treated as a (0) or a (1) in a K-
Map. Treating a don’t care as a (0) means that you do not need to
group it. Treating a don’t care as a (1) allows you to make a
grouping larger, resulting in a simpler term in the SOP equation.
80
Karnaugh maps “Don’t Care”

81
Karnaugh maps “Don’t Care”/ Example (32)

82
Karnaugh maps “Don’t Care”

From the Karnaugh map, the minimized expression for segment a is

83
 Karnaugh maps “ POS”
The following steps and the
illustration show the mapping
process.
Step 1: Determine the binary
value of each sum term in the
standard POS expression.
This is the binary value that
makes the term equal to 0.
Step 2: As each sum term is
evaluated, place a 0 on the
Karnaugh map in the
corresponding cell.
84
 Karnaugh maps“POS”/Example(33)
Map the following standard POS expression on a Karnaugh map:

85
 Karnaugh maps“POS”/Example(34)
Use a Karnaugh map to minimize the following standard POS expression:

The combinations of binary values of the expression are

(0 + 0 + 0)(0 + 0 + 1)(0 + 1 + 0)(0 + 1 + 1)(1 + 1 + 0)

Grouping ‘0s’ as Grouping the 1s as

shown in the figure shown by the gray
and the resulting areas yields an SOP
minimum POS expression that is
expression is equivalent
to grouping the 0s.

86
 Karnaugh maps“POS”/Example(35)
Use a Karnaugh map to minimize the following POS
expression:

87
 Converting Between POS and SOP Using the Karnaugh Map

• When a POS expression is mapped, it can easily be

converted to the equivalent SOP form directly from the
Karnaugh map.
• Also, given a mapped SOP expression, an equivalent
POS expression can be derived directly from the map.
This provides a good way to compare.
• For a POS expression, all the cells that do not contain 0s
contain 1s, from which the SOP expression is derived.
• For an SOP expression, all the cells that do not contain
1s contain 0s, from which the POS expression is derived.

88
Converting Between POS and SOP Using the Karnaugh
Map/Example (36)
Using a Karnaugh map, convert the following standard POS expression into
a minimum POS expression, a standard SOP expression, and a minimum
SOP expression.

89
 2.5 Describe the operation of encoder,
decoder, and magnitude
comparator using Boolean
equations and truth tables.

90
Half Adder
Basic rules of binary addition are performed by a half adder, which
has two binary inputs (A and B) and two binary outputs (Carry out
and Sum).
The inputs and outputs can be summarised on a truth table.
The logic symbol and equivalent circuit are:

Logic symbol Equivalent circuit

91
Full Adder
By contrast, a full adder has three binary inputs (A, B, and Carry in)
and two binary outputs (Carry out and Sum). The truth table
summarises the operation.
A full-adder can be constructed from two half adders as shown:

92
Full Adder

93
Full Adder/Example (37)
For the given inputs, determine the intermediate and final outputs of the full
adder.

The first half-adder has inputs of 1 and

0; therefore the Sum =1 and the Carry
out = 0.
The second half-adder has inputs of 1
and 1; therefore the Sum = 0 and the
Carry out = 1.
The OR gate has inputs of 1 and 0,
therefore the final carry out = 1.
Notice that the result from the previous
example can be read directly on the truth
table for a full adder.

94
Full Adder/Example (38)
For each of the three full-adders in Figure below, determine the outputs for
the inputs shown.

95
Parallel Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.

The output carry (C4) is not ready until it propagates through all of
the full adders. This is called ripple carry,
carry delaying the addition
process.

96
Parallel Adder
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimise the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

97
Parallel Adder/Example (39)
Use the 4-bit parallel adder to find the sum and output carry for the addition of
the following two 4-bit numbers if the input carry (Co) is 0:

98
Comparator
The basic function of a comparator is to compare the magnitude of
2 binary numbers to determine whether they are equal or not.
not

The XOR gate is a basic one bit comparator as shown below. If

A = B then X = 0, otherwise X = 1.

99
Comparator/Example(40)
Design a circuit that compare two 2-bit binary numbers A = A1 A0
and B = B1 B0

The output of the circuit is equal to 1 if the numbers are equal

otherwise ‘0’.
Solution:
Solution

100
Comparators/Example(41)
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1

A2
B2
A=B
A3
B3

A4
B4

101
Comparator 74HC85: 4-bit Magnitude comparator
The 74HC85 compares two 4-bit binary
numbers say A and B and determines whether
the number are equal ( A = B) or Less than
(A < B) or greater than (A > B).

To determine an inequality of binary number

A and B, first examine the MSB in each
number.
number The following conditions are
possible:
•If A3 = 1 and B3 = 0, then A > B
•if A3 = 0 and B3 = 1, then A < B
•if A3 = B3, then must examine the next lower
bit position for inequality.

102
Comparators/Example(42)

103
Comparators
Cascading inputs are provided to expand the comparator to
larger numbers.
numbers

COMP
A0 0
A1 A
A2
A3 3
A>B A>B
Cascading inputs Outputs
A=B A=B
A<B A<B
B0 0
B1 B
The IC shown is the 4-bit 74LS85.
B2
B3 3

104
Comparators
IC comparators can be expanded using the cascading inputs as
shown. The lowest order comparator has a HIGH on the A = B
input.
input
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

105
An 8-bit magnitude comparator using two 74HC85s.
Concept of Encoding - Decoding

106
Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input.
input Two simple decoders that detect
the presence of the binary code 0011 are shown. The first has an
active HIGH output;
output the second has an active LOW output.
output
A0 A0

A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for Active LOW decoder for 0011

0011

107
Decoders/Example(43)
Assume the output of the decoder shown is a logic 1. What are
the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

108
Decoders/Example(44)
Design a circuit that generates a ‘1’ at the output when it detects
`1001’ at the input.
A3 A2 A1 A0 Output = Q
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
1 0 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

109
Decoders/Example(45)
Design a circuit that generates a ‘1’ at the output when it detects
1011’ at the input.

A3 A2 A1 A0 Output = Q
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
1 0 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

110
Decoders/Example(46)
Design a circuit that generates a ‘1’ at the output when it detects
`1001’ or ‘1011’ at the input.

111
Multiple output Decoders
IC decoders have multiple outputs to decode any combination of
inputs. For example the binary-to-decimal decoder shown here has
16 outputs – one for each combination of binary inputs.
Bin/Dec
0 1
For the input shown, 1 1
2 1
what is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 8 1 outputs (Active low)
0 A2
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

112
n – to - 2n Decoder
Accepts a value and decodes it
Output corresponds to value of n inputs
Consists of:
 Inputs (n)
 Outputs (2n, numbered from 0  2n-1)
-1

Selectors / Enable (active high or active

low)

113
2 – to - 4 Decoder

114
3 – to - 8 Decoder

115
3 – to - 8 Decoder

116
3–to-8 Decoder from two 2-to-4
Decoders

117
4 – to - 16 Decoders
A specific integrated circuit decoder is the X/Y
74HC154 (shown as a 4-to-16 decoder). 0
1
2
It includes two active LOW chip select 3
lines which must be at the active level to 4
5
enable the outputs.
outputs A0 1 6
A1 2 7
These lines can be used to expand the A2 4 8
A3 8 9
decoder to larger inputs. 10
11
12
13
14
CS1 & 15
CS2 EN
Active low output 74HC154

118
4 – to– 16 decoder
Truth Table for 4-to-16 Lines Decoder – Active Low Output

119
Decoders: BCD-to-Decimal decoder
BCD-to-decimal decoders accept a binary coded
BCD/DEC (1)
decimal input and activate one of ten possible 0
(2)
1
decimal digit indications. (3)
2
(15) (4)
A0 1 3
(14) (5)
A1 2 4
A2 (13) 4 5
(6)
(12) (7)
A3 8 6
Example( 47) 7
(9)
Assume the inputs to the 74HC42 decoder are 8
(10)
(11)
the sequence 0101, 0110, 0011, and 0010. 9
Describe the output. 74HC42

All lines are HIGH except for one active output, which
is LOW. The active outputs are 5, 6, 3, and 2 in that
order.
120
Decoders: BCD-to-Decimal decoder
Any input greater than 910 is invalid and will not be detected by the
decoder which cause all of the outputs will be inactive (5V).

121
The BCD-to-7-Segment Decoder
Another useful decoder is the 74LS47.
74LS47 This is a BCD-to-seven
segment display with active LOW outputs.
outputs
The a-g outputs are designed for much higher current than most
devices (hence the word driver in the name). V CC

Ripple Blanking Output

(16)
BCD/7-seg
(4)
BI/RBO BI/RBO
(13)
(7) a
1 (12)
(1) b
BCD 2 (11)
(2) c Outputs
inputs 4 (10) to seven
(6) d
8 (9) segment
e
(3) (15) device
LT LT f
(5) (14)
RBI RBI g
Lamp Test
74LS47 (8)

Ripple Blanking Input GND

122
The BCD-to-7-Segment Decoder
Here the 7447A is connected to an LED seven segment display. display
Notice the current limiting resistors, required to prevent overdriving
the LED display.
+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 RBI 11 10
c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8 * Remember to connect V+
through a resistor (at least 330Ω)

123
124
BCD to 7-segment Decoder

125
BCD to 7-segment Decoder/ Example(48)
Design a combinational circuit that is having as inputs the
binary representation (b0 – b3) of decimal number. The circuit
will drive its outputs to a 7-segment display.

126
ELE-2213 BCD to 7-segment Decoder

127
BCD to 7-segment Decoder

128
BCD to 7-segment Decoder

129
BCD to 7-segment Decoder

130
BCD Decoder / driver
The 74LS47 features lamp test (when LT is LOW and BI/RBO is HIGH all 7-
segments are on) and zero suppression,
suppression which blanks unnecessary leading zeros
but keeps significant zeros as illustrated here. The BI/RBO (Blanking Input//Ripple
Blanking Output) output is connected to the RBI (Ripple Blanking Input) input of
the next decoder. If BCD input is 0000 and RBI is LOW all segments will
nonactive. This causes RBO to be low and causes display to be blank.

leading zero suppression

131
BCD Decoder / driver
Trailing zero suppression blanks unnecessary trailing zeros to the
right of the decimal point as illustrated here. The RBI (Ripple
Blanking Input) input is connected to the BI/RBO (Ripple Blanking
Output) output of the following decoder.

trailing zero suppression

132
Encoders
An encoder accepts an active logic level on one of its inputs and
converts it to a coded output,
output such as BCD or binary.

1
The decimal-to-BCD is an encoder A0
with ten inputs for the decimal 2

digits and four outputs for the 3

A1
active digit of the BCD code.
code
4
5
A2
There is no zero input because the 6
7
outputs are all LOW when the 8
input is zero.
zero A3
9

Decimal to BCD basic logic diagram

133
Decimal to BCD Encoder
Decimal A3 A2 A1 A0 A0 = 1 + 3 + 5 + 7 + 9
Digit
0 0 0 0 0
A1 = 2 + 3+ 6 + 7
1 0 0 0 1 A2 = 4 + 5+ 6 + 7
2 0 0 1 0 A3 = 8 + 9
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

134
Encoders/Example(49)
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with the red
lines. Thus the output is 0011.
1 0 1
A0
2 0
1
3 1
A1

4 0
0 0
5 0 A2
6 0
7
8 0 0
A3
0
9

135
Code Converters/Example(50)
There are various code converters that change one code to another.
Two examples are the four bit binary-to-Gray converter and the
Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0 1 LSB
1 0
LSB

0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB

Binary-to-Gray Gray-to-Binary

136
Encoders
The 74HC147 is an example of an IC encoder. It is has ten active-
LOW inputs and converts the active input to an active-LOW BCD
output.
VCC
This device offers additional flexibility in (16)
that it is a priority encoder.
encoder This means (11)
HPRI/BCD
1
that if more than one input is active,
active the (12)
2
(13)
one with the highest order decimal digit (1)
3
1
(9)
4 (7)
will be active.
active Decimal input (2) 5
2
(6)
BCD
(3) 4 output
6 (14)
(4) 8
7
(5)
8
(10) 9
(8)
74HC147
GND
The next slide shows an
137
application …
2n – to - n Encoder
Accepts a value and encodes it
Consists of:
 Inputs (2n)
 Outputs (n)

138
Multiplexer (MUX)
A multiplexer can use addressing bits to select one of
several input bits to be the output.
output
A selector chooses a single data input and passes it to the
MUX output.
It has one output selected at a time.
time

Which data line is selected if S1S0 = 10? I2

139
4 to 1 line multiplexer
2n MUX to 1: n for this MUX is 2 Which means 2 selection
lines s0 and s1
 Selectors (# depends on # of inputs) = n
 Enable (active high or active low)
low

S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3

140
4 to 1 line multiplexer/example(51)
The data-input and data-select waveforms in Figure below are
applied to the 4 to 1 line multiplexer in Figure below .
Determine the output waveform in relation to the inputs.

141
Multiplexers versus Decoders
A Multiplexer uses n binary select bits to choose from a
maximum of 2n unique input lines.

Decoders have 2n number of output lines while multiplexers

have only one output line.

The output of the multiplexer is the data input whose index is

specified by the n bit code.

142
Multiplexer versus Decoder

Note that the multiplexer has an extra OR gate. A1 and A0 are the
two inputs in decoder. There are four inputs plus two selects in
multiplexer.
143
 END LO2

144