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Winsem2020-21 Ece3002 Eth Vl2020210503037 Reference Material I 05-Feb-2021 Cmos Cmos New
Winsem2020-21 Ece3002 Eth Vl2020210503037 Reference Material I 05-Feb-2021 Cmos Cmos New
W
I D nCox VGS VTN 1 VDS
1 2
2
L
= channel length modulation coefficient
threshold voltage
oxide thickness
oxide permitivity
permitivity of silicon
doping concentration
charge of an electron
Sub threshold region
Subthreshold current
Subtreshold
region
•Regions of Operation
•Noise margin
•Inverter capacitances
•Delay, Rise and Fall time
CMOS Inverter
• Complementary NMOS and PMOS
devices VDD
• In steady-state, only one device is on
(no static power consumption)
• Vin=1: NMOS on, PMOS off Vin Vout
– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off
– Vout = VOH = VDD
Gnd
12
CMOS Inverter: VTC
PMOS NMOS
Vin=4V
Drain current IDS
VDD
Vin=3V
Vout
Vin=2V
Vin=1V
13
CMOS inverter operation
VDD
• NMOS transistor:
– Cutoff if Vin < VTN
Vin Vout
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VDD) < VTP → Vin < VDD+VTP
– Linear if (V -V )>V -V -V → V >V - V
out DD in DD TP out in TP
14
CMOS
P linear
inverter VTC
P cutoff
N cutoff N linear
P linear
N sat P sat
N sat
P sat
N linear
15
CMOS inverter VTC
• Increase W of PMOS
VDD kp=kn
kp increases
VTC moves to right
kp=5kn • Increase W of NMOS
Vout
kn increases
kp=0.2kn
VTC moves to left
• For VTH = VDD/2
k n = kp
VDD Wn 2Wp
Vin
16
Inverter model: VTC
Voltage transfer curve (VTC):
plot of output voltage Vout vs. input voltage Vin
Vout
actual
VDD
Vin
17
Actual inverter: Voltage Swing VOH and VOL
• VOH and VOL represent the “high” and
“low” output voltages of the inverter
• VOH = output voltage when Vin = ‘0’
• VOL = output voltage when Vin = ‘1’
VDD
VOH • Ideally,VOH = VDD,VOL = 0
• Difference (VOH-VOL) is the voltage swing of
the gate
Vout
– Full-swing logic swings
VOL from ground to VDD
VDD
Vin
18
Inverter threshold
VOL
VDD
Vin
19
Inverter threshold
Both the transistors are in saturation
So….
Equating the Saturation current of both the PMOS and NMOS
If Kn=Kp
Vtn=|Vtp|
22
Noise margin (cont)
• Noise margin is a measure of the
interconnect robustness of an inverter
– NML = VIL - VOL
– NMH = VOH - VIH
• Models a chain of inverters. Example:
“1”
VOH – First inverter output is VOH
NMH – Second inverter recognizes input > VIH as
VIH
logic ‘1’
VIL – Difference VOH-VIH is “safety zone” for
NML
VOL noise
“0”
23
AND LOGIC
Power Dissipation
Power dissipation in CMOS circuits
comes from two components:
Static Power
Cap on node f:
• Junction cap
Cdb,p and Cdb,n
Cgd,p Cdb,p
Vin f • Gate capacitance
Cgd,n Cdb,n Cgd,p and Cgd,n
Cint Cg
• Interconnect cap
• Receiver gate cap
Cgs,n Csb,n
Gnd
33
CMOS inverter: capacitances
35
CMOS inverter: capacitances
Cgd1
Vout Vout
C gd , p C gd ,n 2CoxWLD
36
CMOS inverter: capacitances
• Interconnect capacitance
– Due to capacitance of metal and poly lines used to
connect transistors
– Complex; includes parallel-plate and fringing-field
components
– For wide wires:
tox = thickness of field oxide
Cint ox
WL
tox
Sample capacitances for 1m process:
poly: 0.058 fF/m2 M1: 0.031 fF/m2
M2: 0.015 fF/m2 M3: 0.010 fF/m2
37
Review: CMOS inverter capacitances
In Out
In Out In Out
Control Control
Control
g g g
a b a b a b
gb gb gb
S
Selector: I
Choose I0 if S = 0 0
Choose I1 if S = 1 S
S Z
I
1
S
Z0
Demultiplexer:
I to Z0 if S = 0 S
I S
I to Z1 if S = 1
Z1
S
49
Use of Multiplexers or Demultiplexers
A Y
Demultiplexers Multiplexers
B Z
A Y
Demultiplexers Multiplexers
B Z
Z0
"0"
I
S S
Z1
"0"
A0 A1 B0 B1
Multiple input sources
Sa MUX MUX Sb
A B
Sum
S0 S1
General Concept of Using Multiplexers
n
2 data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point
Z = A' I 0 + A I 1
A Z I1 I0 A Z
0 I0 0 0 0 0
1 I1 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
Functional form
1 0 1 1
Logical form 1 1 0 1
1 1 1 1
I0
I1
4:1 Z Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
I2 mux
I3
A B
I0
I1
I2
I3
I4
8:1
Z Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
mux
I5 A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
I6
I7 n
In general, Z = 2 -1m I
k=0 k k
A B C in minterm shorthand form for a 2 n:1 Mux
ECE C03 Lecture 4 54
Alternative Implementation
A B
I0 Z
I1
I2
I3
Gate
GateLevel
Level Transmission
TransmissionGate
Gate
Implementation
Implementation Implementation
Implementationofof
ofof4:1
4:1Mux
Mux 4:1
4:1Mux
Mux
A B
C
I6 0
I7 1 S
1 0 A B C F
0 1 0 0 0 1 C 0
1 C F
2 F 0 0 1 0 C 1 4:1
0 3 8:1 0
0 1 0 1 2 MUX
0 4 MUX C 1
0 0 1 1 0 3
5 S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1
A B C 1
1 1 1 1
"Lookup Table"
ECE C03 Lecture 4 57
Generalization of Multiplexer/Selector Logic
I1 I2 … I F
n
… 0 0 0 1 1 Four possible
n-1 Mux 0 1 0 1 configurations
control variables 1 of the truth table rows
single Mux
data variable 0 In In 1 Can be expressed as
a function of In, 0, 1
Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
1 0
K-map D 1
Choose A,B,C 0 2
as control variables 8:1 G
1 3
D 4 mux
D 5
Multiplexer D 6
Implementation D 7 S2 S1 S0
TTL
TTLpackage
packageefficient
efficient A B C
May be gate inefficient
May be gate inefficient
ECE C03 Lecture 4 58
Decoders/Demultiplexers
n
Decoder: single data input, n control inputs, 2 outputs
O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1 O2 = G • S0 • S1 • S2
O1 = G • S0 • S1 O3 = G • S0 • S1 • S2
O2 = G • S0 • S1 O4 = G • S0 • S1 • S2
O3 = G • S0 • S1 O5 = G • S0 • S1 • S2
O6 = G • S0 • S1 • S2
ECE C03 Lecture 4 O7 = G • S0 • S1 • S2 59
Alternative Implementations
G /G
Output0 Output0
Select
Select
Output1 Output1
1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable
G /G
Output0 Output0
Output1 Output1
Output2 Output2
Output3 Output3
2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable
ECE C03 Lecture 4 60
Switch Level Implementations Select
Select G Output
0
G Output Select
0 Select
Select "0"
Select
Select
Output Select
1
Select Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times "0"
Select
61
Switch Implementation of 2:4
Decoder
Select Select
0 1
G Output
0
G Output
2
"0"
"0"
G Output
3
"0"
"0"
62
Decoder as a Logic Building Block
0 ABC
1 ABC
2 ABC Decoder Generates Appropriate
Enb
3:8 3 ABC Minterm based on Control Signals
dec 4 ABC
5 ABC
6 ABC
S2 S1 S0 7 ABC
A B C
Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')
A B C D
If active low enable, then use NAND gates!
D
Latch
D Q
Q
CLK
CLK = 1 CLK = 0
CLK
D Q
Q
S
D Q D Q D Q
S S
Clk Clk Clk
Clk 1 Clk
Master Transmission
Gate Latch Slave Transmission
Gate Latch
MSL with unprotected input
(Gerosa et al. 1994), Copyright © 1994 IEEE
Nov. 14, 2003 70