Silicon-On-Insulator

Technology
 CONTENTS
• Brief about MOSFETs
• Issues relating MOSFETs
• SCEs
• Sub-threshold current
• Introduction to SOI
• SOI Fabrication
• SOI MOSFETs
• How SOI solves SCEs?
• Application
• Constraints
• Conclusion
 Brief about MOSFETs
• MOSFETs (Metal-Oxide-Semiconductor Field-Effect
Transistors) are four-terminal voltage-controlled devices.
• Two types depending on what type channel is formed==>
nMOS(n-type channel)
pMOS(p-type channel)

                                                  

 Contd…
• Modes of operation:
cut-off region
linear region
saturation region

Current Equation is:

for VDS<(VGS –VT0)

for VDS>=(VGS –
VT0)
 Issues about MOSFETs
• Limitation on scaling
• Short-Channel Effects
• Parasitic Capacitances & Latch-up
Scaling:some device dimensions are scaled down with
each new generation but some of them can’t be
arbitrarily scaled due to physical limitations.
Latch-up:generation of low impedance path in CMOS
such that it virtually short circuits power supply to
gnd,thus causing permanent device damage due to
excessive current flow.
 Short-Channel Effects(SCES)
• A MOSFET device is considered to be short when the channel
length is the same order of magnitude as the depletion-layer
widths of the source and drain junction.
• The short-channel effects are attributed to two physical
phenomena:-
1.the limitation imposed on electron drift characteristics in the
channel.
2.the modification of the threshold voltage due to the
shortening of channel length.
 Contd…
• Following are some short-channel effects imposed by small
geometry devices:

. Impact ionisation
. velocity saturation
. surface scattering
. oxide breakdown
. hot electrons
 Sub-Threshold Current
• Sub-threshold leakage current is the current that flows between
the source and drain of a MOSFET under the condition
(VGS<VT0).
• Current flows in the channel because potential barrier of channel is
reduced due to increase in the drain-to-source voltage.
• In the past, the subthreshold leakage of transistors has been very
small, but as transistors have been scaled down, subthreshold
leakage can compose nearly 50% of total power consumption.
• Scaling reduces the threshold voltage
in the same proportion. As threshold
voltages are reduced, subthreshold.
leakage rises exponentially.
 Sub-Threshold slope
• By measuring how many millivolts MOSFETS take to
change the drain current by one order of magnitude, i.e.
one decade of current on a logarithmic scale,this
characteristic is called the subthreshold slope.
• In MOSFET, the subthreshold swing is limited by thermal
voltage and it is 60 mV/decade at room temperature.
• This value ultimately determines how low in power your
device technology can be.
• SOI (IBM) -- subthreshold slope of 75-85 mV/decade.
 Silicon on insulator technology (SOI) refers to the use of a layered
silicon-insulator-silicon substrate in place of conventional silicon
substrates in semiconductor manufacturing. SOI-based devices differ
from conventional silicon-built devices in that the silicon junction is
above an electrical insulator, typically silicon dioxide.
 Introduction
• The first implementation of SOI was announced by IBM in August
1998.
• Implementation of SOI technology is one of the manufacturing
strategies employed to allow continued miniaturization of
microelectronic devices.
• Performance gains 20-35% when design is moved from bulk Si to
SOI.
• Benefits of SOI technology relative to conventional silicon (bulk
CMOS) :-
Lowers parasitic capacitance due to isolation from the bulk
silicon, which improves power consumption and thus high speed
performance.
Reduced short channel effects.

Reduced Short channel effects

 Contd…
Better sub-threshold slope.
No Latch up due to BOX(buried oxide).
Lower Threshold voltage.
Reduction in junction depth leads to low leakage current.
Higher Device density.
 SOI Fabrication
• Different methods used to fabricate SOI wafers:
SIMOX(Separation by IMplantation of OXygen) - uses an
oxygen ion beam implantation process followed by high
temperature annealing to create a buried SiO2 layer.
 SIMOX Wafer
 Fabrication
Ion-Implanting a high dose of oxygen ions(~1.4X10 18 O+ ions/cm2) into silicon wafer
 High temperature anneal to form SiO2 layer
 BESOI Wafer
 Fabrication
- Prepare 2 initial wafers
• Growing SiO2 on a wafer for substrate
• Make etchstop layer in a wafer for device layer
: boron doped layer, silicon-germanium layer,
carbon implanted layer, porous silicon layer
- Cleaning and bonding
- Two oxidizing wafers held together placed face-
to-face by applying external pressure at
oxidizing ambient
- Applying moderate voltage across two oxidized
wafers placed face-to-face at 1100~1200C
- One oxidized wafer and one bare wafer, both
are treated with acid solution forms O-H group
on surface and drying. Wafers placed face-to-
face and adhesive contact is formed at RT. And
1100C anneal in N2 ambient.
- Grinding or etching of upper wafer
- CMP touch polishing
Comparison of SIMOX vs. BESOI

 Low Cost Bonded SOI wafer fabrication suggested

- SMART Cut SOI
- Nanocleave Bonded Wafer SOI
 SMART-Cut SOI Wafer

 Hydrogen-implantation-induced layer splitting

 Smart Cut
- Allow reuse of sacrificial wafer  only one wafer
is required
 Fabrication
Two initial silicon wafers (A & B)
Wafer A is oxidized to form BOX
Wafer A is implanted by high dose hydrogen
(~5X106 H+ ions/cm2) through oxide, peak
located 0.2um below oxide-surface
Both Wafer A and B are cleaned and bonded.
Bonded wafer annealed at 400~600C
During anneal, hydrogen make micro crack
along the peak of hydrogen and wafer A
delaminate from along the line
High temperature anneal to reduce defects for
both wafers
CMP touch polishing
 Contd..
Wafer Bonding-One prominent example of the wafer
bonding process is the Smart Cut.
• The insulating layer is formed by directly bonding
oxidized silicon with a second substrate. The majority
of the second substrate is subsequently removed, the
remnants forming the topmost Si layer.
• Generally,wafers manufactured by this method have
thicker silicon layer above the insulator layer than those
produced by the SIMOX process.
• The newest of these technologies, “NanoCleave”,
represents a unique, second generation,approach that offers a
streamlined process flow and the potential for significantly
lower SOI manufacturing costs.

• With advanced SOI fabrication technology, such as

NanoCleave, the cost of SOI wafers can be substantially
reduced and create SOI wafers with exceptional material
quality and high yield.

• Unlike most other competing technologies, the critical

layer transfer and wafer bonding steps are accomplished at
room temperature.
 NANOCLEAVE PROCESS FABRICATION STEPS

SOI layer transfer techniques involve creating a dual-

layer of device-silicon and an insulator layer) (the Buried
OXide or “BOX”) grown on a “donor” wafer and bonded to a
“handle” wafer. These silicon and buried oxide layers are then
separated (‘cleaved’) from the donor wafer, producing a
finished SOI wafer. The NanoCleave process greatly simplifies
this layering sequence compared to earlier processes, resulting
in the potential for major cost reductions in SOI production.
 
 
 
NANO CLEAVE PROCESS FLOW
The NanoCleave process includes four main steps:

1. A “donor” wafer is formed by forming a high-quality

silicon layer (which will become the device layer in the final
SOI wafer). A cleave plane situated beneath this layer acts as a
guide for the cleave front during the separation process. A
thermal oxide is grown on the silicon layer that becomes part
of the buried oxide layer in the finished SOI wafer, Figure 4.
The thermal oxide growth process produces a buried oxide
layer that is free of pinholes and silicon inclusions.
2. The NanoCleave process uses implantation in combination
with other proprietary process steps to promote low-energy
cleaving along the desired wafer separation plane. A standard
beam line implanter is presently used for 200mm production
in the SiGen pilot line. However, looking ahead towards the
needs of high-volume 200mm and 300 mm SOI wafer
production, the implant step can be more cost-effectively
performed by Plasma Immersion Ion Implantation (PIII) using
tools, such as the SiGen PIII implanter.
3. Plasma treatment of the wafer surfaces enables the donor wafer
to be bonded to a bare or oxidized “handle” wafer with a bond
interface far stronger than the cleave plane. Because the device
silicon layer is separated by the buried oxide layer, a handle wafer
with considerably relaxed electrical and chemical specifications,
and therefore lower cost, can be used in this process.

4. Using Controlled Cleave Process (CCP), the donor and handle

are separated at room temperature. Using a controlled propagation
along a single cleave front, this atomic layer cleaving process
results in an as-cleaved surface roughness less than 1nm (typically
2-5 Angstroms). This is an order of magnitude smoother than the 80
Angstroms of typical hydrogen-induced thermal cleaving.Such a
smooth surface is acceptable for many IC applications with no
additional surface polishing.
 SOI MOSFETs
Two types of SOI-devices:
PD-SOI(Partial Depletion Type)
FD-SOI(Complete Depletion Type)

PD-SOI (Partially Depleted SOI) MOSFETs

1.Depletion width at maximum applied voltage <

thickness of silicon film thickness
Floating Body Effect
-Kink effect
• Generated holes moving floating body and
accumulated
lower the potential barrier between
floating body to source
 same effect with positive bias at floating body
decrease threshold voltage
unwanted increase of drain current
 Suppressing of Floating Body Effect

Kink

Drain Current
channel
N+ N+
Depletion
Region

Buried Oxide

Substrate Drain Voltage

 FD (Fully Depleted) SOI MOSFETs

 Entirely depleted through the thickness of silicon film

 Smaller floating body effect
 Benefits of FD SOI
-Sharper subthreshold slope
-Higher drive current
-Higher transconductance
-Reduced parasitic capacitance
-Reduced short channel effect

channel
N+ Depletion
N+
Region
Buried Oxide

Substrate
 How SOI solves SCEs?
• SOI have higher immunity to SCEs as compared to
bulk MOSFETs.
• This is due to the drain-source junction depth which is
50-100nm in 0.25-0.35 micro-meter SOI technology,
extremly shallow compared to bulk MOSFETs.
• Silicon film thickness of 10-15nm.
• Body doping also reduces SCEs.
 Application
• SOI has opened the door for opportunities in the low-
power arena.
• Used in wireless technology which requires the use of
high resistivity substrates.
• Used in case of faster speed operations.
• Microprocessors are built with SOI as substrate.
• SOI is an attractive alternative for low-voltage digital
CMOS logic, microprocessors, memories, sensors and
integrated optical electronics.
 Constraints
• Major challenge in SOI devices is the Floating body Effects.
• Here the body floats i.e., electrically isolated , therefore
substrate-source bias voltage is not fixed and hence device
threshold fluctuates.
• Among them Kink effect is noticable,more in case of PD-SOI
devices
• Due to this there is a sudden increase in drain current with
discontinuity resulting in worsening of the differential drain
conductance.
• Hence most of the effort in mapping bulk Si circuits to SOI is
spent fixing these effects-a challenge.
 Conclusion
• Today SOI is being used by many companies despite of the fact
that it is expensive and bringing it into the mainstream of Si
technology has been challenging.
• However,as we move to the 0.1micro-meter generation and
beyond,SOI offers the total solution to problems of bulk-Si
substrate and SOI will be the technology of choice.
THANK YOU