Field Effect Transistors: Celso José Faria de Araújo, DR

FIELD EFFECT TRANSISTORS
(FET)
Celso José Faria de Araújo, Dr.

FET X BJT (NPN)
Drain Collector
Gate Base
Source Emitter
FET BJT
 3 terminal device  3 terminal device emitter
 Channel e- current
to collector e- current
from source to drain controlled by the current
controlled by the injected into the base
electric field
generated by the gate
 Extremely high input
impedance for base
2
Field Effect Transistors
Electronics – Celso José Faria de Araújo, M.Sc.
Types of FETs
• In addition to carrier type (N or P channel), there are differences in
how the control element is constructed (Junction x Insulated) and
those devices must be used differently
npn
Depletion mode junction FETs (JFET)
pnp
npn
Metal oxide semi-conductor FET (MOSFET)
pnp
– depletion/enhancement mode
– enhancement mode
(insulated gate FETs, IGFETs, are the same as MOSFETs)
3
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W =
2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m. 4
v GS > VTN
S G
D vDS Small Waterfalls analogy
+ + Water
n n
Depletion p Acceptor Ion

Region
S G v GS > VTN v =v -V
D DS GS TN
+ +
n n
Depletion p
Region
S G v GS > VTN v >v -V

D DS GS TN
+ +
n n
Depletion p
Region Pinch-off Point
( a ) MOSFET in the linear region

( b ) MOSFET with channel just pinched
off at the drain.
( c ) Channel pinch off for vDS > vGS - VTN
5
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate
beneath the gate.
6
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS.
Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion
region is not shown (for simplicity).
7
W vDS 
2
vGS  Vtn
iD  μnCOX  vGS  Vtn  vDS  
L 2  0  vDS  vDSSAT= vGS-Vtn
8.00e-4
V =5 V
k n'  μnCOX
GS
small vDS
6.00e-4
W
Drain-Source Current (A)
VGS = 4 V iD  k n'  vGS  Vtn  vDS

L
VTN =1V
diD W
4.00e-4
 k n'  vGS  Vtn 
VGS = 3 V dvDS L
2.00e-4
V =2 V
GS
0.00e+0
0.0 0.2 0.4 0.6 0.8
Drain-Source Voltage (V)

NMOS i-v characteristics in the linear region (VSB = 0)
Linear Region (small vDS) 8

Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape and its resistance
increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
9
The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.
10
2.20e-4
iD  0 for vGS  Vtn
Linear V =5V
GS
2.00e-4 Region
W  v
2

iD  k n  vGS  Vtn  vDS 
' DS
1.80e-4
Pinchoff Locus 
1.60e-4
L 2 
vGS  Vtn
Saturation Region
1.40e-4
VGS= 4 V for 
vDS  vDS SAT  vGS  Vtn
1.20e-4
1.00e-4
k n' W
 vGS  Vtn  2
8.00e-5
iD 
6.00e-5 V
GS
=3V
2 L
4.00e-5
V Š1V vGS  Vtn
VGS= 2 V GS for 
vDS  vDS SAT  vGS  Vtn
2.00e-5
0.00e+0
0 2 4 6 8 10 12
Drain-Source Voltage (V) D

ID
Output characteristics G
for an NMOS transistor with vD  vS
Vtn = 1 V and k’n (W/L)= 25 x 10-6 A/V2
SB
11
Derivation of the iD - vDS characteristic of the NMOS transistor.
12
The PMOS Transistor
v v < 0
S G v < 0
D
i
iS G Gate iD Drain
Source
p+ Channel Region p+
N-Type Substrate
Body
i v > 0
B B
Cross section of an enhancement-mode PMOS transistor
B
S D
S D
ID
ID
G G
13
iD  0 for vGS  Vtp
 2

iD  k p  vGS  Vtp vDS 
' W v DS

L 2 
vGS  Vtp
for 
vDS  vDSSAT  vGS  Vtp
k p' W
iD   vGS  Vtp  2
2 L
vGS  Vtp
for 
vDS  vDS SAT  vGS  Vtp
SB
Output characteristics for a
PMOS transistor with
G
Vtp = -1V and k’P (W/L)= 25 x 10-6 A/V2 vS  vD
ID
D
14
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well.
Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.
15
(d)
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated.
(b)The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2 (d) The iD - vGS characteristic for an enhancement-
type NMOS transistor in saturation.
16
Channel Length Modulation
 Cox W
iD   vGS  Vt  2  I DSAT  L  LM L   vDS 
1
 VA  L
2 L LM 
I DSAT  Cox W
iD   I DSAT 1  L  iD   vGS  Vt  2 1   vDS 
1  L  LM  2 L
LM
LM
Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective
channel length (by L).
17
 Cox W
iD   vGS  Vt  2 1   vDS   Saturation
2 L
Output Resistance:
-1
 i  vDS  1
ro   D   
 vDS vGS  constant 

ID
VA
ro    I D  
1
 VDS  VA
ID
VA is directly proportional to L; thus two devices with the same process, and having channel lengths L1 e L2,
will have Early voltage VA1 and VA2,.
VA1 L1

V A2 L2
Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.
18
Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output
resistance models the linear dependence of iD on vDS and is given by ro  VA/ID.
19
Summary of equations for the enhancement-mode MOSFET
D D D S
P-channel
N-channel ID
G B G k n'  μnCox G B G
or or
ID
Vtn > 0 k  μ p Cox
'
p
Vtp < 0
S S vDS  0 D
vDS  0 S
Region N - Type P - Type
vGS  Vtn vSG  Vtp
Cutoff
iD  0 iD  0
vGS  Vtn and vDS  vGS  Vtn vSG  Vtp and vSD  vSG  Vtp
Triodo
 
 
2
vDS  
 
2
(Linear) iD  k n' W v  V v  ' W vSD
L  GS 2  iD  k p v  V v 
tn DS
L  SG tp SD 2 
vGS  Vtn and vDS  vGS  Vtn vSG  Vtp and vSD  vSG  Vtp
Saturation k n' W 2 V  2 VSD 
iD 
2 L
 vGS  Vtn  1  DS  iD 
k p' W
L
v  V  1 
 V 
 VA 
SG tp
2  A 
20
The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2:
(a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.
21
Bias Circuits 1
-  usually neglected ( 1/  =VA)
- Q-point most often located in saturation for analog circuits
R2
VG  VDD
VDD R1  R2 R2
VGS  VDD  RS I D
VS  RS I D R1  R2
RD
R1
ID
VDS  VDD   RD  RS  I D
VG
k n' W
ID   VGS  Vt  ( assuming the MOSFET to be
2
R2 RG 2 L in the saturation region )
RS
2
k  R2
'
 ( two solutions  only one
ID  W  n
VDD  Vt  RS I D 
2 L  R1  R2  is possible )
Ex: VDD = 10 V R1 = 150 k R2 = 100 k RS = 10 k

RD = 50 k k’n(W/L) = 50 A/V2 Vt = 1 V
Solution: ID = 100 A VDS = 4 V

22
Bias Circuits 2
VDD VDD Analysis
k n' W
RD
 VGS  Vt 
RD 2
RG
ID 
ID
2 L
RG
RS
VGS  VDD  RD I D
k n'
I D  VDD  Vt  RD I D 
-VSS
2
Two power supplies are 2

available
VGS  VDS   I G  0
VDD
V DD / RD
RD
load line
curve VDS = VGS
V GS1
Q
RG
I V GS2
V GS3
-VSS
A simple circuit utilizing V DS = VGS2 V DD
a current source
23
Example: VDD = 5V ;IREF=10A; Q1 and Q2 are
matched ; L=10 m and W=100 m; Vt = 1V ;
k’n=20  A/V2 VA = 10L; Vo=+3V
1 100
I D1  I REF  100  20 VGS  1 2
2 10
Q1: I  V converter VGS  2V
Q2: V  I converter 52
R  30 K
If Q2 in saturation 100
v omin  VGS  Vt  vomin  2  1  1V
100V
VA  10 x 10  100V  ro   1M
W 
100 μA
then
Vo 3V
Io
 L
W L
2 I o    3 μA  3%
ro 1M
I REF
1 Basic MOSFET current mirror.
24
DC Bias Point
1 'W
k n VGS  Vt     0
2
ID 
2 L
VD  VDD  RD I D  VD  VGS  Vt
The signal Current in the Drain Terminal
k n VGS  v gs  Vt 
1 'W 2
vGS  VGS  v gs  iD 
2 L
1 W
iD  k n' VGS  Vt  2  kn' W VGS  Vt  vgs  1 kn' W vgs2
2 L L 2 L
1 'W 2 W
k n v gs  k n' VGS  Vt  vgs  vgs  2(VGS  Vt )
2 L L
                    
small signal
W
iD  I D  id  id  k n' VGS  Vt  vgs
L
i i W
gm  D  d  k n' VGS  Vt   2kn' W L I D
vGS v gs L
    vGSVGS                 
transconductance
Voltage Gain
vD  VDD  RD iD  VDD  RD ( I D  id )  VD  RD id
vd
vd  id RD   g m RD v gs  Av    g m RD
v gs
The operation of the MOSFET as an amplifier. 25

(b.1) -Model
(a.1) -Model
(a.2) T-Model (b.2) T-Model
Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation effect); and
(b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
26
Example: Vt = 1.5V ; k’n(W/L)=0.25 mA/V2 VA = 50V
DC Analysis
1
0.25mVD  1.5
2
VGS  VD  I D 
2
VD  15  RD I D  15  10K I D
I D  1.06mA and VD  4.4V  Physically Meaningful
g m  0.25m(4.4  1.5)  0.725mA/V
50
ro   47KΩ
1.06m
AC Analysis
vo v v
 g m vi  o i  0
ro // RD // RL RG
Voltage Gain
vo
Av    g m  1  ro // RD // RL // RG   3.37 V
vi  RG  V
Input Resistance
vi  vo  4.3vi
ii   vi  vo  RG  1   
RG  vi  RG
vi RG
Rin    2.33MΩ
ii 4.3
27
Body Transconductance
iD
g mb    gm
vBS vGS  constante
v DS  constante
0.1  χ  0.3
Small-signal equivalent-circuit model of a MOSFET in which the body is not connected to the source.
28
Basic amplifier configurations with current sources
VDD VDD
VDD
I
I
vo
vo
vI
vo
vI
I
vI
-VSS
Source follower Common-source Common-gate

or common-drain amplifier amplifier
amplifier
29
ID2
ID2
Ri   Ro  ro1 // ro 2
Av   g m1  ro1 // ro 2 
The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to determine
the transfer characteristic; and transfer characteristic.
30
Example: VDD=10V;Vtn = | Vtp| = 1V ; k’n= 2 k’p= 20 A/V2
(W=100 m; L =10 m |VA|= 100V for both the n and p device)
IREF=100 A.
vO
I REF  I D 2  I D1  100 μA Slope = -100V/V
10
I D 3  I REF  100 μA 
1 ' W 

k p   VSG  Vtp
2  L 3
 2
 VSG  2.41V
8.59
Bias Point
vOmax  10  (VSG  Vtp )  8.59V
vOmin  VI  Vtn  1V
4.795

VO  vOmax  vOmin  ro1
ro1  ro 2
 vOmin  4.795V
1 ' W 
k n   VI  Vtn   VI  2V
2
I D1  I REF  100 μA 
2  L 1
1
W 
g m1  2k   I REF  0.2m A
'
n
 L 1 V
1.96 2 2.04 vI
VA
ro1  ro 2   1MΩ
I REF
^ ^
v
Av  o   g m1  ro1 // ro 2   100 V v o  3.795Vp  v i  40mVp
vi V
Rin    Ro   ro1 // ro 2   0.5MΩ
31
vo  1
Av    g m1  g mb1   ro1 // ro 2 
vi  ro1 
Av   g m1  g mb1  ro1 // ro 2 
vi 1  ro 2 
Ri   1  
ii g  g  1  ro1 
m1 mb1
ro1
1  ro 2 
Ri  1  
g m1  g mb1  ro1 
The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).
32
vo g m1 RS g m1
Av   
vi 1  g m1 RS g  g  1  1
m1 mb1
ro1 ro 2
g m1 1
Av  
g m1  g mb1 1  χ
Ro   1  //  1  // r // r
 o1 o 2
 g m1   g mb1 
1
Ro   1  //  1 

 g m1   g mb1  g m1 1  χ 
The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
33
 W L 1  W L  1
vO  VDD  Vt  V  v

 W L  2 t  W L  2 I
Av  
W L1 1

W L 1
W L 2 1   2 W L 2
(a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer characteristic.
34
vo  1  
Av    g m1   // ro1 // ro 2 
vi  g mb1  
g m1 W L  1 1
Av   
g mb 2 W L  2 χ
The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic. 35
rDSN  1
 ' W  
k 
 n L   VDD  V 
tn 
  n 
Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
36
rDSP  1
 ' W 

k p   VDD  Vtp 
  L  p 
Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
37
1
VIH   5VDD  2Vt 
8
1
VIL   3VDD  2Vt 
8
Noise Margins
1
NM H   3VDD  2Vt 
8
1
NM L   3VDD  2Vt 
8
The voltage transfer characteristic of the CMOS inverter.
38
Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the
operating point as the input goes high and C discharges through the Q N; (d) equivalent circuit during the capacitor discharge.
39
Strong inversion and saturation:
VGS – Vt > 200 mV
g m  2 k W L  I D
VA  VDS
ro 
ID
2
C gs  CoxW L
3
(a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected to the
substrate (body); (c) the equivalent circuit model of (b) with C db neglected (to simplify analysis).
40
Io gm

I i s  C gs  C gd 
For physical frequencies s = j, it cam be seen that the magnitude of the current gain becomes
unity at the frequency:
gm
fT 
2π C gs  C gd 
Determining the short-circuit current gain Io/Ii.
41
The Junction Field-Effect Transistor
G Depletion
G Depletion
region
region
p
p
p
p
v =0 VP < vGS < 0
GS
S D W'
S D
n W
+- n
i
G
p
p
p
Depletion
Depletion
region
G G region
G Depletion
region
vGS = VP < 0
( a ) JFET with zero gate-source bias
p
p
n
D
( b ) JFET with negative gate-source voltage
S Pinched-Off Channel
+- that is less negative than the pinch-off
voltage VP. Note W’ < W
p ( c ) JFET at pinch-off with VGS = VP
p
Depletion
G region
42
Depletion
G
region
p
v
GS < 0
S D
+- n i DS
( a ) JFET with small drain-source
v
DS
Depletion
G region
Depletion
G region
p
p
v
GS
S D
+- n i DS
( b ) JFET with channel just at
v =v
DS DSP
pinch-off with vDS = vDSP
p
Depletion
G region
The Junction Field-Effect Transistor ( a ) JFET with small drain-source ( b ) JFET with channel just at
pinch-off with vDS = vDSP 43
Summary of equations for the JFET
D
S P-channel
iD N-channel G
VP  0 VP  0
G
iD
vGS max  0 vGS min  0
S D
Region N - Type P - Type

vGS  VP vGS  VP
Cutoff
iD  0 iD  0
VP  vGS  0 and vDS  vGS  VP 0  vGS  VP and vDS  vGS  VP
Triodo
  v v  v 
2
   v v  v 
2

(Linear) iD  I DSS 21  GS
 DS
  DS
  iD  I DSS 21  GS
 DS
  DS
 
  VP   VP  VP     VP   VP  VP  
VP  vGS  0 and vDS  vGS  VP 0  vGS  VP and vDS  vGS  VP
2 2
Saturation  v   VDS   v   VDS 
iD  I DSS 1  GS  1   iD  I DSS 1  GS  1  
 V A   
 VP    VP   VA 
 2 I DSS  VGS   2 I DSS  ID VA

g m   1 
 V
  


 I  ro 
 VP  P   VP  DSS ID
44
2.20e-4
Linear V =0V
GS
2.00e-4 Region I DSS
1.80e-4 Pinch-off Locus

1.60e-4
Pinch-off Region
(Saturation)
1.40e-4
V = -1 V
1.20e-4 GS
1.00e-4
8.00e-5
6.00e-5 V GS= -2 V
4.00e-5
VGSŠ VP
2.00e-5 VGS= -3 V
0.00e+0
0 2 4 6 8 10 12
Drain-Source Voltage (V)
Output characteristics for a JFET with IDSS = 200 A and VP = -4V
45
1.50e-3
Drain-Source Current (A) 1.00e-3 I

DSS
5.00e-4
0.00e+0
V
P
-5.00e-4
-6 -5 -4 -3 -2 -1 0 1 2 3
Gate-Source Voltage (V)
Transfer characteristic for a saturated JFET with IDSS = 1 mA and VP = -3.5V
46
When to use JFETs
 JFET have much higher input impedances
and much lower input currents than BJTs.
 BJTs are more linear than JFETs.
 The gain of a BJT is much higher than that
of a JFET.
47
JFET (Example)
The JFET in the circuit below has VP=-3V, IDSS=9mA, For the JFET circuit designed in the former exercise,
and =0. Find the values of all resistors so that VG=5V, let an input signal vi be capacitively coupled to the
ID=4mA, and VD=11V. Design for 0.05mA in the gate, a large bypass capacitor be connected between
voltage divider. the source and ground, and the output signal vo be
taken from the drain through a large coupling
capacitor. The resulting common-source amplifier is
shown below. Calculate gm and ro (assuming
VA=100V). Also find Ri and Ro.
R G2 2
5 15  5  VS 
R G2  R G1 4m  9m1  
 3
        
15  2x9m  4m
A  r  100  25KΩ
 0.05m Saturation
g m   
  4m
V o 4m
R G2  R G1 VS'  6V  VS''  10V   3  9m
  
R G1  200KΩ Ok
R G2  100KΩ R S  1.5KΩ
vo
15  11 Av    g m  ro // R D   3.85 V
V
RD   1KΩ vi
4m Ro  ro // R D  962  Ri  R G1//R G2  66.7KΩ
48
References
 SEDRA. Adel S. e SMITH, Kenneth C. Microelectronic
Circuits. Oxford University Press.
 BOYLESTAD, Robert e NASHELSKY, Louis.
Dispositivos Eletrônicos e Teoria de Circuitos. Prentice
Hall do Brasil.
 SZE, S. M. Physics of Semiconductor Devices. John
Wiley & Sons.
 SCHILLING, Donald L. e BELOVE, Charles. Circuitos
Eletrônicos Discretos e Integrados. Guanabara Dois.
 COMER, David J. Introduction to Semiconductor
Circuits Design. Addison Wesley Publishing Company.
 MALVINO, Albert P. Eletrônica. Volume I. McGraw-
Hill.
49

Field Effect Transistors: Celso José Faria de Araújo, DR

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FIELD EFFECT TRANSISTORS

Celso José Faria de Araújo, Dr.

(insulated gate FETs, IGFETs, are the same as MOSFETs)

Depletion p Acceptor Ion

S G v GS > VTN v >v -V

( a ) MOSFET in the linear region

VGS = 4 V iD  k n'  vGS  Vtn  vDS

Drain-Source Voltage (V)

Linear Region (small vDS) 8

Drain-Source Voltage (V) D

Ex: VDD = 10 V R1 = 150 k R2 = 100 k RS = 10 k

Solution: ID = 100 A VDS = 4 V

Two power supplies are 2

The operation of the MOSFET as an amplifier. 25

(a.2) T-Model (b.2) T-Model

Source follower Common-source Common-gate

The voltage transfer characteristic of the CMOS inverter.

VGS – Vt > 200 mV

Determining the short-circuit current gain Io/Ii.

Region N - Type P - Type

 2 I DSS  VGS   2 I DSS  ID VA

1.80e-4 Pinch-off Locus

Drain-Source Current (A)

Drain-Source Voltage (V)

Output characteristics for a JFET with IDSS = 200 A and VP = -4V

Drain-Source Current (A) 1.00e-3 I

Gate-Source Voltage (V)

Transfer characteristic for a saturated JFET with IDSS = 1 mA and VP = -3.5V

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