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Microcontroller Archt
Microcontroller Archt
X = AD + CBD
Y= C+D
Z = C ( DB + CA)
Where
C=AB D=A+B
A 8
8 C
8 bit OR gate can be represented as B 8
A 8 8
8 bit NAND gate can be represented as 8 C
B
A 8
8 C
8 bit NOR gate can be represented as B 8
8
A 8
8 bit EXOR gate can be represented as 8
C
B
A 8
8
8 bit EXNOR gate can be represented as 8 C
B
A 8 8
8 bit NOT gate can be represented as C
X = AD + CBD
C = AB
D = A+B
A 8 8 A 8
8C 8 8
8 8
B 8
8
CB 8 8
CBD 8
X
8 8
8 8
8 8 8 8
8 AD
D
A 8 8 A 8 CB
8C 8 8
8
B 8
8
8 Z
8 8
8 8
8 8 8 D 8
8 AD
Summary
For every equation different circuit is required.
A 8 8
8 C
B
8
A 8
8 C
B
A 8
8 C
B 8
8
A 8
8 C
B
A 8 8
C
Integrate all gates into one IC
7 3 bit D0
D1
8
decoder D2
A 8
8 C
B
A 8 8 8 Q
8 C
B
A 8 8
8 C
B
8
A 8
8 C
B
8
A 8
8 C
B
A 8 8
8 C
B
8 8
A A’
Integrate all gates into one IC
7 3 bit D0
D1
8
decoder D2
A 8
8
B
A 8 8 8 Q
8
B
A 8 8
8
B
8
A 8
8
B
8
A 8
B 8
A 8 8
B 8
8 8
A
Integrate all gates into one IC
7 3 bit D0
D1
8 8
decoder D2
A 8
8
B
8 8 8 Q
8
B
8 8
8
B
8 8
8
B
8 8
B 8
8 8
B 8
8 8
Integrate all gates into one IC
7 3 bit D0
D1
8 8
decoder D2
A 8
8 8
B
8 8 8 Q
8
8 8
8
8 8
8
8 8
8
8 8
8
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8
B
8 8 8 Q
8
8 8
Function D0 D1 D2 D3
8
AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8
NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8
NOT 0 1 1 1
8 8
8
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2 Enclose this integrated circuit in a DIL package
8 8
decoder D3 This IC has 30 terminals in it and a state table
A 8 to configure operating mode
8 8
B Now a option available that we can use same
IC to build an application circuit configuring it
8 in different modes.
8 8 Q
This modification is just we want
8
State table
8 8
Function D0 D1 D2 D3
8
AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8
NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8
NOT 0 1 1 1
8 8
8
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2 Enclose this integrated circuit in a DIL package
Advantages
8 8
decoder D3 No
Thisneed to30
IC has keep multiple
terminals ininventory of table
it and a state
A 8 different IC’soperating mode
to configure
8 8 Cost will reduce due to large production
B Now a option available that we can use same
Workability with same IC is easy
IC to build an application circuit configuring it
8 in different modes.
8 8 Q Disadvantages
This modification is just we want
8 Large space is required
State table
8 8
Function D0 D1 D2 D3
8
AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8
NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8
NOT 0 1 1 1
8 8
8
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2 Advantages
8 8
decoder D3 No need to keep multiple inventory of
A 8 different IC’s
8 8 Cost will reduce due to large production
B Workability with same IC is easy
8 8 8 Q Disadvantages
8 Large space is required
State table
8 8
Function D0 D1 D2 D3
8
AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8
NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8
NOT 0 1 1 1
8 8
8
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3 In order to implement the solution of digital
A 8 equation through this IC. Lots of space is
8 8 required
B
In process to reduce the space consumption
8 8 8 Q engineers reconstructed the architecture of IC.
8
State table
8 8
Function D0 D1 D2 D3
8
AND 0 0 0 1
OR 0 table
State 0 1 0
8 8 Function D00 D01 D12 D13
NAND
8 AND 0 0 0 1
NOR 0 1 0 0
OR
EXOR 0
0 0
1 1
0 0
1
8 8 NAND
EXNOR 0
0 0
1 1
1 1
0
8 NOR 0 1 0 0
NOT 0 1 1 1
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8 NOT 0 1 1 1
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8 If Dir = 0 then current will flow from right to left and
B
If Dir = 1 then current will flow from left to right
8 8 8 Q
8
8 8
8
8 NOT 0 1 1 1
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8 If Dir = 0 then current will flow from right to left and
B
If Dir = 1 then current will flow from left to right
8 8 8 Q
8 TRIS
8 8
8
8 State table
8 Function D0 D1 D2 D3
8
Pout Pin AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8 NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8 TRIS NOT 0 1 1 1
8
P
8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8
B
8 8 8 Q
8
8 8 TRIS
8
P
8 State table
8 Function D0 D1 D2 D3
8 AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8 NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8 TRIS NOT 0 1 1 1
8
P
8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8
B Let make this suitable for an 8 bit operation
8 8 8 Q
8
8 8 A TRIS
8
TRISA TA0
A0
8 State table
8 Function D0 D1 D2 D3
8 AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8 NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8 NOT 0 1 1 1
8 8
Integrate all gates into one IC
D0
7 4 bit D1
D2
8 8
decoder D3
A 8
8 8
B Let make this suitable for an 8 bit operation
Enclose all 8 into 1
8 8 8 Q
8 TA0
PA0
A0 TRISA TA0
PA1 TA1
8 8 A1 TRISA TA1
8 TA2
PA2 A2 TRISA TA2
PA3 TA3 State table
8 8 A3 TRISA TA3 Function D0 D1 D2 D3
8 PA4 TA4 AND 0 0 0 1
A4 TRISA TA5
TA5 OR 0 0 1 0
8 PA5 A5
8 TRISA TA5 NAND 0 0 1 1
8 PA6 TA6 NOR 0 1 0 0
A6 TRISA TA6
EXOR 0 1 0 1
PA7 TA7
8 A7 TRISA TA7
8 EXNOR 0 1 1 0
8 NOT 0 1 1 1
TRISA TRIS T7 T6 T5 T4 T3 T2 T1 T0
8
A
8
PORT P7 P6 P5 P4 P3 P2 P1 P0
PORTB B7 B6 B5 B4 B3 B2 B1 B0
PORTA A7 A6 A5 A4 A3 A2 A1 A0
8 TRISA T7 T6 T5 T4 T3 T2 T1 T0
8 TRISB T7 T6 T5 T4 T3 T2 T1 T0 D0
4 bit 4
D1 Counter
decoder D2 oscillator
A 7
8 8
D3
8
B 8 8
8 8 8 Q
8
8 8
8 8
TRISA
A 8 State table
8 8 Function D0 D1 D2 D3
8 AND 0 0 0 1
OR 0 0 1 0
8 8 NAND 0 0 1 1
8 NOR 0 1 0 0
EXOR 0 1 0 1
8 8 EXNOR 0 1 1 0
8 NOT 0 1 1 1
8 8