Segment: Timer Programmable Interval

S e gme nt 7
PROGRAMMABLE INTERVAL TIMER 8254

Contents:
✓ Why 8254?
✓ 8254 Vs 8253.
✓ Features and Application of 8254.
✓ Pin functions.
✓ Read and Write Operation.
✓ Modes of operation.
✓ Problems on 8086-8254 based system.
What is 8254?
The Intel 8254 is a counter/timer device designed to solve the common timing
control problems in microcomputer system design. 8254 is the high speed
version of the 8253.
07
06
05
2
3
° 24
23
22
vcc
WR
RD
D4 4 21 cs
D3 5 20 Al
Intel
02 6 19 AO
8254
D1 7 18 CLK 2
DO 8 17 OUT2
CL 9 16 GATE
K0 10 15 2
OU 11 14 JcuK
T0 12 13 1
GAT ] GATE
8254 Vs 8253 E0 1
G OUT 1
Characteristic s 8254
ND 8253
F re que nc y Ra nge DC to 8 MHz DC to 2 MHz
DC to 10 MHz (8254-2)
Speci al Command Status read-back No such command

command
Lecture materials on "Programmable interval timer, 8254" By- Mohammed Abdul Kader, Lecturer, EEE, IUC
Application
Some of the other counter/timer functions common to microcomputers

which can be implemented with the 8254 are:
✓ Real time clock
✓ Event-counter
✓ Digital one-shot
✓ Programmable rate generator
✓ Square wave generator
✓ Binary rate multiplier
✓ Complex waveform generator
✓ Complex motor controller
8254 Features
✓ It includes three 16-bit counters that can work independently in 6

different modes.
✓ It is packaged in a 24-pin DIP(Dual in-line package) and requires
+5V power supply.
✓ It can count either in binary or BCD.
✓ It's counters can operate at a maximum frequency of 10 MHz.
Functional Diagram
DATA CL f
D7 -D0 BUS COUNTER --- G AT E
0
BUFFE O
Cl_lT []
R
t
RD CLK 1
1F? FREAD' h( =
WRITE z COUNTER
GATE 1
•
1. 1
AO LOGIC
A1
cr° OUT 1
LL
I -
z
cs
CTRL. CL 2
COUNTER
WwWO I
2 GATE 2
FD
OUT 2
REG.
Lecture materials on "Programmable interval timer, 8254" By- Mohammed Abdul Kader, Lecturer, E E E , IU C
Pin functions
AO, Al: The address inputs select one of the four internal registers within the
8254.
Al AO F un c t i o n
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control
Word
CS: Chip select enables the 8254 for programming and for reading or writing a
counter.
Vee: Power connects to the +5V power supply.
GND: Ground connects to the system ground bus.

GATE : The gate input controls the operation of the counter in some modes of
operation.
GATEO Gate input of counter 0
GATE 1 Gate in pu t of cou n t er 1
GATE2 Gate inpu t of cou n t er 2
Pin functions (Continue d)
D0-D7: Bidirectional three state data bus lines connected to system data bus.
CLK : The clock input is the timing source for each of the internal counters.
This input is often connected to the PCLK signal from the
microprocessor system bus controller.
CLKO Clock input of counter 0
CLKl Clock input of counter 1
CLK2 Clock input of counter 2
OUT: A counter output is where the waveform generated by the counter is

available.
OUT0 Output of counter 0

OUTl Output of cou n t er 1
OUT2 Output of cou n t er 2
RD: Read causes data to be read from the 8254 and often connected to the
IORC signal.
WR: Write causes data to be written to the 8254 and often connects to the
write strobe (/OWC)
Lecture materials on "Programmable interval timer, 8254" By- Mohammed Abdul Kader, Lecturer, EEE,
IUC
8254 S y s t e m I n t e r f a c e
\ ADDRESS BUS (16) ~
A; Ao
~ CONTROL BUS \
OR / Ow
) DATA BUS (8) \
,
8
1 w
' < W
' Ao cs n W
A > R
COUNTER 0-Dr COUNTER
0 8254 2
I I I
'our GA cuK 'our cLK' 'our GATE cuK
COUNTER
GA
TE TE1
' '
¥
ff I •
ff f
ff
Lecture materials on "Programmable interval timer, 8254" By- Mohammed Abdul Kader, Lecturer, EEE, IIUC
P r o g r a m m i n g the 8254 (Control Word F o r m a t )
An.Ao = 11 C S = 0 RD =1 WRR = 0
D7 De Ds D4 Da D5 D; Do
I SC I sc [m RW I [ ] MO I I
1 0
o w] M2 BCD
SC-Select Counter M--Mode
SC1 SCO M2 M1 MO
0 0 Select Counter 0 0 0 0 Mode0
0 1 Select Counter 1 0 0 1 Mode 1
1 0 Select Counter 2 X 1 0 Mode2
1 1 Read-Back Command X 1 1 Mode3
(see Read Operations) 1 0 0 Mode4
1 0 1 Mode5
RW--Read/Write
RW1 RWO
BCD
0 0 Counter Latch Command (see Read
Operations) 0 Binary Counter 16-bits
0 f Read/Write least significant byte only 1 Binary Coded Decimal (BCD) Counter
(4 Decades)
1 0 Read/Write most significant byte only
1 1 Read/ Write least significant byte first,
then most significant byte
NOTE:
Don't care bits (X) should be 0 to insure compatibility with future Intel products.
8254 Write operation
The programming procedure for the 8254 is very flexible. Only two conversion
need to be remember.
1) For each Cou n t er , the Con t r ol Wor d m ust be w ritten befor e the
in it ia l cou n t is wr it t en .
2) The initial count must follow the count format specified in the Control
Word (least significant byte only, most significant byte only, or least
significant byte and then most significant byte).
With a clock and an appropriate gate signal to one of the counters , the above
steps should start the counter and provide appropriate output according to the
control word.
8254 Read Operations
There are three possible methods for reading the counters:

✓ A simple read operation
✓ The Counter Latch Command, and
✓ The Read-Back Command.
Simple Read O pe ration
✓ This operation read the counter after stopping.
✓ To read the Counter, which is selected with the Al, AO inputs, the CLK
input of the selected Counter must be inhibited by using either the GATE
input or external logic. Otherwise, the count may be in the process of
changing when it is read, giving an undefined result.
✓ Two I/O read oper at ion are per for m ed by the MP U
1. The first I/O operation reads the low order byte.
2. The second I/O operation reads high order byte.
Counter Latch Command
✓ This allows reading the contents of the Counters "on the fly"
without affecting counting in progress.
✓ The selected Counter's output latch (OL) latches the count at the
time the Counter Latch Command is received.
✓ This cou n t is held in the la t ch un til it is read by the CPU (or until th e
Cou n t er is repr ogr a m m ed). The cou n t is th en un la t ch ed
au t om a t ica lly and the OL re tu rn s to "followin g" the cou n t in g elem ent
(CE).
Counter Latch Command (Continued)
✓ Counter Latch Commands do not affect the programmed Mode of the
Counter in any way.
A+,Ao = 11CS = 0:RD = 1WR = 0
✓ Example: ' $ '
D, D¢ Ds D, D% D, Do
; Latching cou n t er 0 O D,
[so sc O I X X X I X
MOV DX, C_REG
] o I I I
MOV AL, 00000000B ; count latched
for counter 0.
I
SC1,SC-specify counter to be latched
OUT DX,AL SC1 SCO Counter

0 0 0
;Reading counter0 0 1 1
f 0 2
MOV DX, CNTR0
1 1 Read-Back
IN AL, DX Command
05 ,04-00 designates Counter Latch
Command
X-don't care
NOTE:
Don't care bits (X) should be O to insure
compatibility with future Intel products.
Fig: Counter Latching Command

Lecture materials on "Programmable
Format
Read-Back Command
✓ This command is used to read several counters at a time. It eliminates the
need of writing separate counter-latch commands for different counters.
✓ It allows the user t o check the cou n t valu e, program m ed Mode, and
cu r r en t states of the OUT pin and Null Count flag of the selected cou n t er /
cou n t er s.
✓ The read back command is written to the Control Word Register.
✓ The command is written into the Control Word Register and has the format
shown in Figure.
A0, A1 = 11 CS=0
✓ The read-back command may be
used to latch multiple counter D De D; D, Dg D D; Do
output latches (OL) by setting the []ilcouvr[srrus[cwr 2[cvr

COUNT bit D5 =O and selecting
the desired counter(s).
i[cvrolo]
De.:0 = Latch countof selected
Latch status of selected
counter(s)
Dz: counters(s)
✓ A single read back com m and Select Counter 2
O=
Select Counter 1
is functionally equivalent t o Dg: 1=
Selectfor
Do: Reserved future expansion;
Counter O Must be
Dg: 1 =
sever a l cou n ter latch 0
D;: 1 =
com m an d s . Figure Read-Back Command Format
✓ Each counter's latched count is held in the OL until it is read (or the com ~~
is reprogrammed). The counter is automatically unlatched when read , bub
other counters remain latched until they are read.
Read-Back Command (Continued)
✓ The read-back command may also be used to latch status information of
selected counter(s) by setting STATUS bit D4 = 0. Status must be to
be read; status of a counter is accessed by a read from t ha t counter.
latched
✓ The counter status format is shown in Figure below.
Nul
Output l RW1 RWO M1 MO
M2 BCD
Cou
D 1 nt OUT Pin is 1
7 = OUT Pin is
D 0 = Null Count
O
¢ 1 Count available for
= reading
Ds-Do Counter programmed
mode O
=
✓ Bits D5 through DO contain the counter's programmed Mode exactly as
written in the last Mode Control Word.
✓ OUTPUT bit D7 contains the current state of the OUT pin. This allows bke
user to monitor the counter's output via software, possibly eliminating
some hardware from a system.
Read-Back Command (Continued)
Example:
; Count and St a t u s la t ch ed for cou n t 0
MOV DX, C_REG
MOV AL, 11000010B; count latched for count 0
OUTDX,AL
; R eading the status for count 0

la t ch ed
MOVDX, TRM0 Status
IN AL, DX ;
Rea din g
MOV AH, AL latched count for counter 0
; Reading
th e
; Reading LSB of cou n t er
IN AL, DX 0
MOVBL,AL ; Reading MSB of cou n t er
IN AL, DX 0
MOVBH, AL
Modes of Operation
Mode 0: Interrupt on terminal count.
Mode 1: Hardware Retriggerable One-Shot.
Mode 2: Rate Generator.
Mode 3: Square Wave Mode.
Mode 4: Software Triggered Mode.
Mode 5: Hardware Triggered Mode.
M o d e 0: I n t e r r u p t o n t e r m i n a l c o u n t .
WR
CLK
* N stands for an
undefined count.
GATE
OUT
I I I I 11 $ 111 : II : I
✓ Mode O is typically used for event counting.
✓ A fter the Con t r ol Wor d is wr it t en , OUT is initially low, and will rem ain
low until the C ounter reaches zer o. OUT th en goes high and rem ains high
un t il a new cou n t or a new Mode O Con t r ol Wor d is w ritten in t o the
✓ A Cou
ftern t er
the. Con t r ol Wor d and initial cou n t are w ritten to a Cou n t er ,
th einitial cou n t will be loaded on the next CLK pu lse. This CLK pulse
decrement the count, so for an initial count of N, OUT does not go high until
not
N + 1 CLK pulses after the initial count is written.
does
Mode 0: Interru pt on terminal coun t. (C ontinu ed)
✓ GATE =1 enables counting; GATE = 0 disables counting.
✓ GATE has no effect on OUT. If G becomes a logic O in the middle of the

count, the counter will remain stop until G again becomes a logic 1.
✓ If a new count is written to the Counter, it will be loaded on the next

CLK pulse and counting will continue from the new count.
CW= 10 LSB=3 C W=10 LSB=3 LSB =2

WR WR
CLK
CLK
GATE
GATE
.- OUT
I
OUT L t i
v y v y j v
I I I 1 3 1 1 1 1 1 % 15 I I I 1 ' 3 1 1 : 1 1 : II
- '---y----1
Freeze 1
✓ At the rising edge of WR(CW) OUT becomes high.
< At the first falling edge of clock after first rising edge of WR(LSB), counter
starts counting. d'
Mode 1: Hardware Retriggerable One-Shot.
CW=12 LSB=3
WR
CIL
K
GATE
. «
OUT
;l
✓ Causes the counter to function as a retriggerable, monostable

multivibrator (one-shot).
✓ OUT is initially (after loading CW) high. Also remain high when count
is written.
✓ When gate is triggered, OUT goes low and will remain low until the
Counter reaches zero. On completion of count OUT goes high again.
Mode 1: Hardware Retriggerable One-Shot. (Continued)
✓ If the GATE input occurs within the duration of counting , the counter is
again reloaded with the count and start counting from the beginning.
CW = 12 LSB = 3
CW = 1 2 LSB =2 LS B= 4
WR WR
CLK CLK
GATE GATE
OUT OUT

✓ At the first falling edge of clock after first rising edge of GATE counter
starts counting.
Mode 2: RATE GENERATOR
CW=14 LSB=3
WR
CLK
GATE
OUT
✓ Allows the counter to generate a series of continuous pulses that are one
clock pulse wide.
✓ The separation between pulses is determined by the count.

✓ If count N is loaded then, output will remain high for (N-1) clock period
and low for 1 clock period.
Mode 2: RATE GENERATOR (Continued)
✓ For example, for a count of 10, the output is a logic 1 for nine clock
period and low for 1 clock period. This cycle is repeated until the counter
is programmed with a new count or until G pin is placed at a logic O level.
✓ The G input must be logic 1 for this mode to generate a continuous series
of pulses.
✓ In mode 2, a COUNT of 1 is illegal.

CW=1 4 LSB = 3 CW = 14 LSB = 4 L SB=5
WR
CL
K I
X
GATE I
n t-
I
O'UT .. - - . . . . .- - ......- ::- - - ..........

y y y y y
I I I 1 . 3 1 1 [ 3 1 : 11 % L
Freeze
✓ At the first falling edge of clock after first rising edge of WR(LSB), c o u n g
starts counting.
M o d e 3: Square Wa v e Mode.
CW=16 LS B= 4
WR
CLK
OUT
✓ Generates a continuous square wave at the out connection.
✓ Mode 3 is similar to Mode 2 except for the duty cycle of OUT.

✓ If the count (N) is even, the output is high for one half (N/2) of the count
and low for one half (N/2) of the count.
✓ If the count (N) is odd, the output is high for one clocking period
longer than it is low i.e. high for (N+l)/2 clock pulses and low for (N-
1)/2 clock pulses.
Mode 3: Square Wave Mode. (Continued)
✓ For example, if the count is programmed for a count of 5 , the output is

high for three clocks and low for two clocks.
✓ Gate should be maintained at logic 1 always (GATE =1 enables counting;

GATE =O disables counting. If GATE goes low while OUT is low, OUT is
set high immediately; no CLK pulse is required).
CW= 16 LSB CW= 16 LSB =

=5 4
WR WR
CLK
CLK
GATE
. i
OUT 1 1
0UT 1
d I 1 '
j j
j · E L L I : E L L ·FIE:AIL:I:I: L:TI:I
Freeze
✓ At the rising edge of WR(CW) becomes high.
OUT
< At the first falling edge of clock after first rising edge of WR(LSB), count%
starts counting.
Mode 4: Soft wa re Tr i g g e r e d One -shot .
CW=18 LSB=3
WR
CLK
s « l l
OUT
I N I N N I N O
3
1
0
2 I 01 I
1
O
0 I FFFIF I I FD
FF I
I I I FE
IFF
✓ Allows the counter to produce a single pulse at the output.
✓ If count of N is loaded, then OUT will be high for N clock cycles and low
for one clock cycle at the end.
✓ The cycle does not begin until the counter is loaded again.
Mode 4: Software Triggered One-shot. (Continued)
✓ G input must be maintained at logic 1 throughout the operation.

✓ This mode operates as a software triggered one-shot .
N.B. The G input must be a logic 1 for the counter to operate for these three
modes (Mode 2, 3, 4)
CW= 18 LSB =3 CW = 1 8 LSB = 3 LSB = 2
WR
CLK
r r l
OUT I I I I
I I I I
I1
y y y y
III11:1311I% 15L III131:1I:11:

Freeze

< At the first falling edge of clock after first rising edge of WR(LSB),
counter
starts counting. d'
Lecture materials on "Programmable interval timer , 8254" By- Mohammed Abdul Kader, Lecturer, EEE, IUC
Mode 5: Hardware Triggered Mode.
CW = 1A LSB = 3
WR
CLK
GATE
••••• •••• ••••••
OUT
✓ A hardware triggered one-shot that function as mode 4, except that it

is started by a trigger pulse on the G pin instead of by software.
✓ When the GATE pulse is triggered from low to high the cou n t
begin s.
At the end of the count OUT goes low for one clock period.
✓ This mode is also called HARDWARE TRIGGERED STROBE
(RETRIGG ERABLE)
Mode 5: Hardware Tri gge re d M ode .
CW= 1A LSB = LSB = 5

CW = 1A LSB = 3
3
WR
WR
CLK
CLK
GATE
----------- GATE
OUT
· OUT
I I I 1 I I I 3 1 $111: 15I I I I I I $ 1 ; 1 { 1%1i1?1
✓ At the first falling edge of clock after first rising edge of GATE , counter
starts counting.
Lecture materials on "Programmable interval timer, 8254" By- Mohammed Abdul Kader, Lecturer, E E E , IU C
Problem 1
(a) Identify the port address of the control register and counter 2 in figure.
(b) W rite a subroutine to initialize cou n t er 2 in mode 0 w ith a cou n t of
50,000. The subroutine should also include reading cou n t s on the fly; when
cou n t zero, it should return to the main program.
reaches
(c) Write a main program to display seconds by calling the subroutine as many
times as necessary.
+5V
--
24 12
1 D7 Vcc GND' C L K 2 18 2 MHz
Clock
Data
Bus l
8
D0
GATE 2
16
17
+5V
OUT2
15
CLK 1
cs GATE 1 14
8254
13
OUT 1
Al Al
9
A0 A0
CLK 0
1
RD RD GATE 0 1
10
WR W OUT 0
R
Lecture materials on "Programmable interval timer , 8254" By- Mohammed Abdul Kader, Lecturer, EEE, IUC
Probl e m 1 (Continued)
Solution (a):
A15 A14 A13 A12 Al l ............A5 A4 A3 A2 Al AO Address
1 0 0 0 ..................... 0 0 0 0 0 8000H Counter 0
1 0 0 0 ...................... 0 0 0 0 1 8001H Counter 1
1 0 0 0 ...................... 0 0 0 1 0 8002H Counter 2
1 0 0 0 ...................... 0 0 0 1 1 8003H Control
Register
Address of counter 2 = 8002H

Address of control register = 8003H
Solution (b):
We have to initialize counter 2 in ModeO.
Count=(50,000)10 = C350H
Control Word to initialize counter 2 in modeO and to load 16-bit count:
1 0 1 1 0 0 0 0 BOH
Counter 2 Load 16 bit count ModeO Count in binary Control Word
To read count 2 on the fly counter latch command is:
D
1 I0 0 I 0 0 I 0 I 0 I 0 80H
Counter 2 Counter latch command Don't care Counter latch
command
(
Probl e m 1 (Continued)
Solution (b)
Subroutine:
COUNTER PROC NEAR
CNT2 EQU 8002H
CNTR EQU 8003H
MOV AL, B0H
OU T CN TR,A L
MOV AL, 50H
OU T CN TR2, AL
MOV AL, C3H
OUT CN TR2, AL
READ: MOV AL, 80H
OUT CNTR, A L
IN AL, CN T2
MOV DL, A L
IN AL,
CNT2
OR AL, DL
JNZ READ
RET
COUNTER ENDP
Problem 1 (Continued)
Solution (c)
Clock frequency, f, = 2 MHz
Time period of each clock cycle,
1
t. = = 5 x 1 0 ' s ec
c 2 x 106
Every time subroutine is called then, 50000 x 5 x 1 0 = 25 ms is counted.
To count 1 sec subroutine needed to be called, (_") = 40 times = 28H times
25ms
Main Program:
Assuming segment registers are already initialized.
MOV BL, OOH
SECOND: MOV CL, 28H
WAIT: CALL COUNTER
DEC CL
JNZ WAIT
MOV AL, BL
ADD AL, 01
DAA
OUT 25H, AL; assuming 8 bit port 25H
MOV BL, AL
JM P SECON
HLT D
Problem 2
Write instructions to generate a pulse in
every 50 us later from counter 0.
Consider the figure of problem 1.
Solution
To generate a pulse in every 50 us later, we should initialize counter0 in
mode 2. Gate0 should be high.
Count:
Clock frequency, f, = 2 MHz
p u l se t i me
Needed count, N = . = 100 = 64H
cl o ck p e ri o d
Control Word
0 I 0 0 I 1 0 I 1 I 0 0 14H
Counter 0 Load least significant byte Mode2 Coun Control
only t in Word
binar
Instructions: y
CNT0 EQU 8000H OUT CNTR, AL

CNTR EQU 8003H MOV AL, 64H
MOV AL, 14H OU T CNT0, AL
Problem 3
W rite instructions to generate a 1
KHz square wave from Cou n t er l .
Assum e th e gate of cou n t er l is tied t o
+5V th r ou gh a l 0K resist or . Explain
the significa n ce
ofTo generate the
connecting a square
gate towave
+5V. from
(use cou it should1)be initialize in Mode 3.
n t erofl ,problem
figure
Needed count= 2000 = 07DOH
Solution
Control Word:
0 1 1 1 0 1 1 0 76H
Control
Counter 1 Load both byte Mode3 Count in binary Word
Instructions:
CNTl EQU 8001H
CNTR EQU 8003H
MOV AL, 76H Gate should be maintained at logic 1 always
OUT CNTR,AL (GATE =1 enables counting; GATE =O disables
MO AL, DOH counting.
V CNTl, AL
OUT AL, 07H
MO CNTl, AL
V
Problem 4
Write a subroutine to generate an interrupt
every 1sec. Consider the figure of
problem 1.
Solution
To obtain a pulse every 1 sec, the count should be 2 2°, which is too large for
one 16-bit counter. We can divide this counter as follows:
Counter 1 [gate pulse=2 MHz]--- Mode 2 ----- Count 50,000 (C350H)
Counter 2 [gate pulse=outl (output of counter 1)]---- Mode 2 ---- Count 40 (28H)
So, finally we get 50,000 x 40 = 2 x 10° count and from OUT2 we get the
desired output.
Control word:
Counter 1= 0111 010 0 = 74H
Counter 2= 10 01 010 0=94H
OUT CNTR, AL
Subroutine:
MOV AL, 50H
INTRP PROC NEAR
OUT CNTl, AL
CN TI E U 8001 H
MOV AL, C3H
CN T2 EQU 8002H
OUT CNTl, AL
CNTR EQU 8003H
MOV AL, 28H
MOV AL, 74H
OUT CNT2, AL
OUT CNTR, AL
RET
MOV AL, 94H INTRP ENDP
Problem 5:
Write the instruction to generate a 100 KHz square-wave at OUT0 and a 200
KHz continuous pulse at OUTl of 8254. Consider a clock of 8 MHz at clk0 and
clk1. Again address pins A« and A, of 8254 are directly connected to A% and A, of
8086 and A,, of 8086 is connected to CS of 8254 through an inverter.
Solution
To generate 100 KHz square wave at OUT0,
No. of count: xx100 KHz=8MHz; >x=80=50H
Control Word:
0 0 0 1 0 1 1 0 16H
I I I I Control
Counter 0 Load lest significant Mode3 Count in binary
Word
byte
To generate 200 KHz continuous pulse at OUTl,

No. of count, xx 200 KHz = 8MHz; > x = 40 = 28H
Control Word:
0 I 1 0 I 1 0 I 1 I 0 0 54H
Counter 1 Load list significant byte Mode3 Count in
Word
0
binary control
Problem 5 (Continued)
Address:
As address pins Aa and A, of 8254 are directly connected to A%and of 8086
and A,, of 8086 is connected to CS of 8254 through an inverter. So,
A,
Address of Counter 0 = 8000H
Addr ess of Counter 1= 8001H
Addr ess of counter 2=8002H
Addr ess of Control Register = 8003H
Subroutine:
CNT0 EQU 8000 H
CNT1 EQU 8001H
CNTR EQU 8003H
MOV AL, 16H
OUT CN TR,
AL MOV AL,
50H OUT
CN T0, AL MOV
AL, 54H OUT
CN TR, AL
MOV AL, 28H
OUT CN T l , AL

Segment: Timer Programmable Interval

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Segment: Timer Programmable Interval

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S e gme nt 7

PROGRAMMABLE INTERVAL TIMER 8254

Speci al Command Status read-back No such command

Some of the other counter/timer functions common to microcomputers

✓ It includes three 16-bit counters that can work independently in 6

Vee: Power connects to the +5V power supply.

GND: Ground connects to the system ground bus.

OUT: A counter output is where the waveform generated by the counter is

OUT0 Output of counter 0

\ ADDRESS BUS (16) ~

) DATA BUS (8) \

8254 Read Operations

There are three possible methods for reading the counters:

OUT DX,AL SC1 SCO Counter

Fig: Counter Latching Command

output latches (OL) by setting the []ilcouvr[srrus[cwr 2[cvr

; R eading the status for count 0

Mode 0: Interrupt on terminal count.

Mode 1: Hardware Retriggerable One-Shot.

Mode 2: Rate Generator.

Mode 3: Square Wave Mode.

Mode 4: Software Triggered Mode.

Mode 5: Hardware Triggered Mode.

✓ GATE =1 enables counting; GATE = 0 disables counting.

✓ GATE has no effect on OUT. If G becomes a logic O in the middle of the

✓ If a new count is written to the Counter, it will be loaded on the next

CW= 10 LSB=3 C W=10 LSB=3 LSB =2

✓ Causes the counter to function as a retriggerable, monostable

✓ At the rising edge of WR(CW) OUT becomes high.

✓ The separation between pulses is determined by the count.

✓ In mode 2, a COUNT of 1 is illegal.

O'UT .. - - . . . . .- - ......- ::- - - ..........

✓ At the rising edge of WR(CW) OUT becomes high.

✓ Generates a continuous square wave at the out connection.

✓ Mode 3 is similar to Mode 2 except for the duty cycle of OUT.

✓ For example, if the count is programmed for a count of 5 , the output is

✓ Gate should be maintained at logic 1 always (GATE =1 enables counting;

CW= 16 LSB CW= 16 LSB =

✓ Allows the counter to produce a single pulse at the output.

✓ G input must be maintained at logic 1 throughout the operation.

III11:1311I% 15L III131:1I:11:

✓ At the rising edge of WR(CW) OUT becomes high.

✓ A hardware triggered one-shot that function as mode 4, except that it

CW= 1A LSB = LSB = 5

I I I 1 I I I 3 1 $111: 15I I I I I I $ 1 ; 1 { 1%1i1?1

✓ At the rising edge of WR(CW) OUT becomes high.

Address of counter 2 = 8002H

Counter 2 Load 16 bit count ModeO Count in binary Control Word

To read count 2 on the fly counter latch command is:

CNT0 EQU 8000H OUT CNTR, AL

To generate 200 KHz continuous pulse at OUTl,

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