(Chapter -2)

Microprocessor Based
Systems
Chapter 2

Software Architecture of the

8088 and 8086 Microprocessors
 Topics to Cover:
 Microarchitecture of the 8088/8086 Microprocessor
 Software Model of the 8088/8086 Microprocessor
 Memory Address Space and Data Organization
 Data Types
 Segment Registers and Memory Segmentation
 Dedicated, Reserved, and General-Use Memory
 Instruction Pointer
 Data Registers
 Pointer and Index Registers
 Status Register
 Generating a Memory Address
 The Stack
 Input/Output Address Space
 Memory Addressing in
8086/8088

 What is memory?
 How a memory is addressed?
 4 BYTE memory?
 8 Byte memory?
 Address bits concern
MEMORY ADDRESS SPACE
& DATA ORGANIZATION
 8088 microcomputer supports 1Mbyte
of external memory.
 Address Range over 00000H to
FFFFFH.
 20 bit address. Why?
Physical Address
v/s not as
 Data organized as 8-bit bytes,
Logical
16-bit words but can Address?
be fetched as
16-bit word or 8-bit byte.
MEMORY ADDRESS SPACE
& DATA ORGANIZATION
MEMORY ADDRESS SPACE
& DATA ORGANIZATION
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 lower-addressed byte is the least
significant byte of the word, and the
higher-addressed byte is its most
significant byte
 MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Which word is stored in memory
beginning at address 00724H?
 Remember, Lower address lower
byte, Higher address higher byte.

Two bytes represent

the word
0101010100000010
B or 5502H
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Even-address boundary
 least significant address bit 0
 Odd-address boundary
 least significant address bit 1
 Aligned Word
 To permit efficient use of memory, words of
data can be stored at what are called even- or
odd-addressed word boundaries
 least significant address bit 0→ Aligned Word
 least significant address bit 1→ Misaligned Word
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Aligned Word
 To permit efficient use of memory, words
of data can be stored at what are called
even- or odd-addressed word boundaries
 least significant byte located at an even
address
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Aligned Word V/S Misaligned word

A word of data stored at an even-address

boundary, such as 00000H, 00002H,
00004H, and so on, is said to be an
aligned word
a word of data stored at an odd address
boundary, such as 00001H, 00003H, or
00005H and so on, is called a misaligned
word
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Aligned Word V/S Misaligned word
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Aligned Word V/S Misaligned word
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Double Word
 Equals to two 16-bit words or four 8-bit
bytes or 32-bits
 An example: Pointer
 What is pointer?
 A pointer is a two-word address element
that is used to access data or code in
memory
 Saves reference to another memory location
MEMORY ADDRESS SPACE &
DATA ORGANIZATION
 Pointer:
 segment base address
 Offset address

 a double word of data can be aligned or

misaligned. An aligned double word is
located at an address that is a multiple
of 4 (e.g., 0000H, 00004H, and 00008H)
MEMORY ADDRESS SPACE &
DATA ORGANIZATION

 Lower word lower address, higher

word higher address
 Dword: A000 55FFH
 Starting address: 00008H
MICROARCHITECTURE OF THE
8088/8086 MICROPROCESSOR
MICROARCHITECTURE OF THE
8088/8086 MICROPROCESSOR

8088/8086 Address/Data bus Memory

(Address/data lines) 1MB
MICROARCHITECTURE OF THE
8088/8086 MICROPROCESSOR
 Software Model of
8088/8086 µP
In order to program µP, one have
to consider the processor view
as shown in fig:
 Remember our aim is to understand
the microprocessor operation from
a software point of view.
 For this, one does not need to know
all of its hardware architectural
features i.e. the functions,
interconnection and operation of the
internal circuits of microprocessors
may not need to consider at this
stage.
 Software Model of
8088/8086 µP
Important to the Programmer:
 Registers: Various Registers within
the Device. Their Purpose,
Functions, Operating capabilities
and Limitations.
 Memory & I/O: Furthermore, it is
essential that the programmer know
how External Memory and
Input/Output Peripherals are
organized.
 Software Model of
8088/8086 µP
Important to the Programmer:

 Combination of Registers &

Memory + I/O:
How information is arranged in
registers, memory and input/output.
And how memory and I/O are
addressed to obtain instructions and
data.
 Software Model of
8088/8086 µP
 Internally, it contains Registers. All
the abbreviations in the figure are
actually the name of registers.
 Each Register is of 16-bit as
8086/8088 is of 16-bit.
 No of Registers: 13 + SR = 14

Registers names are:

Memory and I/O Space
Memory and I/O Space
Input/Output Address Space:
Software Model of 8088/8086
with Memory & I/O
 Registers: Segment Registers &
Memory Segmentation
 Memory Segmentation:
 Although 8086/8088 µP can access
up to 1MByte of Memory. Not all
this memory is active at a time
due to lack of resources.
 Actually, 1 MByte of memory is
partitioned into 64K Segments.
Why??
 For the time being, remember
each register is of 16-bit, so one
can get maximum value of 2^16=
65536 = 64K.
 Only four of these 64K segments
are active at a time.
 Registers: Segment Registers &
Memory Segmentation
 Memory Segmentation:
 Partitioned into 64K Segments.
 Only 4 Segments out of all
64K Segments will be active.

 Why?? Answer is:

 Segment Registers:
 Four Segment Register:
CS, DS, SS, ES
Segment Registers and
Memory Segmentation

 Code
Data Segment:
Stack
Extra Segment:
Segment:
Segment:
Stores
Stores
Also forInstructions
Program
Temporary
Data Data.
i.e. Codes
Storage.
Information
like Push, Pop, Jump, Call etc.  Actually, data
code
stores in the
memory.
 Data
Code Segment
Segment
Register contains
the Base
Address i.e.
Starting Address
on which the
instructions
data started to
started to enter.
enter.
Registers: Segment Registers &
Memory Segmentation
Generating a Physical memory
Address
Generating a Physical
Memory Address

 Code Segment: Instruction Pointer

 Data Segment: Source/Destination
Index
 Stack Segment: Stack/Base Pointer
 Extra Segment: Like Data Segment
Generating a Physical memory
Address
Generating a Physical memory
Address
Generating a Physical memory
Address
Generating a Physical memory
Address
Generating a Physical memory
Address
• Many different
logical
addresses map
to the same
physical
address
location in
memory.
 Code Segment : Instruction
Pointer

Code Segment : Instruction Pointer

16 Bit Address in
Segment
Registers

20 Bit
Address Bus
Code Segment : Instruction
Pointer

Code Segment
Offset : Instruction Pointer
Address
Physical
Address

Base Address 20 Bit

Address Bus
 Code Segment : Instruction
Pointer
CS: IP = 0000:0001

0001

0000

Base Address: 0000

Offset Address: 0001 B.Add: 0000(0)
Off. Add:+ 0001
Phy. Add:= 00001
 Code Segment : Instruction
Pointer

Code Segment : Instruction Pointer

0003

0000

Base Address: 0000

Offset Address: 0003 B.Add: 0000(0)
Off. Add:+ 0003
Phy. Add:= 00003
 Code Segment : Instruction
Pointer
CS:IP = 0000:FFFF

FFFF

0000

Base Address: 0000

Offset Address: FFFF B.Add: 0000(0)
Off. Add:+ FFFF
Phy. Add:= 0FFFF
Data Types
 Done with:
 byte (8 bits), word (16 bits), and double word (32 bits)
 Next: Integer
 unsigned or signed integer numbers
 can be either byte-wide or word-wide
 represent decimal numbers in the range 0 through 255 (byte-
wide)
 o represent decimal numbers in the range 0 through 65,535
(word-wide)
Data Types
Data Types

 Signed Integer
 Byte-wide integer represent decimal
numbers in the range -128 to +127 .
 Byte-wide integer represent decimal
numbers in the range +32,767 to -32,768
Data Types

Represent -1 & -2 in signed

byte?
 Data Types
The 8088 can also process
data that is coded as binary-
coded decimal (BCD)
numbers
• Packed BCD vs unpacked BCD
Data Types
DEDICATED, RESERVED,
AND GENERAL-USE MEMORY

 Out of 1MB memory, some address

locations have dedicated functions and
should NOT be used as general
memory
 DEDICATED, RESERVED,
AND GENERAL-USE MEMORY
• another reserved pointer area,
located from address FFFFCH through
An interrupt service
FFFFFH
• reserved for use with future products
routine (ISR) is a software
and should not be used
routine
• FFFF0H thatFFFFBH
through hardwareas dedicated
invokes in such
for functions response to of
as storage anthe
Open for user hardware reset jump instruction
interrupt.
• FFFF0H is where the 8088/8086
begins execution after receiving a
reset
• 00H – 7FH = 128 bytes

}
• used for storage of pointers to
interrupt service routines
• Pointers require 4 bytes of
memory as pointer is two-word
address
• How many pointers can be
saved?
 INSTRUCTION POINTER

• 16 bits in length Answer:

• identifies the because IP and CS
location of the next are both 16 bits in
length, but a 20-bit
word of instruction address is needed
• contains the offset to access memory
of the next word of the offset in IP is
instruction combined with the
• Why need offset? current value in CS
to generate the
Denoted as CS:IP, Logical addressing address of the
INSTRUCTION POINTER

• The 8088 updates the value in IP

such that it points to the first byte
of the next sequential word of code
—IP can be incremented by 1, 2, or
3.

• 8088 prefetches up to four bytes of

instruction code & stores in
instruction queue, holds there until
execution
INSTRUCTION POINTER

• Instruction cycle
• Read instruction from queue
• Decode it
• (Read operands from internal
registers or memory (data
segment) if required)
• Perform operation
• Result written back to memory or
internal register
INSTRUCTION POINTER

Any 64Kbyte segment of memory can

be used to store the instruction code
Change the value in CS and the new
Code Segment in memory is
activated.
DATA REGISTERS

8088 has four general-purpose data

registers
DATA REGISTERS

some of the data registers may also

store address information such as a
base address or an input/output
address.

Example:
BX could hold a 16-bit base address
e.g. in XLAT command.
POINTER AND INDEX
REGISTERS

Apart from AX, BX, CX, DX

8088 has four other general-purpose
registers:
two pointer registers and two
index registers
POINTER AND INDEX
REGISTERS

• Used to store what are called offset

addresses
• Offset: displacement of a storage
location in memory from the
segment base address
• used as a pointer or index to select
a specific storage location within a
64Kbyte segment of memory
POINTER AND INDEX
REGISTERS

• index registers → data segment or

extra segment
• pointer registers → stack segment
• only accessed as words (unlike to
data registers)
• SS:SP → TOS (top of stack)
• SS:BP → to access data within the
stack segment (addressing mode,
will be studied late)
POINTER AND INDEX
REGISTERS
• index registers combines with DS
or ES automatically.
• Indexed Addressing
• source index (SI) register holds
an offset address of Source
operand
• destination index (DI) register
holds an offset address of
Destination operand
POINTER AND INDEX
REGISTERS

• an operand that is to be
processed may be located in
memory instead of the internal
register
• In this case, an index address is
used to identify the location of
the operand in memory
• The index registers can also be
source or destination registers
• MOV SI, 0005H;
STATUS REGISTER(Flag
Register)
STATUS REGISTER(Flag
Register)
• Also 16 bit long; however only 9
bit are used.
• 6 bits for status flags
• carry flag (CF)
• parity flag (PF)
• auxiliary carry flag (AF)
• zero flag (ZF)
• sign flag (SF)
• overflow flag (OF)
STATUS REGISTER(Flag
Register)
• Also 16 bit long; however only 9
bit are used.
• 3 bits for control flags
• direction flag (DF)
• interrupt enable flag (IF)
• trap flag (TF)
STATUS REGISTER(Flag
Register)
STATUS REGISTER(Flag
Register)
STATUS REGISTER(Flag
Register)
• The carry flag (CF): CF is set if there is a carry-
out or a borrow-in for the most significant bit of
the result during the execution of an instruction.
Otherwise, CF is reset.

• The parity flag (PF): PF is set if the result

produced by the instruction has even parity—that
is, if it contains an even number of bits at the 1
logic level. If parity is odd, PF is reset.
STATUS REGISTER(Flag
Register)
• The auxiliary carry flag (AF): AF is set if there is
a carry-out from the low nibble into the high nibble
or a borrow-in from the high nibble into the low
nibble of the lower byte in a 16-bit word.
Otherwise, AF is reset.

• The zero flag (ZF): ZF is set if the result

produced by an instruction is zero. Otherwise, ZF is
reset.
STATUS REGISTER(Flag
Register)
• The sign flag (SF): The MSB of the result
is copiedFlag
Overflow into(O)
SF.–Thus, SF is
This flag set
will beifset
the(1) if
the result
result ofnegative
is a a signed number
operationorisreset
too large to
if it is
fitpositive.
in the number of bits available to represent
it, otherwise reset (0). After any operation, if
The generates
• D[6] overflowany flagcarry
(OF): When OF is
and passes to D[7]
set,
it indicates
OR thatnot
if D[6] does the signed result
generates carry is out
but of
D[7]
range. If the
generates, result flag
overflow is not out of set,
becomes range,
i.e.,OF1.
remains
If D[6] and reset.
D[7] both generate carry or both
do not generate any carry, then overflow flag
becomes reset, i.e., 0.
 STATUS REGISTER(Flag
Register)
• The overflow flag (OF): When OF is set, it
indicates that the signed result is out of
range. If the result is not out of range, OF
remains reset.
• MOV AL, 50H (50 is 01010000 which is
positive)
• MOV BL, 32H (32 is 00110010 which is
positive)
• ADD AL, BL (82 is 10000010 which is
negative)
• Overflow flag became set as we added 2 +ve
numbers and we got a -ve number.
STATUS REGISTER(Flag
Register)
• The trap flag (TF): If TF is set, the
8088 goes into the single-step
mode of operation. When in the
single-step mode, it executes an
instruction and then jumps to a
special service routine that may
determine the effect of executing the
instruction. This type of operation is
very useful for debugging programs.
STATUS REGISTER(Flag
Register)
• The interrupt flag (IF): For the
8088 to recognize maskable interrupt
requests at its interrupt (INT) input,
the IF flag must be set. When IF is
reset, requests at INT are ignored and
the maskable interrupt interface is
disabled.
STATUS REGISTER(Flag
Register)
• The direction flag (DF): The logic
level of DF determines the direction in
which string operations will occur
THE STACK
• used for temporary storage of
information
• Data or addresses
• When Call instruction is executed
• automatically pushes CS, IP
values
THE STACK
• push instructions
• PUSH SI
• contents of SI stored on stack
• POP SI
• value at the top of the stack to be
popped back into SI
THE STACK
At the end of the subroutine, a return
instruction causes the values of CS and
IP to be popped off the stack and put
back into the internal register where
they originally resided
THE STACK
• stack is 64Kbytes long
• SS register points to the lowest
address word
• SP and BP register offset into the
stack segment of memory
• Stack is filled opposite to normal
memory
 THE STACK
SS:SP
Points to
Top of the
Stack
(ToS)

At the microcomputer’s
startup, the value in SP
is initialized to FFFEH
THE STACK
THE STACK
• Data transferred to and from the
stack are word-wide, not byte-wide

PUSH operation:
Each time a word is to be pushed
• SP is first automatically
decremented by two
• Then contents are written on stack
THE STACK
• Therefore, the stack grows down in
memory from the bottom of the stack,
which corresponds to the physical
address SS:FFFEH, toward the end of
the stack, which corresponds to the
physical address obtained from SS
and offset 0000H (SS:0000H).
THE STACK
• POP Operation
When a value is popped, the reverse
of this sequence occurs
•SS and SP points to the location of the
last value pushed
• contents are first popped off
• SP is automatically incremented by
two
• top of the stack then corresponds to
the address of the previous value
pushed onto the stack
THE STACK(PUSH Operation)

how the contents of a register

are pushed onto the
Stack?
THE STACK(PUSH Operation)
 THE STACK(POP Operation)
• What happens when POP
AX and POP BX are
executed?

1. read the value from the

top of the stack Why these
2. put it into the AX values are still
register as 1234H there?
3. Next, SP is incremented
to give 0008H

4. POP BX instruction,
loads value BBAAH into
the BX register
5. SP is incremented once
more & equals to s
000AH
 THE STACK(POP Operation)
ANSWER:
Values read out of
addresses 1056H and
1058H remain at these
locations, but now reside
at locations that are above
the top of the stack;
therefore, they no longer
represent valid stack data.
If new information is
pushed to the stack, these
values are written over
 THE STACK(POP Operation)
Any number of stacks
may exist in an 8088
microcomputer. Simply
changing the value in
the SS register brings
in a new stack. For
instance, executing the
instruction MOV SS, DX
loads a new value from
DX into SS. Although
many stacks can exist,
only one can be active
at a time.
 INPUT/OUTPUT ADDRESS
SPACE
• 8088 has separate memory and input/output (I/O)
address spaces
• I/O address space is the place where I/O interfaces, such as
printer and monitor ports, are implemented+
• range is from 0000H to FFFFH (64Kbyte)
• therefore, unlike memory, I/O addresses are only 16 bits long
• Each of these addresses corresponds to one byte-wide I/O port
• Page 0: Certain of the 8088’s I/O instructions can perform
only input or output data-transfer operations to I/O devices
located in this part of the I/O address space
• Other I/O instructions can input or output data for devices
located anywhere in the I/O address space.
• I/O data transfers can be byte-wide or word-wide
• eight locations reserved by Intel Corporation and should not be
used (00F8H through 00FFH)