EE 401 -VLSI DESIGN

WEEK-04

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 THE CMOS PROCESS FLOW

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 Initial sequences in CMOS fabrication

P+ wafer with thin p-type

epitaxial layer of silicon
grown on top

The formation of n-well

regions using masking step
to define location of pFETS

Nitride Pattern is used to

achieve electrical isolation

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 Initial sequences in CMOS fabrication

Etching of Silicon

Oxide is grown or deposited

in the etched region
FOX: Glass insulation between
active areas defines the field
regions and the oxide is called
field oxide

Ready for transistor

fabrication process

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 THE SELF ALIGNED GATE
PROCESS

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 THE SELF ALLIGNED GATE PROCESS
INVOLVES THE PLACEMENT OF THE GATE
POLY FIRST ONTO THE WAFER TO CREATE A
POLY MASK FOR DOPING OF THE HEAVILY
DOPED P TYPE OR N TYPE REGIONS. THUS A
NEW MASK IS SAVED EVENTUALLY SAVING
FIVE OR SIX FABRICATION STEPS SINCE POLY
GATE ITSELF ACTS AS A MASK FOR DOPING.

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 Formation of nFETs and pFETS

The poly silicon layer is deposited and patterned to form transistors gate

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 Formation of nFETs and pFETs

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 First metal interconnect layer

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 First metal interconnect layer

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 First metal interconnect layer

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 Bonding Pad Structure

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 Common Variations from the Standard
Processing Steps

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 Lightly Doped Drain (LDD)
Structures

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 THE DAMASCENE
PROCESS

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 INTRODUCTION TO THE
DESIGN RULES

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