Lecture 4-2 Timing

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 Outlines
• Timing definition
• How to read a timing report
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 SOME DEFINTIONS
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 Edge-Triggered D Flip Flop

Setup time Hold time

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Setup time: inputs become stable before rising clock;

Hold time: inputs remain stable after rising clock;

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 How Fast My Design Can Run?
• Up to 100MHz? 200MHz?
• Slower at 10KHz, 20KHz? Any speed?
Data
Cache
Mux Regs

Regs ALU
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Inst

IRW
IRM
IRR

IRA
PC

Cache

A FIFO B
10 cycles 5 or 15 cycles

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 How Fast My Design Can Run?
• Fastest clock cycle time: Tc

Tc

clk
Flip-Flops
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clk clk
Flop

Flop
Combinational Logic
2-Pha

11: Sequential Circuits 6

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 Max Delay
clk clk Tc >= tpcq + tpd + tsetup
Q1 D2
Combinational Logic
F1

F2
tpd <=Tc – (tpcq + tsetup )
Tc

tsetup Register overhead

clk
tpcq
If delay of comb. Logic is too
Q1 tpd long)
Þ Setup time violation
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D2 DFF will catch the wrong value

1. clock run slower
Tc become larger
2. comb. Logic faster
Tpd smaller by
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 Platform Based Design Group

Min-Delay: Flip-Flops
clk
F1
Q1
CL
𝑡 𝑐𝑑 +𝑡 𝑐𝑐𝑞 ≥ 𝑡 h𝑜𝑙𝑑
clk
tcd  thold  tccq
D2
F2

clk

Q1 tccq tcd
If not hold,
D2 thold (comb. Logic delay is too short)
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Þ hold time violation

Þ DFF will catch the wrong value
1. Decreasing clock rate does not work
2. Increase tcd (e.g. add delay, buffer)
11: Sequential Circuits 8
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 Timing Paths
• Input to register, register to register, register to output
– Start from or end to DFFs
• Input to output
Input to register register to register register to output
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Input to output

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 Example

tdCQ = tcCQ = ts = 150ps

th = 250ps
tdMax = 850ps
tcMin = 100ps

Is hold time constraint met?

≤
250ps <= 100+ 150ps
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What is the minimum cycle time?

≥
tcy >= 1150ps

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 Add Clock Skew tk
Cycle get larger

Hold time tigher

Skew always reduces slack (margin)

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Clock skew: arrival time of clock signal difference

check timing path as in timing report

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 Summary
• Delays in digital systems
– Propagation delay
– Contamination delay
• Flip-flop timing constraints
– Setup time (ts)
– Hold time (th)
• Cycle time determined by maximum delay
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• Correct operation depends on minimum delay

• Clock skew affects both

(c) 2005-2012 W. J. Dally
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 HOW TO READ YOUR TIMING REPORT
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 How to Read and Interpret Timing Report
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 Platform Based Design Group

Constraint File (note. These numbers may not

match the following slides)
// 設定 clock, I/O 限制
create_clock "clk" -name clk -period 2 -waveform {0 1.7}
set_clock_uncertainty 0.2 clk
set_fix_hold all_clocks()
set_input_delay 0.5 -clock clk {in}
set_output_delay -max 0.8 -clock clk {isprime}
// 設定 loading
set_load -pin_load 5 {isprime}
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//Note: these commands are for practical applications to include

// clock jitter, input/output loading capacitances

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 Clock Network and Clock Skew
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 Specify Timing Assertions
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 Timing Verification of Synchronous Designs
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Clock skew

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 Four Sections in a Timing Report
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 Data Arrival Section
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 Data Required Section
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 Summary - Slack
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