10/30/2023

Clock Skew

 The clock doesn’t arrive at all registers at same time

 Skew: difference between two clock edges
 Perform worst case analysis to guarantee dynamic discipline
is not violated for any register – many registers in a system!

delay CLK

CLK1 CLK2
Q1 C D2
L

R1 R2

t skew

CLK1

CLK2

CLK

Clock Skew

 In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥
CLK2

Q1

D2

tpcq tpd tsetup tskew

1
 10/30/2023

Clock Skew

 In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤
Q1

D2

tpcq tpd tsetup tskew

Clock Skew

 In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤ Tc – (tpcq + tsetup + tskew)
Q1

D2

tpcq tpd tsetup tskew

2
 10/30/2023

Sequential Logic Design

Metastability

 Violating setup/hold time can lead to bad clk

situation known as metastable state
 Metastable state: Any flip-flop state other D
than stable 1 or 0
 Eventually settles to one or other, but we
setup time
don’t know which violation
 For internal circuits, we can make sure
observe setup time Q
 But what if input comes from external
metastable
(asynchronous) source, e.g., button state
press?
 Partial solution
ai
 Insert synchronizer flip-flop for
asynchronous input
 Special flip-flop with very small setup/hold
time
 Doesn’t completely prevent metastability a

ai

synchronizer

Sequential Logic Design

Metastability

 One flip-flop doesn’t completely solve problem

 How about adding more synchronizer flip-flops?
 Helps, but just decreases probability of metastability
 So how solve completely?
 Can’t! May be unsettling to new designers. But we just can’t guarantee a design that
won’t ever be metastable. We can just minimize the mean time between failure (MTBF)
-- a number often given along with a circuit

Probability of flip-flop being metastable is…

very
very very incredibly
low low low low
ai

synchronizers

3
 10/30/2023

Sequential Logic Design

Example of Reducing Metastability Probability

 Recall earlier secure car key controller

Inputs: a; Outputs: r a

Wait
r=0 a’
a
Adding synchronizer flip-flop reduces
K1 K2 K3 K4 metastability probability in state register, at
r=1 r=1 r=0 r=1 expense of 1 cycle delay
outputs

a r
Original
D a r
Combinational a
FSM

n2 flip-flop
inputs

logic Combinational
n1 n2
logic
n0 n1
n0
s2 s1 s0 s2 s1 s0

clk
State register clk
State register

Summary

 Sequential circuits
 Have state
 Created robust bit-storage device: D flip-flop
 Put several together to build register, which we used to store state
 Defined FSM model to capture sequential behavior
 Using mathematical models – Boolean equations for combinational
circuit, and FSMs for sequential circuits – is important
 Defined Capture/Convert process for sequential circuit design
 Converted FSM to standard controller architecture
 So now we know how to build the class of sequential circuits known as
controllers