BASIC CMOS

DOAN MINH TUE

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P-N Junction

 Physic of semiconductor
 Zeros bias
 Forward bias
 Reverse bias
 IV curve of the silicon p-n junction diode

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 Semiconductor
 A semiconductor is a material product usually comprised of silicon, which conducts electricity more
than an insulator, such as glass, but less than a pure conductor, such as copper or aluminum. Their
conductivity and other properties can be altered with the introduction of impurities, called doping, to
meet the specific needs of the electronic component in which it resides

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 Mobility
 In solid-state physics, the electron mobility characterises how quickly an electron can move
through a metal or semiconductor when pulled by an electric field. There is an analogous
quantity for holes, called hole mobility. The term carrier mobility refers in general to both electron
and hole mobility
 Semiconductor mobility depends on the impurity concentrations (including donor and acceptor
concentrations), defect concentration, temperature, and electron and hole concentrations. It also
depends on the electric field, particularly at high fields when velocity saturation occurs
 The mobility of electrons is faster than that of holes

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 Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

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 Doping
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

N-type P-type

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 Zero bias in P-N Junction
 In a p-n junction, without an external applied voltage, an equilibrium condition is reached in
which a potential difference forms across the junction. This potential difference is called built-in
potential

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 Forward bias in PN Junction
 In forward bias, the p-type is connected with the positive terminal and the n-type is connected
with the negative, current can flow (depending upon the magnitude of the applied voltage). This
configuration is called "Forward Biased”
 Reduce the width of the depletion region
 Diffusion current increases exponentially

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 Reverse bias in PN Junction
 Connecting the p-type region to the negative terminal of the voltage supply and the n-type region
to the positive terminal corresponds to reverse bias
 Increase the width of the depletion region
 Diffusion current is reduced exponentially

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IV curve of the silicon p-n junction diode

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CMOS basic

 Why CMOS?
 MOSFET structure
 MOSFET operation
 I/V Characteristics
 Second-Order Effects
 Fabrication process
 FINFET vs MOSFET

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Why CMOS?
 CMOS technologies rapidly captured the digital market: CMOS gates dissipated power only
during switching and required very few devices
 MOS devices could be scaled down more easily than those of other types of transistors
 The low cost of fabrication and the possibility of placing both analog and digital circuits on the
same chip so as to improve the overall performance and/or reduce the cost of packaging made
CMOS technology attractive
 Another critical advantage of MOS devices over bipolar transistors is that the former can operate
with lower supply voltages. The lower supplies have permitted a smaller power consumption for
complex integrated circuits

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MOSFET structure
 Four-terminal device: gate (G), source (S), drain (D) and bulk (B)
 The device size (channel region) is specified by width (W) and length (L)
 Two kinds of MOSFETs: n-channel (NMOS) and p-channel (PMOS)
 Source and drain terminals are specified by the operation voltage

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MOSFET operation

 Threshold Voltage
 Cut-off
 Triode Region
 Saturation region

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 Threshold Voltage
 Voltage at gate Vg required to fully invert our semiconductor
 For , electrons are attracted to the interface under gate, establishing a "channel" for conduction.
The channel is also called the “inversion layer’’
 For , depletion region under channel remains relatively constant, but the charge in inversion
layer increases

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 Cut-off region
 Cut-off: <
• MOSFET is “OFF”
• No formation of channel
• No Drain current flows ( ID = 0 )
• MOSFET operates as an “open switch”

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 Triode Region
 Triode Region: > and < –
• Formation of channel, connect the source and drain terminals
• A positive voltage between terminals D and S will create an flow through the channel
• The channel connecting terminal Drain and terminal Source is treated as a resistor

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 Saturation region
 Saturation region: > and > –
• MOSFET “ON”
• MOSFET operates as a low resistance “closed switch”
• At the point = – , the channel is pinched off at the drain side

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 I/V Characteristics
 Cut-off region: < )
=0
 Triode region: > )
–) -

 Deep triode Region: << –

–)

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 Saturation: > )

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Second-Order Effects

 Body Effect
 Channel-Length Modulation
 Subthreshold conduction

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 Body Effect
 As becomes more negative, more holes can break loose from atoms under the gate area,
leaving negative ions behind => depletion region can contribute more charge => inversion layer
forms for larger => threshold voltage increase

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 Channel-Length Modulation
 Channel length modulation is a shortening of the length of the inverted channel region with
increase in drain bias for large drain biases. The result of channel length modulation is an
increase in current with drain bias
 As increase, the width of depletion region between inversion layer and drain increase =>
effective channel length decrease => increase

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 Subthreshold Conduction
 Subthreshold conduction is the current between the source and drain of a MOSFET when the
transistor is in subthreshold region, or weak-inversion region, that is, for gate-to-source voltages
below the threshold voltage

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Fabrication process

 CMOS transistors are fabricated on silicon wafer

 Lithography process similar to printing press
 On each step, different materials are deposited or etched
 Easiest to understand by viewing both top and cross-section of wafer in a
simplified manufacturing process

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Fabrication Steps

 Step 1: First we choose a substrate as a base for

fabrication. For N- well, a P-type silicon substrate is
selected

 Step 2: Oxidation

 Step 3: Growing of Photoresist

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 Step 4:
• Expose photoresist through n-well mask
• Strip off exposed photoresist

 Step 5: Etching

 Step 6: Removal of Whole Photoresist

Layer

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 Step 7: Formation of N-well

 Step 8: Removal of SiO2

 Step 9: Deposition of Polysilicon

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 Step 10: Formation of Gate Region

 Step 11: Oxidation Process

 Step 12: Masking and Diffusion

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 Step 13: Removal of Oxide

 Step 14: P-type Diffusion

 Step 15: Laying of Thick Field oxide

 Step 16: Metallization

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FINFET vs MOSFET
• FinFET is a multi gate MOSFET. It is named as FinFET because the 3D structure above the
subtrate looks like set of fins.
• It is 3D transistor and widely used in integration circuit recently instead of planar CMOS FET.
• It is used more than other FETs because of its area of performance, lower leakage power, low
voltage operation.

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FINFET vs MOSFET?

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Single stage amplifier

• Common-source
• Common-gate
• Source-follower
• Cas-code

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Common-source
• In common-source amplifiers, the input is (somehow!) connected to G and the output is
(somehow!) taken from D

• We can divide CS amplifiers into two groups:

o Without source degeneration(no body effect for the main transistor)

o With source degeneration (with body effect for the main transistor)

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Common-Source Stage with Resistive Load
• Resistive Load is often used in high-speed circuit because of the linearity of resistance, and also
the output voltage swing may reach up to Vdd

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Large-Signal Analysis
• When < , M1 is in cut-off region, =0, =
• When >

• When
and triode region
• When , M1 is in the triode region

• If
if

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Small-Signal Model
• Assuming that the transistor is in saturation region and channel length modulation is ignored

• Output Voltage:

• Small-signal Gain:

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• Channel length modulation becomes more significant as increases
• Using the Small-Signal Model because of its simplicity

// =>
• Intrinsic gain
If ≈ ∞, then
Called the “intrinsic gain” of a transistor, this quantity represents the
maximum voltage gain that can be achieved using a single device.
For ideal long-channel device -> ∞, Intrinsic gain -> ∞.In today’s
CMOS technology, gm of short-channel devices is between
roughly 5 and 10. We usually assume 1/gm << .

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• Input impedance of common source is ∞
• Output impedance of common source is

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