ĐHBK Tp HCM - Khoa Đ-ĐT

BMĐT
Môn học: Xử lý tín hiệu số với FPGA
GVPT: Nguyễn Lý Thiên Trường
Email: truongnguyen@hcmut.edu.vn
203-B3

Chương 1
Giới thiệu
 Xử lý tín hiệu số với FPGA
 Mục tiêu môn học
 Giới thiệu tổng quan về FPGA.
 SV có thể sử dụng ngôn ngữ Verilog cho việc thiết kế mạch số trên FPGA.
 Giới thiệu một số phương pháp để thiết kế các hệ thống VLSI cho một số ứng
dụng xử lý tín hiệu số điển hình.
 SV có khả năng vận dụng một số kỹ thuật thiết kế kiến ​trúc và thuật toán cấp cao
cho phép tối ưu hóa thuật toán, kiến ​trúc mạch số.
 Đánh giá môn học
 Kiểm tra tại lớp: 30%
 Kiểm tra giữa kỳ: 20%
 Thi cuối kỳ: 50%
 Giáo trình
 Keshab K. Parhi, VLSI Digital Signal Processing Systems – Design and
Implementation, Wiely, 1999.
 Sách tham khảo
 U. Meyer-Baese , Digital Signal Processing with Field Programmable Gate Arrays
 Pong P. Chu, FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version
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Sách tham khảo

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Phần mềm

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Phần mềm

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 Topics
1. Introduction
2. Digital circuit design with Verilog
3. Iteration Bound
4. Pipelining and Parallel Processing
5. Retiming
6. Unfolding
7. Folding
8. Systolic Architecture Design
9. Algorithmic Strength Reduction in Filters and Transforms
10. Bit-Level Arithmetic Architectures

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 Nội dung

1. Giới thiệu nội dung môn học

2. Tổng quan Tự đọc thêm
trong slide bài giảng
3. Phương pháp luận thiết kế
4. FPGA (Field-Programmable Gate Array)
5. HDL

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DE10 Standard Development Kit

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Board Comparisons

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 FPGA internal structure
(or CLB)

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 FPGA internal structure
(or CLB)

in1

in2
out

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 FPGA internal structure
(or CLB)

in1

in2
out

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 FPGA internal structure

(SB)
 A state-of-the-art FPGA contains thousands of configurable logic blocks (CLBs)
 Each CLB will have several basic logic elements (LE) consisting of a look-up table
(LUT) for implementing combinational logic and a memory element known as a flip-flop
(FF)
 The wires connecting the various CLBs can be programmed as well through a series of
switching boxes (SB) in the routing channels
 A high-level description language such as VHDL or Verilog is used to describe how an 13
FPGA internal structure

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 Look Up Table (LUT)
 A look up table is basically a binary truth table.
 It has a set of input bits, and the LUT mechanism maps these
to a set of output bits.

e.g. F(0102) = 12

Any guess as to what

Boolean function this
LUT is configured for?

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 Look Up Table (LUT)
 A look up table is basically a binary truth table.
 It has a set of input bits, and the LUT mechanism maps these
to a set of output bits.

e.g. F(0102) = 12

ANSWER:
It’s simply an XOR of all the
inputs

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Programmable Interconnect to CLB I/O as:
LUT or MUXes
Programming lines CLB
Programmable
interconnect

A Programmable
logic blocks

Inputs B LUT
or
C MUX

... CLB
A
B LUT Hopefully you can now
or
C MUX easily see how the
D programming is going
to happen…

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Programmable Interconnect:
Switch Blocks

CLB
Programmable
interconnect

Programmable
logic blocks

The switch block is an efficient

particularly for implementing
the routing at junctions in
Example Switch Block configurations: between PLBs, it allows for
various configurations that the
comparatively simpler
multiplexer doesn’t provide*.
left-top , Bottom- bottom-top ,
all * Although of course multiple MUXes
right-bottom (right,left) right-left
could mimic this behaviour.

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ASIC/FPGA Design Flow

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FPGA Design Flow

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 FPGA Design Flow
Design Design and RTL Coding
Specification - Behavioral or Structural Description of Design
- Writing VHDL (or Verilog), deciding i/o, formulating tests

RTL Simulation
- Functional Simulation
- Verify Logic Model & Data Flow
- View model-specified timing
M512
LE Synthesis
- Translate Design into Device Specific Primitives
M4K I/O - Optimization to Meet Required Area & Performance Constraints

Place and Route (PAR)

- Map primitives to specific locations inside
FPGA with reference to area & performance
constraints
- Specify routing resources to use

……

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 FPGA Design Flow
Place and
Route (PAR)

tclk
Timing Analysis
- Verify performance specifications
- Static timing analysis

Gate Level Simulation

- Timing simulation
- Verify design will work on target platform

Program and test on hardware

- Generate bit file
- Program target device
- Activate the system
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FPGA Design Flow - HDL description

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 FPGA Design Flow – Logic Synthesis

(Register Transfer Level (RTL) view)

https://www.semiconvn.com/home/hoc-thiet-ke-vi-mach/bai-hc-vi-mch/8192-quy-trinh-thiet-ke-fpga-tong-quat.html 28
FPGA Design Flow - Mapping

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FPGA Design Flow - Place & Route

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

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FPGA Design Flow - Placement

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FPGA Design Flow - Routing

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FPGA Design Flow - Configuration

PGA
F

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FPGA Design Flow:
Where is most time spent?
Every development project is different. In my own experience,
most of the time is probably spent…
!
Eish Design and RTL Coding
- Behavioral or Structural Description of Design
- Writing HDL, deciding i/o, formulating tests
tclk Timing Analysis
Engineer’s - Verify performance specifications
time - Static timing analysis

Eish!
Place and Route (PAR)
- Map primitives inside FPGA
- Specify routing resources to use

PC’s time

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 Performance Metrics of a Digital Chip
 Cost
 NRE (fixed) costs - design effort
 RE (variable) costs - cost of parts, assembly, test
 Speed
 Delay (ns)
 Power Dissipation
 Energy to Perform a Function

 Energy per bit (nJ/b)

 Reliability
 Noise immunity Noise margin
 Scalability Larger Designs
 Time-to-Market
Non-recurring engineering (NRE) = Kỹ thuật không định kỳ (NRE) đề cập đến chi phí một lần
để nghiên cứu, thiết kế, phát triển và thử nghiệm một sản phẩm mới hoặc cải tiến sản phẩm. 35