Semiconductor memory

1
 Content
• static RAM
• dynamic RAM
• ROM / PROM / EPROM

Semiconductor Memory 2
 SRAM block diagram

Address
address Memory cells
decoder

R/W
Control
OE input buffer output buffer
logic
CS

data I/O
Semiconductor Memory 3
 RAM
• DRAM: Dynamic RAM:
– data is stored on a capacitor for one bit
– read/write data through an access transistor (or pass transistor)
– charge on capacitor is decreased (through semiconductor
junctions)  data can be lost  requires a "refresh" circuit every
few milliseconds
• SRAM: Static RAM:
– Also allows reading and writing information
– No need for periodic refresh circuit like DRAM

Semiconductor Memory 4
 SRAM

VDD
M1 M2

L1 L2
A B

P1

P2
Q1 Q2
VDD

VDD
RAS
P3 P4 Q5 Q6
DOUT DOUT
DOUT DOUT
DIN CAS DIN
DIN DIN Q4 Q7

R\W R\W
R\W R\W Q3

Read/Write Amplifier Semiconductor Memory Read/Write Amplifier 5

• RAS: Row Address Select
– Active high to select row
• CAS: Column Address Select
– Active high to select col
• P1, P2, P3, P4: pass transistor (access
transistor)
• M1, M2: active-load

Semiconductor Memory 6
 Read SRAM
• Cell stores the value 1 :
– Q1 OFF: A = HIGH
– Q2 ON: B = LOW
• Read cell:
– R\W = 0: Q3 ON
– RAS = 1: P1 and P2 ON
– CAS = 1: P3 and P4 ON
– Gate pole of Q7 is connected to GND via P4, P2 and Q2: Q7 will
be turn-off  DOUT = HIGH

• Similarly

Semiconductor Memory 7
 Write SRAM
• Cell stores the value 1 :
– Q1 OFF: A = HIGH
– Q2 ON: B = LOW
• Write 0 to cell:
– R\W = 1: Q3 ON
– RAS = 1: P1 and P2 ON
– CAS = 1: P3 and P4 ON
– DIN = 0: Q4 OFF, however Q4’ (of the left read/write amplifier)
will be ON (use inversion of DIN)  voltage of A is reduced 
Q2 turns from ON to OFF  Q1 turns from OFF to ON
– Q1 ON, Q2 OFF  cell stores the value 0

Semiconductor Memory 8
CY6264
SRAM 8K x 8

Semiconductor Memory 9
Reading cycle

Semiconductor Memory 10
Semiconductor Memory 11
Writing cycle

Semiconductor Memory 12
Semiconductor Memory 13
 DRAM
• DRAM: appeared in the 1970s
• Advantages:
– Higher density than SRAM
– Low power consumption
• Disadvantage:
– Slower access speed
– Need refresh circuit

Semiconductor Memory 14
 DRAM cell
bit line

word line

CL CS
M

CL CS

Normally, CL is several dozen times bigger than CS( CS ~ 40fF, CL ~ 300fF)

Voltage of CL charge = 5V:
If CS is charged by 4.5V (value “1”)  the balancing voltage is ~ 4.9V
If CS is charged by 0V (value “0”) the balancing voltage is ~ 4.5V

Semiconductor Memory 15
 DT Dummy row
DT
CD1
C1 MD1
CL P
Half bit line

Row0
CS

Row63
CS

P
VDD
MP1
MC1
I/O I/O
DATA
MS3
MS1

MS
CAS SI

SG
MS2
MS4
DATA
I/O I/O
MC2 MP2
VDD

P
Row64
CS

Row127
CS

DB Dummy row
DB
Half bit line CD2
MD2

CL P

Semiconductor Memory 16
 Read RAM
1. Signal P = high, then P = low
2. Row selection signal is active high and signal
dummy row is active (if selecting the upper row,
Dummy row Bottom must be active and vice
versa)
3. SI (isolation signal) and SG (signal gate) is
active high
4. Signal CAS is active

Semiconductor Memory 17
 Read DRAM
• Precharge:
– Signal P = high
– MP1 and MP2 is conductive: CL of Half bit line is charged to
VDD
– Pole D of MD1 and MD2 are 0  CD1 and CD2 charge are 0
– Signal P = low: precharge is finished
• Signal selected row is active (1 of 128 signals):
supposing row63 is selected
• if cell stores value “1”: VCS = 4.5V
• if cell stores value “0”: VCS = 0V

Semiconductor Memory 18
 Read value “1” ( VCS = 4.5V)
• CL is connected to CS , balancing voltage VBLT ~
4.9V
• Signal DB is active  VBLB ~ 4.75V (due to the
charge redistribution between CL and CD2, charge
0)
• SI and SG are active:
– MS, MS3 và MS4 are conductive
– VBLT > VBLB  MS2 conducts, MS1 doesn’t conduct  VBLT holds
the value, VBLB = 0.
• CAS is active:
– DATA = VBLT = “1”
– _DATA (inversion of DATA) = VBLB = “0”
Semiconductor Memory 19
 Read value “0”
• Redistribution of charge between V_{CL} and
V_{CS}  VBLT = 4.5V
• Redistribution of charge between V_{CD2} and
C_L  VBLB = 4.75V
• SI and SG are active:
– MS, MS3 and MS4 conduct
– VBLT < VBLB  MS1 conducts while MS2 doesn’t conduct 
VBLB hold the value, VBLT = 0.
• CAS is active:
– DATA = VBLT = “0”
– _DATA (inversion of DATA) = VBLB = “1”

Semiconductor Memory 20
 Write to DRAM
• Information to be written will be placed in DATA
and _DATA
• CAS is active  capacitor C_L is charged
• Signal Row is active, capacitor C_S is charged
via charge on C_L

Semiconductor Memory 21
 refresh
• The charge on the CS will be changed (due to the
resistors between the gate and drain)  need to refresh
the capacitors
• The "refresh" is done continuously in a certain cycle and
is done in rows
• First the CL and CD capacitors are precharged
(assuming precharge of the top rows):
– VCL = VDD
– VCD1 and VCD2 = 0
• Row signal and DB (dummy bottom) signal are active
charge redistribution of capacitors CL
• Then the SI and SG signals are active  refresh voltage
signal of CS
• CAS will be NOT ACTIVE in refresh cycle

Semiconductor Memory 22
 ROM

Address
address Memory cells
Decoder

Control
OE output buffer
logic
CS

Semiconductor Memory 23
 ROM cell
BL BL BL
VDD
WL
WL WL
1

BL BL BL

WL WL
WL
0
GND

Diode ROM MOS ROM 1 MOS ROM 2

Semiconductor Memory 24
 MOS-NOR-ROM
V DD
Pull-up devices

WL[0]

GND
WL [1]

WL [2]

GND
WL [3]

BL [0] BL [1] BL [2] BL [3]

Semiconductor Memory 25
• Information of words are retrieved at bit line (BL)
• BL will be the NOR of the WL (Word line) signals
• ROM types based on the above cell types are
called PROM (Programmable ROM)
• Disadvantage: program 1 time.
• Solution: using EPROM

Semiconductor Memory 26
 The MOS has an open gate

20 V 0V 5V

20 V 0V 5V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

Semiconductor Memory 27
Voltage threshold of MOS

“0”-state “1”-state

“ON ”

DV T

“OFF ”
V WL V GS

Semiconductor Memory 28
 EPROM
• When the memory bit is not programmed, which means that the
floating gate is not charged, the control gate acts as a normal
control terminal. If a High voltage (size > 2V) is applied to the gate
pole, a conduction will be formed between D and S .

• To program the memory element, the floating gate needs to be

charged so that to form a conduction between D and S, the voltage
applied to the control gate must be many times greater than 2V.

• Charges can be held at the floating gate for a period of several

years.

• To clear the EPROM to return the memory elements to the

unprogrammed state, electrons need to be released from the
floating gate. This is done by the impact of ultraviolet light on the
memory element (20 min size). When the electrons receive the
energy of the photons, they will leave the floating gate and return to
the base. EPROMs are therefore fabricated with a window to allow
UV irradiation to the memory elements.
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Semiconductor Memory
 Electrically Erasable PROM
(EEPROM)
• Disadvantages of EPROM:
– need to be removed from the circuit when programming
– Depending on the intensity of the ultraviolet light, the ROM
erasing time can be long (1 hour).
• EEPROM: allows erasing ROM by voltage.

Semiconductor Memory 30
 EEPROM
• floating gate and Drain are placed very close
together (< 20nm)
• when a voltage of ~20V is applied to the control
gate and D (grounded) terminals, a high electric
field will induce a current in the insulator 
floating gate is charged
• To discharge the voltage on the floating gate, a
reverse voltage is applied to D and the control
gate. The electric field will cause the electrons to
leave the floating gate.

Semiconductor Memory 31
 Flash EEPROM
• Using high voltages (20V) to erase ROM is the
disadvantage of EEPROM
• Flash Memory is a variant of EEPROM with the
control and floating terminals placed very close
together (about 10nm) this allows for discharge
by applying 12V voltages between the control
gate and the source.
– erase: VGS = -12V (S is grounded and D is open)
– program: VGS = 12V (G is grounded) and D is 7V, As
with EPROM the electrons moving in the conduction channel will
be moved by the electric field G through the oxide region and to
the floating gate terminal.

Semiconductor Memory 32
CMOS EEPROM 27C256

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