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Proof
Boolean Functions
Examples
Then
Another method
Canonical and Standard Forms
Minterms / Maxterms
Canonical and Standard Forms
f1 = x’y’z + xy’z’ + xyz = m1 + m4 + m7
Let f1’= x’y’z’ + x’yz’ + x’yz + xy’z + xyz’
then the complement of f1’ is
f1 = (x+y+z)(x+y’+z)(x+y’+z’)(x’+y+z’)(x’+y’+z)
= M0M2M3M5M6
Canonical and Standard Forms
f2 = x’yz + xy’z + xyz’ + xyz = m3 + m5 + m6 + m7
Similarly, the complement of f2’ is
f2 = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
=M0M1M2M4
Canonical and Standard Forms
Boolean functions expressed as a sum of minterms or
product of maxterms are said to be in canonical form
Canonical and Standard Forms
By Demorgan’s theorem
Conversion between Canonical Forms
mj’ = Mj
F = xy + x’z
= Σ(1, 3, 6, 7)
=Π(0, 2, 4, 5)
Standard Forms
The terms that form the function may contain one,
two or any number of literals. There are two types of
standard forms: the sums of products and products of
sums
F1 y xy xyz F x( y z )( x y z)
Standard Forms
because
Extension to Multiple Inputs
To overcome the difficulty, define the multiple NOR (or
NAND) as a complemented OR (or AND) gate
Extension to Multiple Inputs
Exclusive-OR
are commutative and associative
Multiple-input Exclusive-OR gates are uncommon from
the hardware standpoint
It is normally implemented by cascading 2-input gates
Positive and Negative Logic
Choosing the high-level H to represent logic 1 defines a
positive logic system
Choosing the low-level L to represent logic 1 defines a
negative logic system
Integrated Circuits
IC is a silicon semiconductor crystal, call chip
Levels of Integration
Small-scale integration SSI, smaller than 10 gates
Medium-scale integration MSI, 10-1000 gates
Large-scale integration LSI, thousands of gates
Very Large-scale integration VLSI, hundred of
thousands of gates
Integrated Circuits
Fan-out
Number of standard loads that the output of a typical gate
can drive without impairing its normal operation
Fan-in
The number of inputs
Power-dissipation
Power consumption
Propagation delay
Average transition delay from input to output
Noise margin
Max. external noise voltage added to an input signal that
does not cause an undesirable change in the current output.
Integrated Circuits
CAD computer aided design
ASIC application specific integrated circuit
FPGA field-programmable gate array
PLD programmable logic device
HDL hardware description language